Linux-2.6.12-rc2v2.6.12-rc2

Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.

Let it rip!

531 files changed, 48911 insertions, 0 deletions

diff --git a/include/asm-arm/a.out.h b/include/asm-arm/a.out.h
new file mode 100644
index 000000000000..3e5fe64c4394
--- /dev/null
+++ b/include/asm-arm/a.out.h
@@ -0,0 +1,39 @@
+#ifndef __ARM_A_OUT_H__
+#define __ARM_A_OUT_H__
+
+#include <linux/personality.h>
+#include <asm/types.h>
+
+struct exec
+{
+  __u32 a_info;         /* Use macros N_MAGIC, etc for access */
+  __u32 a_text;         /* length of text, in bytes */
+  __u32 a_data;         /* length of data, in bytes */
+  __u32 a_bss;          /* length of uninitialized data area for file, in bytes */
+  __u32 a_syms;         /* length of symbol table data in file, in bytes */
+  __u32 a_entry;        /* start address */
+  __u32 a_trsize;       /* length of relocation info for text, in bytes */
+  __u32 a_drsize;       /* length of relocation info for data, in bytes */
+};
+
+/*
+ * This is always the same
+ */
+#define N_TXTADDR(a)    (0x00008000)
+
+#define N_TRSIZE(a)     ((a).a_trsize)
+#define N_DRSIZE(a)     ((a).a_drsize)
+#define N_SYMSIZE(a)    ((a).a_syms)
+
+#define M_ARM 103
+
+#ifdef __KERNEL__
+#define STACK_TOP       ((current->personality == PER_LINUX_32BIT) ? \
+                         TASK_SIZE : TASK_SIZE_26)
+#endif
+
+#ifndef LIBRARY_START_TEXT
+#define LIBRARY_START_TEXT      (0x00c00000)
+#endif
+
+#endif /* __A_OUT_GNU_H__ */
diff --git a/include/asm-arm/apm.h b/include/asm-arm/apm.h
new file mode 100644
index 000000000000..3a50eb759c28
--- /dev/null
+++ b/include/asm-arm/apm.h
@@ -0,0 +1,65 @@
+/* -*- linux-c -*-
+ *
+ * (C) 2003 zecke@handhelds.org
+ *
+ * GPL version 2
+ *
+ * based on arch/arm/kernel/apm.c
+ * factor out the information needed by architectures to provide
+ * apm status
+ *
+ *
+ */
+#ifndef ARM_ASM_SA1100_APM_H
+#define ARM_ASM_SA1100_APM_H
+
+#include <linux/config.h>
+#include <linux/apm_bios.h>
+
+/*
+ * This structure gets filled in by the machine specific 'get_power_status'
+ * implementation.  Any fields which are not set default to a safe value.
+ */
+struct apm_power_info {
+        unsigned char   ac_line_status;
+#define APM_AC_OFFLINE                  0
+#define APM_AC_ONLINE                   1
+#define APM_AC_BACKUP                   2
+#define APM_AC_UNKNOWN                  0xff
+
+        unsigned char   battery_status;
+#define APM_BATTERY_STATUS_HIGH         0
+#define APM_BATTERY_STATUS_LOW          1
+#define APM_BATTERY_STATUS_CRITICAL     2
+#define APM_BATTERY_STATUS_CHARGING     3
+#define APM_BATTERY_STATUS_NOT_PRESENT  4
+#define APM_BATTERY_STATUS_UNKNOWN      0xff
+
+        unsigned char   battery_flag;
+#define APM_BATTERY_FLAG_HIGH           (1 << 0)
+#define APM_BATTERY_FLAG_LOW            (1 << 1)
+#define APM_BATTERY_FLAG_CRITICAL       (1 << 2)
+#define APM_BATTERY_FLAG_CHARGING       (1 << 3)
+#define APM_BATTERY_FLAG_NOT_PRESENT    (1 << 7)
+#define APM_BATTERY_FLAG_UNKNOWN        0xff
+
+        int             battery_life;
+        int             time;
+        int             units;
+#define APM_UNITS_MINS                  0
+#define APM_UNITS_SECS                  1
+#define APM_UNITS_UNKNOWN               -1
+
+};
+
+/*
+ * This allows machines to provide their own "apm get power status" function.
+ */
+extern void (*apm_get_power_status)(struct apm_power_info *);
+
+/*
+ * Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND)
+ */
+void apm_queue_event(apm_event_t event);
+
+#endif
diff --git a/include/asm-arm/arch-cl7500/acornfb.h b/include/asm-arm/arch-cl7500/acornfb.h
new file mode 100644
index 000000000000..3867231a4470
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/acornfb.h
@@ -0,0 +1,34 @@
+#include <linux/config.h>
+#define acornfb_valid_pixrate(var) (var->pixclock >= 39325 && var->pixclock <= 40119)
+
+static inline void
+acornfb_vidc20_find_rates(struct vidc_timing *vidc,
+                          struct fb_var_screeninfo *var)
+{
+        u_int bandwidth;
+  
+        vidc->control |= VIDC20_CTRL_PIX_CK;
+
+        /* Calculate bandwidth */
+        bandwidth = var->pixclock * 8 / var->bits_per_pixel;
+
+        /* Encode bandwidth as VIDC20 setting */
+        if (bandwidth > 16667*2)
+                vidc->control |= VIDC20_CTRL_FIFO_16;
+        else if (bandwidth > 13333*2)
+                vidc->control |= VIDC20_CTRL_FIFO_20;
+        else if (bandwidth > 11111*2)
+                vidc->control |= VIDC20_CTRL_FIFO_24;
+        else
+                vidc->control |= VIDC20_CTRL_FIFO_28;
+
+        vidc->pll_ctl  = 0x2020;
+}
+
+#ifdef CONFIG_CHRONTEL_7003
+#define acornfb_default_control()       VIDC20_CTRL_PIX_HCLK
+#else
+#define acornfb_default_control()       VIDC20_CTRL_PIX_VCLK
+#endif
+
+#define acornfb_default_econtrol()      VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3) | VIDC20_ECTL_ECK
diff --git a/include/asm-arm/arch-cl7500/debug-macro.S b/include/asm-arm/arch-cl7500/debug-macro.S
new file mode 100644
index 000000000000..a5d489d7955a
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/debug-macro.S
@@ -0,0 +1,31 @@
+/* linux/include/asm-arm/arch-cl7500/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mov     \rx, #0xe0000000
+                orr     \rx, \rx, #0x00010000
+                orr     \rx, \rx, #0x00000be0
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldrb    \rd, [\rx, #0x14]
+                tst     \rd, #0x20
+                beq     1001b
+                .endm
diff --git a/include/asm-arm/arch-cl7500/dma.h b/include/asm-arm/arch-cl7500/dma.h
new file mode 100644
index 000000000000..1d6a8829d327
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/dma.h
@@ -0,0 +1,22 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/dma.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS         0xd0000000
+#define MAX_DMA_CHANNELS        0
+
+#define DMA_S0                  0
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-cl7500/entry-macro.S b/include/asm-arm/arch-cl7500/entry-macro.S
new file mode 100644
index 000000000000..686f413f82d6
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/entry-macro.S
@@ -0,0 +1,3 @@
+
+#include <asm/hardware/entry-macro-iomd.S>
+
diff --git a/include/asm-arm/arch-cl7500/hardware.h b/include/asm-arm/arch-cl7500/hardware.h
new file mode 100644
index 000000000000..2339b764f69f
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/hardware.h
@@ -0,0 +1,71 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/hardware.h
+ *
+ * Copyright (C) 1996-1999 Russell King.
+ * Copyright (C) 1999 Nexus Electronics Ltd.
+ *
+ * This file contains the hardware definitions of the 
+ * CL7500 evaluation board.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/arch/memory.h>
+#include <asm/hardware/iomd.h>
+
+#ifdef __ASSEMBLY__
+#define IOMEM(x) x
+#else
+#define IOMEM(x) ((void __iomem *)(x))
+#endif
+
+/*
+ * What hardware must be present
+ */
+#define HAS_IOMD
+#define HAS_VIDC20
+
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+
+#define IO_START                0x03000000      /* I/O */
+#define IO_SIZE                 0x01000000
+#define IO_BASE                 IOMEM(0xe0000000)
+
+#define ISA_START               0x0c000000      /* ISA */
+#define ISA_SIZE                0x00010000
+#define ISA_BASE                0xe1000000
+
+#define FLASH_START             0x01000000      /* XXX */
+#define FLASH_SIZE              0x01000000
+#define FLASH_BASE              0xe2000000
+
+#define LED_START               0x0302B000
+#define LED_SIZE                0x00001000
+#define LED_BASE                0xe3000000
+#define LED_ADDRESS             (LED_BASE + 0xa00)
+
+/* Let's define SCREEN_START for CL7500, even though it's a lie. */
+#define SCREEN_START            0x02000000      /* VRAM */
+#define SCREEN_END              0xdfc00000
+#define SCREEN_BASE             0xdf800000
+
+#define FLUSH_BASE              0xdf000000
+
+#define VIDC_BASE               (void __iomem *)0xe0400000
+#define IOMD_BASE               IOMEM(0xe0200000)
+#define IOC_BASE                IOMEM(0xe0200000)
+#define FLOPPYDMA_BASE          IOMEM(0xe002a000)
+#define PCIO_BASE               IOMEM(0xe0010000)
+
+#define FLUSH_BASE_PHYS         0x00000000      /* ROM */
+
+#define vidc_writel(val)        __raw_writel(val, VIDC_BASE)
+
+/* in/out bias for the ISA slot region */
+#define ISASLOT_IO              0x80400000
+
+#endif
diff --git a/include/asm-arm/arch-cl7500/io.h b/include/asm-arm/arch-cl7500/io.h
new file mode 100644
index 000000000000..f0113bc75630
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/io.h
@@ -0,0 +1,253 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/io.h
+ *  from linux/include/asm-arm/arch-rpc/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ *
+ * Modifications:
+ *  06-Dec-1997 RMK     Created.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * GCC is totally crap at loading/storing data.  We try to persuade it
+ * to do the right thing by using these whereever possible instead of
+ * the above.
+ */
+#define __arch_base_getb(b,o)                   \
+ ({                                             \
+        unsigned int v, r = (b);                \
+        __asm__ __volatile__(                   \
+                "ldrb   %0, [%1, %2]"           \
+                : "=r" (v)                      \
+                : "r" (r), "Ir" (o));           \
+        v;                                      \
+ })
+
+#define __arch_base_getl(b,o)                   \
+ ({                                             \
+        unsigned int v, r = (b);                \
+        __asm__ __volatile__(                   \
+                "ldr    %0, [%1, %2]"           \
+                : "=r" (v)                      \
+                : "r" (r), "Ir" (o));           \
+        v;                                      \
+ })
+
+#define __arch_base_putb(v,b,o)                 \
+ ({                                             \
+        unsigned int r = (b);                   \
+        __asm__ __volatile__(                   \
+                "strb   %0, [%1, %2]"           \
+                :                               \
+                : "r" (v), "r" (r), "Ir" (o));  \
+ })
+
+#define __arch_base_putl(v,b,o)                 \
+ ({                                             \
+        unsigned int r = (b);                   \
+        __asm__ __volatile__(                   \
+                "str    %0, [%1, %2]"           \
+                :                               \
+                : "r" (v), "r" (r), "Ir" (o));  \
+ })
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
+ * and are translated to the start of IO.  Note that all addresses are
+ * shifted left!
+ */
+#define __PORT_PCIO(x)  (!((x) & 0x80000000))
+
+/*
+ * Dynamic IO functions - let the compiler
+ * optimize the expressions
+ */
+static inline void __outb (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "strb   %1, [%0, %2, lsl #2]    @ outb"
+        : "=&r" (temp)
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+static inline void __outw (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "str    %1, [%0, %2, lsl #2]    @ outw"
+        : "=&r" (temp)
+        : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+static inline void __outl (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "str    %1, [%0, %2, lsl #2]    @ outl"
+        : "=&r" (temp)
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
+static inline unsigned sz __in##fnsuffix (unsigned int port)            \
+{                                                                               \
+        unsigned long temp, value;                                              \
+        __asm__ __volatile__(                                                   \
+        "tst    %2, #0x80000000\n\t"                                            \
+        "mov    %0, %4\n\t"                                                     \
+        "addeq  %0, %0, %3\n\t"                                                 \
+        "ldr" instr "   %1, [%0, %2, lsl #2]    @ in" #fnsuffix                 \
+        : "=&r" (temp), "=r" (value)                                            \
+        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
+        : "cc");                                                                \
+        return (unsigned sz)value;                                              \
+}
+
+static inline unsigned int __ioaddr (unsigned int port)                 \
+{                                                                               \
+        if (__PORT_PCIO(port))                                                  \
+                return (unsigned int)(PCIO_BASE + (port << 2));                 \
+        else                                                                    \
+                return (unsigned int)(IO_BASE + (port << 2));                   \
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)   \
+        DECLARE_DYN_IN(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"")
+DECLARE_IO(int,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)                                                     \
+({                                                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]    @ outbc"                                \
+                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2));          \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]    @ outbc"                                \
+                : : "r" (value), "r" (IO_BASE), "r" ((port) << 2));             \
+})
+
+#define __inbc(port)                                                            \
+({                                                                              \
+        unsigned char result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]    @ inbc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]    @ inbc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result;                                                                 \
+})
+
+#define __outwc(value,port)                                                     \
+({                                                                              \
+        unsigned long v = value;                                                \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outwc"                                \
+                : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2));        \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outwc"                                \
+                : : "r" (v|v<<16), "r" (IO_BASE), "r" ((port) << 2));           \
+})
+
+#define __inwc(port)                                                            \
+({                                                                              \
+        unsigned short result;                                                  \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inwc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inwc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result & 0xffff;                                                        \
+})
+
+#define __outlc(value,port)                                                     \
+({                                                                              \
+        unsigned long v = value;                                                \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outlc"                                \
+                : : "r" (v), "r" (PCIO_BASE), "Jr" ((port) << 2));              \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outlc"                                \
+                : : "r" (v), "r" (IO_BASE), "r" ((port) << 2));                 \
+})
+
+#define __inlc(port)                                                            \
+({                                                                              \
+        unsigned long result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inlc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inlc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result;                                                                 \
+})
+
+#define __ioaddrc(port)                                                         \
+        (__PORT_PCIO((port)) ? PCIO_BASE + ((port) << 2) : IO_BASE + ((port) << 2))
+
+#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
+#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
+#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
+#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
+/* the following macro is deprecated */
+#define ioaddr(port)                    __ioaddr((port))
+
+#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
+#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
+
+#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
+#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)    (x)
+
+#endif
diff --git a/include/asm-arm/arch-cl7500/irq.h b/include/asm-arm/arch-cl7500/irq.h
new file mode 100644
index 000000000000..4b286331f3f8
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/irq.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-arm/arch-cl7500/irq.h
+ *
+ * Copyright (C) 1996 Russell King
+ * Copyright (C) 1999, 2001 Nexus Electronics Ltd.
+ *
+ * Changelog:
+ *   10-10-1996 RMK     Brought up to date with arch-sa110eval
+ *   22-08-1998 RMK     Restructured IRQ routines
+ *   11-08-1999 PJB     Created ARM7500 version, derived from RiscPC code
+ */
+
+#include <asm/hardware/iomd.h>
+#include <asm/io.h>
+
+static inline int fixup_irq(unsigned int irq)
+{
+        if (irq == IRQ_ISA) {
+                int isabits = *((volatile unsigned int *)0xe002b700);
+                if (isabits == 0) {
+                        printk("Spurious ISA IRQ!\n");
+                        return irq;
+                }
+                irq = IRQ_ISA_BASE;
+                while (!(isabits & 1)) {
+                        irq++;
+                        isabits >>= 1;
+                }
+        }
+
+        return irq;
+}
diff --git a/include/asm-arm/arch-cl7500/irqs.h b/include/asm-arm/arch-cl7500/irqs.h
new file mode 100644
index 000000000000..f20996eadf19
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/irqs.h
@@ -0,0 +1,66 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/irqs.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
+
+#define IRQ_INT2                0
+#define IRQ_INT1                2
+#define IRQ_VSYNCPULSE          3
+#define IRQ_POWERON             4
+#define IRQ_TIMER0              5
+#define IRQ_TIMER1              6
+#define IRQ_FORCE               7
+#define IRQ_INT8                8
+#define IRQ_ISA                 9
+#define IRQ_INT6                10
+#define IRQ_INT5                11
+#define IRQ_INT4                12
+#define IRQ_INT3                13
+#define IRQ_KEYBOARDTX          14
+#define IRQ_KEYBOARDRX          15
+
+#define IRQ_DMA0                16
+#define IRQ_DMA1                17
+#define IRQ_DMA2                18
+#define IRQ_DMA3                19
+#define IRQ_DMAS0               20
+#define IRQ_DMAS1               21
+
+#define IRQ_IOP0                24
+#define IRQ_IOP1                25
+#define IRQ_IOP2                26
+#define IRQ_IOP3                27
+#define IRQ_IOP4                28
+#define IRQ_IOP5                29
+#define IRQ_IOP6                30
+#define IRQ_IOP7                31
+
+#define IRQ_MOUSERX             40
+#define IRQ_MOUSETX             41
+#define IRQ_ADC                 42
+#define IRQ_EVENT1              43
+#define IRQ_EVENT2              44
+
+#define IRQ_ISA_BASE            48
+#define IRQ_ISA_3               48
+#define IRQ_ISA_4               49
+#define IRQ_ISA_5               50
+#define IRQ_ISA_7               51
+#define IRQ_ISA_9               52
+#define IRQ_ISA_10              53
+#define IRQ_ISA_11              54
+#define IRQ_ISA_14              55      
+
+#define FIQ_INT9                0
+#define FIQ_INT5                1
+#define FIQ_INT6                4
+#define FIQ_INT8                6
+#define FIQ_FORCE               7
+
+/*
+ * This is the offset of the FIQ "IRQ" numbers
+ */
+#define FIQ_START               64
+
+#define IRQ_TIMER               IRQ_TIMER0
diff --git a/include/asm-arm/arch-cl7500/memory.h b/include/asm-arm/arch-cl7500/memory.h
new file mode 100644
index 000000000000..9776bba8e585
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/memory.h
@@ -0,0 +1,29 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/memory.h
+ *
+ * Copyright (c) 1996,1997,1998 Russell King.
+ *
+ * Changelog:
+ *  20-Oct-1996 RMK     Created
+ *  31-Dec-1997 RMK     Fixed definitions to reduce warnings
+ *  11-Jan-1998 RMK     Uninlined to reduce hits on cache
+ *  08-Feb-1998 RMK     Added __virt_to_bus and __bus_to_virt
+ *  21-Mar-1999 RMK     Renamed to memory.h
+ *              RMK     Added TASK_SIZE and PAGE_OFFSET
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x10000000UL)
+
+/*
+ * These are exactly the same on the RiscPC as the
+ * physical memory view.
+ */
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-cl7500/param.h b/include/asm-arm/arch-cl7500/param.h
new file mode 100644
index 000000000000..974bf69fbb1a
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/param.h
@@ -0,0 +1,5 @@
+/*
+ *  linux/include/asm-arm/arch-cl7500/param.h
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
diff --git a/include/asm-arm/arch-cl7500/system.h b/include/asm-arm/arch-cl7500/system.h
new file mode 100644
index 000000000000..a9505d6a74d7
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/system.h
@@ -0,0 +1,23 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/system.h
+ *
+ * Copyright (c) 1999 Nexus Electronics Ltd.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/hardware/iomd.h>
+#include <asm/io.h>
+
+static inline void arch_idle(void)
+{
+        iomd_writeb(0, IOMD_SUSMODE);
+}
+
+#define arch_reset(mode)                        \
+        do {                                    \
+                iomd_writeb(0, IOMD_ROMCR0);    \
+                cpu_reset(0);                   \
+        } while (0)
+
+#endif
diff --git a/include/asm-arm/arch-cl7500/timex.h b/include/asm-arm/arch-cl7500/timex.h
new file mode 100644
index 000000000000..8a4175fc0106
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/timex.h
@@ -0,0 +1,13 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/timex.h
+ *
+ * CL7500 architecture timex specifications
+ *
+ * Copyright (C) 1999 Nexus Electronics Ltd
+ */
+
+/*
+ * On the ARM7500, the clock ticks at 2MHz.
+ */
+#define CLOCK_TICK_RATE         2000000
+
diff --git a/include/asm-arm/arch-cl7500/uncompress.h b/include/asm-arm/arch-cl7500/uncompress.h
new file mode 100644
index 000000000000..68601b3e3b95
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/uncompress.h
@@ -0,0 +1,43 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/uncompress.h
+ *
+ * Copyright (C) 1999, 2000 Nexus Electronics Ltd.
+ */
+
+#define BASE 0x03010000
+#define SERBASE (BASE + (0x2f8 << 2))
+
+static __inline__ void putc(char c)
+{
+        while (!(*((volatile unsigned int *)(SERBASE + 0x14)) & 0x20));
+        *((volatile unsigned int *)(SERBASE)) = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                putc(*s);
+                if (*s == '\n')
+                        putc('\r');
+                s++;
+        }
+}
+
+static __inline__ void arch_decomp_setup(void)
+{
+        int baud = 3686400 / (9600 * 32);
+
+        *((volatile unsigned int *)(SERBASE + 0xC)) = 0x80;
+        *((volatile unsigned int *)(SERBASE + 0x0)) = baud & 0xff;
+        *((volatile unsigned int *)(SERBASE + 0x4)) = (baud & 0xff00) >> 8;
+        *((volatile unsigned int *)(SERBASE + 0xC)) = 3; /* 8 bits */
+        *((volatile unsigned int *)(SERBASE + 0x10)) = 3; /* DTR, RTS */
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-cl7500/vmalloc.h b/include/asm-arm/arch-cl7500/vmalloc.h
new file mode 100644
index 000000000000..91883def4889
--- /dev/null
+++ b/include/asm-arm/arch-cl7500/vmalloc.h
@@ -0,0 +1,15 @@
+/*
+ * linux/include/asm-arm/arch-cl7500/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
diff --git a/include/asm-arm/arch-clps711x/autcpu12.h b/include/asm-arm/arch-clps711x/autcpu12.h
new file mode 100644
index 000000000000..1588a365f610
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/autcpu12.h
@@ -0,0 +1,78 @@
+/*
+ * AUTCPU12 specific defines
+ *
+ * (c) 2001 Thomas Gleixner, autronix automation <gleixner@autronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_AUTCPU12_H
+#define __ASM_ARCH_AUTCPU12_H
+
+/*
+ * The CS8900A ethernet chip has its I/O registers wired to chip select 2
+ * (nCS2). This is the mapping for it.
+ */
+#define AUTCPU12_PHYS_CS8900A           CS2_PHYS_BASE           /* physical */
+#define AUTCPU12_VIRT_CS8900A           (0xfe000000)            /* virtual */
+
+/*
+ * The flash bank is wired to chip select 0
+ */
+#define AUTCPU12_PHYS_FLASH             CS0_PHYS_BASE           /* physical */
+
+/* offset for device specific information structure */
+#define AUTCPU12_LCDINFO_OFFS           (0x00010000)    
+/*
+* Videomemory is the internal SRAM (CS 6)       
+*/
+#define AUTCPU12_PHYS_VIDEO             CS6_PHYS_BASE
+#define AUTCPU12_VIRT_VIDEO             (0xfd000000)
+
+/*
+* All special IO's are tied to CS1
+*/
+#define AUTCPU12_PHYS_CHAR_LCD          CS1_PHYS_BASE +0x00000000  /* physical */
+
+#define AUTCPU12_PHYS_NVRAM             CS1_PHYS_BASE +0x02000000  /* physical */
+
+#define AUTCPU12_PHYS_CSAUX1            CS1_PHYS_BASE +0x04000000  /* physical */
+
+#define AUTCPU12_PHYS_SMC               CS1_PHYS_BASE +0x06000000  /* physical */
+
+#define AUTCPU12_PHYS_CAN               CS1_PHYS_BASE +0x08000000  /* physical */
+
+#define AUTCPU12_PHYS_TOUCH             CS1_PHYS_BASE +0x0A000000  /* physical */
+
+#define AUTCPU12_PHYS_IO                CS1_PHYS_BASE +0x0C000000  /* physical */
+
+#define AUTCPU12_PHYS_LPT               CS1_PHYS_BASE +0x0E000000  /* physical */
+
+/* 
+* defines for smartmedia card access 
+*/
+#define AUTCPU12_SMC_RDY                (1<<2)
+#define AUTCPU12_SMC_ALE                (1<<3)
+#define AUTCPU12_SMC_CLE                (1<<4)
+#define AUTCPU12_SMC_PORT_OFFSET        PBDR
+#define AUTCPU12_SMC_SELECT_OFFSET      0x10
+/*
+* defines for lcd contrast 
+*/
+#define AUTCPU12_DPOT_PORT_OFFSET       PEDR
+#define AUTCPU12_DPOT_CS                (1<<0)
+#define AUTCPU12_DPOT_CLK               (1<<1)
+#define AUTCPU12_DPOT_UD                (1<<2)
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/debug-macro.S b/include/asm-arm/arch-clps711x/debug-macro.S
new file mode 100644
index 000000000000..bc0a5760722b
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/debug-macro.S
@@ -0,0 +1,46 @@
+/* linux/include/asm-arm/arch-clps711x/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <asm/hardware/clps7111.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #CLPS7111_PHYS_BASE
+                movne   \rx, #CLPS7111_VIRT_BASE
+#ifndef CONFIG_DEBUG_CLPS711X_UART2
+                add     \rx, \rx, #0x0000       @ UART1
+#else
+                add     \rx, \rx, #0x1000       @ UART2
+#endif
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x0480]     @ UARTDR
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
+                tst     \rd, #1 << 11           @ UBUSYx
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+                tst     \rx, #0x1000            @ UART2 does not have CTS here
+                bne     1002f
+1001:           ldr     \rd, [\rx, #0x0140]     @ SYSFLGx
+                tst     \rd, #1 << 8            @ CTS
+                bne     1001b
+1002:
+                .endm
+
diff --git a/include/asm-arm/arch-clps711x/dma.h b/include/asm-arm/arch-clps711x/dma.h
new file mode 100644
index 000000000000..3c4c5c843252
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/dma.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+
+#define MAX_DMA_CHANNELS        0
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/include/asm-arm/arch-clps711x/entry-macro.S b/include/asm-arm/arch-clps711x/entry-macro.S
new file mode 100644
index 000000000000..b31079a1d4a9
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/entry-macro.S
@@ -0,0 +1,51 @@
+/*
+ * include/asm-arm/arch-CLPS711x/entry-macro.S
+ *
+ * Low-level IRQ helper macros for CLPS711X-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware/clps7111.h>
+
+                .macro  disable_fiq
+                .endm
+
+#if (INTSR2 - INTSR1) != (INTMR2 - INTMR1)
+#error INTSR stride != INTMR stride
+#endif
+
+                .macro  get_irqnr_and_base, irqnr, stat, base, mask
+                mov     \base, #CLPS7111_BASE
+                ldr     \stat, [\base, #INTSR1]
+                ldr     \mask, [\base, #INTMR1]
+                mov     \irqnr, #4
+                mov     \mask, \mask, lsl #16
+                and     \stat, \stat, \mask, lsr #16
+                movs    \stat, \stat, lsr #4
+                bne     1001f
+
+                add     \base, \base, #INTSR2 - INTSR1
+                ldr     \stat, [\base, #INTSR1]
+                ldr     \mask, [\base, #INTMR1]
+                mov     \irqnr, #16
+                mov     \mask, \mask, lsl #16
+                and     \stat, \stat, \mask, lsr #16
+
+1001:           tst     \stat, #255
+                addeq   \irqnr, \irqnr, #8
+                moveq   \stat, \stat, lsr #8
+                tst     \stat, #15
+                addeq   \irqnr, \irqnr, #4
+                moveq   \stat, \stat, lsr #4
+                tst     \stat, #3
+                addeq   \irqnr, \irqnr, #2
+                moveq   \stat, \stat, lsr #2
+                tst     \stat, #1
+                addeq   \irqnr, \irqnr, #1
+                moveq   \stat, \stat, lsr #1
+                tst     \stat, #1                       @ bit 0 should be set
+                .endm
+
+
diff --git a/include/asm-arm/arch-clps711x/hardware.h b/include/asm-arm/arch-clps711x/hardware.h
new file mode 100644
index 000000000000..1386871e1a5a
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/hardware.h
@@ -0,0 +1,238 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/hardware.h
+ *
+ *  This file contains the hardware definitions of the Prospector P720T.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+
+#define CLPS7111_VIRT_BASE      0xff000000
+#define CLPS7111_BASE           CLPS7111_VIRT_BASE
+
+/*
+ * The physical addresses that the external chip select signals map to is
+ * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
+ * processors.  CONFIG_EP72XX_BOOT_ROM is only available if these
+ * processors are in use.
+ */
+#ifndef CONFIG_EP72XX_ROM_BOOT
+#define CS0_PHYS_BASE           (0x00000000)
+#define CS1_PHYS_BASE           (0x10000000)
+#define CS2_PHYS_BASE           (0x20000000)
+#define CS3_PHYS_BASE           (0x30000000)
+#define CS4_PHYS_BASE           (0x40000000)
+#define CS5_PHYS_BASE           (0x50000000)
+#define CS6_PHYS_BASE           (0x60000000)
+#define CS7_PHYS_BASE           (0x70000000)
+#else
+#define CS0_PHYS_BASE           (0x70000000)
+#define CS1_PHYS_BASE           (0x60000000)
+#define CS2_PHYS_BASE           (0x50000000)
+#define CS3_PHYS_BASE           (0x40000000)
+#define CS4_PHYS_BASE           (0x30000000)
+#define CS5_PHYS_BASE           (0x20000000)
+#define CS6_PHYS_BASE           (0x10000000)
+#define CS7_PHYS_BASE           (0x00000000)
+#endif
+
+#if defined (CONFIG_ARCH_EP7211)
+
+#define EP7211_VIRT_BASE        CLPS7111_VIRT_BASE
+#define EP7211_BASE             CLPS7111_VIRT_BASE
+#include <asm/hardware/ep7211.h>
+
+#elif defined (CONFIG_ARCH_EP7212)
+
+#define EP7212_VIRT_BASE        CLPS7111_VIRT_BASE
+#define EP7212_BASE             CLPS7111_VIRT_BASE
+#include <asm/hardware/ep7212.h>
+
+#endif
+
+#define SYSPLD_VIRT_BASE        0xfe000000
+#define SYSPLD_BASE             SYSPLD_VIRT_BASE
+
+#ifndef __ASSEMBLER__
+
+#define PCIO_BASE               IO_BASE
+
+#endif
+
+
+#if  defined (CONFIG_ARCH_AUTCPU12)
+
+#define  CS89712_VIRT_BASE      CLPS7111_VIRT_BASE
+#define  CS89712_BASE           CLPS7111_VIRT_BASE
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+#include <asm/hardware/cs89712.h>
+
+#endif
+
+
+#if defined (CONFIG_ARCH_CDB89712)
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+#include <asm/hardware/cs89712.h>
+
+/* dynamic ioremap() areas */
+#define FLASH_START      0x00000000
+#define FLASH_SIZE       0x800000
+#define FLASH_WIDTH      4
+
+#define SRAM_START       0x60000000
+#define SRAM_SIZE        0xc000
+#define SRAM_WIDTH       4
+
+#define BOOTROM_START    0x70000000
+#define BOOTROM_SIZE     0x80
+#define BOOTROM_WIDTH    4
+
+
+/* static cdb89712_map_io() areas */
+#define REGISTER_START   0x80000000
+#define REGISTER_SIZE    0x4000
+#define REGISTER_BASE    0xff000000
+
+#define ETHER_START      0x20000000
+#define ETHER_SIZE       0x1000
+#define ETHER_BASE       0xfe000000
+
+#endif
+
+
+#if defined (CONFIG_ARCH_EDB7211)
+
+/*
+ * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3) 
+ * and repeat across it. This is the mapping for it.
+ *
+ * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This 
+ * was cause for much consternation and headscratching. This should probably
+ * be made a compile/run time kernel option.
+ */
+#define EP7211_PHYS_EXTKBD              CS3_PHYS_BASE   /* physical */
+
+#define EP7211_VIRT_EXTKBD              (0xfd000000)    /* virtual */
+
+
+/*
+ * The CS8900A ethernet chip has its I/O registers wired to chip select 2 
+ * (nCS2). This is the mapping for it.
+ *
+ * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This 
+ * was cause for much consternation and headscratching. This should probably
+ * be made a compile/run time kernel option.
+ */
+#define EP7211_PHYS_CS8900A             CS2_PHYS_BASE   /* physical */
+
+#define EP7211_VIRT_CS8900A             (0xfc000000)    /* virtual */
+
+
+/*
+ * The two flash banks are wired to chip selects 0 and 1. This is the mapping
+ * for them.
+ *
+ * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
+ * in jumpered boot mode.
+ */
+#define EP7211_PHYS_FLASH1              CS0_PHYS_BASE   /* physical */
+#define EP7211_PHYS_FLASH2              CS1_PHYS_BASE   /* physical */
+
+#define EP7211_VIRT_FLASH1              (0xfa000000)    /* virtual */
+#define EP7211_VIRT_FLASH2              (0xfb000000)    /* virtual */
+
+#endif /* CONFIG_ARCH_EDB7211 */
+
+
+/*
+ * Relevant bits in port D, which controls power to the various parts of
+ * the LCD on the EDB7211.
+ */
+#define EDB_PD1_LCD_DC_DC_EN    (1<<1)
+#define EDB_PD2_LCDEN           (1<<2)
+#define EDB_PD3_LCDBL           (1<<3)
+
+
+#if defined (CONFIG_ARCH_CEIVA)
+
+#define  CEIVA_VIRT_BASE        CLPS7111_VIRT_BASE
+#define  CEIVA_BASE             CLPS7111_VIRT_BASE
+
+#include <asm/hardware/clps7111.h>
+#include <asm/hardware/ep7212.h>
+
+
+/*
+ * The two flash banks are wired to chip selects 0 and 1. This is the mapping
+ * for them.
+ *
+ * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
+ * in jumpered boot mode.
+ */
+#define CEIVA_PHYS_FLASH1       CS0_PHYS_BASE   /* physical */
+#define CEIVA_PHYS_FLASH2       CS1_PHYS_BASE   /* physical */
+
+#define CEIVA_VIRT_FLASH1       (0xfa000000)    /* virtual */
+#define CEIVA_VIRT_FLASH2       (0xfb000000)    /* virtual */
+
+#define CEIVA_FLASH_SIZE        0x100000
+#define CEIVA_FLASH_WIDTH       2
+
+#define SRAM_START       0x60000000
+#define SRAM_SIZE        0xc000
+#define SRAM_WIDTH       4
+
+#define BOOTROM_START    0x70000000
+#define BOOTROM_SIZE     0x80
+#define BOOTROM_WIDTH    4
+
+/*
+ * SED1355 LCD controller
+ */
+#define CEIVA_PHYS_SED1355      CS2_PHYS_BASE
+#define CEIVA_VIRT_SED1355      (0xfc000000)
+
+/*
+ * Relevant bits in port D, which controls power to the various parts of
+ * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
+ */
+
+// Reset line to SED1355 (must be high to operate)
+#define CEIVA_PD1_LCDRST        (1<<1)
+// LCD panel enable (set to one, to enable LCD)
+#define CEIVA_PD4_LCDEN         (1<<4)
+// Backlight (set to one, to turn on backlight
+#define CEIVA_PD5_LCDBL         (1<<5)
+
+/*
+ * Relevant bits in port B, which report the status of the buttons.
+ */
+
+// White button
+#define CEIVA_PB4_WHT_BTN       (1<<4)
+// Black button
+#define CEIVA_PB0_BLK_BTN       (1<<0)
+#endif // #if defined (CONFIG_ARCH_CEIVA)
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/io.h b/include/asm-arm/arch-clps711x/io.h
new file mode 100644
index 000000000000..14d7e8da5453
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/io.h
@@ -0,0 +1,37 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/io.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+/*
+ * We don't support ins[lb]/outs[lb].  Make them fault.
+ */
+#define __raw_readsb(p,d,l)     do { *(int *)0 = 0; } while (0)
+#define __raw_readsl(p,d,l)     do { *(int *)0 = 0; } while (0)
+#define __raw_writesb(p,d,l)    do { *(int *)0 = 0; } while (0)
+#define __raw_writesl(p,d,l)    do { *(int *)0 = 0; } while (0)
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/irqs.h b/include/asm-arm/arch-clps711x/irqs.h
new file mode 100644
index 000000000000..76025dc87637
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/irqs.h
@@ -0,0 +1,53 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/irqs.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Interrupts from INTSR1
+ */
+#define IRQ_CSINT                       4
+#define IRQ_EINT1                       5
+#define IRQ_EINT2                       6
+#define IRQ_EINT3                       7
+#define IRQ_TC1OI                       8
+#define IRQ_TC2OI                       9
+#define IRQ_RTCMI                       10
+#define IRQ_TINT                        11
+#define IRQ_UTXINT1                     12
+#define IRQ_URXINT1                     13
+#define IRQ_UMSINT                      14
+#define IRQ_SSEOTI                      15
+
+#define INT1_IRQS                       (0x0000fff0)
+#define INT1_ACK_IRQS                   (0x00004f10)
+
+/*
+ * Interrupts from INTSR2
+ */
+#define IRQ_KBDINT                      (16+0)  /* bit 0 */
+#define IRQ_SS2RX                       (16+1)  /* bit 1 */
+#define IRQ_SS2TX                       (16+2)  /* bit 2 */
+#define IRQ_UTXINT2                     (16+12) /* bit 12 */
+#define IRQ_URXINT2                     (16+13) /* bit 13 */
+
+#define INT2_IRQS                       (0x30070000)
+#define INT2_ACK_IRQS                   (0x00010000)
+
+#define NR_IRQS                         30
+
diff --git a/include/asm-arm/arch-clps711x/memory.h b/include/asm-arm/arch-clps711x/memory.h
new file mode 100644
index 000000000000..bd978947db42
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/memory.h
@@ -0,0 +1,128 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <linux/config.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0xc0000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+
+#if defined(CONFIG_ARCH_CDB89712)
+
+#define __virt_to_bus(x)        (x)
+#define __bus_to_virt(x)        (x)
+
+#elif defined (CONFIG_ARCH_AUTCPU12)
+
+#define __virt_to_bus(x)        (x)
+#define __bus_to_virt(x)        (x)
+
+#else
+
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
+#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+
+#endif
+
+
+/*
+ * Like the SA1100, the EDB7211 has a large gap between physical RAM
+ * banks.  In 2.2, the Psion (CL-PS7110) port added custom support for
+ * discontiguous physical memory.  In 2.4, we can use the standard
+ * Linux NUMA support.
+ *
+ * This is not necessary for EP7211 implementations with only one used
+ * memory bank.  For those systems, simply undefine CONFIG_DISCONTIGMEM.
+ */
+
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * Because of the wide memory address space between physical RAM banks on the 
+ * SA1100, it's much more convenient to use Linux's NUMA support to implement
+ * our memory map representation.  Assuming all memory nodes have equal access 
+ * characteristics, we then have generic discontiguous memory support.
+ *
+ * Of course, all this isn't mandatory for SA1100 implementations with only
+ * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
+ *
+ * The nodes are matched with the physical memory bank addresses which are 
+ * incidentally the same as virtual addresses.
+ * 
+ *      node 0:  0xc0000000 - 0xc7ffffff
+ *      node 1:  0xc8000000 - 0xcfffffff
+ *      node 2:  0xd0000000 - 0xd7ffffff
+ *      node 3:  0xd8000000 - 0xdfffffff
+ */
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) \
+                (((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn) \
+        (((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr) \
+                        NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
+
+#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+/*
+ * Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+        (((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
+
+/*
+ * The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
+ * uses only one of the two banks (bank #1).  However, even within
+ * bank #1, memory is discontiguous.
+ *
+ * The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
+ * them, so we use 24 for the node max shift to get 16MB node sizes.
+ */
+#define NODE_MAX_MEM_SHIFT      24
+#define NODE_MAX_MEM_SIZE       (1<<NODE_MAX_MEM_SHIFT)
+
+#endif /* CONFIG_DISCONTIGMEM */
+
+#endif
+
diff --git a/include/asm-arm/arch-clps711x/param.h b/include/asm-arm/arch-clps711x/param.h
new file mode 100644
index 000000000000..86f6bd29623d
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/param.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-clps711x/syspld.h b/include/asm-arm/arch-clps711x/syspld.h
new file mode 100644
index 000000000000..960578a22a8e
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/syspld.h
@@ -0,0 +1,121 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/syspld.h
+ *
+ *  System Control PLD register definitions.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSPLD_H
+#define __ASM_ARCH_SYSPLD_H
+
+#define SYSPLD_PHYS_BASE        (0x10000000)
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+#define SYSPLD_REG(type,off)    (*(volatile type *)(SYSPLD_BASE + off))
+#else
+#define SYSPLD_REG(type,off)    (off)
+#endif
+
+#define PLD_INT         SYSPLD_REG(u32, 0x000000)
+#define PLD_INT_PENIRQ          (1 << 5)
+#define PLD_INT_UCB_IRQ         (1 << 1)
+#define PLD_INT_KBD_ATN         (1 << 0)        /* EINT1 */
+
+#define PLD_PWR         SYSPLD_REG(u32, 0x000004)
+#define PLD_PWR_EXT             (1 << 5)
+#define PLD_PWR_MODE            (1 << 4)        /* 1 = PWM, 0 = PFM */
+#define PLD_S4_ON               (1 << 3)        /* LCD bias voltage enable */
+#define PLD_S3_ON               (1 << 2)        /* LCD backlight enable */
+#define PLD_S2_ON               (1 << 1)        /* LCD 3V3 supply enable */
+#define PLD_S1_ON               (1 << 0)        /* LCD 3V supply enable */
+
+#define PLD_KBD         SYSPLD_REG(u32, 0x000008)
+#define PLD_KBD_WAKE            (1 << 1)
+#define PLD_KBD_EN              (1 << 0)
+
+#define PLD_SPI         SYSPLD_REG(u32, 0x00000c)
+#define PLD_SPI_EN              (1 << 0)
+
+#define PLD_IO          SYSPLD_REG(u32, 0x000010)
+#define PLD_IO_BOOTSEL          (1 << 6)        /* boot sel switch */
+#define PLD_IO_USER             (1 << 5)        /* user defined switch */
+#define PLD_IO_LED3             (1 << 4)
+#define PLD_IO_LED2             (1 << 3)
+#define PLD_IO_LED1             (1 << 2)
+#define PLD_IO_LED0             (1 << 1)
+#define PLD_IO_LEDEN            (1 << 0)
+
+#define PLD_IRDA        SYSPLD_REG(u32, 0x000014)
+#define PLD_IRDA_EN             (1 << 0)
+
+#define PLD_COM2        SYSPLD_REG(u32, 0x000018)
+#define PLD_COM2_EN             (1 << 0)
+
+#define PLD_COM1        SYSPLD_REG(u32, 0x00001c)
+#define PLD_COM1_EN             (1 << 0)
+
+#define PLD_AUD         SYSPLD_REG(u32, 0x000020)
+#define PLD_AUD_DIV1            (1 << 6)
+#define PLD_AUD_DIV0            (1 << 5)
+#define PLD_AUD_CLK_SEL1        (1 << 4)
+#define PLD_AUD_CLK_SEL0        (1 << 3)
+#define PLD_AUD_MIC_PWR         (1 << 2)
+#define PLD_AUD_MIC_GAIN        (1 << 1)
+#define PLD_AUD_CODEC_EN        (1 << 0)
+
+#define PLD_CF          SYSPLD_REG(u32, 0x000024)
+#define PLD_CF2_SLEEP           (1 << 5)
+#define PLD_CF1_SLEEP           (1 << 4)
+#define PLD_CF2_nPDREQ          (1 << 3)
+#define PLD_CF1_nPDREQ          (1 << 2)
+#define PLD_CF2_nIRQ            (1 << 1)
+#define PLD_CF1_nIRQ            (1 << 0)
+
+#define PLD_SDC         SYSPLD_REG(u32, 0x000028)
+#define PLD_SDC_INT_EN          (1 << 2)
+#define PLD_SDC_WP              (1 << 1)
+#define PLD_SDC_CD              (1 << 0)
+
+#define PLD_FPGA        SYSPLD_REG(u32, 0x00002c)
+
+#define PLD_CODEC       SYSPLD_REG(u32, 0x400000)
+#define PLD_CODEC_IRQ3          (1 << 4)
+#define PLD_CODEC_IRQ2          (1 << 3)
+#define PLD_CODEC_IRQ1          (1 << 2)
+#define PLD_CODEC_EN            (1 << 0)
+
+#define PLD_BRITE       SYSPLD_REG(u32, 0x400004)
+#define PLD_BRITE_UP            (1 << 1)
+#define PLD_BRITE_DN            (1 << 0)
+
+#define PLD_LCDEN       SYSPLD_REG(u32, 0x400008)
+#define PLD_LCDEN_EN            (1 << 0)
+
+#define PLD_ID          SYSPLD_REG(u32, 0x40000c)
+
+#define PLD_TCH         SYSPLD_REG(u32, 0x400010)
+#define PLD_TCH_PENIRQ          (1 << 1)
+#define PLD_TCH_EN              (1 << 0)
+
+#define PLD_GPIO        SYSPLD_REG(u32, 0x400014)
+#define PLD_GPIO2               (1 << 2)
+#define PLD_GPIO1               (1 << 1)
+#define PLD_GPIO0               (1 << 0)
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/system.h b/include/asm-arm/arch-clps711x/system.h
new file mode 100644
index 000000000000..2ab981fee37f
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/system.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/system.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/hardware/clps7111.h>
+
+static inline void arch_idle(void)
+{
+        clps_writel(1, HALT);
+        __asm__ __volatile__(
+        "mov    r0, r0\n\
+        mov     r0, r0");
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif
diff --git a/include/asm-arm/arch-clps711x/time.h b/include/asm-arm/arch-clps711x/time.h
new file mode 100644
index 000000000000..9cb27cd4e6ae
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/time.h
@@ -0,0 +1,48 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/time.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <asm/leds.h>
+#include <asm/hardware/clps7111.h>
+
+extern void clps711x_setup_timer(void);
+
+/*
+ * IRQ handler for the timer
+ */
+static irqreturn_t
+p720t_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+        do_leds();
+        do_timer(regs);
+#ifndef CONFIG_SMP
+        update_process_times(user_mode(regs));
+#endif
+        do_profile(regs);
+        return IRQ_HANDLED;
+}
+
+/*
+ * Set up timer interrupt, and return the current time in seconds.
+ */
+void __init time_init(void)
+{
+        clps711x_setup_timer();
+        timer_irq.handler = p720t_timer_interrupt;
+        setup_irq(IRQ_TC2OI, &timer_irq);
+}
diff --git a/include/asm-arm/arch-clps711x/timex.h b/include/asm-arm/arch-clps711x/timex.h
new file mode 100644
index 000000000000..dcbb381da3dd
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/timex.h
+ *
+ *  Prospector 720T architecture timex specifications
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE 512000
diff --git a/include/asm-arm/arch-clps711x/uncompress.h b/include/asm-arm/arch-clps711x/uncompress.h
new file mode 100644
index 000000000000..7d0ab791b16c
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/uncompress.h
@@ -0,0 +1,67 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/uncompress.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include <linux/config.h>
+#include <asm/arch/io.h>
+#include <asm/arch/hardware.h>
+#include <asm/hardware/clps7111.h>
+
+#undef CLPS7111_BASE
+#define CLPS7111_BASE CLPS7111_PHYS_BASE
+
+#define barrier()               __asm__ __volatile__("": : :"memory")
+#define __raw_readl(p)          (*(unsigned long *)(p))
+#define __raw_writel(v,p)       (*(unsigned long *)(p) = (v))
+
+#ifdef CONFIG_DEBUG_CLPS711X_UART2
+#define SYSFLGx SYSFLG2
+#define UARTDRx UARTDR2
+#else
+#define SYSFLGx SYSFLG1
+#define UARTDRx UARTDR1
+#endif
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        char c;
+
+        while ((c = *s++) != '\0') {
+                while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
+                        barrier();
+                clps_writel(c, UARTDRx);
+
+                if (c == '\n') {
+                        while (clps_readl(SYSFLGx) & SYSFLG_UTXFF)
+                                barrier();
+                        clps_writel('\r', UARTDRx);
+                }
+        }
+        while (clps_readl(SYSFLGx) & SYSFLG_UBUSY)
+                barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-clps711x/vmalloc.h b/include/asm-arm/arch-clps711x/vmalloc.h
new file mode 100644
index 000000000000..42571ed5e493
--- /dev/null
+++ b/include/asm-arm/arch-clps711x/vmalloc.h
@@ -0,0 +1,31 @@
+/*
+ *  linux/include/asm-arm/arch-clps711x/vmalloc.h
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-ebsa110/debug-macro.S b/include/asm-arm/arch-ebsa110/debug-macro.S
new file mode 100644
index 000000000000..dcd03a40c502
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/debug-macro.S
@@ -0,0 +1,34 @@
+/* linux/include/asm-arm/arch-ebsa110/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+**/
+
+                .macro  addruart,rx
+                mov     \rx, #0xf0000000
+                orr     \rx, \rx, #0x00000be0
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldrb    \rd, [\rx, #0x14]
+                and     \rd, \rd, #0x60
+                teq     \rd, #0x60
+                bne     1002b
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldrb    \rd, [\rx, #0x18]
+                tst     \rd, #0x10
+                beq     1001b
+                .endm
diff --git a/include/asm-arm/arch-ebsa110/dma.h b/include/asm-arm/arch-ebsa110/dma.h
new file mode 100644
index 000000000000..d491776ac1cc
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/dma.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  EBSA110 DMA definitions
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        0
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/include/asm-arm/arch-ebsa110/entry-macro.S b/include/asm-arm/arch-ebsa110/entry-macro.S
new file mode 100644
index 000000000000..b12ca04f998c
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/entry-macro.S
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-ebsa110/entry-macro.S
+ *
+ * Low-level IRQ helper macros for ebsa110 platform.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+
+
+#define IRQ_STAT                0xff000000      /* read */
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, stat, base, tmp
+        mov     \base, #IRQ_STAT
+        ldrb    \stat, [\base]                  @ get interrupts
+        mov     \irqnr, #0
+        tst     \stat, #15
+        addeq   \irqnr, \irqnr, #4
+        moveq   \stat, \stat, lsr #4
+        tst     \stat, #3
+        addeq   \irqnr, \irqnr, #2
+        moveq   \stat, \stat, lsr #2
+        tst     \stat, #1
+        addeq   \irqnr, \irqnr, #1
+        moveq   \stat, \stat, lsr #1
+        tst     \stat, #1                       @ bit 0 should be set
+        .endm
+
diff --git a/include/asm-arm/arch-ebsa110/hardware.h b/include/asm-arm/arch-ebsa110/hardware.h
new file mode 100644
index 000000000000..4e41c2358f4e
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/hardware.h
@@ -0,0 +1,66 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/hardware.h
+ *
+ *  Copyright (C) 1996-2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This file contains the hardware definitions of the EBSA-110.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * The EBSA110 has a weird "ISA IO" region:
+ *
+ * Region 0 (addr = 0xf0000000 + io << 2)
+ * --------------------------------------------------------
+ * Physical region      IO region
+ * f0000fe0 - f0000ffc  3f8 - 3ff  ttyS0
+ * f0000e60 - f0000e64  398 - 399
+ * f0000de0 - f0000dfc  378 - 37f  lp0
+ * f0000be0 - f0000bfc  2f8 - 2ff  ttyS1
+ *
+ * Region 1 (addr = 0xf0000000 + (io & ~1) << 1 + (io & 1))
+ * --------------------------------------------------------
+ * Physical region      IO region
+ * f00014f1             a79        pnp write data
+ * f00007c0 - f00007c1  3e0 - 3e1  pcmcia
+ * f00004f1             279        pnp address
+ * f0000440 - f000046c  220 - 236  eth0
+ * f0000405             203        pnp read data
+ */
+
+#define ISAMEM_PHYS             0xe0000000
+#define ISAMEM_SIZE             0x10000000
+
+#define ISAIO_PHYS              0xf0000000
+#define ISAIO_SIZE              PGDIR_SIZE
+
+#define TRICK0_PHYS             0xf2000000
+#define TRICK1_PHYS             0xf2400000
+#define TRICK2_PHYS             0xf2800000
+#define TRICK3_PHYS             0xf2c00000
+#define TRICK4_PHYS             0xf3000000
+#define TRICK5_PHYS             0xf3400000
+#define TRICK6_PHYS             0xf3800000
+#define TRICK7_PHYS             0xf3c00000
+
+#define ISAMEM_BASE             0xe0000000
+#define ISAIO_BASE              0xf0000000
+
+#define PIT_BASE                0xfc000000
+#define SOFT_BASE               0xfd000000
+
+/*
+ * RAM definitions
+ */
+#define FLUSH_BASE_PHYS         0x40000000
+#define FLUSH_BASE              0xdf000000
+
+#define UNCACHEABLE_ADDR        0xff000000      /* IRQ_STAT */
+
+#endif
+
diff --git a/include/asm-arm/arch-ebsa110/io.h b/include/asm-arm/arch-ebsa110/io.h
new file mode 100644
index 000000000000..68e04c0bb3f7
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/io.h
@@ -0,0 +1,78 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/io.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  06-Dec-1997 RMK     Created.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffff
+
+u8 __inb8(unsigned int port);
+void __outb8(u8  val, unsigned int port);
+
+u8 __inb16(unsigned int port);
+void __outb16(u8  val, unsigned int port);
+
+u16 __inw(unsigned int port);
+void __outw(u16 val, unsigned int port);
+
+u32 __inl(unsigned int port);
+void __outl(u32 val, unsigned int port);
+
+u8  __readb(void __iomem *addr);
+u16 __readw(void __iomem *addr);
+u32 __readl(void __iomem *addr);
+
+void __writeb(u8  val, void __iomem *addr);
+void __writew(u16 val, void __iomem *addr);
+void __writel(u32 val, void __iomem *addr);
+
+/*
+ * Argh, someone forgot the IOCS16 line.  We therefore have to handle
+ * the byte stearing by selecting the correct byte IO functions here.
+ */
+#ifdef ISA_SIXTEEN_BIT_PERIPHERAL
+#define inb(p)                  __inb16(p)
+#define outb(v,p)               __outb16(v,p)
+#else
+#define inb(p)                  __inb8(p)
+#define outb(v,p)               __outb8(v,p)
+#endif
+
+#define inw(p)                  __inw(p)
+#define outw(v,p)               __outw(v,p)
+
+#define inl(p)                  __inl(p)
+#define outl(v,p)               __outl(v,p)
+
+#define readb(b)                __readb(b)
+#define readw(b)                __readw(b)
+#define readl(b)                __readl(b)
+#define readb_relaxed(addr)     readb(addr)
+#define readw_relaxed(addr)     readw(addr)
+#define readl_relaxed(addr)     readl(addr)
+
+#define writeb(v,b)             __writeb(v,b)
+#define writew(v,b)             __writew(v,b)
+#define writel(v,b)             __writel(v,b)
+
+#define __arch_ioremap(cookie,sz,c,a)   ((void __iomem *)(cookie))
+#define __arch_iounmap(cookie)          do { } while (0)
+
+extern void insb(unsigned int port, void *buf, int sz);
+extern void insw(unsigned int port, void *buf, int sz);
+extern void insl(unsigned int port, void *buf, int sz);
+
+extern void outsb(unsigned int port, const void *buf, int sz);
+extern void outsw(unsigned int port, const void *buf, int sz);
+extern void outsl(unsigned int port, const void *buf, int sz);
+
+#endif
diff --git a/include/asm-arm/arch-ebsa110/irqs.h b/include/asm-arm/arch-ebsa110/irqs.h
new file mode 100644
index 000000000000..ded9bd9d7b8b
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/irqs.h
@@ -0,0 +1,20 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/irqs.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define NR_IRQS                 8
+
+#define IRQ_EBSA110_PRINTER     0
+#define IRQ_EBSA110_COM1        1
+#define IRQ_EBSA110_COM2        2
+#define IRQ_EBSA110_ETHERNET    3
+#define IRQ_EBSA110_TIMER0      4
+#define IRQ_EBSA110_TIMER1      5
+#define IRQ_EBSA110_PCMCIA      6
+#define IRQ_EBSA110_IMMEDIATE   7
diff --git a/include/asm-arm/arch-ebsa110/memory.h b/include/asm-arm/arch-ebsa110/memory.h
new file mode 100644
index 000000000000..5a9493e12275
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/memory.h
@@ -0,0 +1,31 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/memory.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-Oct-1996 RMK    Created
+ *   31-Dec-1997 RMK    Fixed definitions to reduce warnings
+ *   21-Mar-1999 RMK    Renamed to memory.h
+ *               RMK    Moved TASK_SIZE and PAGE_OFFSET here
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x00000000UL)
+
+/*
+ * We keep this 1:1 so that we don't interfere
+ * with the PCMCIA memory regions
+ */
+#define __virt_to_bus(x)        (x)
+#define __bus_to_virt(x)        (x)
+
+#endif
diff --git a/include/asm-arm/arch-ebsa110/param.h b/include/asm-arm/arch-ebsa110/param.h
new file mode 100644
index 000000000000..be19b08d1c75
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/param.h
@@ -0,0 +1,4 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/param.h
+ */
+#define HZ      200
diff --git a/include/asm-arm/arch-ebsa110/system.h b/include/asm-arm/arch-ebsa110/system.h
new file mode 100644
index 000000000000..d7c8fece0bc5
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/system.h
@@ -0,0 +1,39 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/system.h
+ *
+ *  Copyright (C) 1996-2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+/*
+ * EBSA110 idling methodology:
+ *
+ * We can not execute the "wait for interrupt" instruction since that
+ * will stop our MCLK signal (which provides the clock for the glue
+ * logic, and therefore the timer interrupt).
+ *
+ * Instead, we spin, polling the IRQ_STAT register for the occurrence
+ * of any interrupt with core clock down to the memory clock.
+ */
+static inline void arch_idle(void)
+{
+        const char *irq_stat = (char *)0xff000000;
+
+        /* disable clock switching */
+        asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
+
+        /* wait for an interrupt to occur */
+        while (!*irq_stat);
+
+        /* enable clock switching */
+        asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
+}
+
+#define arch_reset(mode)        cpu_reset(0x80000000)
+
+#endif
diff --git a/include/asm-arm/arch-ebsa110/timex.h b/include/asm-arm/arch-ebsa110/timex.h
new file mode 100644
index 000000000000..1e9ef045092b
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/timex.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/timex.h
+ *
+ *  Copyright (C) 1997, 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  EBSA110 architecture timex specifications
+ */
+
+/*
+ * On the EBSA, the clock ticks at weird rates.
+ * This is therefore not used to calculate the
+ * divisor.
+ */
+#define CLOCK_TICK_RATE         47894000
+
diff --git a/include/asm-arm/arch-ebsa110/uncompress.h b/include/asm-arm/arch-ebsa110/uncompress.h
new file mode 100644
index 000000000000..eee95581a923
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/uncompress.h
@@ -0,0 +1,44 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/uncompress.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        unsigned long tmp1, tmp2;
+        __asm__ __volatile__(
+        "ldrb   %0, [%2], #1\n"
+"       teq     %0, #0\n"
+"       beq     3f\n"
+"1:     strb    %0, [%3]\n"
+"2:     ldrb    %1, [%3, #0x14]\n"
+"       and     %1, %1, #0x60\n"
+"       teq     %1, #0x60\n"
+"       bne     2b\n"
+"       teq     %0, #'\n'\n"
+"       moveq   %0, #'\r'\n"
+"       beq     1b\n"
+"       ldrb    %0, [%2], #1\n"
+"       teq     %0, #0\n"
+"       bne     1b\n"
+"3:     ldrb    %1, [%3, #0x14]\n"
+"       and     %1, %1, #0x60\n"
+"       teq     %1, #0x60\n"
+"       bne     3b"
+        : "=&r" (tmp1), "=&r" (tmp2)
+        : "r" (s), "r" (0xf0000be0) : "cc");
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-ebsa110/vmalloc.h b/include/asm-arm/arch-ebsa110/vmalloc.h
new file mode 100644
index 000000000000..759659be109f
--- /dev/null
+++ b/include/asm-arm/arch-ebsa110/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa110/vmalloc.h
+ *
+ *  Copyright (C) 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (PAGE_OFFSET + 0x1f000000)
diff --git a/include/asm-arm/arch-ebsa285/debug-macro.S b/include/asm-arm/arch-ebsa285/debug-macro.S
new file mode 100644
index 000000000000..237853db6e2f
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/debug-macro.S
@@ -0,0 +1,66 @@
+/* linux/include/asm-arm/arch-ebsa285/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <asm/hardware/dec21285.h>
+
+#ifndef CONFIG_DEBUG_DC21285_PORT
+        /* For NetWinder debugging */
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x7c000000        @ physical
+                movne   \rx, #0xff000000        @ virtual
+                orr     \rx, \rx, #0x000003f8
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldrb    \rd, [\rx, #0x5]
+                and     \rd, \rd, #0x60
+                teq     \rd, #0x60
+                bne     1002b
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldrb    \rd, [\rx, #0x6]
+                tst     \rd, #0x10
+                beq     1001b
+                .endm
+#else
+        /* For EBSA285 debugging */
+                .equ    dc21285_high, ARMCSR_BASE & 0xff000000
+                .equ    dc21285_low,  ARMCSR_BASE & 0x00ffffff
+
+                .macro  addruart,rx
+                mov     \rx, #dc21285_high
+                .if     dc21285_low
+                orr     \rx, \rx, #dc21285_low
+                .endif
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x160]      @ UARTDR
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x178]      @ UARTFLG
+                tst     \rd, #1 << 3
+                bne     1001b
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+#endif
diff --git a/include/asm-arm/arch-ebsa285/dma.h b/include/asm-arm/arch-ebsa285/dma.h
new file mode 100644
index 000000000000..c43046eb8bc7
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/dma.h
@@ -0,0 +1,30 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/dma.h
+ *
+ *  Architecture DMA routines
+ *
+ *  Copyright (C) 1998,1999 Russell King
+ *  Copyright (C) 1998,1999 Philip Blundell
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ */
+#define MAX_DMA_ADDRESS         0xffffffff
+
+/*
+ * The 21285 has two internal DMA channels; we call these 8 and 9.
+ * On CATS hardware we have an additional eight ISA dma channels
+ * numbered 0..7.
+ */
+#define _ISA_DMA(x)             (0+(x))
+#define _DC21285_DMA(x)         (8+(x))
+
+#define MAX_DMA_CHANNELS        10
+
+#define DMA_FLOPPY              _ISA_DMA(2)
+#define DMA_ISA_CASCADE         _ISA_DMA(4)
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ebsa285/entry-macro.S b/include/asm-arm/arch-ebsa285/entry-macro.S
new file mode 100644
index 000000000000..db5729ff6349
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/entry-macro.S
@@ -0,0 +1,105 @@
+/*
+ * include/asm-arm/arch-footbridge/entry-macro.S
+ *
+ * Low-level IRQ helper macros for footbridge-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware/dec21285.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .equ    dc21285_high, ARMCSR_BASE & 0xff000000
+                .equ    dc21285_low, ARMCSR_BASE & 0x00ffffff
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     r4, #dc21285_high
+                .if     dc21285_low
+                orr     r4, r4, #dc21285_low
+                .endif
+                ldr     \irqstat, [r4, #0x180]          @ get interrupts
+
+                mov     \irqnr, #IRQ_SDRAMPARITY
+                tst     \irqstat, #IRQ_MASK_SDRAMPARITY
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_UART_RX
+                movne   \irqnr, #IRQ_CONRX
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_DMA1
+                movne   \irqnr, #IRQ_DMA1
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_DMA2
+                movne   \irqnr, #IRQ_DMA2
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_IN0
+                movne   \irqnr, #IRQ_IN0
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_IN1
+                movne   \irqnr, #IRQ_IN1
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_IN2
+                movne   \irqnr, #IRQ_IN2
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_IN3
+                movne   \irqnr, #IRQ_IN3
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI
+                movne   \irqnr, #IRQ_PCI
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_DOORBELLHOST
+                movne   \irqnr, #IRQ_DOORBELLHOST
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_I2OINPOST
+                movne   \irqnr, #IRQ_I2OINPOST
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_TIMER1
+                movne   \irqnr, #IRQ_TIMER1
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_TIMER2
+                movne   \irqnr, #IRQ_TIMER2
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_TIMER3
+                movne   \irqnr, #IRQ_TIMER3
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_UART_TX
+                movne   \irqnr, #IRQ_CONTX
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI_ABORT
+                movne   \irqnr, #IRQ_PCI_ABORT
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI_SERR
+                movne   \irqnr, #IRQ_PCI_SERR
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_DISCARD_TIMER
+                movne   \irqnr, #IRQ_DISCARD_TIMER
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI_DPERR
+                movne   \irqnr, #IRQ_PCI_DPERR
+                bne     1001f
+
+                tst     \irqstat, #IRQ_MASK_PCI_PERR
+                movne   \irqnr, #IRQ_PCI_PERR
+1001:
+                .endm
+
diff --git a/include/asm-arm/arch-ebsa285/hardware.h b/include/asm-arm/arch-ebsa285/hardware.h
new file mode 100644
index 000000000000..2ef2200f108c
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/hardware.h
@@ -0,0 +1,139 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/hardware.h
+ *
+ *  Copyright (C) 1998-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains the hardware definitions of the EBSA-285.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+#include <asm/arch/memory.h>
+
+#ifdef CONFIG_ARCH_FOOTBRIDGE
+/*   Virtual      Physical      Size
+ * 0xff800000   0x40000000      1MB     X-Bus
+ * 0xff000000   0x7c000000      1MB     PCI I/O space
+ * 0xfe000000   0x42000000      1MB     CSR
+ * 0xfd000000   0x78000000      1MB     Outbound write flush (not supported)
+ * 0xfc000000   0x79000000      1MB     PCI IACK/special space
+ * 0xfb000000   0x7a000000      16MB    PCI Config type 1
+ * 0xfa000000   0x7b000000      16MB    PCI Config type 0
+ * 0xf9000000   0x50000000      1MB     Cache flush
+ * 0xf0000000   0x80000000      16MB    ISA memory
+ */
+#define XBUS_SIZE               0x00100000
+#define XBUS_BASE               0xff800000
+
+#define PCIO_SIZE               0x00100000
+#define PCIO_BASE               0xff000000
+
+#define ARMCSR_SIZE             0x00100000
+#define ARMCSR_BASE             0xfe000000
+
+#define WFLUSH_SIZE             0x00100000
+#define WFLUSH_BASE             0xfd000000
+
+#define PCIIACK_SIZE            0x00100000
+#define PCIIACK_BASE            0xfc000000
+
+#define PCICFG1_SIZE            0x01000000
+#define PCICFG1_BASE            0xfb000000
+
+#define PCICFG0_SIZE            0x01000000
+#define PCICFG0_BASE            0xfa000000
+
+#define FLUSH_SIZE              0x00100000
+#define FLUSH_BASE              0xf9000000
+
+#define PCIMEM_SIZE             0x01000000
+#define PCIMEM_BASE             0xf0000000
+
+#elif defined(CONFIG_ARCH_CO285)
+/*
+ * This is the COEBSA285 cut-down mapping
+ */
+#define PCIMEM_SIZE             0x80000000
+#define PCIMEM_BASE             0x80000000
+
+#define FLUSH_SIZE              0x00100000
+#define FLUSH_BASE              0x7e000000
+
+#define WFLUSH_SIZE             0x01000000
+#define WFLUSH_BASE             0x7d000000
+
+#define ARMCSR_SIZE             0x00100000
+#define ARMCSR_BASE             0x7cf00000
+
+#define XBUS_SIZE               0x00020000
+#define XBUS_BASE               0x7cee0000
+
+#define PCIO_SIZE               0x00010000
+#define PCIO_BASE               0x7ced0000
+
+#else
+
+#error "Undefined footbridge architecture"
+
+#endif
+
+#define XBUS_LEDS               ((volatile unsigned char *)(XBUS_BASE + 0x12000))
+#define XBUS_LED_AMBER          (1 << 0)
+#define XBUS_LED_GREEN          (1 << 1)
+#define XBUS_LED_RED            (1 << 2)
+#define XBUS_LED_TOGGLE         (1 << 8)
+
+#define XBUS_SWITCH             ((volatile unsigned char *)(XBUS_BASE + 0x12000))
+#define XBUS_SWITCH_SWITCH      ((*XBUS_SWITCH) & 15)
+#define XBUS_SWITCH_J17_13      ((*XBUS_SWITCH) & (1 << 4))
+#define XBUS_SWITCH_J17_11      ((*XBUS_SWITCH) & (1 << 5))
+#define XBUS_SWITCH_J17_9       ((*XBUS_SWITCH) & (1 << 6))
+
+#define FLUSH_BASE_PHYS         0x50000000
+#define UNCACHEABLE_ADDR        (ARMCSR_BASE + 0x108)
+
+
+/* PIC irq control */
+#define PIC_LO                  0x20
+#define PIC_MASK_LO             0x21
+#define PIC_HI                  0xA0
+#define PIC_MASK_HI             0xA1
+
+/* GPIO pins */
+#define GPIO_CCLK               0x800
+#define GPIO_DSCLK              0x400
+#define GPIO_E2CLK              0x200
+#define GPIO_IOLOAD             0x100
+#define GPIO_RED_LED            0x080
+#define GPIO_WDTIMER            0x040
+#define GPIO_DATA               0x020
+#define GPIO_IOCLK              0x010
+#define GPIO_DONE               0x008
+#define GPIO_FAN                0x004
+#define GPIO_GREEN_LED          0x002
+#define GPIO_RESET              0x001
+
+/* CPLD pins */
+#define CPLD_DS_ENABLE          8
+#define CPLD_7111_DISABLE       4
+#define CPLD_UNMUTE             2
+#define CPLD_FLASH_WR_ENABLE    1
+
+#ifndef __ASSEMBLY__
+extern void gpio_modify_op(int mask, int set);
+extern void gpio_modify_io(int mask, int in);
+extern int  gpio_read(void);
+extern void cpld_modify(int mask, int set);
+#endif
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x1000
+#define PCIBIOS_MIN_MEM         0x81000000
+
+#endif
diff --git a/include/asm-arm/arch-ebsa285/io.h b/include/asm-arm/arch-ebsa285/io.h
new file mode 100644
index 000000000000..70576b17f922
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/io.h
@@ -0,0 +1,45 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/io.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Modifications:
+ *   06-12-1997 RMK     Created.
+ *   07-04-1999 RMK     Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffff
+
+/*
+ * Translation of various region addresses to virtual addresses
+ */
+#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+#if 1
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            ((a) + PCIMEM_BASE)
+#else
+
+static inline void __iomem *___mem_pci(void __iomem *p)
+{
+        unsigned long a = (unsigned long)p;
+        BUG_ON(a <= 0xc0000000 || a >= 0xe0000000);
+        return p;
+}
+
+static inline void __iomem *___mem_isa(void __iomem *p)
+{
+        unsigned long a = (unsigned long)p;
+        BUG_ON(a >= 16*1048576);
+        return p + PCIMEM_BASE;
+}
+#define __mem_pci(a)            ___mem_pci(a)
+#define __mem_isa(a)            ___mem_isa(a)
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-ebsa285/irqs.h b/include/asm-arm/arch-ebsa285/irqs.h
new file mode 100644
index 000000000000..3e766f1cecf1
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/irqs.h
@@ -0,0 +1,98 @@
+/*
+ * linux/include/asm-arm/arch-ebsa285/irqs.h
+ *
+ * Copyright (C) 1998 Russell King
+ * Copyright (C) 1998 Phil Blundell
+ *
+ * Changelog:
+ *  20-Jan-1998 RMK     Started merge of EBSA286, CATS and NetWinder
+ *  01-Feb-1999 PJB     ISA IRQs start at 0 not 16
+ */
+#include <asm/mach-types.h>
+
+#define NR_IRQS                 36
+#define NR_DC21285_IRQS         16
+
+#define _ISA_IRQ(x)             (0 + (x))
+#define _ISA_INR(x)             ((x) - 0)
+#define _DC21285_IRQ(x)         (16 + (x))
+#define _DC21285_INR(x)         ((x) - 16)
+
+/*
+ * This is a list of all interrupts that the 21285
+ * can generate and we handle.
+ */
+#define IRQ_CONRX               _DC21285_IRQ(0)
+#define IRQ_CONTX               _DC21285_IRQ(1)
+#define IRQ_TIMER1              _DC21285_IRQ(2)
+#define IRQ_TIMER2              _DC21285_IRQ(3)
+#define IRQ_TIMER3              _DC21285_IRQ(4)
+#define IRQ_IN0                 _DC21285_IRQ(5)
+#define IRQ_IN1                 _DC21285_IRQ(6)
+#define IRQ_IN2                 _DC21285_IRQ(7)
+#define IRQ_IN3                 _DC21285_IRQ(8)
+#define IRQ_DOORBELLHOST        _DC21285_IRQ(9)
+#define IRQ_DMA1                _DC21285_IRQ(10)
+#define IRQ_DMA2                _DC21285_IRQ(11)
+#define IRQ_PCI                 _DC21285_IRQ(12)
+#define IRQ_SDRAMPARITY         _DC21285_IRQ(13)
+#define IRQ_I2OINPOST           _DC21285_IRQ(14)
+#define IRQ_PCI_ABORT           _DC21285_IRQ(15)
+#define IRQ_PCI_SERR            _DC21285_IRQ(16)
+#define IRQ_DISCARD_TIMER       _DC21285_IRQ(17)
+#define IRQ_PCI_DPERR           _DC21285_IRQ(18)
+#define IRQ_PCI_PERR            _DC21285_IRQ(19)
+
+#define IRQ_ISA_TIMER           _ISA_IRQ(0)
+#define IRQ_ISA_KEYBOARD        _ISA_IRQ(1)
+#define IRQ_ISA_CASCADE         _ISA_IRQ(2)
+#define IRQ_ISA_UART2           _ISA_IRQ(3)
+#define IRQ_ISA_UART            _ISA_IRQ(4)
+#define IRQ_ISA_FLOPPY          _ISA_IRQ(6)
+#define IRQ_ISA_PRINTER         _ISA_IRQ(7)
+#define IRQ_ISA_RTC_ALARM       _ISA_IRQ(8)
+#define IRQ_ISA_2               _ISA_IRQ(9)
+#define IRQ_ISA_PS2MOUSE        _ISA_IRQ(12)
+#define IRQ_ISA_HARDDISK1       _ISA_IRQ(14)
+#define IRQ_ISA_HARDDISK2       _ISA_IRQ(15)
+
+#define IRQ_MASK_UART_RX        (1 << 2)
+#define IRQ_MASK_UART_TX        (1 << 3)
+#define IRQ_MASK_TIMER1         (1 << 4)
+#define IRQ_MASK_TIMER2         (1 << 5)
+#define IRQ_MASK_TIMER3         (1 << 6)
+#define IRQ_MASK_IN0            (1 << 8)
+#define IRQ_MASK_IN1            (1 << 9)
+#define IRQ_MASK_IN2            (1 << 10)
+#define IRQ_MASK_IN3            (1 << 11)
+#define IRQ_MASK_DOORBELLHOST   (1 << 15)
+#define IRQ_MASK_DMA1           (1 << 16)
+#define IRQ_MASK_DMA2           (1 << 17)
+#define IRQ_MASK_PCI            (1 << 18)
+#define IRQ_MASK_SDRAMPARITY    (1 << 24)
+#define IRQ_MASK_I2OINPOST      (1 << 25)
+#define IRQ_MASK_PCI_ABORT      ((1 << 29) | (1 << 30))
+#define IRQ_MASK_PCI_SERR       (1 << 23)
+#define IRQ_MASK_DISCARD_TIMER  (1 << 27)
+#define IRQ_MASK_PCI_DPERR      (1 << 28)
+#define IRQ_MASK_PCI_PERR       (1 << 31)
+
+/*
+ * Netwinder interrupt allocations
+ */
+#define IRQ_NETWINDER_ETHER10   IRQ_IN0
+#define IRQ_NETWINDER_ETHER100  IRQ_IN1
+#define IRQ_NETWINDER_VIDCOMP   IRQ_IN2
+#define IRQ_NETWINDER_PS2MOUSE  _ISA_IRQ(5)
+#define IRQ_NETWINDER_IR        _ISA_IRQ(6)
+#define IRQ_NETWINDER_BUTTON    _ISA_IRQ(10)
+#define IRQ_NETWINDER_VGA       _ISA_IRQ(11)
+#define IRQ_NETWINDER_SOUND     _ISA_IRQ(12)
+
+#undef RTC_IRQ
+#define RTC_IRQ         IRQ_ISA_RTC_ALARM
+#define I8042_KBD_IRQ   IRQ_ISA_KEYBOARD
+#define I8042_AUX_IRQ   (machine_is_netwinder() ? IRQ_NETWINDER_PS2MOUSE : IRQ_ISA_PS2MOUSE)
+#define IRQ_FLOPPYDISK  IRQ_ISA_FLOPPY
+
+#define irq_canonicalize(_i)    (((_i) == IRQ_ISA_CASCADE) ? IRQ_ISA_2 : _i)
diff --git a/include/asm-arm/arch-ebsa285/memory.h b/include/asm-arm/arch-ebsa285/memory.h
new file mode 100644
index 000000000000..d0466f9987d3
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/memory.h
@@ -0,0 +1,75 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/memory.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-Oct-1996 RMK    Created
+ *   31-Dec-1997 RMK    Fixed definitions to reduce warnings.
+ *   17-May-1998 DAG    Added __virt_to_bus and __bus_to_virt functions.
+ *   21-Nov-1998 RMK    Changed __virt_to_bus and __bus_to_virt to macros.
+ *   21-Mar-1999 RMK    Added PAGE_OFFSET for co285 architecture.
+ *                      Renamed to memory.h
+ *                      Moved PAGE_OFFSET and TASK_SIZE here
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <linux/config.h>
+
+#if defined(CONFIG_FOOTBRIDGE_ADDIN)
+/*
+ * If we may be using add-in footbridge mode, then we must
+ * use the out-of-line translation that makes use of the
+ * PCI BAR
+ */
+#ifndef __ASSEMBLY__
+extern unsigned long __virt_to_bus(unsigned long);
+extern unsigned long __bus_to_virt(unsigned long);
+#endif
+
+#elif defined(CONFIG_FOOTBRIDGE_HOST)
+
+#define __virt_to_bus(x)        ((x) - 0xe0000000)
+#define __bus_to_virt(x)        ((x) + 0xe0000000)
+
+#else
+
+#error "Undefined footbridge mode"
+
+#endif
+
+#if defined(CONFIG_ARCH_FOOTBRIDGE)
+
+/* Task size and page offset at 3GB */
+#define TASK_SIZE               (0xbf000000UL)
+#define PAGE_OFFSET             (0xc0000000UL)
+
+#elif defined(CONFIG_ARCH_CO285)
+
+/* Task size and page offset at 1.5GB */
+#define TASK_SIZE               (0x5f000000UL)
+#define PAGE_OFFSET             (0x60000000UL)
+
+#else
+
+#error "Undefined footbridge architecture"
+
+#endif
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             (0x00000000UL)
+
+/*
+ * This decides where the kernel will search for a free chunk of vm
+ * space during mmap's.
+ */
+#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
+
+#endif
diff --git a/include/asm-arm/arch-ebsa285/param.h b/include/asm-arm/arch-ebsa285/param.h
new file mode 100644
index 000000000000..3827103b27a0
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/param.h
@@ -0,0 +1,3 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/param.h
+ */
diff --git a/include/asm-arm/arch-ebsa285/system.h b/include/asm-arm/arch-ebsa285/system.h
new file mode 100644
index 000000000000..bf91c695c4b5
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/system.h
@@ -0,0 +1,69 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/system.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/hardware/dec21285.h>
+#include <asm/io.h>
+#include <asm/hardware.h>
+#include <asm/leds.h>
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        if (mode == 's') {
+                /*
+                 * Jump into the ROM
+                 */
+                cpu_reset(0x41000000);
+        } else {
+                if (machine_is_netwinder()) {
+                        /* open up the SuperIO chip
+                         */
+                        outb(0x87, 0x370);
+                        outb(0x87, 0x370);
+
+                        /* aux function group 1 (logical device 7)
+                         */
+                        outb(0x07, 0x370);
+                        outb(0x07, 0x371);
+
+                        /* set GP16 for WD-TIMER output
+                         */
+                        outb(0xe6, 0x370);
+                        outb(0x00, 0x371);
+
+                        /* set a RED LED and toggle WD_TIMER for rebooting
+                         */
+                        outb(0xc4, 0x338);
+                } else {
+                        /* 
+                         * Force the watchdog to do a CPU reset.
+                         *
+                         * After making sure that the watchdog is disabled
+                         * (so we can change the timer registers) we first
+                         * enable the timer to autoreload itself.  Next, the
+                         * timer interval is set really short and any
+                         * current interrupt request is cleared (so we can
+                         * see an edge transition).  Finally, TIMER4 is
+                         * enabled as the watchdog.
+                         */
+                        *CSR_SA110_CNTL &= ~(1 << 13);
+                        *CSR_TIMER4_CNTL = TIMER_CNTL_ENABLE |
+                                           TIMER_CNTL_AUTORELOAD |
+                                           TIMER_CNTL_DIV16;
+                        *CSR_TIMER4_LOAD = 0x2;
+                        *CSR_TIMER4_CLR  = 0;
+                        *CSR_SA110_CNTL |= (1 << 13);
+                }
+        }
+}
diff --git a/include/asm-arm/arch-ebsa285/timex.h b/include/asm-arm/arch-ebsa285/timex.h
new file mode 100644
index 000000000000..df60b3812d96
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/timex.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/timex.h
+ *
+ *  Copyright (C) 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  EBSA285 architecture timex specifications
+ */
+
+/*
+ * We assume a constant here; this satisfies the maths in linux/timex.h
+ * and linux/time.h.  CLOCK_TICK_RATE is actually system dependent, but
+ * this must be a constant.
+ */
+#define CLOCK_TICK_RATE         (50000000/16)
diff --git a/include/asm-arm/arch-ebsa285/uncompress.h b/include/asm-arm/arch-ebsa285/uncompress.h
new file mode 100644
index 000000000000..c2fd84e2d90e
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/uncompress.h
@@ -0,0 +1,46 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/uncompress.h
+ *
+ *  Copyright (C) 1996-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/mach-types.h>
+
+/*
+ * Note! This could cause problems on the NetWinder
+ */
+#define DC21285_BASE ((volatile unsigned int *)0x42000160)
+#define SER0_BASE    ((volatile unsigned char *)0x7c0003f8)
+
+static __inline__ void putc(char c)
+{
+        if (machine_is_netwinder()) {
+                while ((SER0_BASE[5] & 0x60) != 0x60);
+                SER0_BASE[0] = c;
+        } else {
+                while (DC21285_BASE[6] & 8);
+                DC21285_BASE[0] = c;
+        }
+}
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                putc(*s);
+                if (*s == '\n')
+                        putc('\r');
+                s++;
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-ebsa285/vmalloc.h b/include/asm-arm/arch-ebsa285/vmalloc.h
new file mode 100644
index 000000000000..def705a3c209
--- /dev/null
+++ b/include/asm-arm/arch-ebsa285/vmalloc.h
@@ -0,0 +1,26 @@
+/*
+ *  linux/include/asm-arm/arch-ebsa285/vmalloc.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+
+#ifdef CONFIG_ARCH_FOOTBRIDGE
+#define VMALLOC_END       (PAGE_OFFSET + 0x30000000)
+#else
+#define VMALLOC_END       (PAGE_OFFSET + 0x20000000)
+#endif
diff --git a/include/asm-arm/arch-epxa10db/debug-macro.S b/include/asm-arm/arch-epxa10db/debug-macro.S
new file mode 100644
index 000000000000..1d11c51f498f
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/debug-macro.S
@@ -0,0 +1,41 @@
+/* linux/include/asm-arm/arch-epxa10db/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <asm/arch/excalibur.h>
+#define UART00_TYPE
+#include <asm/arch/uart00.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                ldr     \rx, =EXC_UART00_BASE   @ physical base address
+                orrne   \rx, \rx, #0xff000000   @ virtual base
+                orrne   \rx, \rx, #0x00f00000
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #UART_TD(0)]
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #UART_TSR(0)]
+                and     \rd, \rd,  #UART_TSR_TX_LEVEL_MSK
+                cmp     \rd, #15
+                beq     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #UART_TSR(0)]
+                ands    \rd, \rd,  #UART_TSR_TX_LEVEL_MSK
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-epxa10db/dma.h b/include/asm-arm/arch-epxa10db/dma.h
new file mode 100644
index 000000000000..5d97734d1077
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/dma.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/include/asm-arm/arch-camelot/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+
+#define MAX_DMA_CHANNELS        0
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/include/asm-arm/arch-epxa10db/entry-macro.S b/include/asm-arm/arch-epxa10db/entry-macro.S
new file mode 100644
index 000000000000..de6ae08334e2
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/entry-macro.S
@@ -0,0 +1,25 @@
+/*
+ * include/asm-arm/arch-epxa10db/entry-macro.S
+ *
+ * Low-level IRQ helper macros for epxa10db platform
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/arch/platform.h>
+#undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */
+#include <asm/arch/int_ctrl00.h>
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                ldr     \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE))
+                ldr     \irqnr,[\irqstat]
+                cmp     \irqnr,#0
+                subne   \irqnr,\irqnr,#1
+
+                .endm
+
diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h
new file mode 100644
index 000000000000..b737b8aabe2f
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/ether00.h
@@ -0,0 +1,482 @@
+#ifndef __ETHER00_H
+#define __ETHER00_H
+
+
+
+/*
+ * Register definitions for the Ethernet MAC
+ */
+
+/*
+ * Copyright (c) Altera Corporation 2000.
+ * All rights reserved.
+ */
+
+/*
+*       Structures for the DMA controller
+*/
+typedef struct fda_desc
+        {
+        struct fda_desc *       FDNext;
+        long                            FDSystem;
+        long                            FDStat;
+        short                           FDLength;
+        short                           FDCtl;
+        }FDA_DESC;
+
+typedef struct buf_desc
+        {
+        char *  BuffData;
+        short   BuffLength;
+        char    BDStat;
+        char    BDCtl;
+        }BUF_DESC;
+
+/*
+*       Control masks for the DMA controller
+*/
+#define FDCTL_BDCOUNT_MSK                                               (0x1F)
+#define FDCTL_BDCOUNT_OFST                                              (0)
+#define FDCTL_FRMOPT_MSK                                                (0x7C00)
+#define FDCTL_FRMOPT_OFST                                               (10)
+#define FDCTL_COWNSFD_MSK                                               (0x8000)
+#define FDCTL_COWNSFD_OFST                                              (15)
+
+#define BDCTL_RXBDSEQN_MSK                                              (0x7F)
+#define BDCTL_RXBDSEQN_OFST                                             (0)
+#define BDCTL_COWNSBD_MSK                                               (0x80)
+#define BDCTL_COWNSBD_OFST                                              (7)
+
+#define FDNEXT_EOL_MSK                                                  (0x1)
+#define FDNEXT_EOL_OFST                                                 (0)
+#define FDNEXT_EOL_POINTER_MSK                                  (0xFFFFFFF0)
+#define FDNEXT_EOL_POINTER_OFST                                 (4)
+
+#define ETHER_ARC_SIZE         (21)
+
+/*
+*       Register definitions and masks
+*/
+#define ETHER_DMA_CTL(base)                                                     (ETHER00_TYPE (base + 0x100))
+#define ETHER_DMA_CTL_DMBURST_OFST                              (2)
+#define ETHER_DMA_CTL_DMBURST_MSK                               (0x1FC)
+#define ETHER_DMA_CTL_POWRMGMNT_OFST                    (11)
+#define ETHER_DMA_CTL_POWRMGMNT_MSK                             (0x1000)
+#define ETHER_DMA_CTL_TXBIGE_OFST                               (14)
+#define ETHER_DMA_CTL_TXBIGE_MSK                                (0x4000)
+#define ETHER_DMA_CTL_RXBIGE_OFST                               (15)
+#define ETHER_DMA_CTL_RXBIGE_MSK                                (0x8000)
+#define ETHER_DMA_CTL_TXWAKEUP_OFST                             (16)
+#define ETHER_DMA_CTL_TXWAKEUP_MSK                              (0x10000)
+#define ETHER_DMA_CTL_SWINTREQ_OFST                             (17)
+#define ETHER_DMA_CTL_SWINTREQ_MSK                              (0x20000)
+#define ETHER_DMA_CTL_INTMASK_OFST                              (18)
+#define ETHER_DMA_CTL_INTMASK_MSK                               (0x40000)
+#define ETHER_DMA_CTL_M66ENSTAT_OFST                    (19)
+#define ETHER_DMA_CTL_M66ENSTAT_MSK                             (0x80000)
+#define ETHER_DMA_CTL_RMTXINIT_OFST                             (20)
+#define ETHER_DMA_CTL_RMTXINIT_MSK                              (0x100000)
+#define ETHER_DMA_CTL_RMRXINIT_OFST                             (21)
+#define ETHER_DMA_CTL_RMRXINIT_MSK                              (0x200000)
+#define ETHER_DMA_CTL_RXALIGN_OFST                              (22)
+#define ETHER_DMA_CTL_RXALIGN_MSK                               (0xC00000)
+#define ETHER_DMA_CTL_RMSWRQ_OFST                               (24)
+#define ETHER_DMA_CTL_RMSWRQ_MSK                                (0x1000000)
+#define ETHER_DMA_CTL_RMEMBANK_OFST                             (25)
+#define ETHER_DMA_CTL_RMEMBANK_MSK                              (0x2000000)
+
+#define ETHER_TXFRMPTR(base)                                                    (ETHER00_TYPE (base + 0x104))
+
+#define ETHER_TXTHRSH(base)                                                     (ETHER00_TYPE (base + 0x308))
+
+#define ETHER_TXPOLLCTR(base)                                                   (ETHER00_TYPE (base + 0x30c))
+
+#define ETHER_BLFRMPTR(base)                                                    (ETHER00_TYPE (base + 0x110))
+#define ETHER_BLFFRMPTR_EOL_OFST                                (0)
+#define ETHER_BLFFRMPTR_EOL_MSK                                 (0x1)
+#define ETHER_BLFFRMPTR_ADDRESS_OFST                    (4)
+#define ETHER_BLFFRMPTR_ADDRESS_MSK                             (0xFFFFFFF0)
+
+#define ETHER_RXFRAGSIZE(base)                                          (ETHER00_TYPE (base + 0x114))
+#define ETHER_RXFRAGSIZE_MINFRAG_OFST                   (2)
+#define ETHER_RXFRAGSIZE_MINFRAG_MSK                    (0xFFC)
+#define ETHER_RXFRAGSIZE_ENPACK_OFST                    (15)
+#define ETHER_RXFRAGSIZE_ENPACK_MSK                             (0x8000)
+
+#define ETHER_INT_EN(base)                                                      (ETHER00_TYPE (base + 0x118))
+#define ETHER_INT_EN_FDAEXEN_OFST                               (0)
+#define ETHER_INT_EN_FDAEXEN_MSK                                (0x1)
+#define ETHER_INT_EN_BLEXEN_OFST                                (1)
+#define ETHER_INT_EN_BLEXN_MSK                                  (0x2)
+#define ETHER_INT_EN_STARGABTEN_OFST                    (2)
+#define ETHER_INT_EN_STARGABTEN_MSK                             (0x4)
+#define ETHER_INT_EN_RTARGABTEN_OFST                    (3)
+#define ETHER_INT_EN_RTARGABTEN_MSK                             (0x8)
+#define ETHER_INT_EN_RMASABTEN_OFST                             (4)
+#define ETHER_INT_EN_RMASABTEN_MSK                              (0x10)
+#define ETHER_INT_EN_SSYSERREN_OFST                             (5)
+#define ETHER_INT_EN_SSYSERREN_MSK                              (0x20)
+#define ETHER_INT_EN_DPARERREN_OFST                             (6)
+#define ETHER_INT_EN_DPARERREN_MSK                              (0x40)
+#define ETHER_INT_EN_EARNOTEN_OFST                              (7)
+#define ETHER_INT_EN_EARNOTEN_MSK                               (0x80)
+#define ETHER_INT_EN_DPARDEN_OFST                               (8)
+#define ETHER_INT_EN_DPARDEN_MSK                                (0x100)
+#define ETHER_INT_EN_DMPARERREN_OFST                    (9)
+#define ETHER_INT_EN_DMPARERREN_MSK                             (0x200)
+#define ETHER_INT_EN_TXCTLCMPEN_OFST                    (10)
+#define ETHER_INT_EN_TXCTLCMPEN_MSK                             (0x400)
+#define ETHER_INT_EN_NRABTEN_OFST                               (11)
+#define ETHER_INT_EN_NRABTEN_MSK                                (0x800)
+
+#define ETHER_FDA_BAS(base)                                                     (ETHER00_TYPE (base + 0x11C))
+#define ETHER_FDA_BAS_ADDRESS_OFST                              (4)
+#define ETHER_FDA_BAS_ADDRESS_MSK                               (0xFFFFFFF0)
+
+#define ETHER_FDA_LIM(base)                                                     (ETHER00_TYPE (base + 0x120))
+#define ETHER_FDA_LIM_COUNT_OFST                                (4)
+#define ETHER_FDA_LIM_COUNT_MSK                                 (0xFFF0)
+
+#define ETHER_INT_SRC(base)                                                     (ETHER00_TYPE (base + 0x124))
+#define ETHER_INT_SRC_INTMACTX_OFST                             (0)
+#define ETHER_INT_SRC_INTMACTX_MSK                              (0x1)
+#define ETHER_INT_SRC_INTMACRX_OFST                             (1)
+#define ETHER_INT_SRC_INTMACRX_MSK                              (0x2)
+#define ETHER_INT_SRC_INTSBUS_OFST                              (2)
+#define ETHER_INT_SRC_INTSBUS_MSK                               (0x4)
+#define ETHER_INT_SRC_INTFDAEX_OFST                             (3)
+#define ETHER_INT_SRC_INTFDAEX_MSK                              (0x8)
+#define ETHER_INT_SRC_INTBLEX_OFST                              (4)
+#define ETHER_INT_SRC_INTBLEX_MSK                               (0x10)
+#define ETHER_INT_SRC_SWINT_OFST                                (5)
+#define ETHER_INT_SRC_SWINT_MSK                                 (0x20)
+#define ETHER_INT_SRC_INTEARNOT_OFST                    (6)
+#define ETHER_INT_SRC_INTEARNOT_MSK                             (0x40)
+#define ETHER_INT_SRC_DMPARERR_OFST                             (7)
+#define ETHER_INT_SRC_DMPARERR_MSK                              (0x80)
+#define ETHER_INT_SRC_INTEXBD_OFST                              (8)
+#define ETHER_INT_SRC_INTEXBD_MSK                               (0x100)
+#define ETHER_INT_SRC_INTTXCTLCMP_OFST                  (9)
+#define ETHER_INT_SRC_INTTXCTLCMP_MSK                   (0x200)
+#define ETHER_INT_SRC_INTNRABT_OFST                             (10)
+#define ETHER_INT_SRC_INTNRABT_MSK                              (0x400)
+#define ETHER_INT_SRC_FDAEX_OFST                                (11)
+#define ETHER_INT_SRC_FDAEX_MSK                                 (0x800)
+#define ETHER_INT_SRC_BLEX_OFST                                 (12)
+#define ETHER_INT_SRC_BLEX_MSK                                  (0x1000)
+#define ETHER_INT_SRC_DMPARERRSTAT_OFST                 (13)
+#define ETHER_INT_SRC_DMPARERRSTAT_MSK                  (0x2000)
+#define ETHER_INT_SRC_NRABT_OFST                                (14)
+#define ETHER_INT_SRC_NRABT_MSK                                 (0x4000)
+#define ETHER_INT_SRC_INTLINK_OFST                              (15)
+#define ETHER_INT_SRC_INTLINK_MSK                               (0x8000)
+#define ETHER_INT_SRC_INTEXDEFER_OFST                   (16)
+#define ETHER_INT_SRC_INTEXDEFER_MSK                    (0x10000)
+#define ETHER_INT_SRC_INTRMON_OFST                              (17)
+#define ETHER_INT_SRC_INTRMON_MSK                               (0x20000)
+#define ETHER_INT_SRC_IRQ_MSK                                   (0x83FF)
+
+#define ETHER_PAUSECNT(base)                                                    (ETHER00_TYPE (base + 0x40))
+#define ETHER_PAUSECNT_COUNT_OFST                               (0)
+#define ETHER_PAUSECNT_COUNT_MSK                                (0xFFFF)
+
+#define ETHER_REMPAUCNT(base)                                                   (ETHER00_TYPE (base + 0x44))
+#define ETHER_REMPAUCNT_COUNT_OFST                              (0)
+#define ETHER_REMPAUCNT_COUNT_MSK                               (0xFFFF)
+
+#define ETHER_TXCONFRMSTAT(base)                                                (ETHER00_TYPE (base + 0x348))
+#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST   (0)
+#define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK    (0x3FFFFF)
+
+#define ETHER_MAC_CTL(base)                                                     (ETHER00_TYPE (base + 0))
+#define ETHER_MAC_CTL_HALTREQ_OFST                              (0)
+#define ETHER_MAC_CTL_HALTREQ_MSK                               (0x1)
+#define ETHER_MAC_CTL_HALTIMM_OFST                              (1)
+#define ETHER_MAC_CTL_HALTIMM_MSK                               (0x2)
+#define ETHER_MAC_CTL_RESET_OFST                                (2)
+#define ETHER_MAC_CTL_RESET_MSK                                 (0x4)
+#define ETHER_MAC_CTL_FULLDUP_OFST                              (3)
+#define ETHER_MAC_CTL_FULLDUP_MSK                               (0x8)
+#define ETHER_MAC_CTL_MACLOOP_OFST                              (4)
+#define ETHER_MAC_CTL_MACLOOP_MSK                               (0x10)
+#define ETHER_MAC_CTL_CONN_OFST                                 (5)
+#define ETHER_MAC_CTL_CONN_MSK                                  (0x60)
+#define ETHER_MAC_CTL_LOOP10_OFST                               (7)
+#define ETHER_MAC_CTL_LOOP10_MSK                                (0x80)
+#define ETHER_MAC_CTL_LNKCHG_OFST                               (8)
+#define ETHER_MAC_CTL_LNKCHG_MSK                                (0x100)
+#define ETHER_MAC_CTL_MISSROLL_OFST                             (10)
+#define ETHER_MAC_CTL_MISSROLL_MSK                              (0x400)
+#define ETHER_MAC_CTL_ENMISSROLL_OFST                   (13)
+#define ETHER_MAC_CTL_ENMISSROLL_MSK                    (0x2000)
+#define ETHER_MAC_CTL_LINK10_OFST                               (15)
+#define ETHER_MAC_CTL_LINK10_MSK                                (0x8000)
+
+#define ETHER_ARC_CTL(base)                                                     (ETHER00_TYPE (base + 0x4))
+#define ETHER_ARC_CTL_STATIONACC_OFST                   (0)
+#define ETHER_ARC_CTL_STATIONACC_MSK                    (0x1)
+#define ETHER_ARC_CTL_GROUPACC_OFST                             (1)
+#define ETHER_ARC_CTL_GROUPACC_MSK                              (0x2)
+#define ETHER_ARC_CTL_BROADACC_OFST                             (2)
+#define ETHER_ARC_CTL_BROADACC_MSK                              (0x4)
+#define ETHER_ARC_CTL_NEGARC_OFST                               (3)
+#define ETHER_ARC_CTL_NEGARC_MSK                                (0x8)
+#define ETHER_ARC_CTL_COMPEN_OFST                               (4)
+#define ETHER_ARC_CTL_COMPEN_MSK                                (0x10)
+
+#define ETHER_TX_CTL(base)                                                      (ETHER00_TYPE (base + 0x8))
+#define ETHER_TX_CTL_TXEN_OFST                                  (0)
+#define ETHER_TX_CTL_TXEN_MSK                                   (0x1)
+#define ETHER_TX_CTL_TXHALT_OFST                                (1)
+#define ETHER_TX_CTL_TXHALT_MSK                                 (0x2)
+#define ETHER_TX_CTL_NOPAD_OFST                                 (2)
+#define ETHER_TX_CTL_NOPAD_MSK                                  (0x4)
+#define ETHER_TX_CTL_NOCRC_OFST                                 (3)
+#define ETHER_TX_CTL_NOCRC_MSK                                  (0x8)
+#define ETHER_TX_CTL_FBACK_OFST                                 (4)
+#define ETHER_TX_CTL_FBACK_MSK                                  (0x10)
+#define ETHER_TX_CTL_NOEXDEF_OFST                               (5)
+#define ETHER_TX_CTL_NOEXDEF_MSK                                (0x20)
+#define ETHER_TX_CTL_SDPAUSE_OFST                               (6)
+#define ETHER_TX_CTL_SDPAUSE_MSK                                (0x40)
+#define ETHER_TX_CTL_MII10_OFST                                 (7)
+#define ETHER_TX_CTL_MII10_MSK                                  (0x80)
+#define ETHER_TX_CTL_ENUNDER_OFST                               (8)
+#define ETHER_TX_CTL_ENUNDER_MSK                                (0x100)
+#define ETHER_TX_CTL_ENEXDEFER_OFST                             (9)
+#define ETHER_TX_CTL_ENEXDEFER_MSK                              (0x200)
+#define ETHER_TX_CTL_ENLCARR_OFST                               (10)
+#define ETHER_TX_CTL_ENLCARR_MSK                                (0x400)
+#define ETHER_TX_CTL_ENEXCOLL_OFST                              (11)
+#define ETHER_TX_CTL_ENEXCOLL_MSK                               (0x800)
+#define ETHER_TX_CTL_ENLATECOLL_OFST                            (12)
+#define ETHER_TX_CTL_ENLATECOLL_MSK                             (0x1000)
+#define ETHER_TX_CTL_ENTXPAR_OFST                               (13)
+#define ETHER_TX_CTL_ENTXPAR_MSK                                (0x2000)
+#define ETHER_TX_CTL_ENCOMP_OFST                                (14)
+#define ETHER_TX_CTL_ENCOMP_MSK                                 (0x4000)
+
+#define ETHER_TX_STAT(base)                                                     (ETHER00_TYPE (base + 0xc))
+#define ETHER_TX_STAT_TXCOLL_OFST                               (0)
+#define ETHER_TX_STAT_TXCOLL_MSK                                (0xF)
+#define ETHER_TX_STAT_EXCOLL_OFST                               (4)
+#define ETHER_TX_STAT_EXCOLL_MSK                                (0x10)
+#define ETHER_TX_STAT_TXDEFER_OFST                              (5)
+#define ETHER_TX_STAT_TXDEFER_MSK                               (0x20)
+#define ETHER_TX_STAT_PAUSED_OFST                               (6)
+#define ETHER_TX_STAT_PAUSED_MSK                                (0x40)
+#define ETHER_TX_STAT_INTTX_OFST                                (7)
+#define ETHER_TX_STAT_INTTX_MSK                                 (0x80)
+#define ETHER_TX_STAT_UNDER_OFST                                (8)
+#define ETHER_TX_STAT_UNDER_MSK                                 (0x100)
+#define ETHER_TX_STAT_EXDEFER_OFST                              (9)
+#define ETHER_TX_STAT_EXDEFER_MSK                               (0x200)
+#define ETHER_TX_STAT_LCARR_OFST                                (10)
+#define ETHER_TX_STAT_LCARR_MSK                                 (0x400)
+#define ETHER_TX_STAT_TX10STAT_OFST                             (11)
+#define ETHER_TX_STAT_TX10STAT_MSK                              (0x800)
+#define ETHER_TX_STAT_LATECOLL_OFST                             (12)
+#define ETHER_TX_STAT_LATECOLL_MSK                              (0x1000)
+#define ETHER_TX_STAT_TXPAR_OFST                                (13)
+#define ETHER_TX_STAT_TXPAR_MSK                                 (0x2000)
+#define ETHER_TX_STAT_COMP_OFST                                 (14)
+#define ETHER_TX_STAT_COMP_MSK                                  (0x4000)
+#define ETHER_TX_STAT_TXHALTED_OFST                             (15)
+#define ETHER_TX_STAT_TXHALTED_MSK                              (0x8000)
+#define ETHER_TX_STAT_SQERR_OFST                                (16)
+#define ETHER_TX_STAT_SQERR_MSK                                 (0x10000)
+#define ETHER_TX_STAT_TXMCAST_OFST                              (17)
+#define ETHER_TX_STAT_TXMCAST_MSK                               (0x20000)
+#define ETHER_TX_STAT_TXBCAST_OFST                              (18)
+#define ETHER_TX_STAT_TXBCAST_MSK                               (0x40000)
+#define ETHER_TX_STAT_VLAN_OFST                                 (19)
+#define ETHER_TX_STAT_VLAN_MSK                                  (0x80000)
+#define ETHER_TX_STAT_MACC_OFST                                 (20)
+#define ETHER_TX_STAT_MACC_MSK                                  (0x100000)
+#define ETHER_TX_STAT_TXPAUSE_OFST                              (21)
+#define ETHER_TX_STAT_TXPAUSE_MSK                               (0x200000)
+
+#define ETHER_RX_CTL(base)                                                      (ETHER00_TYPE (base + 0x10))
+#define ETHER_RX_CTL_RXEN_OFST                                  (0)
+#define ETHER_RX_CTL_RXEN_MSK                                   (0x1)
+#define ETHER_RX_CTL_RXHALT_OFST                                (1)
+#define ETHER_RX_CTL_RXHALT_MSK                                 (0x2)
+#define ETHER_RX_CTL_LONGEN_OFST                                (2)
+#define ETHER_RX_CTL_LONGEN_MSK                                 (0x4)
+#define ETHER_RX_CTL_SHORTEN_OFST                               (3)
+#define ETHER_RX_CTL_SHORTEN_MSK                                (0x8)
+#define ETHER_RX_CTL_STRIPCRC_OFST                              (4)
+#define ETHER_RX_CTL_STRIPCRC_MSK                               (0x10)
+#define ETHER_RX_CTL_PASSCTL_OFST                               (5)
+#define ETHER_RX_CTL_PASSCTL_MSK                                (0x20)
+#define ETHER_RX_CTL_IGNORECRC_OFST                             (6)
+#define ETHER_RX_CTL_IGNORECRC_MSK                              (0x40)
+#define ETHER_RX_CTL_ENALIGN_OFST                               (8)
+#define ETHER_RX_CTL_ENALIGN_MSK                                (0x100)
+#define ETHER_RX_CTL_ENCRCERR_OFST                              (9)
+#define ETHER_RX_CTL_ENCRCERR_MSK                               (0x200)
+#define ETHER_RX_CTL_ENOVER_OFST                                (10)
+#define ETHER_RX_CTL_ENOVER_MSK                                 (0x400)
+#define ETHER_RX_CTL_ENLONGERR_OFST                             (11)
+#define ETHER_RX_CTL_ENLONGERR_MSK                              (0x800)
+#define ETHER_RX_CTL_ENRXPAR_OFST                               (13)
+#define ETHER_RX_CTL_ENRXPAR_MSK                                (0x2000)
+#define ETHER_RX_CTL_ENGOOD_OFST                                (14)
+#define ETHER_RX_CTL_ENGOOD_MSK                                 (0x4000)
+
+#define ETHER_RX_STAT(base)                                                     (ETHER00_TYPE (base + 0x14))
+#define ETHER_RX_STAT_LENERR_OFST                               (4)
+#define ETHER_RX_STAT_LENERR_MSK                                (0x10)
+#define ETHER_RX_STAT_CTLRECD_OFST                              (5)
+#define ETHER_RX_STAT_CTLRECD_MSK                               (0x20)
+#define ETHER_RX_STAT_INTRX_OFST                                (6)
+#define ETHER_RX_STAT_INTRX_MSK                                 (0x40)
+#define ETHER_RX_STAT_RX10STAT_OFST                             (7)
+#define ETHER_RX_STAT_RX10STAT_MSK                              (0x80)
+#define ETHER_RX_STAT_ALIGNERR_OFST                             (8)
+#define ETHER_RX_STAT_ALIGNERR_MSK                              (0x100)
+#define ETHER_RX_STAT_CRCERR_OFST                               (9)
+#define ETHER_RX_STAT_CRCERR_MSK                                (0x200)
+#define ETHER_RX_STAT_OVERFLOW_OFST                             (10)
+#define ETHER_RX_STAT_OVERFLOW_MSK                              (0x400)
+#define ETHER_RX_STAT_LONGERR_OFST                              (11)
+#define ETHER_RX_STAT_LONGERR_MSK                               (0x800)
+#define ETHER_RX_STAT_RXPAR_OFST                                (13)
+#define ETHER_RX_STAT_RXPAR_MSK                                 (0x2000)
+#define ETHER_RX_STAT_GOOD_OFST                                 (14)
+#define ETHER_RX_STAT_GOOD_MSK                                  (0x4000)
+#define ETHER_RX_STAT_RXHALTED_OFST                             (15)
+#define ETHER_RX_STAT_RXHALTED_MSK                              (0x8000)
+#define ETHER_RX_STAT_RXMCAST_OFST                              (17)
+#define ETHER_RX_STAT_RXMCAST_MSK                               (0x10000)
+#define ETHER_RX_STAT_RXBCAST_OFST                              (18)
+#define ETHER_RX_STAT_RXBCAST_MSK                               (0x20000)
+#define ETHER_RX_STAT_RXVLAN_OFST                               (19)
+#define ETHER_RX_STAT_RXVLAN_MSK                                (0x40000)
+#define ETHER_RX_STAT_RXPAUSE_OFST                              (20)
+#define ETHER_RX_STAT_RXPAUSE_MSK                               (0x80000)
+#define ETHER_RX_STAT_ARCSTATUS_OFST                            (21)
+#define ETHER_RX_STAT_ARCSTATUS_MSK                             (0xF00000)
+#define ETHER_RX_STAT_ARCENT_OFST                               (25)
+#define ETHER_RX_STAT_ARCENT_MSK                                (0x1F000000)
+
+#define ETHER_MD_DATA(base)                                                     (ETHER00_TYPE (base + 0x18))
+
+#define ETHER_MD_CA(base)                                                               (ETHER00_TYPE (base + 0x1c))
+#define ETHER_MD_CA_ADDR_OFST                                   (0)
+#define ETHER_MD_CA_ADDR_MSK                                    (0x1F)
+#define ETHER_MD_CA_PHY_OFST                                    (5)
+#define ETHER_MD_CA_PHY_MSK                                     (0x3E0)
+#define ETHER_MD_CA_WR_OFST                                     (10)
+#define ETHER_MD_CA_WR_MSK                                      (0x400)
+#define ETHER_MD_CA_BUSY_OFST                                   (11)
+#define ETHER_MD_CA_BUSY_MSK                                    (0x800)
+#define ETHER_MD_CA_PRESUPP_OFST                                (12)
+#define ETHER_MD_CA_PRESUPP_MSK                                 (0x1000)
+
+#define ETHER_ARC_ADR(base)           (ETHER00_TYPE (base + 0x160))
+#define ETHER_ARC_ADR_ARC_LOC_OFST                              (2)
+#define ETHER_ARC_ADR_ARC_LOC_MSK                               (0xFFC)
+
+#define ETHER_ARC_DATA(base)  (ETHER00_TYPE (base + 0x364))
+
+#define ETHER_ARC_ENA(base)   (ETHER00_TYPE (base + 0x28))
+#define ETHER_ARC_ENA_MSK                                       (0x1FFFFF)
+
+#define ETHER_PROM_CTL(base)                                                    (ETHER00_TYPE (base + 0x2c))
+#define ETHER_PROM_CTL_PROM_ADDR_OFST                   (0)
+#define ETHER_PROM_CTL_PROM_ADDR_MSK                    (0x3F)
+#define ETHER_PROM_CTL_OPCODE_OFST                              (13)
+#define ETHER_PROM_CTL_OPCODE_MSK                               (0x6000)
+#define ETHER_PROM_CTL_OPCODE_READ_MSK                  (0x4000)
+#define ETHER_PROM_CTL_OPCODE_WRITE_MSK                 (0x2000)
+#define ETHER_PROM_CTL_OPCODE_ERASE_MSK                 (0x6000)
+#define ETHER_PROM_CTL_ENABLE_MSK                               (0x0030)
+#define ETHER_PROM_CTL_DISABLE_MSK                              (0x0000)
+#define ETHER_PROM_CTL_BUSY_OFST                                (15)
+#define ETHER_PROM_CTL_BUSY_MSK                                 (0x8000)
+
+#define ETHER_PROM_DATA(base)                                                   (ETHER00_TYPE (base + 0x30))
+
+#define ETHER_MISS_CNT(base)                                                    (ETHER00_TYPE (base + 0x3c))
+#define ETHER_MISS_CNT_COUNT_OFST                               (0)
+#define ETHER_MISS_CNT_COUNT_MSK                                (0xFFFF)
+
+#define ETHER_CNTDATA(base)                                                     (ETHER00_TYPE (base + 0x80))
+
+#define ETHER_CNTACC(base)                                                      (ETHER00_TYPE (base + 0x84))
+#define ETHER_CNTACC_ADDR_OFST                                  (0)
+#define ETHER_CNTACC_ADDR_MSK                                   (0xFF)
+#define ETHER_CNTACC_WRRDN_OFST                                 (8)
+#define ETHER_CNTACC_WRRDN_MSK                                  (0x100)
+#define ETHER_CNTACC_CLEAR_OFST                                 (9)
+#define ETHER_CNTACC_CLEAR_MSK                                  (0x200)
+
+#define ETHER_TXRMINTEN(base)                                                   (ETHER00_TYPE (base + 0x88))
+#define ETHER_TXRMINTEN_MSK                                             (0x3FFFFFFF)
+
+#define ETHER_RXRMINTEN(base)                                                   (ETHER00_TYPE (base + 0x8C))
+#define ETHER_RXRMINTEN_MSK                                             (0xFFFFFF)
+
+/*
+*       RMON Registers
+*/
+#define         RMON_COLLISION0                                         0x0
+#define         RMON_COLLISION1                                         0x1
+#define         RMON_COLLISION2                                         0x2
+#define         RMON_COLLISION3                                         0x3
+#define         RMON_COLLISION4                                         0x4
+#define         RMON_COLLISION5                                         0x5
+#define         RMON_COLLISION6                                         0x6
+#define         RMON_COLLISION7                                         0x7
+#define         RMON_COLLISION8                                         0x8
+#define         RMON_COLLISION9                                         0x9
+#define         RMON_COLLISION10                                        0xa
+#define         RMON_COLLISION11                                        0xb
+#define         RMON_COLLISION12                                        0xc
+#define         RMON_COLLISION13                                        0xd
+#define         RMON_COLLISION14                                        0xe
+#define         RMON_COLLISION15                                        0xf
+#define         RMON_COLLISION16                                        0x10
+#define         RMON_FRAMES_WITH_DEFERRED_XMISSIONS     0x11
+#define         RMON_LATE_COLLISIONS                            0x12
+#define         RMON_FRAMES_LOST_DUE_TO_MAC_XMIT        0x13
+#define         RMON_CARRIER_SENSE_ERRORS                       0x14
+#define         RMON_FRAMES_WITH_EXCESSIVE_DEFERAL      0x15
+#define         RMON_UNICAST_FRAMES_TRANSMITTED_OK      0x16
+#define         RMON_MULTICAST_FRAMES_XMITTED_OK        0x17
+#define         RMON_BROADCAST_FRAMES_XMITTED_OK        0x18
+#define         RMON_SQE_TEST_ERRORS                            0x19
+#define         RMON_PAUSE_MACCTRL_FRAMES_XMITTED       0x1A
+#define         RMON_MACCTRL_FRAMES_XMITTED                     0x1B
+#define         RMON_VLAN_FRAMES_XMITTED                        0x1C
+#define         RMON_OCTETS_XMITTED_OK                          0x1D
+#define         RMON_OCTETS_XMITTED_OK_HI                       0x1E
+
+#define         RMON_RX_PACKET_SIZES0                           0x40
+#define         RMON_RX_PACKET_SIZES1                           0x41
+#define         RMON_RX_PACKET_SIZES2                           0x42
+#define         RMON_RX_PACKET_SIZES3                           0x43
+#define         RMON_RX_PACKET_SIZES4                           0x44
+#define         RMON_RX_PACKET_SIZES5                           0x45
+#define         RMON_RX_PACKET_SIZES6                           0x46
+#define         RMON_RX_PACKET_SIZES7                           0x47
+#define         RMON_FRAME_CHECK_SEQUENCE_ERRORS        0x48
+#define         RMON_ALIGNMENT_ERRORS                           0x49
+#define         RMON_FRAGMENTS                                          0x4A
+#define         RMON_JABBERS                                            0x4B
+#define         RMON_FRAMES_LOST_TO_INTMACRCVERR        0x4C
+#define         RMON_UNICAST_FRAMES_RCVD_OK                     0x4D
+#define         RMON_MULTICAST_FRAMES_RCVD_OK           0x4E
+#define         RMON_BROADCAST_FRAMES_RCVD_OK           0x4F
+#define         RMON_IN_RANGE_LENGTH_ERRORS                     0x50
+#define         RMON_OUT_OF_RANGE_LENGTH_ERRORS         0x51
+#define         RMON_VLAN_FRAMES_RCVD                           0x52
+#define         RMON_PAUSE_MAC_CTRL_FRAMES_RCVD         0x53
+#define         RMON_MAC_CTRL_FRAMES_RCVD                       0x54
+#define         RMON_OCTETS_RCVD_OK                                     0x55
+#define         RMON_OCTETS_RCVD_OK_HI                          0x56
+#define         RMON_OCTETS_RCVD_OTHER                          0x57
+#define         RMON_OCTETS_RCVD_OTHER_HI                       0x58
+
+#endif /* __ETHER00_H */
diff --git a/include/asm-arm/arch-epxa10db/excalibur.h b/include/asm-arm/arch-epxa10db/excalibur.h
new file mode 100644
index 000000000000..5c91dd6d7822
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/excalibur.h
@@ -0,0 +1,91 @@
+/* megafunction wizard: %ARM-Based Excalibur%
+   GENERATION: STANDARD
+   VERSION: WM1.0
+   MODULE: ARM-Based Excalibur
+   PROJECT: excalibur
+   ============================================================
+   File Name: v:\embedded\linux\bootldr\excalibur.h
+   Megafunction Name(s): ARM-Based Excalibur
+   ============================================================
+
+   ************************************************************
+   THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+   ************************************************************/
+
+#ifndef EXCALIBUR_H_INCLUDED
+#define EXCALIBUR_H_INCLUDED
+
+#define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN
+#define EXC_DEFINE_BOOT_FROM_FLASH
+
+#define EXC_INPUT_CLK_FREQUENCY (50000000)
+#define EXC_AHB1_CLK_FREQUENCY (150000000)
+#define EXC_AHB2_CLK_FREQUENCY (75000000)
+#define EXC_SDRAM_CLK_FREQUENCY (75000000)
+
+/* Registers Block */
+#define EXC_REGISTERS_BASE (0x7fffc000)
+#define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000)
+#define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040)
+#define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080)
+#define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140)
+#define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200)
+#define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00)
+#define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300)
+#define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00)
+#define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280)
+#define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380)
+#define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400)
+#define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800)
+#define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
+#define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100)
+
+#define EXC_REGISTERS_SIZE (0x00004000)
+
+/* EBI Block(s) */
+#define EXC_EBI_BLOCK0_BASE (0x40000000)
+#define EXC_EBI_BLOCK0_SIZE (0x00400000)
+#define EXC_EBI_BLOCK0_WIDTH (8)
+#define EXC_EBI_BLOCK0_NON_CACHEABLE
+#define EXC_EBI_BLOCK1_BASE (0x40400000)
+#define EXC_EBI_BLOCK1_SIZE (0x00400000)
+#define EXC_EBI_BLOCK1_WIDTH (16)
+#define EXC_EBI_BLOCK1_NON_CACHEABLE
+#define EXC_EBI_BLOCK2_BASE (0x40800000)
+#define EXC_EBI_BLOCK2_SIZE (0x00400000)
+#define EXC_EBI_BLOCK2_WIDTH (16)
+#define EXC_EBI_BLOCK2_NON_CACHEABLE
+#define EXC_EBI_BLOCK3_BASE (0x40c00000)
+#define EXC_EBI_BLOCK3_SIZE (0x00400000)
+#define EXC_EBI_BLOCK3_WIDTH (16)
+#define EXC_EBI_BLOCK3_NON_CACHEABLE
+
+/* SDRAM Block(s) */
+#define EXC_SDRAM_BLOCK0_BASE (0x00000000)
+#define EXC_SDRAM_BLOCK0_SIZE (0x04000000)
+#define EXC_SDRAM_BLOCK0_WIDTH (32)
+#define EXC_SDRAM_BLOCK1_BASE (0x04000000)
+#define EXC_SDRAM_BLOCK1_SIZE (0x04000000)
+#define EXC_SDRAM_BLOCK1_WIDTH (32)
+
+/* Single Port SRAM Block(s) */
+#define EXC_SPSRAM_BLOCK0_BASE (0x08000000)
+#define EXC_SPSRAM_BLOCK0_SIZE (0x00020000)
+#define EXC_SPSRAM_BLOCK1_BASE (0x08020000)
+#define EXC_SPSRAM_BLOCK1_SIZE (0x00020000)
+
+/* PLD Block(s) */
+#define EXC_PLD_BLOCK0_BASE (0x80000000)
+#define EXC_PLD_BLOCK0_SIZE (0x00004000)
+#define EXC_PLD_BLOCK0_NON_CACHEABLE
+#define EXC_PLD_BLOCK1_BASE (0xf000000)
+#define EXC_PLD_BLOCK1_SIZE (0x00004000)
+#define EXC_PLD_BLOCK1_NON_CACHEABLE
+#define EXC_PLD_BLOCK2_BASE (0x80008000)
+#define EXC_PLD_BLOCK2_SIZE (0x00004000)
+#define EXC_PLD_BLOCK2_NON_CACHEABLE
+#define EXC_PLD_BLOCK3_BASE (0x8000c000)
+#define EXC_PLD_BLOCK3_SIZE (0x00004000)
+#define EXC_PLD_BLOCK3_NON_CACHEABLE
+
+#endif
diff --git a/include/asm-arm/arch-epxa10db/hardware.h b/include/asm-arm/arch-epxa10db/hardware.h
new file mode 100644
index 000000000000..b992c2924a77
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/hardware.h
@@ -0,0 +1,64 @@
+/*
+ *  linux/include/asm-arm/arch-epxa10/hardware.h
+ *
+ *  This file contains the hardware definitions of the Integrator.
+ *
+ *  Copyright (C) 1999 ARM Limited.
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/arch/platform.h>
+
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define IO_BASE                 0xf0000000                 // VA of IO 
+#define IO_SIZE                 0x10000000                 // How much?
+#define IO_START                EXC_REGISTERS_BASE              // PA of IO
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) ((x) | 0xf0000000) 
+
+#define FLASH_VBASE             0xFE000000
+#define FLASH_SIZE              0x01000000
+#define FLASH_START             EXC_EBI_BLOCK0_BASE
+#define FLASH_VADDR(x) ((x)|0xFE000000)
+/*
+ * Similar to above, but for PCI addresses (memory, IO, Config and the
+ * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
+ */
+#if 0
+#define PCI_MEMORY_VADDR        0xe8000000
+#define PCI_CONFIG_VADDR        0xec000000
+#define PCI_V3_VADDR            0xed000000
+#define PCI_IO_VADDR            0xee000000
+
+#define PCIO_BASE               PCI_IO_VADDR
+#define PCIMEM_BASE             PCI_MEMORY_VADDR
+
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x6000
+#define PCIBIOS_MIN_MEM         0x00100000
+#endif
+
+
+#endif
+
diff --git a/include/asm-arm/arch-epxa10db/int_ctrl00.h b/include/asm-arm/arch-epxa10db/int_ctrl00.h
new file mode 100644
index 000000000000..23ec864c40bb
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/int_ctrl00.h
@@ -0,0 +1,288 @@
+/*
+ *  
+ *  This file contains the register definitions for the Excalibur
+ *  Timer TIMER00.
+ *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __INT_CTRL00_H
+#define __INT_CTRL00_H
+
+#define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x00 ))
+#define INT_MS_FC_MSK (0x10000)
+#define INT_MS_FC_OFST (16)
+#define INT_MS_M1_MSK (0x8000)
+#define INT_MS_M1_OFST (15)
+#define INT_MS_M0_MSK (0x4000)
+#define INT_MS_M0_OFST (14)
+#define INT_MS_AE_MSK (0x2000)
+#define INT_MS_AE_OFST (13)
+#define INT_MS_PE_MSK (0x1000)
+#define INT_MS_PE_OFST (12)
+#define INT_MS_EE_MSK (0x0800)
+#define INT_MS_EE_OFST (11)
+#define INT_MS_PS_MSK (0x0400)
+#define INT_MS_PS_OFST (10)
+#define INT_MS_T1_MSK (0x0200)
+#define INT_MS_T1_OFST (9)
+#define INT_MS_T0_MSK (0x0100)
+#define INT_MS_T0_OFST (8)
+#define INT_MS_UA_MSK (0x0080)
+#define INT_MS_UA_OFST (7)
+#define INT_MS_IP_MSK (0x0040)
+#define INT_MS_IP_OFST (6)
+#define INT_MS_P5_MSK (0x0020)
+#define INT_MS_P5_OFST (5)
+#define INT_MS_P4_MSK (0x0010)
+#define INT_MS_P4_OFST (4)
+#define INT_MS_P3_MSK (0x0008)
+#define INT_MS_P3_OFST (3)
+#define INT_MS_P2_MSK (0x0004)
+#define INT_MS_P2_OFST (2)
+#define INT_MS_P1_MSK (0x0002)
+#define INT_MS_P1_OFST (1)
+#define INT_MS_P0_MSK (0x0001)
+#define INT_MS_P0_OFST (0)
+
+#define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x04 ))
+#define INT_MC_FC_MSK (0x10000)
+#define INT_MC_FC_OFST (16)
+#define INT_MC_M1_MSK (0x8000)
+#define INT_MC_M1_OFST (15)
+#define INT_MC_M0_MSK (0x4000)
+#define INT_MC_M0_OFST (14)
+#define INT_MC_AE_MSK (0x2000)
+#define INT_MC_AE_OFST (13)
+#define INT_MC_PE_MSK (0x1000)
+#define INT_MC_PE_OFST (12)
+#define INT_MC_EE_MSK (0x0800)
+#define INT_MC_EE_OFST (11)
+#define INT_MC_PS_MSK (0x0400)
+#define INT_MC_PS_OFST (10)
+#define INT_MC_T1_MSK (0x0200)
+#define INT_MC_T1_OFST (9)
+#define INT_MC_T0_MSK (0x0100)
+#define INT_MC_T0_OFST (8)
+#define INT_MC_UA_MSK (0x0080)
+#define INT_MC_UA_OFST (7)
+#define INT_MC_IP_MSK (0x0040)
+#define INT_MC_IP_OFST (6)
+#define INT_MC_P5_MSK (0x0020)
+#define INT_MC_P5_OFST (5)
+#define INT_MC_P4_MSK (0x0010)
+#define INT_MC_P4_OFST (4)
+#define INT_MC_P3_MSK (0x0008)
+#define INT_MC_P3_OFST (3)
+#define INT_MC_P2_MSK (0x0004)
+#define INT_MC_P2_OFST (2)
+#define INT_MC_P1_MSK (0x0002)
+#define INT_MC_P1_OFST (1)
+#define INT_MC_P0_MSK (0x0001)
+#define INT_MC_P0_OFST (0)
+
+#define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x08 ))
+#define INT_SS_FC_SSK (0x8000)
+#define INT_SS_FC_OFST (15)
+#define INT_SS_M1_SSK (0x8000)
+#define INT_SS_M1_OFST (15)
+#define INT_SS_M0_SSK (0x4000)
+#define INT_SS_M0_OFST (14)
+#define INT_SS_AE_SSK (0x2000)
+#define INT_SS_AE_OFST (13)
+#define INT_SS_PE_SSK (0x1000)
+#define INT_SS_PE_OFST (12)
+#define INT_SS_EE_SSK (0x0800)
+#define INT_SS_EE_OFST (11)
+#define INT_SS_PS_SSK (0x0400)
+#define INT_SS_PS_OFST (10)
+#define INT_SS_T1_SSK (0x0200)
+#define INT_SS_T1_OFST (9)
+#define INT_SS_T0_SSK (0x0100)
+#define INT_SS_T0_OFST (8)
+#define INT_SS_UA_SSK (0x0080)
+#define INT_SS_UA_OFST (7)
+#define INT_SS_IP_SSK (0x0040)
+#define INT_SS_IP_OFST (6)
+#define INT_SS_P5_SSK (0x0020)
+#define INT_SS_P5_OFST (5)
+#define INT_SS_P4_SSK (0x0010)
+#define INT_SS_P4_OFST (4)
+#define INT_SS_P3_SSK (0x0008)
+#define INT_SS_P3_OFST (3)
+#define INT_SS_P2_SSK (0x0004)
+#define INT_SS_P2_OFST (2)
+#define INT_SS_P1_SSK (0x0002)
+#define INT_SS_P1_OFST (1)
+#define INT_SS_P0_SSK (0x0001)
+#define INT_SS_P0_OFST (0)
+
+#define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x0C ))
+#define INT_RS_FC_RSK (0x10000)
+#define INT_RS_FC_OFST (16)
+#define INT_RS_M1_RSK (0x8000)
+#define INT_RS_M1_OFST (15)
+#define INT_RS_M0_RSK (0x4000)
+#define INT_RS_M0_OFST (14)
+#define INT_RS_AE_RSK (0x2000)
+#define INT_RS_AE_OFST (13)
+#define INT_RS_PE_RSK (0x1000)
+#define INT_RS_PE_OFST (12)
+#define INT_RS_EE_RSK (0x0800)
+#define INT_RS_EE_OFST (11)
+#define INT_RS_PS_RSK (0x0400)
+#define INT_RS_PS_OFST (10)
+#define INT_RS_T1_RSK (0x0200)
+#define INT_RS_T1_OFST (9)
+#define INT_RS_T0_RSK (0x0100)
+#define INT_RS_T0_OFST (8)
+#define INT_RS_UA_RSK (0x0080)
+#define INT_RS_UA_OFST (7)
+#define INT_RS_IP_RSK (0x0040)
+#define INT_RS_IP_OFST (6)
+#define INT_RS_P5_RSK (0x0020)
+#define INT_RS_P5_OFST (5)
+#define INT_RS_P4_RSK (0x0010)
+#define INT_RS_P4_OFST (4)
+#define INT_RS_P3_RSK (0x0008)
+#define INT_RS_P3_OFST (3)
+#define INT_RS_P2_RSK (0x0004)
+#define INT_RS_P2_OFST (2)
+#define INT_RS_P1_RSK (0x0002)
+#define INT_RS_P1_OFST (1)
+#define INT_RS_P0_RSK (0x0001)
+#define INT_RS_P0_OFST (0)
+
+#define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x10 ))
+#define INT_ID_ID_MSK (0x3F)
+#define INT_ID_ID_OFST (0)
+
+#define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x14 ))
+#define INT_PLD_PRIORITY_PRI_MSK (0x3F)
+#define INT_PLD_PRIORITY_PRI_OFST (0)
+#define INT_PLD_PRIORITY_GA_MSK (0x40)
+#define INT_PLD_PRIORITY_GA_OFST (6)
+
+#define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x18 ))
+#define INT_MODE_MODE_MSK (0x3)
+#define INT_MODE_MODE_OFST (0)
+
+#define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x80 ))
+#define INT_PRIORITY_P0_PRI_MSK (0x3F)
+#define INT_PRIORITY_P0_PRI_OFST (0)
+#define INT_PRIORITY_P0_FQ_MSK (0x40)
+#define INT_PRIORITY_P0_FQ_OFST (6)
+
+#define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x84 ))
+#define INT_PRIORITY_P1_PRI_MSK (0x3F)
+#define INT_PRIORITY_P1_PRI_OFST (0)
+#define INT_PRIORITY_P1_FQ_MSK (0x40)
+#define INT_PRIORITY_P1_FQ_OFST (6)
+
+#define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x88 ))
+#define INT_PRIORITY_P2_PRI_MSK (0x3F)
+#define INT_PRIORITY_P2_PRI_OFST (0)
+#define INT_PRIORITY_P2_FQ_MSK (0x40)
+#define INT_PRIORITY_P2_FQ_OFST (6)
+
+#define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x8C ))
+#define INT_PRIORITY_P3_PRI_MSK (0x3F)
+#define INT_PRIORITY_P3_PRI_OFST (0)
+#define INT_PRIORITY_P3_FQ_MSK (0x40)
+#define INT_PRIORITY_P3_FQ_OFST (6)
+
+#define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x90 ))
+#define INT_PRIORITY_P4_PRI_MSK (0x3F)
+#define INT_PRIORITY_P4_PRI_OFST (0)
+#define INT_PRIORITY_P4_FQ_MSK (0x40)
+#define INT_PRIORITY_P4_FQ_OFST (6)
+
+#define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x94 ))
+#define INT_PRIORITY_P5_PRI_MSK (0x3F)
+#define INT_PRIORITY_P5_PRI_OFST (0)
+#define INT_PRIORITY_P5_FQ_MSK (0x40)
+#define INT_PRIORITY_P5_FQ_OFST (6)
+
+#define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x94 ))
+#define INT_PRIORITY_IP_PRI_MSK (0x3F)
+#define INT_PRIORITY_IP_PRI_OFST (0)
+#define INT_PRIORITY_IP_FQ_MSK (0x40)
+#define INT_PRIORITY_IP_FQ_OFST (6)
+
+#define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr  + 0x9C ))
+#define INT_PRIORITY_UA_PRI_MSK (0x3F)
+#define INT_PRIORITY_UA_PRI_OFST (0)
+#define INT_PRIORITY_UA_FQ_MSK (0x40)
+#define INT_PRIORITY_UA_FQ_OFST (6)
+
+#define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA0 ))
+#define INT_PRIORITY_T0_PRI_MSK (0x3F)
+#define INT_PRIORITY_T0_PRI_OFST (0)
+#define INT_PRIORITY_T0_FQ_MSK (0x40)
+#define INT_PRIORITY_T0_FQ_OFST (6)
+
+#define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA4 ))
+#define INT_PRIORITY_T1_PRI_MSK (0x3F)
+#define INT_PRIORITY_T1_PRI_OFST (0)
+#define INT_PRIORITY_T1_FQ_MSK (0x40)
+#define INT_PRIORITY_T1_FQ_OFST (6)
+
+#define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xA8 ))
+#define INT_PRIORITY_PS_PRI_MSK (0x3F)
+#define INT_PRIORITY_PS_PRI_OFST (0)
+#define INT_PRIORITY_PS_FQ_MSK (0x40)
+#define INT_PRIORITY_PS_FQ_OFST (6)
+
+#define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xAC ))
+#define INT_PRIORITY_EE_PRI_MSK (0x3F)
+#define INT_PRIORITY_EE_PRI_OFST (0)
+#define INT_PRIORITY_EE_FQ_MSK (0x40)
+#define INT_PRIORITY_EE_FQ_OFST (6)
+
+#define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB0 ))
+#define INT_PRIORITY_PE_PRI_MSK (0x3F)
+#define INT_PRIORITY_PE_PRI_OFST (0)
+#define INT_PRIORITY_PE_FQ_MSK (0x40)
+#define INT_PRIORITY_PE_FQ_OFST (6)
+
+#define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB4 ))
+#define INT_PRIORITY_AE_PRI_MSK (0x3F)
+#define INT_PRIORITY_AE_PRI_OFST (0)
+#define INT_PRIORITY_AE_FQ_MSK (0x40)
+#define INT_PRIORITY_AE_FQ_OFST (6)
+
+#define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xB8 ))
+#define INT_PRIORITY_M0_PRI_MSK (0x3F)
+#define INT_PRIORITY_M0_PRI_OFST (0)
+#define INT_PRIORITY_M0_FQ_MSK (0x40)
+#define INT_PRIORITY_M0_FQ_OFST (6)
+
+#define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xBC ))
+#define INT_PRIORITY_M1_PRI_MSK (0x3F)
+#define INT_PRIORITY_M1_PRI_OFST (0)
+#define INT_PRIORITY_M1_FQ_MSK (0x40)
+#define INT_PRIORITY_M1_FQ_OFST (6)
+
+#define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr  + 0xC0 ))
+#define INT_PRIORITY_FC_PRI_MSK (0x3F)
+#define INT_PRIORITY_FC_PRI_OFST (0)
+#define INT_PRIORITY_FC_FQ_MSK (0x40)
+#define INT_PRIORITY_FC_FQ_OFST (6)
+
+#endif /* __INT_CTRL00_H */
+
+
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h
new file mode 100644
index 000000000000..1f0afa257621
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/io.h
@@ -0,0 +1,39 @@
+/*
+ *  linux/include/asm-arm/arch-epxa10db/io.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffff
+
+
+/*
+ * Generic virtual read/write
+ */
+/*#define outsw   __arch_writesw
+#define outsl   __arch_writesl
+#define outsb   __arch_writesb
+#define insb    __arch_readsb
+#define insw    __arch_readsw
+#define insl    __arch_readsl*/
+
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a) 
+
+#endif
diff --git a/include/asm-arm/arch-epxa10db/irqs.h b/include/asm-arm/arch-epxa10db/irqs.h
new file mode 100644
index 000000000000..c3758a3b5d9d
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/irqs.h
@@ -0,0 +1,45 @@
+/*
+ *  linux/include/asm-arm/arch-camelot/irqs.h
+ *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/* Use the Excalibur chip definitions */
+#define INT_CTRL00_TYPE
+#include "asm/arch/int_ctrl00.h"
+
+
+#define IRQ_PLD0                     INT_MS_P0_OFST
+#define IRQ_PLD1                     INT_MS_P1_OFST
+#define IRQ_PLD2                     INT_MS_P2_OFST
+#define IRQ_PLD3                     INT_MS_P3_OFST
+#define IRQ_PLD4                     INT_MS_P4_OFST
+#define IRQ_PLD5                     INT_MS_P5_OFST
+#define IRQ_EXT                      INT_MS_IP_OFST
+#define IRQ_UART                     INT_MS_UA_OFST
+#define IRQ_TIMER0                   INT_MS_T0_OFST
+#define IRQ_TIMER1                   INT_MS_T1_OFST
+#define IRQ_PLL                      INT_MS_PLL_OFST
+#define IRQ_EBI                      INT_MS_EBI_OFST
+#define IRQ_STRIPE_BRIDGE            INT_MS_PLL_OFST
+#define IRQ_AHB_BRIDGE               INT_MS_PLL_OFST
+#define IRQ_COMMRX                   INT_MS_CR_OFST
+#define IRQ_COMMTX                   INT_MS_CT_OFST
+#define IRQ_FAST_COMM                INT_MS_FC_OFST
+
+#define NR_IRQS                         (INT_MS_FC_OFST + 1)
+
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h
new file mode 100644
index 000000000000..3f86bf7f67f0
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/memory.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/arch-epxa10/memory.h
+ *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x00000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (x - PAGE_OFFSET + /*SDRAM_BASE*/0)
+#define __bus_to_virt(x)        (x - /*SDRAM_BASE*/0 + PAGE_OFFSET)
+
+#endif
diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h
new file mode 100644
index 000000000000..d8a7efa12e19
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/mode_ctrl00.h
@@ -0,0 +1,80 @@
+#ifndef __MODE_CTRL00_H
+#define __MODE_CTRL00_H
+
+/*
+ * Register definitions for the reset and mode control
+ */
+
+/*
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+
+
+#define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  ))
+#define BOOT_CR_BF_MSK (0x1)
+#define BOOT_CR_BF_OFST (0)
+#define BOOT_CR_HM_MSK (0x2)
+#define BOOT_CR_HM_OFST (1)
+#define BOOT_CR_RE_MSK (0x4)
+#define BOOT_CR_RE_OFST (2)
+
+#define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x4 ))
+#define RESET_SR_WR_MSK (0x1)
+#define RESET_SR_WR_OFST (0)
+#define RESET_SR_CR_MSK (0x2)
+#define RESET_SR_CR_OFST (1)
+#define RESET_SR_JT_MSK (0x4)
+#define RESET_SR_JT_OFST (2)
+#define RESET_SR_ER_MSK (0x8)
+#define RESET_SR_ER_OFST (3)
+
+#define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x08 ))
+
+#define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x20 ))
+#define SRAM0_SR_SIZE_MSK (0xFFFFF000)
+#define SRAM0_SR_SIZE_OFST (12)
+
+#define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x24 ))
+#define SRAM1_SR_SIZE_MSK (0xFFFFF000)
+#define SRAM1_SR_SIZE_OFST (12)
+
+#define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x30 ))
+
+#define DPSRAM0_SR_MODE_MSK (0xF)
+#define DPSRAM0_SR_MODE_OFST (0)
+#define DPSRAM0_SR_GLBL_MSK (0x30)
+#define DPSRAM0_SR_SIZE_MSK (0xFFFFF000)
+#define DPSRAM0_SR_SIZE_OFST (12)
+
+#define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x34 ))
+#define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0)
+#define DPSRAM0_LCR_LCKADDR_OFST (4)
+
+#define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x38 ))
+#define DPSRAM1_SR_MODE_MSK (0xF)
+#define DPSRAM1_SR_MODE_OFST (0)
+#define DPSRAM1_SR_GLBL_MSK (0x30)
+#define DPSRAM1_SR_GLBL_OFST (4)
+#define DPSRAM1_SR_SIZE_MSK (0xFFFFF000)
+#define DPSRAM1_SR_SIZE_OFST (12)
+
+#define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR  + 0x3C ))
+#define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0)
+#define DPSRAM1_LCR_LCKADDR_OFST (4)
+
+#endif /* __MODE_CTRL00_H */
diff --git a/include/asm-arm/arch-epxa10db/param.h b/include/asm-arm/arch-epxa10db/param.h
new file mode 100644
index 000000000000..783dedd71c8f
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-epxa10db/param.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-epxa10db/platform.h b/include/asm-arm/arch-epxa10db/platform.h
new file mode 100644
index 000000000000..129bb0f212a0
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/platform.h
@@ -0,0 +1,7 @@
+#ifndef PLATFORM_H
+#define PLATFORM_H
+#include "excalibur.h"
+
+#define MAXIRQNUM 15 
+#endif
+
diff --git a/include/asm-arm/arch-epxa10db/pld_conf00.h b/include/asm-arm/arch-epxa10db/pld_conf00.h
new file mode 100644
index 000000000000..7af2c38dacc6
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/pld_conf00.h
@@ -0,0 +1,73 @@
+#ifndef __PLD_CONF00_H
+#define __PLD_CONF00_H
+
+/*
+ * Register definitions for the PLD Configuration Logic
+ */
+
+/*
+ *  
+ *  This file contains the register definitions for the Excalibur
+ *  Interrupt controller INT_CTRL00.
+ *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+ 
+#define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR))  
+#define CONFIG_CONTROL_LK_MSK (0x1)
+#define CONFIG_CONTROL_LK_OFST (0)
+#define CONFIG_CONTROL_CO_MSK (0x2)
+#define CONFIG_CONTROL_CO_OFST (1)
+#define CONFIG_CONTROL_B_MSK  (0x4)
+#define CONFIG_CONTROL_B_OFST (2)
+#define CONFIG_CONTROL_PC_MSK (0x8)
+#define CONFIG_CONTROL_PC_OFST (3)
+#define CONFIG_CONTROL_E_MSK (0x10)
+#define CONFIG_CONTROL_E_OFST (4)
+#define CONFIG_CONTROL_ES_MSK (0xE0)
+#define CONFIG_CONTROL_ES_OFST (5)
+#define CONFIG_CONTROL_ES_0_MSK (0x20)
+#define CONFIG_CONTROL_ES_1_MSK (0x40)
+#define CONFIG_CONTROL_ES_2_MSK (0x80)
+
+#define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0x4 ))
+#define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF)
+#define CONFIG_CONTROL_CLOCK_RATIO_OFST (0)
+
+#define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0x8 ))
+#define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF)
+#define CONFIG_CONTROL_DATA_OFST (0)
+
+#define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR  + 0xC )) 
+#define CONFIG_UNLOCK_MSK (0xFFFFFFFF)
+#define CONFIG_UNLOCK_OFST (0)
+
+#define CONFIG_UNLOCK_MAGIC (0x554E4C4B)
+
+#endif /* __PLD_CONF00_H */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/include/asm-arm/arch-epxa10db/system.h b/include/asm-arm/arch-epxa10db/system.h
new file mode 100644
index 000000000000..345b092a1ed5
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/system.h
@@ -0,0 +1,41 @@
+/*
+ *  linux/include/asm-arm/arch-epxa10db/system.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/platform.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+extern __inline__ void arch_reset(char mode)
+{
+        /* Hmm... We can probably do something with the watchdog... */
+}
+
+#endif
diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h
new file mode 100644
index 000000000000..5e107bd4e109
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/tdkphy.h
@@ -0,0 +1,209 @@
+/*
+ *  linux/drivers/tdkphy.h
+ *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __TDKPHY_H
+#define __TDKPHY_H
+
+/*
+ * Register definitions for the TDK 78Q2120 PHY 
+ * which is on the Camelot board
+ */
+
+/*
+ * Copyright (c) Altera Corporation 2000.
+ * All rights reserved.
+ */
+#define PHY_CONTROL                                                                                     (0)
+#define PHY_CONTROL_COLT_MSK                                                            (0x80)
+#define PHY_CONTROL_COLT_OFST                                                           (7)
+#define PHY_CONTROL_DUPLEX_MSK                                                          (0x100)
+#define PHY_CONTROL_DUPLEX_OFST                                                         (8)
+#define PHY_CONTROL_RANEG_MSK                                                           (0x200)
+#define PHY_CONTROL_RANEG_OFST                                                          (9)
+#define PHY_CONTROL_ISO_MSK                                                                     (0x400)
+#define PHY_CONTROL_ISO_OFST                                                            (10)
+#define PHY_CONTROL_PWRDN_MSK                                                           (0x800)
+#define PHY_CONTROL_PWRDN_OFST                                                          (11)
+#define PHY_CONTROL_ANEGEN_MSK                                                          (0x1000)
+#define PHY_CONTROL_ANEGEN_OFST                                                         (12)
+#define PHY_CONTROL_SPEEDSL_MSK                                                         (0x2000)
+#define PHY_CONTROL_SPEEDSL_OFST                                                        (13)
+#define PHY_CONTROL_LOOPBK_MSK                                                          (0x4000)
+#define PHY_CONTROL_LOOPBK_OFST                                                         (14)
+#define PHY_CONTROL_RESET_MSK                                                           (0x8000)
+#define PHY_CONTROL_RESET_OFST                                                          (15)
+
+#define PHY_STATUS                                                                                      (1)
+#define PHY_STATUS_ETXD_MSK                                                                     (0x1)
+#define PHY_STATUS_EXTD_OFST                                                            (0)
+#define PHY_STATUS_JAB_MSK                                                                      (0x2)
+#define PHY_STATUS_JAB_OFST                                                                     (1)
+#define PHY_STATUS_LINK_MSK                                                                     (0x4)
+#define PHY_STATUS_LINK_OFST                                                            (2)
+#define PHY_STATUS_ANEGA_MSK                                                            (0x8)
+#define PHY_STATUS_ANEGA_OFST                                                           (3)
+#define PHY_STATUS_RFAULT_MSK                                                           (0x10)
+#define PHY_STATUS_RFAULT_OFST                                                          (4)
+#define PHY_STATUS_ANEGC_MSK                                                            (0x20)
+#define PHY_STATUS_ANEGC_OFST                                                           (5)
+#define PHY_STATUS_10T_H_MSK                                                            (0x800)
+#define PHY_STATUS_10T_H_OFST                                                           (11)
+#define PHY_STATUS_10T_F_MSK                                                            (0x1000)
+#define PHY_STATUS_10T_F_OFST                                                           (12)
+#define PHY_STATUS_100_X_H_MSK                                                          (0x2000)
+#define PHY_STATUS_100_X_H_OFST                                                         (13)
+#define PHY_STATUS_100_X_F_MSK                                                          (0x4000)
+#define PHY_STATUS_100_X_F_OFST                                                         (14)
+#define PHY_STATUS_100T4_MSK                                                            (0x8000)
+#define PHY_STATUS_100T4_OFST                                                           (15)
+
+#define PHY_ID1                                                                                         (2)
+#define PHY_ID1_OUI_MSK                                                                         (0xFFFF)
+#define PHY_ID1_OUI_OFST                                                                        (0)
+
+#define PHY_ID2                                                                                         (3)
+#define PHY_ID2_RN_MSK                                                                          (0xF)
+#define PHY_ID2_RN_OFST                                                                         (0)
+#define PHY_ID2_MN_MSK                                                                          (0x3F0)
+#define PHY_ID2_MN_OFST                                                                         (4)
+#define PHY_ID2_OUI_MSK                                                                         (0xFC00)
+#define PHY_ID2_OUI_OFST                                                                        (10)
+
+#define PHY_AUTO_NEG_ADVERTISEMENT                                                      (4)
+#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK                         (0x1F)
+#define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST                        (0)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK                                       (0x20)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST                                      (5)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK                                       (0x40)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST                                      (6)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK                                       (0x80)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST                                      (7)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK                                       (0x100)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST                                      (8)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK                                       (0x200)
+#define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST                                      (9)
+#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK                                      (0x1FE0)
+#define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST                                     (5)
+#define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK                                       (0x2000)
+#define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST                                      (13)
+#define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK                                     (0x4000)
+#define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST                            (14)
+#define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK                                       (0x8000)
+#define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST                                      (15)
+
+#define PHY_AUTO_NEG_LINK_PARTNER                                                       (5)
+#define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK                                        (0x1F)
+#define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST                                       (0)
+#define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK                                        (0x1FE0)
+#define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST                                       (5)
+#define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK                                        (0x2000)
+#define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST                                       (13)
+#define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK                                       (0x4000)
+#define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST                                      (14)
+#define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK                                        (0x8000)
+#define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST                                       (15)
+
+#define PHY_AUTO_NEG_EXPANSION                                                          (6)
+#define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK                                      (0x1)
+#define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST                                     (0)
+#define PHY_AUTO_NEG_EXPANSION_PRX_MSK                                          (0x2)
+#define PHY_AUTO_NEG_EXPANSION_PRX_OFST                                         (1)
+#define PHY_AUTO_NEG_EXPANSION_NPA_MSK                                          (0x4)
+#define PHY_AUTO_NEG_EXPANSION_NPA_OFST                                         (2)
+#define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK                                        (0x8)
+#define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST                                       (3)
+#define PHY_AUTO_NEG_EXPANSION_PDF_MSK                                          (0x10)
+#define PHY_AUTO_NEG_EXPANSION_PDF_OFST                                         (4)
+
+#define PHY_VENDOR_SPECIFIC                                                                     (16)
+#define PHY_VENDOR_SPECIFIC_RXCC_MSK                                            (0x1)
+#define PHY_VENDOR_SPECIFIC_RXCC_OFST                                           (0)
+#define PHY_VENDOR_SPECIFIC_PCSBP_MSK                                           (0x2)
+#define PHY_VENDOR_SPECIFIC_PCSBP_OFST                                          (1)
+#define PHY_VENDOR_SPECIFIC_RVSPOL_MSK                                          (0x10)
+#define PHY_VENDOR_SPECIFIC_RVSPOL_OFST                                         (4)
+#define PHY_VENDOR_SPECIFIC_APOL_MSK                                            (0x20)  
+#define PHY_VENDOR_SPECIFIC_APOL_OFST                                           (5)
+#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK                                       (0x40)
+#define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST                                      (6)
+#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK                                       (0x80)
+#define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST                                      (7)
+#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK                                       (0x100)
+#define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST                                      (8)
+#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK                                       (0x200)
+#define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST                                      (9)
+#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK       (0x400)
+#define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST      (10)
+#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK           (0x800)
+#define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST          (11)
+#define PHY_VENDOR_SPECIFIC_TXHIM_MSK                                           (0x1000)
+#define PHY_VENDOR_SPECIFIC_TXHIM_OFST                                          (12)
+#define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK                                       (0x4000)
+#define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST                                      (14)
+#define PHY_VENDOR_SPECIFIC_RPTR_MSK                                            (0x8000)
+#define PHY_VENDOR_SPECIFIC_RPTR_OFST                                           (15)
+
+#define PHY_IRQ_CONTROL                                                                         (17)
+#define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK                                       (0x1)
+#define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST                                      (0)
+#define PHY_IRQ_CONTROL_RFAULT_INT_MSK                                          (0x2)
+#define PHY_IRQ_CONTROL_RFAULT_INT_OFST                                         (1)
+#define PHY_IRQ_CONTROL_LS_CHG_INT_MSK                                          (0x4)
+#define PHY_IRQ_CONTROL_LS_CHG_INT_OFST                                         (2)
+#define PHY_IRQ_CONTROL_LP_ACK_INT_MSK                                          (0x8)
+#define PHY_IRQ_CONTROL_LP_ACK_INT_OFST                                         (3)
+#define PHY_IRQ_CONTROL_PDF_INT_MSK                                                     (0x10)
+#define PHY_IRQ_CONTROL_PDF_INT_OFST                                            (4)
+#define PHY_IRQ_CONTROL_PRX_INT_MSK                                                     (0x20)
+#define PHY_IRQ_CONTROL_PRX_INT_OFST                                            (5)
+#define PHY_IRQ_CONTROL_RXER_INT_MSK                                            (0x40)
+#define PHY_IRQ_CONTROL_RXER_INT_OFST                                           (6)
+#define PHY_IRQ_CONTROL_JABBER_INT_MSK                                          (0x80)
+#define PHY_IRQ_CONTROL_JABBER_INT_OFST                                         (7)
+#define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK                                        (0x100)
+#define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST                                       (8)
+#define PHY_IRQ_CONTROL_RFAULT_IE_MSK                                           (0x200)
+#define PHY_IRQ_CONTROL_RFAULT_IE_OFST                                          (9)
+#define PHY_IRQ_CONTROL_LS_CHG_IE_MSK                                           (0x400)
+#define PHY_IRQ_CONTROL_LS_CHG_IE_OFST                                          (10)
+#define PHY_IRQ_CONTROL_LP_ACK_IE_MSK                                           (0x800)
+#define PHY_IRQ_CONTROL_LP_ACK_IE_OFST                                          (11)
+#define PHY_IRQ_CONTROL_PDF_IE_MSK                                                      (0x1000)
+#define PHY_IRQ_CONTROL_PDF_IE_OFST                                                     (12)
+#define PHY_IRQ_CONTROL_PRX_IE_MSK                                                      (0x2000)
+#define PHY_IRQ_CONTROL_PRX_IE_OFST                                                     (13)
+#define PHY_IRQ_CONTROL_RXER_IE_MSK                                                     (0x4000)
+#define PHY_IRQ_CONTROL_RXER_IE_OFST                                            (14)
+#define PHY_IRQ_CONTROL_JABBER_IE_MSK                                           (0x8000)
+#define PHY_IRQ_CONTROL_JABBER_IE_OFST                                          (15)
+
+#define PHY_DIAGNOSTIC                                                                          (18)
+#define PHY_DIAGNOSTIC_RX_LOCK_MSK                                                      (0x100)
+#define PHY_DIAGNOSTIC_RX_LOCK_OFST                                                     (8)
+#define PHY_DIAGNOSTIC_RX_PASS_MSK                                                      (0x200)
+#define PHY_DIAGNOSTIC_RX_PASS_OFST                                                     (9)
+#define PHY_DIAGNOSTIC_RATE_MSK                                                         (0x400)
+#define PHY_DIAGNOSTIC_RATE_OFST                                                        (10)
+#define PHY_DIAGNOSTIC_DPLX_MSK                                                         (0x800)
+#define PHY_DIAGNOSTIC_DPLX_OFST                                                        (11)
+#define PHY_DIAGNOSTIC_ANEGF_MSK                                                        (0x1000)
+#define PHY_DIAGNOSTIC_ANEGF_OFST                                                       (12)
+
+#endif /* __TDKPHY_H */
diff --git a/include/asm-arm/arch-epxa10db/timer00.h b/include/asm-arm/arch-epxa10db/timer00.h
new file mode 100644
index 000000000000..52a3fb58b59d
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/timer00.h
@@ -0,0 +1,98 @@
+/*
+ *  
+ *  This file contains the register definitions for the Excalibur
+ *  Timer TIMER00.
+ *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TIMER00_H
+#define __TIMER00_H
+
+/*
+ * Register definitions for the timers
+ */
+
+
+#define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x00 ))
+#define TIMER0_CR_B_MSK (0x20)
+#define TIMER0_CR_B_OFST (0x5)
+#define TIMER0_CR_S_MSK  (0x10)
+#define TIMER0_CR_S_OFST (0x4)
+#define TIMER0_CR_CI_MSK (0x08)
+#define TIMER0_CR_CI_OFST (0x3)
+#define TIMER0_CR_IE_MSK (0x04)
+#define TIMER0_CR_IE_OFST (0x2)
+#define TIMER0_CR_MODE_MSK (0x3)
+#define TIMER0_CR_MODE_OFST (0)
+#define TIMER0_CR_MODE_FREE (0)
+#define TIMER0_CR_MODE_ONE  (1)
+#define TIMER0_CR_MODE_INTVL (2)
+
+#define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x00 ))
+#define TIMER0_SR_B_MSK (0x20)
+#define TIMER0_SR_B_OFST (0x5)
+#define TIMER0_SR_S_MSK  (0x10)
+#define TIMER0_SR_S_OFST (0x4)
+#define TIMER0_SR_CI_MSK (0x08)
+#define TIMER0_SR_CI_OFST (0x3)
+#define TIMER0_SR_IE_MSK (0x04)
+#define TIMER0_SR_IE_OFST (0x2)
+#define TIMER0_SR_MODE_MSK (0x3)
+#define TIMER0_SR_MODE_OFST (0)
+#define TIMER0_SR_MODE_FREE (0)
+#define TIMER0_SR_MODE_ONE  (1)
+#define TIMER0_SR_MODE_INTVL (2)
+
+#define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x010 ))
+#define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x020 ))
+#define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x030 ))
+
+#define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x40 ))
+#define TIMER1_CR_B_MSK (0x20)
+#define TIMER1_CR_B_OFST (0x5)
+#define TIMER1_CR_S_MSK  (0x10)
+#define TIMER1_CR_S_OFST (0x4)
+#define TIMER1_CR_CI_MSK (0x08)
+#define TIMER1_CR_CI_OFST (0x3)
+#define TIMER1_CR_IE_MSK (0x04)
+#define TIMER1_CR_IE_OFST (0x2)
+#define TIMER1_CR_MODE_MSK (0x3)
+#define TIMER1_CR_MODE_OFST (0)
+#define TIMER1_CR_MODE_FREE (0)
+#define TIMER1_CR_MODE_ONE  (1)
+#define TIMER1_CR_MODE_INTVL (2)
+
+#define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x40 ))
+#define TIMER1_SR_B_MSK (0x20)
+#define TIMER1_SR_B_OFST (0x5)
+#define TIMER1_SR_S_MSK  (0x10)
+#define TIMER1_SR_S_OFST (0x4)
+#define TIMER1_SR_CI_MSK (0x08)
+#define TIMER1_SR_CI_OFST (0x3)
+#define TIMER1_SR_IE_MSK (0x04)
+#define TIMER1_SR_IE_OFST (0x2)
+#define TIMER1_SR_MODE_MSK (0x3)
+#define TIMER1_SR_MODE_OFST (0)
+#define TIMER1_SR_MODE_FREE (0)
+#define TIMER1_SR_MODE_ONE  (1)
+#define TIMER1_SR_MODE_INTVL (2)
+
+#define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x050 ))
+#define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x060 ))
+#define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR  + 0x070 ))
+
+#endif /* __TIMER00_H */
diff --git a/include/asm-arm/arch-epxa10db/timex.h b/include/asm-arm/arch-epxa10db/timex.h
new file mode 100644
index 000000000000..b87a75fc9589
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/timex.h
@@ -0,0 +1,26 @@
+/*
+ *  linux/include/asm-arm/arch-epxa10db/timex.h
+ *
+ *  Excalibur timex specifications
+ *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * ??
+ */
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h
new file mode 100644
index 000000000000..5abd8914d68b
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/uart00.h
@@ -0,0 +1,181 @@
+/* *
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __UART00_H
+#define __UART00_H
+
+/*
+ * Register definitions for the UART
+ */
+
+#define UART_TX_FIFO_SIZE      (15)
+
+#define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x00 ))
+#define UART_RSR_RX_LEVEL_MSK (0x1f)
+#define UART_RSR_RX_LEVEL_OFST (0)
+#define UART_RSR_RE_MSK (0x80)
+#define UART_RSR_RE_OFST (7)
+
+#define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x04 ))
+#define UART_RDS_BI_MSK (0x8)
+#define UART_RDS_BI_OFST (4)
+#define UART_RDS_FE_MSK (0x4)
+#define UART_RDS_FE_OFST (2)
+#define UART_RDS_PE_MSK (0x2)
+#define UART_RDS_PE_OFST (1)
+#define UART_RDS_OE_MSK (0x1)
+#define UART_RDS_OE_OFST (0)
+
+#define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x08 ))
+#define UART_RD_RX_DATA_MSK (0xff)
+#define UART_RD_RX_DATA_OFST (0)
+
+#define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x0c ))
+#define UART_TSR_TX_LEVEL_MSK (0x1f)
+#define UART_TSR_TX_LEVEL_OFST (0)
+#define UART_TSR_TXI_MSK (0x80)
+#define UART_TSR_TXI_OFST (7)
+
+#define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x10 ))
+#define UART_TD_TX_DATA_MSK (0xff)
+#define UART_TD_TX_DATA_OFST (0)
+
+#define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x14 ))
+#define UART_FCR_RX_THR_MSK (0xd0)
+#define UART_FCR_RX_THR_OFST (5)
+#define UART_FCR_RX_THR_1 (0x00)
+#define UART_FCR_RX_THR_2 (0x20)
+#define UART_FCR_RX_THR_4 (0x40)
+#define UART_FCR_RX_THR_6 (0x60)
+#define UART_FCR_RX_THR_8 (0x80)
+#define UART_FCR_RX_THR_10 (0xa0)
+#define UART_FCR_RX_THR_12 (0xc0)
+#define UART_FCR_RX_THR_14 (0xd0)
+#define UART_FCR_TX_THR_MSK (0x1c)
+#define UART_FCR_TX_THR_OFST (2)
+#define UART_FCR_TX_THR_0 (0x00)
+#define UART_FCR_TX_THR_2 (0x04)
+#define UART_FCR_TX_THR_4 (0x08)
+#define UART_FCR_TX_THR_8 (0x0c)
+#define UART_FCR_TX_THR_10 (0x10)
+#define UART_FCR_TX_THR_12 (0x14)
+#define UART_FCR_TX_THR_14 (0x18)
+#define UART_FCR_TX_THR_15 (0x1c)
+#define UART_FCR_RC_MSK (0x02)
+#define UART_FCR_RC_OFST (1)
+#define UART_FCR_TC_MSK (0x01)
+#define UART_FCR_TC_OFST (0)
+
+#define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x18 ))
+#define UART_IES_ME_MSK (0x8)
+#define UART_IES_ME_OFST (3)
+#define UART_IES_TIE_MSK (0x4)
+#define UART_IES_TIE_OFST (2)
+#define UART_IES_TE_MSK (0x2)
+#define UART_IES_TE_OFST (1)
+#define UART_IES_RE_MSK (0x1)
+#define UART_IES_RE_OFST (0)
+
+#define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x1c ))
+#define UART_IEC_ME_MSK (0x8)
+#define UART_IEC_ME_OFST (3)
+#define UART_IEC_TIE_MSK (0x4)
+#define UART_IEC_TIE_OFST (2)
+#define UART_IEC_TE_MSK (0x2)
+#define UART_IEC_TE_OFST (1)
+#define UART_IEC_RE_MSK (0x1)
+#define UART_IEC_RE_OFST (0)
+
+#define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x20 ))
+#define UART_ISR_MI_MSK (0x8)
+#define UART_ISR_MI_OFST (3)
+#define UART_ISR_TII_MSK (0x4)
+#define UART_ISR_TII_OFST (2)
+#define UART_ISR_TI_MSK (0x2)
+#define UART_ISR_TI_OFST (1)
+#define UART_ISR_RI_MSK (0x1)
+#define UART_ISR_RI_OFST (0)
+
+#define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x24 ))
+#define UART_IID_IID_MSK (0x7)
+#define UART_IID_IID_OFST (0)
+
+#define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x28 ))
+#define UART_MC_OE_MSK (0x40)
+#define UART_MC_OE_OFST (6)
+#define UART_MC_SP_MSK (0x20)
+#define UART_MC_SP_OFST (5)
+#define UART_MC_EP_MSK (0x10)
+#define UART_MC_EP_OFST (4)
+#define UART_MC_PE_MSK (0x08)
+#define UART_MC_PE_OFST (3)
+#define UART_MC_ST_MSK (0x04)
+#define UART_MC_ST_ONE (0x0)
+#define UART_MC_ST_TWO (0x04)
+#define UART_MC_ST_OFST (2)
+#define UART_MC_CLS_MSK (0x03)
+#define UART_MC_CLS_OFST (0)
+#define UART_MC_CLS_CHARLEN_5 (0)
+#define UART_MC_CLS_CHARLEN_6 (1)
+#define UART_MC_CLS_CHARLEN_7 (2)
+#define UART_MC_CLS_CHARLEN_8 (3)
+
+#define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x2c ))
+#define UART_MCR_AC_MSK (0x80)
+#define UART_MCR_AC_OFST (7)
+#define UART_MCR_AR_MSK (0x40)
+#define UART_MCR_AR_OFST (6)
+#define UART_MCR_BR_MSK (0x20)
+#define UART_MCR_BR_OFST (5)
+#define UART_MCR_LB_MSK (0x10)
+#define UART_MCR_LB_OFST (4)
+#define UART_MCR_DCD_MSK (0x08)
+#define UART_MCR_DCD_OFST (3)
+#define UART_MCR_RI_MSK (0x04)
+#define UART_MCR_RI_OFST (2)
+#define UART_MCR_DTR_MSK (0x02)
+#define UART_MCR_DTR_OFST (1)
+#define UART_MCR_RTS_MSK (0x01)
+#define UART_MCR_RTS_OFST (0)
+
+#define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x30 ))
+#define UART_MSR_DCD_MSK (0x80)
+#define UART_MSR_DCD_OFST (7)
+#define UART_MSR_RI_MSK (0x40)
+#define UART_MSR_RI_OFST (6)
+#define UART_MSR_DSR_MSK (0x20)
+#define UART_MSR_DSR_OFST (5)
+#define UART_MSR_CTS_MSK (0x10)
+#define UART_MSR_CTS_OFST (4)
+#define UART_MSR_DDCD_MSK (0x08)
+#define UART_MSR_DDCD_OFST (3)
+#define UART_MSR_TERI_MSK (0x04)
+#define UART_MSR_TERI_OFST (2)
+#define UART_MSR_DDSR_MSK (0x02)
+#define UART_MSR_DDSR_OFST (1)
+#define UART_MSR_DCTS_MSK (0x01)
+#define UART_MSR_DCTS_OFST (0)
+
+#define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x34 ))
+#define UART_DIV_LO_DIV_MSK (0xff)
+#define UART_DIV_LO_DIV_OFST (0)
+
+#define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR  + 0x38 ))
+#define UART_DIV_HI_DIV_MSK (0xff)
+#define UART_DIV_HI_DIV_OFST (0)
+
+#endif /* __UART00_H */
diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h
new file mode 100644
index 000000000000..d33ad6a93749
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/uncompress.h
@@ -0,0 +1,54 @@
+/*
+ *  linux/include/asm-arm/arch-epxa10db/uncompress.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2001 Altera Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#include "asm/arch/platform.h"
+#include "asm/arch/hardware.h"
+#define UART00_TYPE (volatile unsigned int*)
+#include "asm/arch/uart00.h"
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                while ((*UART_TSR(EXC_UART00_BASE) &
+                       UART_TSR_TX_LEVEL_MSK)==15)
+                        barrier();
+
+                *UART_TD(EXC_UART00_BASE) = *s;
+
+                if (*s == '\n') {
+                        while ((*UART_TSR(EXC_UART00_BASE) &
+                               UART_TSR_TX_LEVEL_MSK)==15)
+                                barrier();
+
+                        *UART_TD(EXC_UART00_BASE) = '\r';
+                }
+                s++;
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-epxa10db/vmalloc.h
new file mode 100644
index 000000000000..d31ef8584760
--- /dev/null
+++ b/include/asm-arm/arch-epxa10db/vmalloc.h
@@ -0,0 +1,31 @@
+/*
+ *  linux/include/asm-arm/arch-epxa10db/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-h720x/boards.h b/include/asm-arm/arch-h720x/boards.h
new file mode 100644
index 000000000000..8021f81f0742
--- /dev/null
+++ b/include/asm-arm/arch-h720x/boards.h
@@ -0,0 +1,53 @@
+/*
+ * linux/include/asm-arm/arch-h720x/boards.h
+ *
+ * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * This file contains the board specific defines for various devices
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
+#error Do not include this file directly. Include asm/hardware.h instead !
+#endif
+
+/* Hynix H7202 developer board specific device defines */
+#ifdef CONFIG_ARCH_H7202
+
+/* FLASH */
+#define FLASH_VIRT              0xd0000000
+#define FLASH_PHYS              0x00000000
+#define FLASH_SIZE              0x02000000
+
+/* onboard LAN controller */
+# define ETH0_PHYS              0x08000000
+
+/* Touch screen defines */
+/* GPIO Port */
+#define PEN_GPIO                GPIO_B_VIRT
+/* Bitmask for pen down interrupt */
+#define PEN_INT_BIT             (1<<7)
+/* Bitmask for pen up interrupt */
+#define PEN_ENA_BIT             (1<<6)
+/* pen up interrupt */
+#define IRQ_PEN                 IRQ_MUX_GPIOB(7)
+
+#endif
+
+/* Hynix H7201 developer board specific device defines */
+#if defined (CONFIG_ARCH_H7201)
+/* ROM DISK SPACE */
+#define ROM_DISK_BASE           0xc1800000
+#define ROM_DISK_START          0x41800000
+#define ROM_DISK_SIZE           0x00700000
+
+/* SRAM DISK SPACE */
+#define SRAM_DISK_BASE          0xf1000000
+#define SRAM_DISK_START         0x04000000
+#define SRAM_DISK_SIZE          0x00400000
+#endif
+
diff --git a/include/asm-arm/arch-h720x/debug-macro.S b/include/asm-arm/arch-h720x/debug-macro.S
new file mode 100644
index 000000000000..82822d362733
--- /dev/null
+++ b/include/asm-arm/arch-h720x/debug-macro.S
@@ -0,0 +1,40 @@
+/* linux/include/asm-arm/arch-h720x/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .equ    io_virt, IO_BASE
+                .equ    io_phys, IO_START
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                @ MMU enabled?
+                moveq   \rx, #io_phys          @ physical base address
+                movne   \rx, #io_virt          @ virtual address
+                add     \rx, \rx, #0x00020000   @ UART1
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x0]        @ UARTDR
+
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5           @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3           @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-h720x/dma.h b/include/asm-arm/arch-h720x/dma.h
new file mode 100644
index 000000000000..bfc6636679f7
--- /dev/null
+++ b/include/asm-arm/arch-h720x/dma.h
@@ -0,0 +1,26 @@
+/*
+ * linux/include/asm-arm/arch-h720x/dma.h
+ *
+ * Architecture DMA routes
+ *
+ * Copyright (C) 1997.1998 Russell King
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS         0xd0000000
+
+#if defined (CONFIG_CPU_H7201)
+#define MAX_DMA_CHANNELS        3
+#elif defined (CONFIG_CPU_H7202)
+#define MAX_DMA_CHANNELS        4
+#else
+#error processor definition missmatch
+#endif
+
+#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-h720x/entry-macro.S b/include/asm-arm/arch-h720x/entry-macro.S
new file mode 100644
index 000000000000..8f165648e2af
--- /dev/null
+++ b/include/asm-arm/arch-h720x/entry-macro.S
@@ -0,0 +1,60 @@
+/*
+ * include/asm-arm/arch-h720x/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Hynix HMS720x based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
+                @ we could use the id register on H7202, but this is not
+                @ properly updated when we come back from asm_do_irq
+                @ without a previous return from interrupt
+                @ (see loops below in irq_svc, irq_usr)
+                @ We see unmasked pending ints only, as the masked pending ints
+                @ are not visible here
+
+                mov     \base, #0xf0000000             @ base register
+                orr     \base, \base, #0x24000         @ irqbase
+                ldr     \irqstat, [\base, #0x04]        @ get interrupt status
+#if defined (CONFIG_CPU_H7201)
+                ldr     \tmp, =0x001fffff
+#else
+                mvn     \tmp, #0xc0000000
+#endif
+                and     \irqstat, \irqstat, \tmp        @ mask out unused ints
+                mov     \irqnr, #0
+
+                mov     \tmp, #0xff00
+                orr     \tmp, \tmp, #0xff
+                tst     \irqstat, \tmp
+                addeq   \irqnr, \irqnr, #16
+                moveq   \irqstat, \irqstat, lsr #16
+                tst     \irqstat, #255
+                addeq   \irqnr, \irqnr, #8
+                moveq   \irqstat, \irqstat, lsr #8
+                tst     \irqstat, #15
+                addeq   \irqnr, \irqnr, #4
+                moveq   \irqstat, \irqstat, lsr #4
+                tst     \irqstat, #3
+                addeq   \irqnr, \irqnr, #2
+                moveq   \irqstat, \irqstat, lsr #2
+                tst     \irqstat, #1
+                addeq   \irqnr, \irqnr, #1
+                moveq   \irqstat, \irqstat, lsr #1
+                tst     \irqstat, #1                   @ bit 0 should be set
+                .endm
+
+                .macro  irq_prio_table
+                .endm
+
+#else
+#error hynix processor selection missmatch
+#endif
+
diff --git a/include/asm-arm/arch-h720x/h7201-regs.h b/include/asm-arm/arch-h720x/h7201-regs.h
new file mode 100644
index 000000000000..49d4f6bd3080
--- /dev/null
+++ b/include/asm-arm/arch-h720x/h7201-regs.h
@@ -0,0 +1,67 @@
+/*
+ * linux/include/asm-arm/arch-h720x/h7201-regs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#define SERIAL2_VIRT            (IO_VIRT + 0x50100)
+#define SERIAL3_VIRT            (IO_VIRT + 0x50200)
+
+/*
+ * PCMCIA
+ */
+#define PCMCIA0_ATT_BASE        0xe5000000
+#define PCMCIA0_ATT_SIZE        0x00200000
+#define PCMCIA0_ATT_START       0x20000000
+#define PCMCIA0_MEM_BASE        0xe5200000
+#define PCMCIA0_MEM_SIZE        0x00200000
+#define PCMCIA0_MEM_START       0x24000000
+#define PCMCIA0_IO_BASE         0xe5400000
+#define PCMCIA0_IO_SIZE         0x00200000
+#define PCMCIA0_IO_START        0x28000000
+
+#define PCMCIA1_ATT_BASE        0xe5600000
+#define PCMCIA1_ATT_SIZE        0x00200000
+#define PCMCIA1_ATT_START       0x30000000
+#define PCMCIA1_MEM_BASE        0xe5800000
+#define PCMCIA1_MEM_SIZE        0x00200000
+#define PCMCIA1_MEM_START       0x34000000
+#define PCMCIA1_IO_BASE         0xe5a00000
+#define PCMCIA1_IO_SIZE         0x00200000
+#define PCMCIA1_IO_START        0x38000000
+
+#define PRIME3C_BASE            0xf0050000
+#define PRIME3C_SIZE            0x00001000
+#define PRIME3C_START           0x10000000
+
+/* VGA Controller */
+#define VGA_RAMBASE             0x50
+#define VGA_TIMING0             0x60
+#define VGA_TIMING1             0x64
+#define VGA_TIMING2             0x68
+#define VGA_TIMING3             0x6c
+
+#define LCD_CTRL_VGA_ENABLE     0x00000100
+#define LCD_CTRL_VGA_BPP_MASK   0x00000600
+#define LCD_CTRL_VGA_4BPP       0x00000000
+#define LCD_CTRL_VGA_8BPP       0x00000200
+#define LCD_CTRL_VGA_16BPP      0x00000300
+#define LCD_CTRL_SHARE_DMA      0x00000800
+#define LCD_CTRL_VDE            0x00100000
+#define LCD_CTRL_LPE            0x00400000      /* LCD Power enable */
+#define LCD_CTRL_BLE            0x00800000      /* LCD backlight enable */
+
+#define VGA_PALETTE_BASE        (IO_VIRT + 0x10800)
diff --git a/include/asm-arm/arch-h720x/h7202-regs.h b/include/asm-arm/arch-h720x/h7202-regs.h
new file mode 100644
index 000000000000..43d8ba8a6013
--- /dev/null
+++ b/include/asm-arm/arch-h720x/h7202-regs.h
@@ -0,0 +1,155 @@
+/*
+ * linux/include/asm-arm/arch-h720x/h7202-regs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#define SERIAL2_OFS             0x2d000
+#define SERIAL2_BASE            (IO_PHYS + SERIAL2_OFS)
+#define SERIAL2_VIRT            (IO_VIRT + SERIAL2_OFS)
+#define SERIAL3_OFS             0x2e000
+#define SERIAL3_BASE            (IO_PHYS + SERIAL3_OFS)
+#define SERIAL3_VIRT            (IO_VIRT + SERIAL3_OFS)
+
+/* Matrix Keyboard Controller */
+#define KBD_VIRT                (IO_VIRT + 0x22000)
+#define KBD_KBCR                0x00
+#define KBD_KBSC                0x04
+#define KBD_KBTR                0x08
+#define KBD_KBVR0               0x0C
+#define KBD_KBVR1               0x10
+#define KBD_KBSR                0x18
+
+#define KBD_KBCR_SCANENABLE     (1 << 7)
+#define KBD_KBCR_NPOWERDOWN     (1 << 2)
+#define KBD_KBCR_CLKSEL_MASK    (3)
+#define KBD_KBCR_CLKSEL_PCLK2   0x0
+#define KBD_KBCR_CLKSEL_PCLK128 0x1
+#define KBD_KBCR_CLKSEL_PCLK256 0x2
+#define KBD_KBCR_CLKSEL_PCLK512 0x3
+
+#define KBD_KBSR_INTR           (1 << 0)
+#define KBD_KBSR_WAKEUP         (1 << 1)
+
+/* USB device controller */
+
+#define USBD_BASE               (IO_VIRT + 0x12000)
+#define USBD_LENGTH             0x3C
+
+#define USBD_GCTRL              0x00
+#define USBD_EPCTRL             0x04
+#define USBD_INTMASK            0x08
+#define USBD_INTSTAT            0x0C
+#define USBD_PWR                0x10
+#define USBD_DMARXTX            0x14
+#define USBD_DEVID              0x18
+#define USBD_DEVCLASS           0x1C
+#define USBD_INTCLASS           0x20
+#define USBD_SETUP0             0x24
+#define USBD_SETUP1             0x28
+#define USBD_ENDP0RD            0x2C
+#define USBD_ENDP0WT            0x30
+#define USBD_ENDP1RD            0x34
+#define USBD_ENDP2WT            0x38
+
+/* PS/2 port */
+#define PSDATA 0x00
+#define PSSTAT 0x04
+#define PSSTAT_TXEMPTY (1<<0)
+#define PSSTAT_TXBUSY (1<<1)
+#define PSSTAT_RXFULL (1<<2)
+#define PSSTAT_RXBUSY (1<<3)
+#define PSSTAT_CLKIN (1<<4)
+#define PSSTAT_DATAIN (1<<5)
+#define PSSTAT_PARITY (1<<6)
+
+#define PSCONF 0x08
+#define PSCONF_ENABLE (1<<0)
+#define PSCONF_TXINTEN (1<<2)
+#define PSCONF_RXINTEN (1<<3)
+#define PSCONF_FORCECLKLOW (1<<4)
+#define PSCONF_FORCEDATLOW (1<<5)
+#define PSCONF_LCE (1<<6)
+
+#define PSINTR 0x0C
+#define PSINTR_TXINT (1<<0)
+#define PSINTR_RXINT (1<<1)
+#define PSINTR_PAR (1<<2)
+#define PSINTR_RXTO (1<<3)
+#define PSINTR_TXTO (1<<4)
+
+#define PSTDLO 0x10 /* clk low before start transmission */
+#define PSTPRI 0x14 /* PRI clock */
+#define PSTXMT 0x18 /* maximum transmission time */
+#define PSTREC 0x20 /* maximum receive time */
+#define PSPWDN 0x3c
+
+/* ADC converter */
+#define ADC_BASE                (IO_VIRT + 0x29000)
+#define ADC_CR                  0x00
+#define ADC_TSCTRL              0x04
+#define ADC_BT_CTRL             0x08
+#define ADC_MC_CTRL             0x0C
+#define ADC_STATUS              0x10
+
+/* ADC control register bits */
+#define ADC_CR_PW_CTRL          0x80
+#define ADC_CR_DIRECTC          0x04
+#define ADC_CR_CONTIME_NO       0x00
+#define ADC_CR_CONTIME_2        0x04
+#define ADC_CR_CONTIME_4        0x08
+#define ADC_CR_CONTIME_ADE      0x0c
+#define ADC_CR_LONGCALTIME      0x01
+
+/* ADC touch panel register bits */
+#define ADC_TSCTRL_ENABLE       0x80
+#define ADC_TSCTRL_INTR         0x40
+#define ADC_TSCTRL_SWBYPSS      0x20
+#define ADC_TSCTRL_SWINVT       0x10
+#define ADC_TSCTRL_S400         0x03
+#define ADC_TSCTRL_S200         0x02
+#define ADC_TSCTRL_S100         0x01
+#define ADC_TSCTRL_S50          0x00
+
+/* ADC Interrupt Status Register bits */
+#define ADC_STATUS_TS_BIT       0x80
+#define ADC_STATUS_MBT_BIT      0x40
+#define ADC_STATUS_BBT_BIT      0x20
+#define ADC_STATUS_MIC_BIT      0x10
+
+/* Touch data registers */
+#define ADC_TS_X0X1             0x30
+#define ADC_TS_X2X3             0x34
+#define ADC_TS_Y0Y1             0x38
+#define ADC_TS_Y2Y3             0x3c
+#define ADC_TS_X4X5             0x40
+#define ADC_TS_X6X7             0x44
+#define ADC_TS_Y4Y5             0x48
+#define ADC_TS_Y6Y7             0x50
+
+/* battery data */
+#define ADC_MB_DATA             0x54
+#define ADC_BB_DATA             0x58
+
+/* Sound data register */
+#define ADC_SD_DAT0             0x60
+#define ADC_SD_DAT1             0x64
+#define ADC_SD_DAT2             0x68
+#define ADC_SD_DAT3             0x6c
+#define ADC_SD_DAT4             0x70
+#define ADC_SD_DAT5             0x74
+#define ADC_SD_DAT6             0x78
+#define ADC_SD_DAT7             0x7c
diff --git a/include/asm-arm/arch-h720x/hardware.h b/include/asm-arm/arch-h720x/hardware.h
new file mode 100644
index 000000000000..dfb778906a9f
--- /dev/null
+++ b/include/asm-arm/arch-h720x/hardware.h
@@ -0,0 +1,192 @@
+/*
+ * linux/include/asm-arm/arch-h720x/hardware.h
+ *
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *
+ * This file contains the hardware definitions of the h720x processors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Do not add implementations specific defines here. This files contains
+ * only defines of the onchip peripherals. Add those defines to boards.h,
+ * which is included by this file.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#define IOCLK (3686400L)
+
+/* Onchip peripherals */
+
+#define IO_VIRT                 0xf0000000      /* IO peripherals */
+#define IO_PHYS                 0x80000000
+#define IO_SIZE                 0x00050000
+
+#ifdef CONFIG_CPU_H7202
+#include "h7202-regs.h"
+#elif defined CONFIG_CPU_H7201
+#include "h7201-regs.h"
+#else
+#error machine definition mismatch
+#endif
+
+/* Macro to access the CPU IO */
+#define CPU_IO(x) (*(volatile u32*)(x))
+
+/* Macro to access general purpose regs (base, offset) */
+#define CPU_REG(x,y) CPU_IO(x+y)
+
+/* Macro to access irq related regs */
+#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
+
+/* CPU registers */
+/* general purpose I/O */
+#define GPIO_VIRT(x)            (IO_VIRT + 0x23000 + ((x)<<5))
+#define GPIO_A_VIRT             (GPIO_VIRT(0))
+#define GPIO_B_VIRT             (GPIO_VIRT(1))
+#define GPIO_C_VIRT             (GPIO_VIRT(2))
+#define GPIO_D_VIRT             (GPIO_VIRT(3))
+#define GPIO_E_VIRT             (GPIO_VIRT(4))
+#define GPIO_AMULSEL            (GPIO_VIRT(0) + 0xA4)
+
+#define AMULSEL_USIN2   (1<<5)
+#define AMULSEL_USOUT2  (1<<6)
+#define AMULSEL_USIN3   (1<<13)
+#define AMULSEL_USOUT3  (1<<14)
+#define AMULSEL_IRDIN   (1<<15)
+#define AMULSEL_IRDOUT  (1<<7)
+
+/* Register offsets general purpose I/O */
+#define GPIO_DATA               0x00
+#define GPIO_DIR                0x04
+#define GPIO_MASK               0x08
+#define GPIO_STAT               0x0C
+#define GPIO_EDGE               0x10
+#define GPIO_CLR                0x14
+#define GPIO_POL                0x18
+#define GPIO_EN                 0x1C
+
+/*interrupt controller */
+#define IRQC_VIRT               (IO_VIRT + 0x24000)
+/* register offset interrupt controller */
+#define IRQC_IER                0x00
+#define IRQC_ISR                0x04
+
+/* timer unit */
+#define TIMER_VIRT              (IO_VIRT + 0x25000)
+/* Register offsets timer unit */
+#define TM0_PERIOD              0x00
+#define TM0_COUNT               0x08
+#define TM0_CTRL                0x10
+#define TM1_PERIOD              0x20
+#define TM1_COUNT               0x28
+#define TM1_CTRL                0x30
+#define TM2_PERIOD              0x40
+#define TM2_COUNT               0x48
+#define TM2_CTRL                0x50
+#define TIMER_TOPCTRL           0x60
+#define TIMER_TOPSTAT           0x64
+#define T64_COUNTL              0x80
+#define T64_COUNTH              0x84
+#define T64_CTRL                0x88
+#define T64_BASEL               0x94
+#define T64_BASEH               0x98
+/* Bitmaks timer unit TOPSTAT reg */
+#define TSTAT_T0INT             0x1
+#define TSTAT_T1INT             0x2
+#define TSTAT_T2INT             0x4
+#define TSTAT_T3INT             0x8
+/* Bit description of TMx_CTRL register */
+#define TM_START                0x1
+#define TM_REPEAT               0x2
+#define TM_RESET                0x4
+/* Bit description of TIMER_CTRL register */
+#define ENABLE_TM0_INTR         0x1
+#define ENABLE_TM1_INTR         0x2
+#define ENABLE_TM2_INTR         0x4
+#define TIMER_ENABLE_BIT        0x8
+#define ENABLE_TIMER64          0x10
+#define ENABLE_TIMER64_INT      0x20
+
+/* PMU & PLL */
+#define PMU_BASE                (IO_VIRT + 0x1000)
+#define PMU_MODE                0x00
+#define PMU_STAT                0x20
+#define PMU_PLL_CTRL            0x28
+
+/* PMU Mode bits */
+#define PMU_MODE_SLOW           0x00
+#define PMU_MODE_RUN            0x01
+#define PMU_MODE_IDLE           0x02
+#define PMU_MODE_SLEEP          0x03
+#define PMU_MODE_INIT           0x04
+#define PMU_MODE_DEEPSLEEP      0x07
+#define PMU_MODE_WAKEUP         0x08
+
+/* PMU ... */
+#define PLL_2_EN                0x8000
+#define PLL_1_EN                0x4000
+#define PLL_3_MUTE              0x0080
+
+/* Control bits for PMU/ PLL */
+#define PMU_WARMRESET           0x00010000
+#define PLL_CTRL_MASK23         0x000080ff
+
+/* LCD Controller */
+#define LCD_BASE                (IO_VIRT + 0x10000)
+#define LCD_CTRL                0x00
+#define LCD_STATUS              0x04
+#define LCD_STATUS_M            0x08
+#define LCD_INTERRUPT           0x0C
+#define LCD_DBAR                0x10
+#define LCD_DCAR                0x14
+#define LCD_TIMING0             0x20
+#define LCD_TIMING1             0x24
+#define LCD_TIMING2             0x28
+#define LCD_TEST                0x40
+
+/* LCD Control Bits */
+#define LCD_CTRL_LCD_ENABLE     0x00000001
+/* Bits per pixel */
+#define LCD_CTRL_LCD_BPP_MASK   0x00000006
+#define LCD_CTRL_LCD_4BPP       0x00000000
+#define LCD_CTRL_LCD_8BPP       0x00000002
+#define LCD_CTRL_LCD_16BPP      0x00000004
+#define LCD_CTRL_LCD_BW         0x00000008
+#define LCD_CTRL_LCD_TFT        0x00000010
+#define LCD_CTRL_BGR            0x00001000
+#define LCD_CTRL_LCD_VCOMP      0x00080000
+#define LCD_CTRL_LCD_MONO8      0x00200000
+#define LCD_CTRL_LCD_PWR        0x00400000
+#define LCD_CTRL_LCD_BLE        0x00800000
+#define LCD_CTRL_LDBUSEN        0x01000000
+
+/* Palette */
+#define LCD_PALETTE_BASE        (IO_VIRT + 0x10400)
+
+/* Serial ports */
+#define SERIAL0_OFS             0x20000
+#define SERIAL0_VIRT            (IO_VIRT + SERIAL0_OFS)
+#define SERIAL0_BASE            (IO_PHYS + SERIAL0_OFS)
+
+#define SERIAL1_OFS             0x21000
+#define SERIAL1_VIRT            (IO_VIRT + SERIAL1_OFS)
+#define SERIAL1_BASE            (IO_PHYS + SERIAL1_OFS)
+
+#define SERIAL_ENABLE           0x30
+#define SERIAL_ENABLE_EN        (1<<0)
+
+/* General defines to pacify gcc */
+#define PCIO_BASE               (0)     /* for inb, outb and friends */
+#define PCIO_VIRT               PCIO_BASE
+
+#define __ASM_ARCH_HARDWARE_INCMACH_H
+#include "boards.h"
+#undef __ASM_ARCH_HARDWARE_INCMACH_H
+
+#endif                          /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-h720x/io.h b/include/asm-arm/arch-h720x/io.h
new file mode 100644
index 000000000000..68814828c9a7
--- /dev/null
+++ b/include/asm-arm/arch-h720x/io.h
@@ -0,0 +1,24 @@
+/*
+ * linux/include/asm-arm/arch-h720x/io.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *
+ *  09-19-2001  JJKIM
+ *              Created from linux/include/asm-arm/arch-l7200/io.h
+ *
+ *  03-27-2003  Robert Schwebel <r.schwebel@pengutronix.de>:
+ *              re-unified header files for h720x
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <asm/arch/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/include/asm-arm/arch-h720x/irq.h b/include/asm-arm/arch-h720x/irq.h
new file mode 100644
index 000000000000..b3821e957aa4
--- /dev/null
+++ b/include/asm-arm/arch-h720x/irq.h
@@ -0,0 +1,14 @@
+/*
+ * include/asm-arm/arch-h720x/irq.h
+ *
+ * Copyright (C) 2000-2002 Jungjun Kim
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ */
+
+#ifndef __ASM_ARCH_IRQ_H
+#define __ASM_ARCH_IRQ_H
+
+extern void __init h720x_init_irq (void);
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-h720x/irqs.h b/include/asm-arm/arch-h720x/irqs.h
new file mode 100644
index 000000000000..8244413988be
--- /dev/null
+++ b/include/asm-arm/arch-h720x/irqs.h
@@ -0,0 +1,116 @@
+/*
+ * linux/include/asm-arm/arch-h720x/irqs.h
+ *
+ * Copyright (C) 2000 Jungjun Kim
+ *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
+ *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
+ *
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#if defined (CONFIG_CPU_H7201)
+
+#define IRQ_PMU         0               /* 0x000001 */
+#define IRQ_DMA         1               /* 0x000002 */
+#define IRQ_LCD         2               /* 0x000004 */
+#define IRQ_VGA         3               /* 0x000008 */
+#define IRQ_PCMCIA1     4               /* 0x000010 */
+#define IRQ_PCMCIA2     5               /* 0x000020 */
+#define IRQ_AFE         6               /* 0x000040 */
+#define IRQ_AIC         7               /* 0x000080 */
+#define IRQ_KEYBOARD    8               /* 0x000100 */
+#define IRQ_TIMER0      9               /* 0x000200 */
+#define IRQ_RTC         10              /* 0x000400 */
+#define IRQ_SOUND       11              /* 0x000800 */
+#define IRQ_USB         12              /* 0x001000 */
+#define IRQ_IrDA        13              /* 0x002000 */
+#define IRQ_UART0       14              /* 0x004000 */
+#define IRQ_UART1       15              /* 0x008000 */
+#define IRQ_SPI         16              /* 0x010000 */
+#define IRQ_GPIOA       17              /* 0x020000 */
+#define IRQ_GPIOB       18              /* 0x040000 */
+#define IRQ_GPIOC       19              /* 0x080000 */
+#define IRQ_GPIOD       20              /* 0x100000 */
+#define IRQ_CommRX      21              /* 0x200000 */
+#define IRQ_CommTX      22              /* 0x400000 */
+#define IRQ_Soft        23              /* 0x800000 */
+
+#define NR_GLBL_IRQS    24
+
+#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
+#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
+#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
+#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
+#define NR_IRQS               IRQ_CHAINED_GPIOD(32)
+
+/* Enable mask for multiplexed interrupts */
+#define IRQ_ENA_MUX     (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
+                        | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
+
+
+#elif defined (CONFIG_CPU_H7202)
+
+#define IRQ_PMU         0               /* 0x00000001 */
+#define IRQ_DMA         1               /* 0x00000002 */
+#define IRQ_LCD         2               /* 0x00000004 */
+#define IRQ_SOUND       3               /* 0x00000008 */
+#define IRQ_I2S         4               /* 0x00000010 */
+#define IRQ_USB         5               /* 0x00000020 */
+#define IRQ_MMC         6               /* 0x00000040 */
+#define IRQ_RTC         7               /* 0x00000080 */
+#define IRQ_UART0       8               /* 0x00000100 */
+#define IRQ_UART1       9               /* 0x00000200 */
+#define IRQ_UART2       10              /* 0x00000400 */
+#define IRQ_UART3       11              /* 0x00000800 */
+#define IRQ_KBD         12              /* 0x00001000 */
+#define IRQ_PS2         13              /* 0x00002000 */
+#define IRQ_AIC         14              /* 0x00004000 */
+#define IRQ_TIMER0      15              /* 0x00008000 */
+#define IRQ_TIMERX      16              /* 0x00010000 */
+#define IRQ_WDT         17              /* 0x00020000 */
+#define IRQ_CAN0        18              /* 0x00040000 */
+#define IRQ_CAN1        19              /* 0x00080000 */
+#define IRQ_EXT0        20              /* 0x00100000 */
+#define IRQ_EXT1        21              /* 0x00200000 */
+#define IRQ_GPIOA       22              /* 0x00400000 */
+#define IRQ_GPIOB       23              /* 0x00800000 */
+#define IRQ_GPIOC       24              /* 0x01000000 */
+#define IRQ_GPIOD       25              /* 0x02000000 */
+#define IRQ_GPIOE       26              /* 0x04000000 */
+#define IRQ_COMMRX      27              /* 0x08000000 */
+#define IRQ_COMMTX      28              /* 0x10000000 */
+#define IRQ_SMC         29              /* 0x20000000 */
+#define IRQ_Soft        30              /* 0x40000000 */
+#define IRQ_RESERVED1   31              /* 0x80000000 */
+#define NR_GLBL_IRQS    32
+
+#define NR_TIMERX_IRQS  3
+
+#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
+#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
+#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
+#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
+#define IRQ_CHAINED_GPIOE(x)  (IRQ_CHAINED_GPIOD(32) + x)
+#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
+#define IRQ_TIMER1            (IRQ_CHAINED_TIMERX(0))
+#define IRQ_TIMER2            (IRQ_CHAINED_TIMERX(1))
+#define IRQ_TIMER64B          (IRQ_CHAINED_TIMERX(2))
+
+#define NR_IRQS         (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
+
+/* Enable mask for multiplexed interrupts */
+#define IRQ_ENA_MUX     (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
+                        (1<<IRQ_GPIOC)  | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
+                        (1<<IRQ_TIMERX)
+
+#else
+#error cpu definition mismatch
+#endif
+
+/* decode irq number to register number */
+#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
+#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
+
+#endif
diff --git a/include/asm-arm/arch-h720x/memory.h b/include/asm-arm/arch-h720x/memory.h
new file mode 100644
index 000000000000..5633447af268
--- /dev/null
+++ b/include/asm-arm/arch-h720x/memory.h
@@ -0,0 +1,31 @@
+/*
+ * linux/include/asm-arm/arch-h720x/memory.h
+ *
+ * Copyright (c) 2000 Jungjun Kim
+ *
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Page offset:
+ *    ( 0xc0000000UL )
+ */
+#define PHYS_OFFSET     (0x40000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ *
+ * There is something to do here later !, Mar 2000, Jungjun Kim
+ */
+
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-h720x/param.h b/include/asm-arm/arch-h720x/param.h
new file mode 100644
index 000000000000..2b80235f9847
--- /dev/null
+++ b/include/asm-arm/arch-h720x/param.h
@@ -0,0 +1,10 @@
+/*
+ * linux/include/asm-arm/arch-h720x/param.h
+ *
+ * Copyright (C) 2000 Jungjun Kim
+ */
+
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+
+#endif
diff --git a/include/asm-arm/arch-h720x/system.h b/include/asm-arm/arch-h720x/system.h
new file mode 100644
index 000000000000..0b025e227ec2
--- /dev/null
+++ b/include/asm-arm/arch-h720x/system.h
@@ -0,0 +1,31 @@
+/*
+ * linux/arch/arm/mach-h720x/system.h
+ *
+ * Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ * linux/include/asm-arm/arch-h720x/system.h
+ *
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <asm/hardware.h>
+
+static void arch_idle(void)
+{
+        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
+        __asm__ __volatile__(
+        "mov    r0, r0\n\t"
+        "mov    r0, r0");
+}
+
+
+static __inline__ void arch_reset(char mode)
+{
+        CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
+}
+
+#endif
diff --git a/include/asm-arm/arch-h720x/timex.h b/include/asm-arm/arch-h720x/timex.h
new file mode 100644
index 000000000000..48a391c4080f
--- /dev/null
+++ b/include/asm-arm/arch-h720x/timex.h
@@ -0,0 +1,15 @@
+/*
+ * linux/include/asm-arm/arch-h720x/timex.h
+ * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_TIMEX
+#define __ASM_ARCH_TIMEX
+
+#define CLOCK_TICK_RATE         3686400
+
+#endif
diff --git a/include/asm-arm/arch-h720x/uncompress.h b/include/asm-arm/arch-h720x/uncompress.h
new file mode 100644
index 000000000000..2fffacf85a01
--- /dev/null
+++ b/include/asm-arm/arch-h720x/uncompress.h
@@ -0,0 +1,39 @@
+/*
+ * linux/include/asm-arm/arch-h720x/uncompress.h
+ *
+ * Copyright (C) 2001-2002 Jungjun Kim
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <asm/arch/hardware.h>
+
+#define LSR     0x14
+#define TEMPTY  0x40
+
+static void putstr(const char *s)
+{
+        char c;
+        volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
+
+        while ( (c = *s++) != '\0') {
+                /* wait until transmit buffer is empty */
+                while((p[LSR] & TEMPTY) == 0x0);
+                /* write next character */
+                *p = c;
+
+                if(c == '\n') {
+                        while((p[LSR] & TEMPTY) == 0x0);
+                        *p = '\r';
+                }
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+
+#endif
diff --git a/include/asm-arm/arch-h720x/vmalloc.h b/include/asm-arm/arch-h720x/vmalloc.h
new file mode 100644
index 000000000000..4af523a5e189
--- /dev/null
+++ b/include/asm-arm/arch-h720x/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ * linux/include/asm-arm/arch-h720x/vmalloc.h
+ */
+
+#ifndef __ARCH_ARM_VMALLOC_H
+#define __ARCH_ARM_VMALLOC_H
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+
+#endif
diff --git a/include/asm-arm/arch-imx/debug-macro.S b/include/asm-arm/arch-imx/debug-macro.S
new file mode 100644
index 000000000000..83f552f7bcc1
--- /dev/null
+++ b/include/asm-arm/arch-imx/debug-macro.S
@@ -0,0 +1,34 @@
+/* linux/include/asm-arm/arch-imx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x00000000        @ physical
+                movne   \rx, #0xe0000000        @ virtual
+                orr     \rx, \rx, #0x00200000
+                orr     \rx, \rx, #0x00006000   @ UART1 offset
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x40]       @ TXDATA
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x98]       @ SR2
+                tst     \rd, #1 << 3            @ TXDC
+                beq     1002b                   @ wait until transmit done
+                .endm
diff --git a/include/asm-arm/arch-imx/dma.h b/include/asm-arm/arch-imx/dma.h
new file mode 100644
index 000000000000..dbdc01780413
--- /dev/null
+++ b/include/asm-arm/arch-imx/dma.h
@@ -0,0 +1,71 @@
+/*
+ *  linux/include/asm-arm/imxads/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+
+#define MAX_DMA_CHANNELS        0
+
+/*
+ * DMA registration
+ */
+
+typedef enum {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 3,
+        DMA_PRIO_LOW = 6
+} imx_dma_prio;
+
+int imx_request_dma(char *name, imx_dma_prio prio,
+                    void (*irq_handler) (int, void *, struct pt_regs *),
+                    void (*err_handler) (int, void *, struct pt_regs *),
+                    void *data);
+
+void imx_free_dma(int dma_ch);
+
+
+#define DMA_REQ_UART3_T        2
+#define DMA_REQ_UART3_R        3
+#define DMA_REQ_SSI2_T         4
+#define DMA_REQ_SSI2_R         5
+#define DMA_REQ_CSI_STAT       6
+#define DMA_REQ_CSI_R          7
+#define DMA_REQ_MSHC           8
+#define DMA_REQ_DSPA_DCT_DOUT  9
+#define DMA_REQ_DSPA_DCT_DIN  10
+#define DMA_REQ_DSPA_MAC      11
+#define DMA_REQ_EXT           12
+#define DMA_REQ_SDHC          13
+#define DMA_REQ_SPI1_R        14
+#define DMA_REQ_SPI1_T        15
+#define DMA_REQ_SSI_T         16
+#define DMA_REQ_SSI_R         17
+#define DMA_REQ_ASP_DAC       18
+#define DMA_REQ_ASP_ADC       19
+#define DMA_REQ_USP_EP(x)    (20+(x))
+#define DMA_REQ_SPI2_R        26
+#define DMA_REQ_SPI2_T        27
+#define DMA_REQ_UART2_T       28
+#define DMA_REQ_UART2_R       29
+#define DMA_REQ_UART1_T       30
+#define DMA_REQ_UART1_R       31
+
+#endif                          /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-imx/entry-macro.S b/include/asm-arm/arch-imx/entry-macro.S
new file mode 100644
index 000000000000..b40ea7cf88ec
--- /dev/null
+++ b/include/asm-arm/arch-imx/entry-macro.S
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-imx/entry-macro.S
+ *
+ * Low-level IRQ helper macros for iMX-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+                .macro  disable_fiq
+                .endm
+#define AITC_NIVECSR   0x40
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, =IO_ADDRESS(IMX_AITC_BASE)
+                @ Load offset & priority of the highest priority
+                @ interrupt pending.
+                ldr     \irqnr, [\irqstat, #AITC_NIVECSR]
+                @ Shift off the priority leaving the offset or
+                @ "interrupt number"
+                mov     \irqnr, \irqnr, lsr #16
+                ldr     \irqstat, =1    @ dummy compare
+                ldr     \base, =0xFFFF          // invalid interrupt
+                cmp     \irqnr, \base
+                bne     1001f
+                ldr     \irqstat, =0
+1001:
+                tst     \irqstat, #1    @ to make the condition code = TRUE
+                .endm
+
diff --git a/include/asm-arm/arch-imx/hardware.h b/include/asm-arm/arch-imx/hardware.h
new file mode 100644
index 000000000000..adffb6acf42a
--- /dev/null
+++ b/include/asm-arm/arch-imx/hardware.h
@@ -0,0 +1,99 @@
+/*
+ *  linux/include/asm-arm/arch-imx/hardware.h
+ *
+ *  Copyright (C) 1999 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include "imx-regs.h"
+
+#ifndef __ASSEMBLY__
+# define __REG(x)       (*((volatile u32 *)IO_ADDRESS(x)))
+
+# define __REG2(x,y)        (*(volatile u32 *)((u32)&__REG(x) + (y)))
+#endif
+
+/*
+ * Memory map
+ */
+
+#define IMX_IO_PHYS             0x00200000
+#define IMX_IO_SIZE             0x00100000
+#define IMX_IO_BASE             0xe0000000
+
+#define IMX_CS0_PHYS            0x10000000
+#define IMX_CS0_SIZE            0x02000000
+#define IMX_CS0_VIRT            0xe8000000
+
+#define IMX_CS1_PHYS            0x12000000
+#define IMX_CS1_SIZE            0x01000000
+#define IMX_CS1_VIRT            0xea000000
+
+#define IMX_CS2_PHYS            0x13000000
+#define IMX_CS2_SIZE            0x01000000
+#define IMX_CS2_VIRT            0xeb000000
+
+#define IMX_CS3_PHYS            0x14000000
+#define IMX_CS3_SIZE            0x01000000
+#define IMX_CS3_VIRT            0xec000000
+
+#define IMX_CS4_PHYS            0x15000000
+#define IMX_CS4_SIZE            0x01000000
+#define IMX_CS4_VIRT            0xed000000
+
+#define IMX_CS5_PHYS            0x16000000
+#define IMX_CS5_SIZE            0x01000000
+#define IMX_CS5_VIRT            0xee000000
+
+#define IMX_FB_VIRT             0xF1000000
+#define IMX_FB_SIZE             (256*1024)
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) ((x) | IMX_IO_BASE)
+
+#ifndef __ASSEMBLY__
+/*
+ * Handy routine to set GPIO functions
+ */
+extern void imx_gpio_mode( int gpio_mode );
+
+/* get frequencies in Hz */
+extern unsigned int imx_get_system_clk(void);
+extern unsigned int imx_get_mcu_clk(void);
+extern unsigned int imx_get_perclk1(void); /* UART[12], Timer[12], PWM */
+extern unsigned int imx_get_perclk2(void); /* LCD, SD, SPI[12]         */
+extern unsigned int imx_get_perclk3(void); /* SSI                      */
+extern unsigned int imx_get_hclk(void);    /* SDRAM, CSI, Memory Stick,*/
+                                           /* I2C, DMA                 */
+#endif
+
+#define MAXIRQNUM                       62
+#define MAXFIQNUM                       62
+#define MAXSWINUM                       62
+
+/*
+ * Use SDRAM for memory
+ */
+#define MEM_SIZE                0x01000000
+
+#ifdef CONFIG_ARCH_MX1ADS
+#include "mx1ads.h"
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
new file mode 100644
index 000000000000..f32c203952cf
--- /dev/null
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -0,0 +1,548 @@
+#ifndef _IMX_REGS_H
+#define _IMX_REGS_H
+/* ------------------------------------------------------------------------
+ *  Motorola IMX system registers
+ * ------------------------------------------------------------------------
+ *
+ */
+
+/*
+ *  Register BASEs, based on OFFSETs
+ *
+ */
+#define IMX_AIPI1_BASE             (0x00000 + IMX_IO_BASE)
+#define IMX_WDT_BASE               (0x01000 + IMX_IO_BASE)
+#define IMX_TIM1_BASE              (0x02000 + IMX_IO_BASE)
+#define IMX_TIM2_BASE              (0x03000 + IMX_IO_BASE)
+#define IMX_RTC_BASE               (0x04000 + IMX_IO_BASE)
+#define IMX_LCDC_BASE              (0x05000 + IMX_IO_BASE)
+#define IMX_UART1_BASE             (0x06000 + IMX_IO_BASE)
+#define IMX_UART2_BASE             (0x07000 + IMX_IO_BASE)
+#define IMX_PWM_BASE               (0x08000 + IMX_IO_BASE)
+#define IMX_DMAC_BASE              (0x09000 + IMX_IO_BASE)
+#define IMX_AIPI2_BASE             (0x10000 + IMX_IO_BASE)
+#define IMX_SIM_BASE               (0x11000 + IMX_IO_BASE)
+#define IMX_USBD_BASE              (0x12000 + IMX_IO_BASE)
+#define IMX_SPI1_BASE              (0x13000 + IMX_IO_BASE)
+#define IMX_MMC_BASE               (0x14000 + IMX_IO_BASE)
+#define IMX_ASP_BASE               (0x15000 + IMX_IO_BASE)
+#define IMX_BTA_BASE               (0x16000 + IMX_IO_BASE)
+#define IMX_I2C_BASE               (0x17000 + IMX_IO_BASE)
+#define IMX_SSI_BASE               (0x18000 + IMX_IO_BASE)
+#define IMX_SPI2_BASE              (0x19000 + IMX_IO_BASE)
+#define IMX_MSHC_BASE              (0x1A000 + IMX_IO_BASE)
+#define IMX_PLL_BASE               (0x1B000 + IMX_IO_BASE)
+#define IMX_GPIO_BASE              (0x1C000 + IMX_IO_BASE)
+#define IMX_EIM_BASE               (0x20000 + IMX_IO_BASE)
+#define IMX_SDRAMC_BASE            (0x21000 + IMX_IO_BASE)
+#define IMX_MMA_BASE               (0x22000 + IMX_IO_BASE)
+#define IMX_AITC_BASE              (0x23000 + IMX_IO_BASE)
+#define IMX_CSI_BASE               (0x24000 + IMX_IO_BASE)
+
+/* PLL registers */
+#define CSCR   __REG(IMX_PLL_BASE)        /* Clock Source Control Register */
+#define CSCR_SYSTEM_SEL (1<<16)
+
+#define MPCTL0 __REG(IMX_PLL_BASE + 0x4)  /* MCU PLL Control Register 0 */
+#define MPCTL1 __REG(IMX_PLL_BASE + 0x8)  /* MCU PLL and System Clock Register 1 */
+#define SPCTL0 __REG(IMX_PLL_BASE + 0xc)  /* System PLL Control Register 0 */
+#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
+#define PCDR   __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
+
+#define CSCR_MPLL_RESTART (1<<21)
+
+/*
+ *  GPIO Module and I/O Multiplexer
+ *  x = 0..3 for reg_A, reg_B, reg_C, reg_D
+ */
+#define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
+#define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
+#define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
+#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
+#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
+#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
+#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
+#define DR(x)      __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
+#define GIUS(x)    __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
+#define SSR(x)     __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
+#define ICR1(x)    __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
+#define ICR2(x)    __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
+#define IMR(x)     __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
+#define ISR(x)     __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
+#define GPR(x)     __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
+#define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
+#define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
+
+#define GPIO_PIN_MASK 0x1f
+#define GPIO_PORT_MASK (0x3 << 5)
+
+#define GPIO_PORTA (0<<5)
+#define GPIO_PORTB (1<<5)
+#define GPIO_PORTC (2<<5)
+#define GPIO_PORTD (3<<5)
+
+#define GPIO_OUT   (1<<7)
+#define GPIO_IN    (0<<7)
+#define GPIO_PUEN  (1<<8)
+
+#define GPIO_PF    (0<<9)
+#define GPIO_AF    (1<<9)
+
+#define GPIO_OCR_MASK (3<<10)
+#define GPIO_AIN   (0<<10)
+#define GPIO_BIN   (1<<10)
+#define GPIO_CIN   (2<<10)
+#define GPIO_GPIO  (3<<10)
+
+#define GPIO_AOUT  (1<<12)
+#define GPIO_BOUT  (1<<13)
+
+/* assignements for GPIO alternate/primary functions */
+
+/* FIXME: This list is not completed. The correct directions are
+ * missing on some (many) pins
+ */
+#define PA0_PF_A24           ( GPIO_PORTA | GPIO_PF | 0 )
+#define PA0_AIN_SPI2_CLK     ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 )
+#define PA0_AF_ETMTRACESYNC  ( GPIO_PORTA | GPIO_AF | 0 )
+#define PA1_AOUT_SPI2_RXD    ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 )
+#define PA1_PF_TIN           ( GPIO_PORTA | GPIO_PF | 1 )
+#define PA2_PF_PWM0          ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
+#define PA3_PF_CSI_MCLK      ( GPIO_PORTA | GPIO_PF | 3 )
+#define PA4_PF_CSI_D0        ( GPIO_PORTA | GPIO_PF | 4 )
+#define PA5_PF_CSI_D1        ( GPIO_PORTA | GPIO_PF | 5 )
+#define PA6_PF_CSI_D2        ( GPIO_PORTA | GPIO_PF | 6 )
+#define PA7_PF_CSI_D3        ( GPIO_PORTA | GPIO_PF | 7 )
+#define PA8_PF_CSI_D4        ( GPIO_PORTA | GPIO_PF | 8 )
+#define PA9_PF_CSI_D5        ( GPIO_PORTA | GPIO_PF | 9 )
+#define PA10_PF_CSI_D6       ( GPIO_PORTA | GPIO_PF | 10 )
+#define PA11_PF_CSI_D7       ( GPIO_PORTA | GPIO_PF | 11 )
+#define PA12_PF_CSI_VSYNC    ( GPIO_PORTA | GPIO_PF | 12 )
+#define PA13_PF_CSI_HSYNC    ( GPIO_PORTA | GPIO_PF | 13 )
+#define PA14_PF_CSI_PIXCLK   ( GPIO_PORTA | GPIO_PF | 14 )
+#define PA15_PF_I2C_SDA      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
+#define PA16_PF_I2C_SCL      ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
+#define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
+#define PA17_AIN_SPI2_SS     ( GPIO_PORTA | GPIO_AIN | 17 )
+#define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
+#define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
+#define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
+#define PA21_PF_A0           ( GPIO_PORTA | GPIO_PF | 21 )
+#define PA22_PF_CS4          ( GPIO_PORTA | GPIO_PF | 22 )
+#define PA23_PF_CS5          ( GPIO_PORTA | GPIO_PF | 23 )
+#define PA24_PF_A16          ( GPIO_PORTA | GPIO_PF | 24 )
+#define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
+#define PA25_PF_A17          ( GPIO_PORTA | GPIO_PF | 25 )
+#define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
+#define PA26_PF_A18          ( GPIO_PORTA | GPIO_PF | 26 )
+#define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
+#define PA27_PF_A19          ( GPIO_PORTA | GPIO_PF | 27 )
+#define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
+#define PA28_PF_A20          ( GPIO_PORTA | GPIO_PF | 28 )
+#define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
+#define PA29_PF_A21          ( GPIO_PORTA | GPIO_PF | 29 )
+#define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
+#define PA30_PF_A22          ( GPIO_PORTA | GPIO_PF | 30 )
+#define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
+#define PA31_PF_A23          ( GPIO_PORTA | GPIO_PF | 31 )
+#define PA31_AF_ETMTRACECLK  ( GPIO_PORTA | GPIO_AF | 31 )
+#define PB8_PF_SD_DAT0       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
+#define PB8_AF_MS_PIO        ( GPIO_PORTB | GPIO_AF | 8 )
+#define PB9_PF_SD_DAT1       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 9 )
+#define PB9_AF_MS_PI1        ( GPIO_PORTB | GPIO_AF | 9 )
+#define PB10_PF_SD_DAT2      ( GPIO_PORTB | GPIO_PF | GPIO_PUEN  | 10 )
+#define PB10_AF_MS_SCLKI     ( GPIO_PORTB | GPIO_AF | 10 )
+#define PB11_PF_SD_DAT3      ( GPIO_PORTB | GPIO_PF | 11 )
+#define PB11_AF_MS_SDIO      ( GPIO_PORTB | GPIO_AF | 11 )
+#define PB12_PF_SD_CLK       ( GPIO_PORTB | GPIO_PF | 12 )
+#define PB12_AF_MS_SCLK0     ( GPIO_PORTB | GPIO_AF | 12 )
+#define PB13_PF_SD_CMD       ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
+#define PB13_AF_MS_BS        ( GPIO_PORTB | GPIO_AF | 13 )
+#define PB14_AF_SSI_RXFS     ( GPIO_PORTB | GPIO_AF | 14 )
+#define PB15_AF_SSI_RXCLK    ( GPIO_PORTB | GPIO_AF | 15 )
+#define PB16_AF_SSI_RXDAT    ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
+#define PB17_AF_SSI_TXDAT    ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
+#define PB18_AF_SSI_TXFS     ( GPIO_PORTB | GPIO_AF | 18 )
+#define PB19_AF_SSI_TXCLK    ( GPIO_PORTB | GPIO_AF | 19 )
+#define PB20_PF_USBD_AFE     ( GPIO_PORTB | GPIO_PF | 20 )
+#define PB21_PF_USBD_OE      ( GPIO_PORTB | GPIO_PF | 21 )
+#define PB22_PFUSBD_RCV      ( GPIO_PORTB | GPIO_PF | 22 )
+#define PB23_PF_USBD_SUSPND  ( GPIO_PORTB | GPIO_PF | 23 )
+#define PB24_PF_USBD_VP      ( GPIO_PORTB | GPIO_PF | 24 )
+#define PB25_PF_USBD_VM      ( GPIO_PORTB | GPIO_PF | 25 )
+#define PB26_PF_USBD_VPO     ( GPIO_PORTB | GPIO_PF | 26 )
+#define PB27_PF_USBD_VMO     ( GPIO_PORTB | GPIO_PF | 27 )
+#define PB28_PF_UART2_CTS    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
+#define PB29_PF_UART2_RTS    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
+#define PB30_PF_UART2_TXD    ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
+#define PB31_PF_UART2_RXD    ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
+#define PC3_PF_SSI_RXFS      ( GPIO_PORTC | GPIO_PF | 3 )
+#define PC4_PF_SSI_RXCLK     ( GPIO_PORTC | GPIO_PF | 4 )
+#define PC5_PF_SSI_RXDAT     ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
+#define PC6_PF_SSI_TXDAT     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
+#define PC7_PF_SSI_TXFS      ( GPIO_PORTC | GPIO_PF | 7 )
+#define PC8_PF_SSI_TXCLK     ( GPIO_PORTC | GPIO_PF | 8 )
+#define PC9_PF_UART1_CTS     ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
+#define PC10_PF_UART1_RTS    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
+#define PC11_PF_UART1_TXD    ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
+#define PC12_PF_UART1_RXD    ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
+#define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
+#define PC14_PF_SPI1_SCLK    ( GPIO_PORTC | GPIO_PF | 14 )
+#define PC15_PF_SPI1_SS      ( GPIO_PORTC | GPIO_PF | 15 )
+#define PC16_PF_SPI1_MISO    ( GPIO_PORTC | GPIO_PF | 16 )
+#define PC17_PF_SPI1_MOSI    ( GPIO_PORTC | GPIO_PF | 17 )
+#define PD6_PF_LSCLK         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
+#define PD7_PF_REV           ( GPIO_PORTD | GPIO_PF | 7 )
+#define PD7_AF_UART2_DTR     ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
+#define PD7_AIN_SPI2_SCLK    ( GPIO_PORTD | GPIO_AIN | 7 )
+#define PD8_PF_CLS           ( GPIO_PORTD | GPIO_PF | 8 )
+#define PD8_AF_UART2_DCD     ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
+#define PD8_AIN_SPI2_SS      ( GPIO_PORTD | GPIO_AIN | 8 )
+#define PD9_PF_PS            ( GPIO_PORTD | GPIO_PF | 9 )
+#define PD9_AF_UART2_RI      ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
+#define PD9_AOUT_SPI2_RXD    ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 )
+#define PD10_PF_SPL_SPR      ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
+#define PD10_AF_UART2_DSR    ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
+#define PD10_AIN_SPI2_TXD    ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 )
+#define PD11_PF_CONTRAST     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
+#define PD12_PF_ACD_OE       ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
+#define PD13_PF_LP_HSYNC     ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
+#define PD14_PF_FLM_VSYNC    ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
+#define PD15_PF_LD0          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
+#define PD16_PF_LD1          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
+#define PD17_PF_LD2          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
+#define PD18_PF_LD3          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
+#define PD19_PF_LD4          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
+#define PD20_PF_LD5          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
+#define PD21_PF_LD6          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
+#define PD22_PF_LD7          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
+#define PD23_PF_LD8          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
+#define PD24_PF_LD9          ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
+#define PD25_PF_LD10         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
+#define PD26_PF_LD11         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
+#define PD27_PF_LD12         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
+#define PD28_PF_LD13         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
+#define PD29_PF_LD14         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
+#define PD30_PF_LD15         ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
+#define PD31_PF_TMR2OUT      ( GPIO_PORTD | GPIO_PF | 31 )
+#define PD31_BIN_SPI2_TXD    ( GPIO_PORTD | GPIO_BIN | 31 )
+
+/*
+ *  DMA Controller
+ */
+#define DCR     __REG(IMX_DMAC_BASE +0x00)      /* DMA Control Register */
+#define DISR    __REG(IMX_DMAC_BASE +0x04)      /* DMA Interrupt status Register */
+#define DIMR    __REG(IMX_DMAC_BASE +0x08)      /* DMA Interrupt mask Register */
+#define DBTOSR  __REG(IMX_DMAC_BASE +0x0c)      /* DMA Burst timeout status Register */
+#define DRTOSR  __REG(IMX_DMAC_BASE +0x10)      /* DMA Request timeout Register */
+#define DSESR   __REG(IMX_DMAC_BASE +0x14)      /* DMA Transfer Error Status Register */
+#define DBOSR   __REG(IMX_DMAC_BASE +0x18)      /* DMA Buffer overflow status Register */
+#define DBTOCR  __REG(IMX_DMAC_BASE +0x1c)      /* DMA Burst timeout control Register */
+#define WSRA    __REG(IMX_DMAC_BASE +0x40)      /* W-Size Register A */
+#define XSRA    __REG(IMX_DMAC_BASE +0x44)      /* X-Size Register A */
+#define YSRA    __REG(IMX_DMAC_BASE +0x48)      /* Y-Size Register A */
+#define WSRB    __REG(IMX_DMAC_BASE +0x4c)      /* W-Size Register B */
+#define XSRB    __REG(IMX_DMAC_BASE +0x50)      /* X-Size Register B */
+#define YSRB    __REG(IMX_DMAC_BASE +0x54)      /* Y-Size Register B */
+#define SAR(x)  __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
+#define DAR(x)  __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
+#define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
+#define CCR(x)  __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
+#define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
+#define BLR(x)  __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
+#define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
+#define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
+
+#define DCR_DRST           (1<<1)
+#define DCR_DEN            (1<<0)
+#define DBTOCR_EN          (1<<15)
+#define DBTOCR_CNT(x)      ((x) & 0x7fff )
+#define CNTR_CNT(x)        ((x) & 0xffffff )
+#define CCR_DMOD_LINEAR    ( 0x0 << 12 )
+#define CCR_DMOD_2D        ( 0x1 << 12 )
+#define CCR_DMOD_FIFO      ( 0x2 << 12 )
+#define CCR_DMOD_EOBFIFO   ( 0x3 << 12 )
+#define CCR_SMOD_LINEAR    ( 0x0 << 10 )
+#define CCR_SMOD_2D        ( 0x1 << 10 )
+#define CCR_SMOD_FIFO      ( 0x2 << 10 )
+#define CCR_SMOD_EOBFIFO   ( 0x3 << 10 )
+#define CCR_MDIR_DEC       (1<<9)
+#define CCR_MSEL_B         (1<<8)
+#define CCR_DSIZ_32        ( 0x0 << 6 )
+#define CCR_DSIZ_8         ( 0x1 << 6 )
+#define CCR_DSIZ_16        ( 0x2 << 6 )
+#define CCR_SSIZ_32        ( 0x0 << 4 )
+#define CCR_SSIZ_8         ( 0x1 << 4 )
+#define CCR_SSIZ_16        ( 0x2 << 4 )
+#define CCR_REN            (1<<3)
+#define CCR_RPT            (1<<2)
+#define CCR_FRC            (1<<1)
+#define CCR_CEN            (1<<0)
+#define RTOR_EN            (1<<15)
+#define RTOR_CLK           (1<<14)
+#define RTOR_PSC           (1<<13)
+
+/*
+ *  Interrupt controller
+ */
+
+#define IMX_INTCNTL        __REG(IMX_AITC_BASE+0x00)
+#define INTCNTL_FIAD       (1<<19)
+#define INTCNTL_NIAD       (1<<20)
+
+#define IMX_NIMASK         __REG(IMX_AITC_BASE+0x04)
+#define IMX_INTENNUM       __REG(IMX_AITC_BASE+0x08)
+#define IMX_INTDISNUM      __REG(IMX_AITC_BASE+0x0c)
+#define IMX_INTENABLEH     __REG(IMX_AITC_BASE+0x10)
+#define IMX_INTENABLEL     __REG(IMX_AITC_BASE+0x14)
+
+/*
+ *  General purpose timers
+ */
+#define IMX_TCTL(x)        __REG( 0x00 + (x))
+#define TCTL_SWR           (1<<15)
+#define TCTL_FRR           (1<<8)
+#define TCTL_CAP_RIS       (1<<6)
+#define TCTL_CAP_FAL       (2<<6)
+#define TCTL_CAP_RIS_FAL   (3<<6)
+#define TCTL_OM            (1<<5)
+#define TCTL_IRQEN         (1<<4)
+#define TCTL_CLK_PCLK1     (1<<1)
+#define TCTL_CLK_PCLK1_16  (2<<1)
+#define TCTL_CLK_TIN       (3<<1)
+#define TCTL_CLK_32        (4<<1)
+#define TCTL_TEN           (1<<0)
+
+#define IMX_TPRER(x)       __REG( 0x04 + (x))
+#define IMX_TCMP(x)        __REG( 0x08 + (x))
+#define IMX_TCR(x)         __REG( 0x0C + (x))
+#define IMX_TCN(x)         __REG( 0x10 + (x))
+#define IMX_TSTAT(x)       __REG( 0x14 + (x))
+#define TSTAT_CAPT         (1<<1)
+#define TSTAT_COMP         (1<<0)
+
+/*
+ * LCD Controller
+ */
+
+#define LCDC_SSA        __REG(IMX_LCDC_BASE+0x00)
+
+#define LCDC_SIZE       __REG(IMX_LCDC_BASE+0x04)
+#define SIZE_XMAX(x)    ((((x) >> 4) & 0x3f) << 20)
+#define SIZE_YMAX(y)    ( (y) & 0x1ff )
+
+#define LCDC_VPW        __REG(IMX_LCDC_BASE+0x08)
+#define VPW_VPW(x)      ( (x) & 0x3ff )
+
+#define LCDC_CPOS       __REG(IMX_LCDC_BASE+0x0C)
+#define CPOS_CC1        (1<<31)
+#define CPOS_CC0        (1<<30)
+#define CPOS_OP         (1<<28)
+#define CPOS_CXP(x)     (((x) & 3ff) << 16)
+#define CPOS_CYP(y)     ((y) & 0x1ff)
+
+#define LCDC_LCWHB      __REG(IMX_LCDC_BASE+0x10)
+#define LCWHB_BK_EN     (1<<31)
+#define LCWHB_CW(w)     (((w) & 0x1f) << 24)
+#define LCWHB_CH(h)     (((h) & 0x1f) << 16)
+#define LCWHB_BD(x)     ((x) & 0xff)
+
+#define LCDC_LCHCC      __REG(IMX_LCDC_BASE+0x14)
+#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
+#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
+#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
+
+#define LCDC_PCR        __REG(IMX_LCDC_BASE+0x18)
+#define PCR_TFT         (1<<31)
+#define PCR_COLOR       (1<<30)
+#define PCR_PBSIZ_1     (0<<28)
+#define PCR_PBSIZ_2     (1<<28)
+#define PCR_PBSIZ_4     (2<<28)
+#define PCR_PBSIZ_8     (3<<28)
+#define PCR_BPIX_1      (0<<25)
+#define PCR_BPIX_2      (1<<25)
+#define PCR_BPIX_4      (2<<25)
+#define PCR_BPIX_8      (3<<25)
+#define PCR_BPIX_12     (4<<25)
+#define PCR_BPIX_16     (4<<25)
+#define PCR_PIXPOL      (1<<24)
+#define PCR_FLMPOL      (1<<23)
+#define PCR_LPPOL       (1<<22)
+#define PCR_CLKPOL      (1<<21)
+#define PCR_OEPOL       (1<<20)
+#define PCR_SCLKIDLE    (1<<19)
+#define PCR_END_SEL     (1<<18)
+#define PCR_END_BYTE_SWAP (1<<17)
+#define PCR_REV_VS      (1<<16)
+#define PCR_ACD_SEL     (1<<15)
+#define PCR_ACD(x)      (((x) & 0x7f) << 8)
+#define PCR_SCLK_SEL    (1<<7)
+#define PCR_SHARP       (1<<6)
+#define PCR_PCD(x)      ((x) & 0x3f)
+
+#define LCDC_HCR        __REG(IMX_LCDC_BASE+0x1C)
+#define HCR_H_WIDTH(x)  (((x) & 0x3f) << 26)
+#define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
+#define HCR_H_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_VCR        __REG(IMX_LCDC_BASE+0x20)
+#define VCR_V_WIDTH(x)  (((x) & 0x3f) << 26)
+#define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
+#define VCR_V_WAIT_2(x) ((x) & 0xff)
+
+#define LCDC_POS        __REG(IMX_LCDC_BASE+0x24)
+#define POS_POS(x)      ((x) & 1f)
+
+#define LCDC_LSCR1      __REG(IMX_LCDC_BASE+0x28)
+#define LSCR1_PS_RISE_DELAY(x)    (((x) & 0x7f) << 26)
+#define LSCR1_CLS_RISE_DELAY(x)   (((x) & 0x3f) << 16)
+#define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
+#define LSCR1_GRAY2(x)            (((x) & 0xf) << 4)
+#define LSCR1_GRAY1(x)            (((x) & 0xf))
+
+#define LCDC_PWMR       __REG(IMX_LCDC_BASE+0x2C)
+#define PWMR_CLS(x)     (((x) & 0x1ff) << 16)
+#define PWMR_LDMSK      (1<<15)
+#define PWMR_SCR1       (1<<10)
+#define PWMR_SCR0       (1<<9)
+#define PWMR_CC_EN      (1<<8)
+#define PWMR_PW(x)      ((x) & 0xff)
+
+#define LCDC_DMACR      __REG(IMX_LCDC_BASE+0x30)
+#define DMACR_BURST     (1<<31)
+#define DMACR_HM(x)     (((x) & 0xf) << 16)
+#define DMACR_TM(x)     ((x) &0xf)
+
+#define LCDC_RMCR       __REG(IMX_LCDC_BASE+0x34)
+#define RMCR_LCDC_EN            (1<<1)
+#define RMCR_SELF_REF           (1<<0)
+
+#define LCDC_LCDICR     __REG(IMX_LCDC_BASE+0x38)
+#define LCDICR_INT_SYN  (1<<2)
+#define LCDICR_INT_CON  (1)
+
+#define LCDC_LCDISR     __REG(IMX_LCDC_BASE+0x40)
+#define LCDISR_UDR_ERR (1<<3)
+#define LCDISR_ERR_RES (1<<2)
+#define LCDISR_EOF     (1<<1)
+#define LCDISR_BOF     (1<<0)
+
+/*
+ *  UART Module. Takes the UART base address as argument
+ */
+#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
+#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
+#define UCR1(x)  __REG( 0x80 + (x)) /* Control Register 1 */
+#define UCR2(x)  __REG( 0x84 + (x)) /* Control Register 2 */
+#define UCR3(x)  __REG( 0x88 + (x)) /* Control Register 3 */
+#define UCR4(x)  __REG( 0x8c + (x)) /* Control Register 4 */
+#define UFCR(x)  __REG( 0x90 + (x)) /* FIFO Control Register */
+#define USR1(x)  __REG( 0x94 + (x)) /* Status Register 1 */
+#define USR2(x)  __REG( 0x98 + (x)) /* Status Register 2 */
+#define UESC(x)  __REG( 0x9c + (x)) /* Escape Character Register */
+#define UTIM(x)  __REG( 0xa0 + (x)) /* Escape Timer Register */
+#define UBIR(x)  __REG( 0xa4 + (x)) /* BRM Incremental Register */
+#define UBMR(x)  __REG( 0xa8 + (x)) /* BRM Modulator Register */
+#define UBRC(x)  __REG( 0xac + (x)) /* Baud Rate Count Register */
+#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
+#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
+#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
+#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
+#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
+#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
+#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
+#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
+#define UTS(x)   __REG( 0xd0 + (x)) /* UART Test Register */
+
+/* UART Control Register Bit Fields.*/
+#define  URXD_CHARRDY    (1<<15)
+#define  URXD_ERR        (1<<14)
+#define  URXD_OVRRUN     (1<<13)
+#define  URXD_FRMERR     (1<<12)
+#define  URXD_BRK        (1<<11)
+#define  URXD_PRERR      (1<<10)
+#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
+#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
+#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
+#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
+#define  UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
+#define  UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
+#define  UCR1_IREN       (1<<7)  /* Infrared interface enable */
+#define  UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
+#define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
+#define  UCR1_SNDBRK     (1<<4)  /* Send break */
+#define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
+#define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
+#define  UCR1_DOZE       (1<<1)  /* Doze */
+#define  UCR1_UARTEN     (1<<0)  /* UART enabled */
+#define  UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
+#define  UCR2_IRTS       (1<<14) /* Ignore RTS pin */
+#define  UCR2_CTSC       (1<<13) /* CTS pin control */
+#define  UCR2_CTS        (1<<12) /* Clear to send */
+#define  UCR2_ESCEN      (1<<11) /* Escape enable */
+#define  UCR2_PREN       (1<<8)  /* Parity enable */
+#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
+#define  UCR2_STPB       (1<<6)  /* Stop */
+#define  UCR2_WS         (1<<5)  /* Word size */
+#define  UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
+#define  UCR2_TXEN       (1<<2)  /* Transmitter enabled */
+#define  UCR2_RXEN       (1<<1)  /* Receiver enabled */
+#define  UCR2_SRST       (1<<0)  /* SW reset */
+#define  UCR3_DTREN      (1<<13) /* DTR interrupt enable */
+#define  UCR3_PARERREN   (1<<12) /* Parity enable */
+#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
+#define  UCR3_DSR        (1<<10) /* Data set ready */
+#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
+#define  UCR3_RI         (1<<8)  /* Ring indicator */
+#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
+#define  UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
+#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
+#define  UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
+#define  UCR3_REF25      (1<<3)  /* Ref freq 25 MHz */
+#define  UCR3_REF30      (1<<2)  /* Ref Freq 30 MHz */
+#define  UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
+#define  UCR3_BPEN       (1<<0)  /* Preset registers enable */
+#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
+#define  UCR4_INVR       (1<<9)  /* Inverted infrared reception */
+#define  UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
+#define  UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
+#define  UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
+#define  UCR4_IRSC       (1<<5)  /* IR special case */
+#define  UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
+#define  UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
+#define  UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
+#define  UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
+#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
+#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
+#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
+#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
+#define  USR1_RTSS       (1<<14) /* RTS pin status */
+#define  USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
+#define  USR1_RTSD       (1<<12) /* RTS delta */
+#define  USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
+#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
+#define  USR1_RRDY       (1<<9)  /* Receiver ready interrupt/dma flag */
+#define  USR1_TIMEOUT    (1<<7)  /* Receive timeout interrupt status */
+#define  USR1_RXDS       (1<<6)  /* Receiver idle interrupt flag */
+#define  USR1_AIRINT     (1<<5)  /* Async IR wake interrupt flag */
+#define  USR1_AWAKE      (1<<4)  /* Aysnc wake interrupt flag */
+#define  USR2_ADET       (1<<15) /* Auto baud rate detect complete */
+#define  USR2_TXFE       (1<<14) /* Transmit buffer FIFO empty */
+#define  USR2_DTRF       (1<<13) /* DTR edge interrupt flag */
+#define  USR2_IDLE       (1<<12) /* Idle condition */
+#define  USR2_IRINT      (1<<8)  /* Serial infrared interrupt flag */
+#define  USR2_WAKE       (1<<7)  /* Wake */
+#define  USR2_RTSF       (1<<4)  /* RTS edge interrupt flag */
+#define  USR2_TXDC       (1<<3)  /* Transmitter complete */
+#define  USR2_BRCD       (1<<2)  /* Break condition */
+#define  USR2_ORE        (1<<1)  /* Overrun error */
+#define  USR2_RDR        (1<<0)  /* Recv data ready */
+#define  UTS_FRCPERR     (1<<13) /* Force parity error */
+#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
+#define  UTS_TXEMPTY     (1<<6)  /* TxFIFO empty */
+#define  UTS_RXEMPTY     (1<<5)  /* RxFIFO empty */
+#define  UTS_TXFULL      (1<<4)  /* TxFIFO full */
+#define  UTS_RXFULL      (1<<3)  /* RxFIFO full */
+#define  UTS_SOFTRST     (1<<0)  /* Software reset */
+
+#endif                          // _IMX_REGS_H
diff --git a/include/asm-arm/arch-imx/io.h b/include/asm-arm/arch-imx/io.h
new file mode 100644
index 000000000000..28a4cca6a4cb
--- /dev/null
+++ b/include/asm-arm/arch-imx/io.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/include/asm-arm/arch-imxads/io.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(a)         ((void __iomem *)(a))
+#define __mem_pci(a)    (a)
+
+#endif
diff --git a/include/asm-arm/arch-imx/irq.h b/include/asm-arm/arch-imx/irq.h
new file mode 100644
index 000000000000..545e065d2325
--- /dev/null
+++ b/include/asm-arm/arch-imx/irq.h
@@ -0,0 +1,20 @@
+/*
+ *  linux/include/asm-arm/arch-imxads/irq.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define fixup_irq(i)    (i)
diff --git a/include/asm-arm/arch-imx/irqs.h b/include/asm-arm/arch-imx/irqs.h
new file mode 100644
index 000000000000..238197cfb9d9
--- /dev/null
+++ b/include/asm-arm/arch-imx/irqs.h
@@ -0,0 +1,116 @@
+/*
+ *  linux/include/asm-arm/arch-imxads/irqs.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ARM_IRQS_H__
+#define __ARM_IRQS_H__
+
+/* Use the imx definitions */
+#include <asm/arch/hardware.h>
+
+/*
+ *  IMX Interrupt numbers
+ *
+ */
+#define INT_SOFTINT                 0
+#define CSI_INT                     6
+#define DSPA_MAC_INT                7
+#define DSPA_INT                    8
+#define COMP_INT                    9
+#define MSHC_XINT                   10
+#define GPIO_INT_PORTA              11
+#define GPIO_INT_PORTB              12
+#define GPIO_INT_PORTC              13
+#define LCDC_INT                    14
+#define SIM_INT                     15
+#define SIM_DATA_INT                16
+#define RTC_INT                     17
+#define RTC_SAMINT                  18
+#define UART2_MINT_PFERR            19
+#define UART2_MINT_RTS              20
+#define UART2_MINT_DTR              21
+#define UART2_MINT_UARTC            22
+#define UART2_MINT_TX               23
+#define UART2_MINT_RX               24
+#define UART1_MINT_PFERR            25
+#define UART1_MINT_RTS              26
+#define UART1_MINT_DTR              27
+#define UART1_MINT_UARTC            28
+#define UART1_MINT_TX               29
+#define UART1_MINT_RX               30
+#define VOICE_DAC_INT               31
+#define VOICE_ADC_INT               32
+#define PEN_DATA_INT                33
+#define PWM_INT                     34
+#define SDHC_INT                    35
+#define I2C_INT                     39
+#define CSPI_INT                    41
+#define SSI_TX_INT                  42
+#define SSI_TX_ERR_INT              43
+#define SSI_RX_INT                  44
+#define SSI_RX_ERR_INT              45
+#define TOUCH_INT                   46
+#define USBD_INT0                   47
+#define USBD_INT1                   48
+#define USBD_INT2                   49
+#define USBD_INT3                   50
+#define USBD_INT4                   51
+#define USBD_INT5                   52
+#define USBD_INT6                   53
+#define BTSYS_INT                   55
+#define BTTIM_INT                   56
+#define BTWUI_INT                   57
+#define TIM2_INT                    58
+#define TIM1_INT                    59
+#define DMA_ERR                     60
+#define DMA_INT                     61
+#define GPIO_INT_PORTD              62
+
+#define IMX_IRQS                         (64)
+
+/* note: the IMX has four gpio ports (A-D), but only
+ *       the following pins are connected to the outside
+ *       world:
+ *
+ * PORT A: bits 0-31
+ * PORT B: bits 8-31
+ * PORT C: bits 3-17
+ * PORT D: bits 6-31
+ *
+ * We map these interrupts straight on. As a result we have
+ * several holes in the interrupt mapping. We do this for two
+ * reasons:
+ *   - mapping the interrupts without holes would get
+ *     far more complicated
+ *   - Motorola could well decide to bring some processor
+ *     with more pins connected
+ */
+
+#define IRQ_GPIOA(x)  (IMX_IRQS + x)
+#define IRQ_GPIOB(x)  (IRQ_GPIOA(32) + x)
+#define IRQ_GPIOC(x)  (IRQ_GPIOB(32) + x)
+#define IRQ_GPIOD(x)  (IRQ_GPIOC(32) + x)
+
+/* decode irq number to use with IMR(x), ISR(x) and friends */
+#define IRQ_TO_REG(irq) ((irq - IMX_IRQS) >> 5)
+
+#define NR_IRQS (IRQ_GPIOD(32) + 1)
+#define IRQ_GPIO(x)
+#endif
diff --git a/include/asm-arm/arch-imx/memory.h b/include/asm-arm/arch-imx/memory.h
new file mode 100644
index 000000000000..116a91fa14f1
--- /dev/null
+++ b/include/asm-arm/arch-imx/memory.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/arch-imx/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MMU_H
+#define __ASM_ARCH_MMU_H
+
+#define PHYS_OFFSET     (0x08000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus__is_a_macro
+#define __virt_to_bus(x)        (x - PAGE_OFFSET +  PHYS_OFFSET)
+#define __bus_to_virt__is_a_macro
+#define __bus_to_virt(x)        (x -  PHYS_OFFSET + PAGE_OFFSET)
+
+#endif
diff --git a/include/asm-arm/arch-imx/mx1ads.h b/include/asm-arm/arch-imx/mx1ads.h
new file mode 100644
index 000000000000..d90fa4b49ce1
--- /dev/null
+++ b/include/asm-arm/arch-imx/mx1ads.h
@@ -0,0 +1,36 @@
+/*
+ * linux/include/asm-arm/arch-imx/mx1ads.h
+ *
+ * Copyright (C) 2004 Robert Schwebel, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ */
+
+#ifndef __ASM_ARCH_MX1ADS_H
+#define __ASM_ARCH_MX1ADS_H
+
+/* ------------------------------------------------------------------------ */
+/* Memory Map for the M9328MX1ADS (MX1ADS) Board                            */
+/* ------------------------------------------------------------------------ */
+
+#define MX1ADS_FLASH_PHYS               0x10000000
+#define MX1ADS_FLASH_SIZE               (16*1024*1024)
+
+#define IMX_FB_PHYS                     (0x0C000000 - 0x40000)
+
+#define CLK32 32000
+
+#endif /* __ASM_ARCH_MX1ADS_H */
diff --git a/include/asm-arm/arch-imx/param.h b/include/asm-arm/arch-imx/param.h
new file mode 100644
index 000000000000..7c724f03333e
--- /dev/null
+++ b/include/asm-arm/arch-imx/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-imx/param.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-imx/system.h b/include/asm-arm/arch-imx/system.h
new file mode 100644
index 000000000000..c645fe9afb9d
--- /dev/null
+++ b/include/asm-arm/arch-imx/system.h
@@ -0,0 +1,40 @@
+/*
+ *  linux/include/asm-arm/arch-imxads/system.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static void
+arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void
+arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+
+#endif
diff --git a/include/asm-arm/arch-imx/timex.h b/include/asm-arm/arch-imx/timex.h
new file mode 100644
index 000000000000..d65ab3cd5d5d
--- /dev/null
+++ b/include/asm-arm/arch-imx/timex.h
@@ -0,0 +1,27 @@
+/*
+ *  linux/include/asm-arm/imx/timex.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+#include <asm/arch/hardware.h>
+#define CLOCK_TICK_RATE         (CLK32)
+
+#endif
diff --git a/include/asm-arm/arch-imx/uncompress.h b/include/asm-arm/arch-imx/uncompress.h
new file mode 100644
index 000000000000..096077f2750b
--- /dev/null
+++ b/include/asm-arm/arch-imx/uncompress.h
@@ -0,0 +1,78 @@
+/*
+ *  linux/include/asm-arm/arch-imxads/uncompress.h
+ *
+ *
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+
+#define UART1_BASE 0x206000
+#define UART2_BASE 0x207000
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR  0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+static void
+putstr(const char *s)
+{
+        unsigned long serial_port;
+
+        do {
+                serial_port = UART1_BASE;
+                if ( UART(UCR1) & UCR1_UARTEN )
+                        break;
+                serial_port = UART2_BASE;
+                if ( UART(UCR1) & UCR1_UARTEN )
+                        break;
+                return;
+        } while(0);
+
+        while (*s) {
+                while ( !(UART(USR2) & USR2_TXFE) )
+                        barrier();
+
+                UART(TXR) = *s;
+
+                if (*s == '\n') {
+                        while ( !(UART(USR2) & USR2_TXFE) )
+                                barrier();
+
+                        UART(TXR) = '\r';
+                }
+                s++;
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-imx/vmalloc.h b/include/asm-arm/arch-imx/vmalloc.h
new file mode 100644
index 000000000000..252038f48163
--- /dev/null
+++ b/include/asm-arm/arch-imx/vmalloc.h
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/arch-imx/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-integrator/bits.h b/include/asm-arm/arch-integrator/bits.h
new file mode 100644
index 000000000000..09b024e0496a
--- /dev/null
+++ b/include/asm-arm/arch-integrator/bits.h
@@ -0,0 +1,61 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *                 from .s file by awk -f s2h.awk
+ */
+/*  Bit field definitions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __bits_h
+#define __bits_h                        1
+
+#define BIT0                            0x00000001
+#define BIT1                            0x00000002
+#define BIT2                            0x00000004
+#define BIT3                            0x00000008
+#define BIT4                            0x00000010
+#define BIT5                            0x00000020
+#define BIT6                            0x00000040
+#define BIT7                            0x00000080
+#define BIT8                            0x00000100
+#define BIT9                            0x00000200
+#define BIT10                           0x00000400
+#define BIT11                           0x00000800
+#define BIT12                           0x00001000
+#define BIT13                           0x00002000
+#define BIT14                           0x00004000
+#define BIT15                           0x00008000
+#define BIT16                           0x00010000
+#define BIT17                           0x00020000
+#define BIT18                           0x00040000
+#define BIT19                           0x00080000
+#define BIT20                           0x00100000
+#define BIT21                           0x00200000
+#define BIT22                           0x00400000
+#define BIT23                           0x00800000
+#define BIT24                           0x01000000
+#define BIT25                           0x02000000
+#define BIT26                           0x04000000
+#define BIT27                           0x08000000
+#define BIT28                           0x10000000
+#define BIT29                           0x20000000
+#define BIT30                           0x40000000
+#define BIT31                           0x80000000
+
+#endif
+
+/*         END */
diff --git a/include/asm-arm/arch-integrator/cm.h b/include/asm-arm/arch-integrator/cm.h
new file mode 100644
index 000000000000..d31c1a71f781
--- /dev/null
+++ b/include/asm-arm/arch-integrator/cm.h
@@ -0,0 +1,36 @@
+/*
+ * update the core module control register.
+ */
+void cm_control(u32, u32);
+
+#define CM_CTRL_LED                     (1 << 0)
+#define CM_CTRL_nMBDET                  (1 << 1)
+#define CM_CTRL_REMAP                   (1 << 2)
+#define CM_CTRL_RESET                   (1 << 3)
+
+/*
+ * Integrator/AP,PP2 specific
+ */
+#define CM_CTRL_HIGHVECTORS             (1 << 4)
+#define CM_CTRL_BIGENDIAN               (1 << 5)
+#define CM_CTRL_FASTBUS                 (1 << 6)
+#define CM_CTRL_SYNC                    (1 << 7)
+
+/*
+ * ARM926/946/966 Integrator/CP specific
+ */
+#define CM_CTRL_LCDBIASEN               (1 << 8)
+#define CM_CTRL_LCDBIASUP               (1 << 9)
+#define CM_CTRL_LCDBIASDN               (1 << 10)
+#define CM_CTRL_LCDMUXSEL_MASK          (7 << 11)
+#define CM_CTRL_LCDMUXSEL_GENLCD        (1 << 11)
+#define CM_CTRL_LCDMUXSEL_SHARPLCD1     (3 << 11)
+#define CM_CTRL_LCDMUXSEL_SHARPLCD2     (4 << 11)
+#define CM_CTRL_LCDMUXSEL_VGA           (7 << 11)
+#define CM_CTRL_LCDEN0                  (1 << 14)
+#define CM_CTRL_LCDEN1                  (1 << 15)
+#define CM_CTRL_STATIC1                 (1 << 16)
+#define CM_CTRL_STATIC2                 (1 << 17)
+#define CM_CTRL_STATIC                  (1 << 18)
+#define CM_CTRL_n24BITEN                (1 << 19)
+#define CM_CTRL_EBIWP                   (1 << 20)
diff --git a/include/asm-arm/arch-integrator/debug-macro.S b/include/asm-arm/arch-integrator/debug-macro.S
new file mode 100644
index 000000000000..484a1aa47098
--- /dev/null
+++ b/include/asm-arm/arch-integrator/debug-macro.S
@@ -0,0 +1,38 @@
+/* linux/include/asm-arm/arch-integrator/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <asm/hardware/amba_serial.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x16000000        @ physical base address
+                movne   \rx, #0xf0000000        @ virtual base
+                addne   \rx, \rx, #0x16000000 >> 4
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #UART01x_DR]
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-integrator/dma.h b/include/asm-arm/arch-integrator/dma.h
new file mode 100644
index 000000000000..7171792290bd
--- /dev/null
+++ b/include/asm-arm/arch-integrator/dma.h
@@ -0,0 +1,28 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/dma.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+
+#define MAX_DMA_CHANNELS        0
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/include/asm-arm/arch-integrator/entry-macro.S b/include/asm-arm/arch-integrator/entry-macro.S
new file mode 100644
index 000000000000..44f7ee613194
--- /dev/null
+++ b/include/asm-arm/arch-integrator/entry-macro.S
@@ -0,0 +1,36 @@
+/*
+ * include/asm-arm/arch-integrator/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Integrator platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+/* FIXME: should not be using soo many LDRs here */
+                ldr     \base, =IO_ADDRESS(INTEGRATOR_IC_BASE)
+                mov     \irqnr, #IRQ_PIC_START
+                ldr     \irqstat, [\base, #IRQ_STATUS]          @ get masked status
+                ldr     \base, =IO_ADDRESS(INTEGRATOR_HDR_BASE)
+                teq     \irqstat, #0
+                ldreq   \irqstat, [\base, #(INTEGRATOR_HDR_IC_OFFSET+IRQ_STATUS)]
+                moveq   \irqnr, #IRQ_CIC_START
+
+1001:           tst     \irqstat, #15
+                bne     1002f
+                add     \irqnr, \irqnr, #4
+                movs    \irqstat, \irqstat, lsr #4
+                bne     1001b
+1002:           tst     \irqstat, #1
+                bne     1003f
+                add     \irqnr, \irqnr, #1
+                movs    \irqstat, \irqstat, lsr #1
+                bne     1002b
+1003:           /* EQ will be set if no irqs pending */
+                .endm
+
diff --git a/include/asm-arm/arch-integrator/hardware.h b/include/asm-arm/arch-integrator/hardware.h
new file mode 100644
index 000000000000..be2716eeaa02
--- /dev/null
+++ b/include/asm-arm/arch-integrator/hardware.h
@@ -0,0 +1,57 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/hardware.h
+ *
+ *  This file contains the hardware definitions of the Integrator.
+ *
+ *  Copyright (C) 1999 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <asm/arch/platform.h>
+
+/*
+ * Where in virtual memory the IO devices (timers, system controllers
+ * and so on)
+ */
+#define IO_BASE                 0xF0000000                 // VA of IO 
+#define IO_SIZE                 0x0B000000                 // How much?
+#define IO_START                INTEGRATOR_HDR_BASE        // PA of IO
+
+/*
+ * Similar to above, but for PCI addresses (memory, IO, Config and the
+ * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
+ */
+#define PCI_MEMORY_VADDR        0xe8000000
+#define PCI_CONFIG_VADDR        0xec000000
+#define PCI_V3_VADDR            0xed000000
+#define PCI_IO_VADDR            0xee000000
+
+#define PCIO_BASE               PCI_IO_VADDR
+#define PCIMEM_BASE             PCI_MEMORY_VADDR
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x) (((x) >> 4) + IO_BASE) 
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x6000
+#define PCIBIOS_MIN_MEM         0x00100000
+
+#endif
+
diff --git a/include/asm-arm/arch-integrator/impd1.h b/include/asm-arm/arch-integrator/impd1.h
new file mode 100644
index 000000000000..d75de4b14237
--- /dev/null
+++ b/include/asm-arm/arch-integrator/impd1.h
@@ -0,0 +1,18 @@
+#define IMPD1_OSC1      0x00
+#define IMPD1_OSC2      0x04
+#define IMPD1_LOCK      0x08
+#define IMPD1_LEDS      0x0c
+#define IMPD1_INT       0x10
+#define IMPD1_SW        0x14
+#define IMPD1_CTRL      0x18
+
+#define IMPD1_CTRL_DISP_LCD     (0 << 0)
+#define IMPD1_CTRL_DISP_VGA     (1 << 0)
+#define IMPD1_CTRL_DISP_LCD1    (2 << 0)
+#define IMPD1_CTRL_DISP_ENABLE  (1 << 2)
+#define IMPD1_CTRL_DISP_MASK    (7 << 0)
+
+struct device;
+
+void impd1_tweak_control(struct device *dev, u32 mask, u32 val);
+
diff --git a/include/asm-arm/arch-integrator/io.h b/include/asm-arm/arch-integrator/io.h
new file mode 100644
index 000000000000..fbea8be67d26
--- /dev/null
+++ b/include/asm-arm/arch-integrator/io.h
@@ -0,0 +1,29 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/io.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffff
+
+#define __io(a)                 ((void __iomem *)(PCI_IO_VADDR + (a)))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            ((a) + PCI_MEMORY_VADDR)
+
+#endif
diff --git a/include/asm-arm/arch-integrator/irqs.h b/include/asm-arm/arch-integrator/irqs.h
new file mode 100644
index 000000000000..ba7b3afee445
--- /dev/null
+++ b/include/asm-arm/arch-integrator/irqs.h
@@ -0,0 +1,82 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/irqs.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/* 
+ *  Interrupt numbers
+ */
+#define IRQ_PIC_START                   0
+#define IRQ_SOFTINT                     0
+#define IRQ_UARTINT0                    1
+#define IRQ_UARTINT1                    2
+#define IRQ_KMIINT0                     3
+#define IRQ_KMIINT1                     4
+#define IRQ_TIMERINT0                   5
+#define IRQ_TIMERINT1                   6
+#define IRQ_TIMERINT2                   7
+#define IRQ_RTCINT                      8
+#define IRQ_AP_EXPINT0                  9
+#define IRQ_AP_EXPINT1                  10
+#define IRQ_AP_EXPINT2                  11
+#define IRQ_AP_EXPINT3                  12
+#define IRQ_AP_PCIINT0                  13
+#define IRQ_AP_PCIINT1                  14
+#define IRQ_AP_PCIINT2                  15
+#define IRQ_AP_PCIINT3                  16
+#define IRQ_AP_V3INT                    17
+#define IRQ_AP_CPINT0                   18
+#define IRQ_AP_CPINT1                   19
+#define IRQ_AP_LBUSTIMEOUT              20
+#define IRQ_AP_APCINT                   21
+#define IRQ_CP_CLCDCINT                 22
+#define IRQ_CP_MMCIINT0                 23
+#define IRQ_CP_MMCIINT1                 24
+#define IRQ_CP_AACIINT                  25
+#define IRQ_CP_CPPLDINT                 26
+#define IRQ_CP_ETHINT                   27
+#define IRQ_CP_TSPENINT                 28
+#define IRQ_PIC_END                     31
+
+#define IRQ_CIC_START                   32
+#define IRQ_CM_SOFTINT                  32
+#define IRQ_CM_COMMRX                   33
+#define IRQ_CM_COMMTX                   34
+#define IRQ_CIC_END                     34
+
+/*
+ * IntegratorCP only
+ */
+#define IRQ_SIC_START                   35
+#define IRQ_SIC_CP_SOFTINT              35
+#define IRQ_SIC_CP_RI0                  36
+#define IRQ_SIC_CP_RI1                  37
+#define IRQ_SIC_CP_CARDIN               38
+#define IRQ_SIC_CP_LMINT0               39
+#define IRQ_SIC_CP_LMINT1               40
+#define IRQ_SIC_CP_LMINT2               41
+#define IRQ_SIC_CP_LMINT3               42
+#define IRQ_SIC_CP_LMINT4               43
+#define IRQ_SIC_CP_LMINT5               44
+#define IRQ_SIC_CP_LMINT6               45
+#define IRQ_SIC_CP_LMINT7               46
+#define IRQ_SIC_END                     46
+
+#define NR_IRQS                         47
+
diff --git a/include/asm-arm/arch-integrator/lm.h b/include/asm-arm/arch-integrator/lm.h
new file mode 100644
index 000000000000..28186b6f2c09
--- /dev/null
+++ b/include/asm-arm/arch-integrator/lm.h
@@ -0,0 +1,23 @@
+
+struct lm_device {
+        struct device           dev;
+        struct resource         resource;
+        unsigned int            irq;
+        unsigned int            id;
+};
+
+struct lm_driver {
+        struct device_driver    drv;
+        int                     (*probe)(struct lm_device *);
+        void                    (*remove)(struct lm_device *);
+        int                     (*suspend)(struct lm_device *, pm_message_t);
+        int                     (*resume)(struct lm_device *);
+};
+
+int lm_driver_register(struct lm_driver *drv);
+void lm_driver_unregister(struct lm_driver *drv);
+
+int lm_device_register(struct lm_device *dev);
+
+#define lm_get_drvdata(lm)      dev_get_drvdata(&(lm)->dev)
+#define lm_set_drvdata(lm,d)    dev_set_drvdata(&(lm)->dev, d)
diff --git a/include/asm-arm/arch-integrator/memory.h b/include/asm-arm/arch-integrator/memory.h
new file mode 100644
index 000000000000..2087ea7d28a9
--- /dev/null
+++ b/include/asm-arm/arch-integrator/memory.h
@@ -0,0 +1,39 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/memory.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x00000000UL)
+#define BUS_OFFSET      (0x80000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        (x - PAGE_OFFSET + BUS_OFFSET)
+#define __bus_to_virt(x)        (x - BUS_OFFSET + PAGE_OFFSET)
+
+#endif
diff --git a/include/asm-arm/arch-integrator/param.h b/include/asm-arm/arch-integrator/param.h
new file mode 100644
index 000000000000..afa582ff3717
--- /dev/null
+++ b/include/asm-arm/arch-integrator/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/param.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-integrator/platform.h b/include/asm-arm/arch-integrator/platform.h
new file mode 100644
index 000000000000..6b67e41669f4
--- /dev/null
+++ b/include/asm-arm/arch-integrator/platform.h
@@ -0,0 +1,465 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *                 from .s file by awk -f s2h.awk
+ */
+/**************************************************************************
+ * * Copyright © ARM Limited 1998.  All rights reserved.
+ * ***********************************************************************/
+/* ************************************************************************
+ * 
+ *   Integrator address map
+ * 
+ *      NOTE: This is a multi-hosted header file for use with uHAL and
+ *            supported debuggers.
+ * 
+ *      $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $
+ * 
+ * ***********************************************************************/
+
+#ifndef __address_h
+#define __address_h                     1
+
+/* ========================================================================
+ *  Integrator definitions
+ * ========================================================================
+ * ------------------------------------------------------------------------
+ *  Memory definitions
+ * ------------------------------------------------------------------------
+ *  Integrator memory map
+ * 
+ */
+#define INTEGRATOR_BOOT_ROM_LO          0x00000000
+#define INTEGRATOR_BOOT_ROM_HI          0x20000000
+#define INTEGRATOR_BOOT_ROM_BASE        INTEGRATOR_BOOT_ROM_HI   /*  Normal position */
+#define INTEGRATOR_BOOT_ROM_SIZE        SZ_512K
+
+/* 
+ *  New Core Modules have different amounts of SSRAM, the amount of SSRAM
+ *  fitted can be found in HDR_STAT.
+ * 
+ *  The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
+ *  the minimum amount of SSRAM fitted on any core module.
+ * 
+ *  New Core Modules also alias the SSRAM.
+ * 
+ */
+#define INTEGRATOR_SSRAM_BASE           0x00000000
+#define INTEGRATOR_SSRAM_ALIAS_BASE     0x10800000
+#define INTEGRATOR_SSRAM_SIZE           SZ_256K
+
+#define INTEGRATOR_FLASH_BASE           0x24000000
+#define INTEGRATOR_FLASH_SIZE           SZ_32M
+
+#define INTEGRATOR_MBRD_SSRAM_BASE      0x28000000
+#define INTEGRATOR_MBRD_SSRAM_SIZE      SZ_512K
+
+/* 
+ *  SDRAM is a SIMM therefore the size is not known.
+ * 
+ */
+#define INTEGRATOR_SDRAM_BASE           0x00040000
+
+#define INTEGRATOR_SDRAM_ALIAS_BASE     0x80000000
+#define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000
+#define INTEGRATOR_HDR1_SDRAM_BASE      0x90000000
+#define INTEGRATOR_HDR2_SDRAM_BASE      0xA0000000
+#define INTEGRATOR_HDR3_SDRAM_BASE      0xB0000000
+
+/* 
+ *  Logic expansion modules
+ * 
+ */
+#define INTEGRATOR_LOGIC_MODULES_BASE   0xC0000000
+#define INTEGRATOR_LOGIC_MODULE0_BASE   0xC0000000
+#define INTEGRATOR_LOGIC_MODULE1_BASE   0xD0000000
+#define INTEGRATOR_LOGIC_MODULE2_BASE   0xE0000000
+#define INTEGRATOR_LOGIC_MODULE3_BASE   0xF0000000
+
+/* ------------------------------------------------------------------------
+ *  Integrator header card registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define INTEGRATOR_HDR_ID_OFFSET        0x00
+#define INTEGRATOR_HDR_PROC_OFFSET      0x04
+#define INTEGRATOR_HDR_OSC_OFFSET       0x08
+#define INTEGRATOR_HDR_CTRL_OFFSET      0x0C
+#define INTEGRATOR_HDR_STAT_OFFSET      0x10
+#define INTEGRATOR_HDR_LOCK_OFFSET      0x14
+#define INTEGRATOR_HDR_SDRAM_OFFSET     0x20
+#define INTEGRATOR_HDR_INIT_OFFSET      0x24     /*  CM9x6 */
+#define INTEGRATOR_HDR_IC_OFFSET        0x40
+#define INTEGRATOR_HDR_SPDBASE_OFFSET   0x100
+#define INTEGRATOR_HDR_SPDTOP_OFFSET    0x200
+
+#define INTEGRATOR_HDR_BASE             0x10000000
+#define INTEGRATOR_HDR_ID               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_ID_OFFSET)
+#define INTEGRATOR_HDR_PROC             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_PROC_OFFSET)
+#define INTEGRATOR_HDR_OSC              (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_OSC_OFFSET)
+#define INTEGRATOR_HDR_CTRL             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_CTRL_OFFSET)
+#define INTEGRATOR_HDR_STAT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_STAT_OFFSET)
+#define INTEGRATOR_HDR_LOCK             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_LOCK_OFFSET)
+#define INTEGRATOR_HDR_SDRAM            (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SDRAM_OFFSET)
+#define INTEGRATOR_HDR_INIT             (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_INIT_OFFSET)
+#define INTEGRATOR_HDR_IC               (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_IC_OFFSET)
+#define INTEGRATOR_HDR_SPDBASE          (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDBASE_OFFSET)
+#define INTEGRATOR_HDR_SPDTOP           (INTEGRATOR_HDR_BASE + INTEGRATOR_HDR_SPDTOP_OFFSET)
+
+#define INTEGRATOR_HDR_CTRL_LED         0x01
+#define INTEGRATOR_HDR_CTRL_MBRD_DETECH 0x02
+#define INTEGRATOR_HDR_CTRL_REMAP       0x04
+#define INTEGRATOR_HDR_CTRL_RESET       0x08
+#define INTEGRATOR_HDR_CTRL_HIGHVECTORS 0x10
+#define INTEGRATOR_HDR_CTRL_BIG_ENDIAN  0x20
+#define INTEGRATOR_HDR_CTRL_FASTBUS     0x40
+#define INTEGRATOR_HDR_CTRL_SYNC        0x80
+
+#define INTEGRATOR_HDR_OSC_CORE_10MHz   0x102
+#define INTEGRATOR_HDR_OSC_CORE_15MHz   0x107
+#define INTEGRATOR_HDR_OSC_CORE_20MHz   0x10C
+#define INTEGRATOR_HDR_OSC_CORE_25MHz   0x111
+#define INTEGRATOR_HDR_OSC_CORE_30MHz   0x116
+#define INTEGRATOR_HDR_OSC_CORE_35MHz   0x11B
+#define INTEGRATOR_HDR_OSC_CORE_40MHz   0x120
+#define INTEGRATOR_HDR_OSC_CORE_45MHz   0x125
+#define INTEGRATOR_HDR_OSC_CORE_50MHz   0x12A
+#define INTEGRATOR_HDR_OSC_CORE_55MHz   0x12F
+#define INTEGRATOR_HDR_OSC_CORE_60MHz   0x134
+#define INTEGRATOR_HDR_OSC_CORE_65MHz   0x139
+#define INTEGRATOR_HDR_OSC_CORE_70MHz   0x13E
+#define INTEGRATOR_HDR_OSC_CORE_75MHz   0x143
+#define INTEGRATOR_HDR_OSC_CORE_80MHz   0x148
+#define INTEGRATOR_HDR_OSC_CORE_85MHz   0x14D
+#define INTEGRATOR_HDR_OSC_CORE_90MHz   0x152
+#define INTEGRATOR_HDR_OSC_CORE_95MHz   0x157
+#define INTEGRATOR_HDR_OSC_CORE_100MHz  0x15C
+#define INTEGRATOR_HDR_OSC_CORE_105MHz  0x161
+#define INTEGRATOR_HDR_OSC_CORE_110MHz  0x166
+#define INTEGRATOR_HDR_OSC_CORE_115MHz  0x16B
+#define INTEGRATOR_HDR_OSC_CORE_120MHz  0x170
+#define INTEGRATOR_HDR_OSC_CORE_125MHz  0x175
+#define INTEGRATOR_HDR_OSC_CORE_130MHz  0x17A
+#define INTEGRATOR_HDR_OSC_CORE_135MHz  0x17F
+#define INTEGRATOR_HDR_OSC_CORE_140MHz  0x184
+#define INTEGRATOR_HDR_OSC_CORE_145MHz  0x189
+#define INTEGRATOR_HDR_OSC_CORE_150MHz  0x18E
+#define INTEGRATOR_HDR_OSC_CORE_155MHz  0x193
+#define INTEGRATOR_HDR_OSC_CORE_160MHz  0x198
+#define INTEGRATOR_HDR_OSC_CORE_MASK    0x7FF
+
+#define INTEGRATOR_HDR_OSC_MEM_10MHz    0x10C000
+#define INTEGRATOR_HDR_OSC_MEM_15MHz    0x116000
+#define INTEGRATOR_HDR_OSC_MEM_20MHz    0x120000
+#define INTEGRATOR_HDR_OSC_MEM_25MHz    0x12A000
+#define INTEGRATOR_HDR_OSC_MEM_30MHz    0x134000
+#define INTEGRATOR_HDR_OSC_MEM_33MHz    0x13A000
+#define INTEGRATOR_HDR_OSC_MEM_40MHz    0x148000
+#define INTEGRATOR_HDR_OSC_MEM_50MHz    0x15C000
+#define INTEGRATOR_HDR_OSC_MEM_60MHz    0x170000
+#define INTEGRATOR_HDR_OSC_MEM_66MHz    0x17C000
+#define INTEGRATOR_HDR_OSC_MEM_MASK     0x7FF000
+
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM7x0  0x0
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x0  0x0800000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM9x6  0x1000000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_CM10x00  0x1800000
+#define INTEGRATOR_HDR_OSC_BUS_MODE_MASK  0x1800000
+
+#define INTEGRATOR_HDR_SDRAM_SPD_OK     (1 << 5)
+
+
+/* ------------------------------------------------------------------------
+ *  Integrator system registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+
+/* 
+ *  System Controller
+ * 
+ */
+#define INTEGRATOR_SC_ID_OFFSET         0x00
+#define INTEGRATOR_SC_OSC_OFFSET        0x04
+#define INTEGRATOR_SC_CTRLS_OFFSET      0x08
+#define INTEGRATOR_SC_CTRLC_OFFSET      0x0C
+#define INTEGRATOR_SC_DEC_OFFSET        0x10
+#define INTEGRATOR_SC_ARB_OFFSET        0x14
+#define INTEGRATOR_SC_PCIENABLE_OFFSET  0x18
+#define INTEGRATOR_SC_LOCK_OFFSET       0x1C
+
+#define INTEGRATOR_SC_BASE              0x11000000
+#define INTEGRATOR_SC_ID                (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
+#define INTEGRATOR_SC_OSC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
+#define INTEGRATOR_SC_CTRLS             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
+#define INTEGRATOR_SC_CTRLC             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
+#define INTEGRATOR_SC_DEC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
+#define INTEGRATOR_SC_ARB               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
+#define INTEGRATOR_SC_PCIENABLE         (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
+#define INTEGRATOR_SC_LOCK              (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)
+
+#define INTEGRATOR_SC_OSC_SYS_10MHz     0x20
+#define INTEGRATOR_SC_OSC_SYS_15MHz     0x34
+#define INTEGRATOR_SC_OSC_SYS_20MHz     0x48
+#define INTEGRATOR_SC_OSC_SYS_25MHz     0x5C
+#define INTEGRATOR_SC_OSC_SYS_33MHz     0x7C
+#define INTEGRATOR_SC_OSC_SYS_MASK      0xFF
+
+#define INTEGRATOR_SC_OSC_PCI_25MHz     0x100
+#define INTEGRATOR_SC_OSC_PCI_33MHz     0x0
+#define INTEGRATOR_SC_OSC_PCI_MASK      0x100
+
+#define INTEGRATOR_SC_CTRL_SOFTRST      (1 << 0)
+#define INTEGRATOR_SC_CTRL_nFLVPPEN     (1 << 1)
+#define INTEGRATOR_SC_CTRL_nFLWP        (1 << 2)
+#define INTEGRATOR_SC_CTRL_URTS0        (1 << 4)
+#define INTEGRATOR_SC_CTRL_UDTR0        (1 << 5)
+#define INTEGRATOR_SC_CTRL_URTS1        (1 << 6)
+#define INTEGRATOR_SC_CTRL_UDTR1        (1 << 7)
+
+/* 
+ *  External Bus Interface
+ * 
+ */
+#define INTEGRATOR_EBI_BASE             0x12000000 
+
+#define INTEGRATOR_EBI_CSR0_OFFSET      0x00
+#define INTEGRATOR_EBI_CSR1_OFFSET      0x04
+#define INTEGRATOR_EBI_CSR2_OFFSET      0x08
+#define INTEGRATOR_EBI_CSR3_OFFSET      0x0C
+#define INTEGRATOR_EBI_LOCK_OFFSET      0x20
+
+#define INTEGRATOR_EBI_CSR0             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
+#define INTEGRATOR_EBI_CSR1             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
+#define INTEGRATOR_EBI_CSR2             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
+#define INTEGRATOR_EBI_CSR3             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
+#define INTEGRATOR_EBI_LOCK             (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
+
+#define INTEGRATOR_EBI_8_BIT            0x00
+#define INTEGRATOR_EBI_16_BIT           0x01
+#define INTEGRATOR_EBI_32_BIT           0x02
+#define INTEGRATOR_EBI_WRITE_ENABLE     0x04
+#define INTEGRATOR_EBI_SYNC             0x08
+#define INTEGRATOR_EBI_WS_2             0x00
+#define INTEGRATOR_EBI_WS_3             0x10
+#define INTEGRATOR_EBI_WS_4             0x20
+#define INTEGRATOR_EBI_WS_5             0x30
+#define INTEGRATOR_EBI_WS_6             0x40
+#define INTEGRATOR_EBI_WS_7             0x50
+#define INTEGRATOR_EBI_WS_8             0x60
+#define INTEGRATOR_EBI_WS_9             0x70
+#define INTEGRATOR_EBI_WS_10            0x80
+#define INTEGRATOR_EBI_WS_11            0x90
+#define INTEGRATOR_EBI_WS_12            0xA0
+#define INTEGRATOR_EBI_WS_13            0xB0
+#define INTEGRATOR_EBI_WS_14            0xC0
+#define INTEGRATOR_EBI_WS_15            0xD0
+#define INTEGRATOR_EBI_WS_16            0xE0
+#define INTEGRATOR_EBI_WS_17            0xF0
+
+
+#define INTEGRATOR_CT_BASE              0x13000000       /*  Counter/Timers */
+#define INTEGRATOR_IC_BASE              0x14000000       /*  Interrupt Controller */
+#define INTEGRATOR_RTC_BASE             0x15000000       /*  Real Time Clock */
+#define INTEGRATOR_UART0_BASE           0x16000000       /*  UART 0 */
+#define INTEGRATOR_UART1_BASE           0x17000000       /*  UART 1 */
+#define INTEGRATOR_KBD_BASE             0x18000000       /*  Keyboard */
+#define INTEGRATOR_MOUSE_BASE           0x19000000       /*  Mouse */
+
+/* 
+ *  LED's & Switches
+ * 
+ */
+#define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
+#define INTEGRATOR_DBG_LEDS_OFFSET      0x04
+#define INTEGRATOR_DBG_SWITCH_OFFSET    0x08
+
+#define INTEGRATOR_DBG_BASE             0x1A000000
+#define INTEGRATOR_DBG_ALPHA            (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
+#define INTEGRATOR_DBG_LEDS             (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
+#define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)
+
+
+#define INTEGRATOR_GPIO_BASE            0x1B000000       /*  GPIO */
+
+/* ------------------------------------------------------------------------
+ *  KMI keyboard/mouse definitions
+ * ------------------------------------------------------------------------
+ */
+/* PS2 Keyboard interface */
+#define KMI0_BASE                       INTEGRATOR_KBD_BASE             
+
+/* PS2 Mouse interface */
+#define KMI1_BASE                       INTEGRATOR_MOUSE_BASE
+
+/* KMI definitions are now in include/asm-arm/hardware/amba_kmi.h -- rmk */
+
+/* ------------------------------------------------------------------------
+ *  Where in the memory map does PCI live?
+ * ------------------------------------------------------------------------
+ *  This represents a fairly liberal usage of address space.  Even though
+ *  the V3 only has two windows (therefore we need to map stuff on the fly),
+ *  we maintain the same addresses, even if they're not mapped.
+ * 
+ */
+#define PHYS_PCI_MEM_BASE               0x40000000   /* 512M to xxx */
+/*  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
+ */
+#define PHYS_PCI_IO_BASE                0x60000000   /* 16M to xxx */
+/*  unused (128-16)M from B1000000-B7FFFFFF
+ */
+#define PHYS_PCI_CONFIG_BASE            0x61000000   /* 16M to xxx */
+/*  unused ((128-16)M - 64K) from XXX
+ */
+#define PHYS_PCI_V3_BASE                0x62000000
+
+#define PCI_DRAMSIZE                    INTEGRATOR_SSRAM_SIZE   
+
+/* 'export' these to UHAL */
+#define UHAL_PCI_IO                     PCI_IO_BASE
+#define UHAL_PCI_MEM                    PCI_MEM_BASE
+#define UHAL_PCI_ALLOC_IO_BASE          0x00004000
+#define UHAL_PCI_ALLOC_MEM_BASE         PCI_MEM_BASE
+#define UHAL_PCI_MAX_SLOT               20
+        
+/* ========================================================================
+ *  Start of uHAL definitions
+ * ========================================================================
+ */
+
+/* ------------------------------------------------------------------------
+ *  Integrator Interrupt Controllers
+ * ------------------------------------------------------------------------
+ * 
+ *  Offsets from interrupt controller base 
+ * 
+ *  System Controller interrupt controller base is
+ * 
+ *      INTEGRATOR_IC_BASE + (header_number << 6)
+ * 
+ *  Core Module interrupt controller base is
+ * 
+ *      INTEGRATOR_HDR_IC 
+ * 
+ */
+#define IRQ_STATUS                      0
+#define IRQ_RAW_STATUS                  0x04
+#define IRQ_ENABLE                      0x08
+#define IRQ_ENABLE_SET                  0x08
+#define IRQ_ENABLE_CLEAR                0x0C
+
+#define INT_SOFT_SET                    0x10
+#define INT_SOFT_CLEAR                  0x14
+
+#define FIQ_STATUS                      0x20
+#define FIQ_RAW_STATUS                  0x24
+#define FIQ_ENABLE                      0x28
+#define FIQ_ENABLE_SET                  0x28
+#define FIQ_ENABLE_CLEAR                0x2C
+
+
+/* ------------------------------------------------------------------------
+ *  Interrupts
+ * ------------------------------------------------------------------------
+ * 
+ *  
+ *  Each Core Module has two interrupts controllers, one on the core module
+ *  itself and one in the system controller on the motherboard.  The
+ *  READ_INT macro in target.s reads both interrupt controllers and returns
+ *  a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
+ *  and bits 24 to 31 are from the core module.
+ *  
+ *  The following definitions relate to the bitmask returned by READ_INT.
+ * 
+ */
+
+/* ------------------------------------------------------------------------
+ *  LED's - The header LED is not accessible via the uHAL API
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define GREEN_LED                       0x01
+#define YELLOW_LED                      0x02
+#define RED_LED                         0x04
+#define GREEN_LED_2                     0x08
+#define ALL_LEDS                        0x0F
+
+#define LED_BANK                        INTEGRATOR_DBG_LEDS
+
+/* 
+ *  Memory definitions - run uHAL out of SSRAM.
+ * 
+ */
+#define uHAL_MEMORY_SIZE                INTEGRATOR_SSRAM_SIZE
+
+/* 
+ *  Application Flash
+ * 
+ */
+#define FLASH_BASE                      INTEGRATOR_FLASH_BASE
+#define FLASH_SIZE                      INTEGRATOR_FLASH_SIZE
+#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
+#define FLASH_BLOCK_SIZE                SZ_128K
+
+/* 
+ *  Boot Flash
+ * 
+ */
+#define EPROM_BASE                      INTEGRATOR_BOOT_ROM_HI
+#define EPROM_SIZE                      INTEGRATOR_BOOT_ROM_SIZE
+#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
+
+/* 
+ *  Clean base - dummy
+ * 
+ */
+#define CLEAN_BASE                      EPROM_BASE
+
+/* 
+ *  Timer definitions
+ * 
+ *  Only use timer 1 & 2
+ *  (both run at 24MHz and will need the clock divider set to 16).
+ * 
+ *  Timer 0 runs at bus frequency and therefore could vary and currently
+ *  uHAL can't handle that.
+ * 
+ */
+
+#define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
+#define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
+#define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)
+
+#define MAX_TIMER                       2
+#define MAX_PERIOD                      699050
+#define TICKS_PER_uSEC                  24
+
+/* 
+ *  These are useconds NOT ticks.  
+ * 
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+
+#define INTEGRATOR_CSR_BASE             0x10000000
+#define INTEGRATOR_CSR_SIZE             0x10000000
+
+#endif
+
+/*      END */
diff --git a/include/asm-arm/arch-integrator/system.h b/include/asm-arm/arch-integrator/system.h
new file mode 100644
index 000000000000..8ea442237d20
--- /dev/null
+++ b/include/asm-arm/arch-integrator/system.h
@@ -0,0 +1,44 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/system.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/cm.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        cm_control(CM_CTRL_RESET, CM_CTRL_RESET);
+}
+
+#endif
diff --git a/include/asm-arm/arch-integrator/timex.h b/include/asm-arm/arch-integrator/timex.h
new file mode 100644
index 000000000000..87a762818ba2
--- /dev/null
+++ b/include/asm-arm/arch-integrator/timex.h
@@ -0,0 +1,26 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/timex.h
+ *
+ *  Integrator architecture timex specifications
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * ??
+ */
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-integrator/uncompress.h b/include/asm-arm/arch-integrator/uncompress.h
new file mode 100644
index 000000000000..3957402741d3
--- /dev/null
+++ b/include/asm-arm/arch-integrator/uncompress.h
@@ -0,0 +1,53 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/uncompress.h
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define AMBA_UART_DR    (*(volatile unsigned char *)0x16000000)
+#define AMBA_UART_LCRH  (*(volatile unsigned char *)0x16000008)
+#define AMBA_UART_LCRM  (*(volatile unsigned char *)0x1600000c)
+#define AMBA_UART_LCRL  (*(volatile unsigned char *)0x16000010)
+#define AMBA_UART_CR    (*(volatile unsigned char *)0x16000014)
+#define AMBA_UART_FR    (*(volatile unsigned char *)0x16000018)
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                while (AMBA_UART_FR & (1 << 5));
+
+                AMBA_UART_DR = *s;
+
+                if (*s == '\n') {
+                        while (AMBA_UART_FR & (1 << 5));
+
+                        AMBA_UART_DR = '\r';
+                }
+                s++;
+        }
+        while (AMBA_UART_FR & (1 << 3));
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-integrator/vmalloc.h b/include/asm-arm/arch-integrator/vmalloc.h
new file mode 100644
index 000000000000..50e9aee79486
--- /dev/null
+++ b/include/asm-arm/arch-integrator/vmalloc.h
@@ -0,0 +1,31 @@
+/*
+ *  linux/include/asm-arm/arch-integrator/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-iop3xx/debug-macro.S b/include/asm-arm/arch-iop3xx/debug-macro.S
new file mode 100644
index 000000000000..cc15f80ebd9a
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/debug-macro.S
@@ -0,0 +1,48 @@
+/* linux/include/asm-arm/arch-iop3xx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mov     \rx, #0xfe000000        @ physical
+#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
+                orr     \rx, \rx, #0x00800000   @ location of the UART
+#elif defined(CONFIG_ARCH_IOP331)
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x000fe000        @ Physical Base
+                movne   \rx, #0
+                orr     \rx, \rx, #0xfe000000
+                orr     \rx, \rx, #0x00f00000   @ Virtual Base
+                orr     \rx, \rx, #0x00001700   @ location of the UART
+#else
+#error Unknown IOP3XX implementation
+#endif
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldrb    \rd, [\rx, #0x5]
+                and     \rd, \rd, #0x60
+                teq     \rd, #0x60
+                bne     1002b
+                .endm
+
+                .macro  waituart,rd,rx
+#if !defined(CONFIG_ARCH_IQ80321) || !defined(CONFIG_ARCH_IQ31244) || !defined(CONFIG_ARCH_IQ80331)
+1001:           ldrb    \rd, [\rx, #0x6]
+                tst     \rd, #0x10
+                beq     1001b
+#endif
+                .endm
diff --git a/include/asm-arm/arch-iop3xx/dma.h b/include/asm-arm/arch-iop3xx/dma.h
new file mode 100644
index 000000000000..797f9e6fc745
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/dma.h
@@ -0,0 +1,16 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/dma.h
+ *
+ *  Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IOP3XX_DMA_H_P
+#define _IOP3XX_DMA_H_P
+
+#define MAX_DMA_ADDRESS         0xffffffff
+
+#endif /* _ASM_ARCH_DMA_H_P */
diff --git a/include/asm-arm/arch-iop3xx/entry-macro.S b/include/asm-arm/arch-iop3xx/entry-macro.S
new file mode 100644
index 000000000000..e2ce7f5467c8
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/entry-macro.S
@@ -0,0 +1,56 @@
+/*
+ * include/asm-arm/arch-iop3xx/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IOP3xx-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#if defined(CONFIG_ARCH_IOP321)
+                .macro  disable_fiq
+                .endm
+
+                /*
+                 * Note: only deal with normal interrupts, not FIQ
+                 */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \irqnr, #0
+                mrc     p6, 0, \irqstat, c8, c0, 0      @ Read IINTSRC
+                cmp     \irqstat, #0
+                beq     1001f
+                clz     \irqnr, \irqstat
+                mov     \base, #31
+                subs    \irqnr,\base,\irqnr
+                add     \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
+1001:
+                .endm
+
+#elif defined(CONFIG_ARCH_IOP331)
+                .macro  disable_fiq
+                .endm
+
+                /*
+                 * Note: only deal with normal interrupts, not FIQ
+                 */
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \irqnr, #0
+                mrc     p6, 0, \irqstat, c4, c0, 0      @ Read IINTSRC0
+                cmp     \irqstat, #0
+                bne     1002f
+                mrc     p6, 0, \irqstat, c5, c0, 0      @ Read IINTSRC1
+                cmp     \irqstat, #0
+                beq     1001f
+                clz     \irqnr, \irqstat
+                rsbs    \irqnr,\irqnr,#31   @ recommend by RMK
+                add     \irqnr,\irqnr,#IRQ_IOP331_XINT8
+                b       1001f
+1002:   clz     \irqnr, \irqstat
+                rsbs    \irqnr,\irqnr,#31   @ recommend by RMK
+                add     \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
+1001:
+                .endm
+
+#endif
+
diff --git a/include/asm-arm/arch-iop3xx/hardware.h b/include/asm-arm/arch-iop3xx/hardware.h
new file mode 100644
index 000000000000..3b138171d086
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/hardware.h
@@ -0,0 +1,57 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/hardware.h
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/types.h>
+
+/*
+ * Note about PCI IO space mappings
+ *
+ * To make IO space accesses efficient, we store virtual addresses in
+ * the IO resources.
+ *
+ * The PCI IO space is located at virtual 0xfe000000 from physical
+ * 0x90000000.  The PCI BARs must be programmed with physical addresses,
+ * but when we read them, we convert them to virtual addresses.  See
+ * arch/arm/mach-iop3xx/iop3xx-pci.c
+ */
+
+#define pcibios_assign_all_busses() 1
+
+
+/*
+ * The min PCI I/O and MEM space are dependent on what specific
+ * chipset/platform we are running on, so instead of hardcoding with
+ * #ifdefs, we just fill these in the platform level PCI init code.
+ */
+#ifndef __ASSEMBLY__
+extern unsigned long iop3xx_pcibios_min_io;
+extern unsigned long iop3xx_pcibios_min_mem;
+
+extern unsigned int processor_id;
+#endif
+
+/*
+ * We just set these to zero since they are really bogus anyways
+ */
+#define PCIBIOS_MIN_IO      (iop3xx_pcibios_min_io)
+#define PCIBIOS_MIN_MEM     (iop3xx_pcibios_min_mem)
+
+/*
+ * Generic chipset bits
+ *
+ */
+#include "iop321.h"
+#include "iop331.h"
+
+/*
+ * Board specific bits
+ */
+#include "iq80321.h"
+#include "iq31244.h"
+#include "iq80331.h"
+#include "iq80332.h"
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h
new file mode 100644
index 000000000000..2761dfd8694d
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/io.h
@@ -0,0 +1,20 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/io.h
+ *
+ *  Copyright (C) 2001  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+#define __io(p)                 ((void __iomem *)(p))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+#endif
diff --git a/include/asm-arm/arch-iop3xx/iop321-irqs.h b/include/asm-arm/arch-iop3xx/iop321-irqs.h
new file mode 100644
index 000000000000..2fcc1654cb9d
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop321-irqs.h
@@ -0,0 +1,100 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/irqs.h
+ *
+ * Author:      Rory Bolt <rorybolt@pacbell.net>
+ * Copyright:   (C) 2002 Rory Bolt
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef _IOP321_IRQS_H_
+#define _IOP321_IRQS_H_
+
+/*
+ * IOP80321 chipset interrupts
+ */
+#define IOP321_IRQ_OFS          0
+#define IOP321_IRQ(x)           (IOP321_IRQ_OFS + (x))
+
+/*
+ * On IRQ or FIQ register
+ */
+#define IRQ_IOP321_DMA0_EOT     IOP321_IRQ(0)
+#define IRQ_IOP321_DMA0_EOC     IOP321_IRQ(1)
+#define IRQ_IOP321_DMA1_EOT     IOP321_IRQ(2)
+#define IRQ_IOP321_DMA1_EOC     IOP321_IRQ(3)
+#define IRQ_IOP321_RSVD_4       IOP321_IRQ(4)
+#define IRQ_IOP321_RSVD_5       IOP321_IRQ(5)
+#define IRQ_IOP321_AA_EOT       IOP321_IRQ(6)
+#define IRQ_IOP321_AA_EOC       IOP321_IRQ(7)
+#define IRQ_IOP321_CORE_PMON    IOP321_IRQ(8)
+#define IRQ_IOP321_TIMER0       IOP321_IRQ(9)
+#define IRQ_IOP321_TIMER1       IOP321_IRQ(10)
+#define IRQ_IOP321_I2C_0        IOP321_IRQ(11)
+#define IRQ_IOP321_I2C_1        IOP321_IRQ(12)
+#define IRQ_IOP321_MESSAGING    IOP321_IRQ(13)
+#define IRQ_IOP321_ATU_BIST     IOP321_IRQ(14)
+#define IRQ_IOP321_PERFMON      IOP321_IRQ(15)
+#define IRQ_IOP321_CORE_PMU     IOP321_IRQ(16)
+#define IRQ_IOP321_BIU_ERR      IOP321_IRQ(17)
+#define IRQ_IOP321_ATU_ERR      IOP321_IRQ(18)
+#define IRQ_IOP321_MCU_ERR      IOP321_IRQ(19)
+#define IRQ_IOP321_DMA0_ERR     IOP321_IRQ(20)
+#define IRQ_IOP321_DMA1_ERR     IOP321_IRQ(21)
+#define IRQ_IOP321_RSVD_22      IOP321_IRQ(22)
+#define IRQ_IOP321_AA_ERR       IOP321_IRQ(23)
+#define IRQ_IOP321_MSG_ERR      IOP321_IRQ(24)
+#define IRQ_IOP321_SSP          IOP321_IRQ(25)
+#define IRQ_IOP321_RSVD_26      IOP321_IRQ(26)
+#define IRQ_IOP321_XINT0        IOP321_IRQ(27)
+#define IRQ_IOP321_XINT1        IOP321_IRQ(28)
+#define IRQ_IOP321_XINT2        IOP321_IRQ(29)
+#define IRQ_IOP321_XINT3        IOP321_IRQ(30)
+#define IRQ_IOP321_HPI          IOP321_IRQ(31)
+
+#define NR_IOP321_IRQS          (IOP321_IRQ(31) + 1)
+
+#define NR_IRQS                 NR_IOP321_IRQS
+
+
+/*
+ * Interrupts available on the IQ80321 board
+ */
+
+/*
+ * On board devices
+ */
+#define IRQ_IQ80321_I82544      IRQ_IOP321_XINT0
+#define IRQ_IQ80321_UART        IRQ_IOP321_XINT1
+
+/*
+ * PCI interrupts
+ */
+#define IRQ_IQ80321_INTA        IRQ_IOP321_XINT0
+#define IRQ_IQ80321_INTB        IRQ_IOP321_XINT1
+#define IRQ_IQ80321_INTC        IRQ_IOP321_XINT2
+#define IRQ_IQ80321_INTD        IRQ_IOP321_XINT3
+
+/*
+ * Interrupts on the IQ31244 board
+ */
+
+/*
+ * On board devices
+ */
+#define IRQ_IQ31244_UART        IRQ_IOP321_XINT1
+#define IRQ_IQ31244_I82546      IRQ_IOP321_XINT0
+#define IRQ_IQ31244_SATA        IRQ_IOP321_XINT2
+#define IRQ_IQ31244_PCIX_SLOT   IRQ_IOP321_XINT3
+
+/*
+ * PCI interrupts
+ */
+#define IRQ_IQ31244_INTA        IRQ_IOP321_XINT0
+#define IRQ_IQ31244_INTB        IRQ_IOP321_XINT1
+#define IRQ_IQ31244_INTC        IRQ_IOP321_XINT2
+#define IRQ_IQ31244_INTD        IRQ_IOP321_XINT3
+
+#endif // _IOP321_IRQ_H_
diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h
new file mode 100644
index 000000000000..200621ff3690
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop321.h
@@ -0,0 +1,345 @@
+/*
+ * linux/include/asm/arch-iop3xx/iop321.h
+ *
+ * Intel IOP321 Chip definitions
+ *
+ * Author: Rory Bolt <rorybolt@pacbell.net>
+ * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IOP321_HW_H_
+#define _IOP321_HW_H_
+
+
+/*
+ * This is needed for mixed drivers that need to work on all
+ * IOP3xx variants but behave slightly differently on each.
+ */
+#ifndef __ASSEMBLY__
+#ifdef  CONFIG_ARCH_IOP321
+#define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420))
+#else
+#define iop_is_321()    0
+#endif
+#endif
+
+/*
+ * IOP321 I/O and Mem space regions for PCI autoconfiguration
+ */
+#define IOP321_PCI_IO_WINDOW_SIZE   0x00010000
+#define IOP321_PCI_LOWER_IO_PA      0x90000000
+#define IOP321_PCI_LOWER_IO_VA      0xfe000000
+#define IOP321_PCI_LOWER_IO_BA      (*IOP321_OIOWTVR)
+#define IOP321_PCI_UPPER_IO_PA      (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_IO_VA      (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_IO_BA      (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_IO_OFFSET        (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
+
+//#define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1)
+#define IOP321_PCI_MEM_WINDOW_SIZE  0x04000000 /* 64M outbound window */
+#define IOP321_PCI_LOWER_MEM_PA     0x80000000
+#define IOP321_PCI_LOWER_MEM_BA     (*IOP321_OMWTVR0)
+#define IOP321_PCI_UPPER_MEM_PA     (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_MEM_BA     (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP321_PCI_MEM_OFFSET       (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
+
+
+/*
+ * IOP321 chipset registers
+ */
+#define IOP321_VIRT_MEM_BASE 0xfeffe000  /* chip virtual mem address*/
+#define IOP321_PHYS_MEM_BASE 0xffffe000  /* chip physical memory address */
+#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
+
+/* Reserved 0x00000000 through 0x000000FF */
+
+/* Address Translation Unit 0x00000100 through 0x000001FF */
+#define IOP321_ATUVID     (volatile u16 *)IOP321_REG_ADDR(0x00000100)
+#define IOP321_ATUDID     (volatile u16 *)IOP321_REG_ADDR(0x00000102)
+#define IOP321_ATUCMD     (volatile u16 *)IOP321_REG_ADDR(0x00000104)
+#define IOP321_ATUSR      (volatile u16 *)IOP321_REG_ADDR(0x00000106)
+#define IOP321_ATURID     (volatile u8  *)IOP321_REG_ADDR(0x00000108)
+#define IOP321_ATUCCR     (volatile u32 *)IOP321_REG_ADDR(0x00000109)
+#define IOP321_ATUCLSR    (volatile u8  *)IOP321_REG_ADDR(0x0000010C)
+#define IOP321_ATULT      (volatile u8  *)IOP321_REG_ADDR(0x0000010D)
+#define IOP321_ATUHTR     (volatile u8  *)IOP321_REG_ADDR(0x0000010E)
+#define IOP321_ATUBIST    (volatile u8  *)IOP321_REG_ADDR(0x0000010F)
+#define IOP321_IABAR0     (volatile u32 *)IOP321_REG_ADDR(0x00000110)
+#define IOP321_IAUBAR0    (volatile u32 *)IOP321_REG_ADDR(0x00000114)
+#define IOP321_IABAR1     (volatile u32 *)IOP321_REG_ADDR(0x00000118)
+#define IOP321_IAUBAR1    (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
+#define IOP321_IABAR2     (volatile u32 *)IOP321_REG_ADDR(0x00000120)
+#define IOP321_IAUBAR2    (volatile u32 *)IOP321_REG_ADDR(0x00000124)
+#define IOP321_ASVIR      (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
+#define IOP321_ASIR       (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
+#define IOP321_ERBAR      (volatile u32 *)IOP321_REG_ADDR(0x00000130)
+/* Reserved 0x00000134 through 0x0000013B */
+#define IOP321_ATUILR     (volatile u8  *)IOP321_REG_ADDR(0x0000013C)
+#define IOP321_ATUIPR     (volatile u8  *)IOP321_REG_ADDR(0x0000013D)
+#define IOP321_ATUMGNT    (volatile u8  *)IOP321_REG_ADDR(0x0000013E)
+#define IOP321_ATUMLAT    (volatile u8  *)IOP321_REG_ADDR(0x0000013F)
+#define IOP321_IALR0      (volatile u32 *)IOP321_REG_ADDR(0x00000140)
+#define IOP321_IATVR0     (volatile u32 *)IOP321_REG_ADDR(0x00000144)
+#define IOP321_ERLR       (volatile u32 *)IOP321_REG_ADDR(0x00000148)
+#define IOP321_ERTVR      (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
+#define IOP321_IALR1      (volatile u32 *)IOP321_REG_ADDR(0x00000150)
+#define IOP321_IALR2      (volatile u32 *)IOP321_REG_ADDR(0x00000154)
+#define IOP321_IATVR2     (volatile u32 *)IOP321_REG_ADDR(0x00000158)
+#define IOP321_OIOWTVR    (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
+#define IOP321_OMWTVR0    (volatile u32 *)IOP321_REG_ADDR(0x00000160)
+#define IOP321_OUMWTVR0   (volatile u32 *)IOP321_REG_ADDR(0x00000164)
+#define IOP321_OMWTVR1    (volatile u32 *)IOP321_REG_ADDR(0x00000168)
+#define IOP321_OUMWTVR1   (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
+/* Reserved 0x00000170 through 0x00000177*/
+#define IOP321_OUDWTVR    (volatile u32 *)IOP321_REG_ADDR(0x00000178)
+/* Reserved 0x0000017C through 0x0000017F*/
+#define IOP321_ATUCR      (volatile u32 *)IOP321_REG_ADDR(0x00000180)
+#define IOP321_PCSR       (volatile u32 *)IOP321_REG_ADDR(0x00000184)
+#define IOP321_ATUISR     (volatile u32 *)IOP321_REG_ADDR(0x00000188)
+#define IOP321_ATUIMR     (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
+#define IOP321_IABAR3     (volatile u32 *)IOP321_REG_ADDR(0x00000190)
+#define IOP321_IAUBAR3    (volatile u32 *)IOP321_REG_ADDR(0x00000194)
+#define IOP321_IALR3      (volatile u32 *)IOP321_REG_ADDR(0x00000198)
+#define IOP321_IATVR3     (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
+/* Reserved 0x000001A0 through 0x000001A3*/
+#define IOP321_OCCAR      (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
+/* Reserved 0x000001A8 through 0x000001AB*/
+#define IOP321_OCCDR      (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
+/* Reserved 0x000001B0 through 0x000001BB*/
+#define IOP321_PDSCR      (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
+#define IOP321_PMCAPID    (volatile u8  *)IOP321_REG_ADDR(0x000001C0)
+#define IOP321_PMNEXT     (volatile u8  *)IOP321_REG_ADDR(0x000001C1)
+#define IOP321_APMCR      (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
+#define IOP321_APMCSR     (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
+/* Reserved 0x000001C6 through 0x000001DF */
+#define IOP321_PCIXCAPID  (volatile u8  *)IOP321_REG_ADDR(0x000001E0)
+#define IOP321_PCIXNEXT   (volatile u8  *)IOP321_REG_ADDR(0x000001E1)
+#define IOP321_PCIXCMD    (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
+#define IOP321_PCIXSR     (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
+#define IOP321_PCIIRSR    (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
+
+/* Messaging Unit 0x00000300 through 0x000003FF */
+
+/* Reserved 0x00000300 through 0x0000030c */
+#define IOP321_IMR0       (volatile u32 *)IOP321_REG_ADDR(0x00000310)
+#define IOP321_IMR1       (volatile u32 *)IOP321_REG_ADDR(0x00000314)
+#define IOP321_OMR0       (volatile u32 *)IOP321_REG_ADDR(0x00000318)
+#define IOP321_OMR1       (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
+#define IOP321_IDR        (volatile u32 *)IOP321_REG_ADDR(0x00000320)
+#define IOP321_IISR       (volatile u32 *)IOP321_REG_ADDR(0x00000324)
+#define IOP321_IIMR       (volatile u32 *)IOP321_REG_ADDR(0x00000328)
+#define IOP321_ODR        (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
+#define IOP321_OISR       (volatile u32 *)IOP321_REG_ADDR(0x00000330)
+#define IOP321_OIMR       (volatile u32 *)IOP321_REG_ADDR(0x00000334)
+/* Reserved 0x00000338 through 0x0000034F */
+#define IOP321_MUCR       (volatile u32 *)IOP321_REG_ADDR(0x00000350)
+#define IOP321_QBAR       (volatile u32 *)IOP321_REG_ADDR(0x00000354)
+/* Reserved 0x00000358 through 0x0000035C */
+#define IOP321_IFHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000360)
+#define IOP321_IFTPR      (volatile u32 *)IOP321_REG_ADDR(0x00000364)
+#define IOP321_IPHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000368)
+#define IOP321_IPTPR      (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
+#define IOP321_OFHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000370)
+#define IOP321_OFTPR      (volatile u32 *)IOP321_REG_ADDR(0x00000374)
+#define IOP321_OPHPR      (volatile u32 *)IOP321_REG_ADDR(0x00000378)
+#define IOP321_OPTPR      (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
+#define IOP321_IAR        (volatile u32 *)IOP321_REG_ADDR(0x00000380)
+
+#define IOP321_IIxR_MASK        0x7f /* masks all */
+#define IOP321_IIxR_IRI         0x40 /* RC Index Register Interrupt */
+#define IOP321_IIxR_OFQF        0x20 /* RC Output Free Q Full (ERROR) */
+#define IOP321_IIxR_ipq         0x10 /* RC Inbound Post Q (post) */
+#define IOP321_IIxR_ERRDI       0x08 /* RO Error Doorbell Interrupt */
+#define IOP321_IIxR_IDI         0x04 /* RO Inbound Doorbell Interrupt */
+#define IOP321_IIxR_IM1         0x02 /* RC Inbound Message 1 Interrupt */
+#define IOP321_IIxR_IM0         0x01 /* RC Inbound Message 0 Interrupt */
+
+/* Reserved 0x00000384 through 0x000003FF */
+
+/* DMA Controller 0x00000400 through 0x000004FF */
+#define IOP321_DMA0_CCR   (volatile u32 *)IOP321_REG_ADDR(0x00000400)
+#define IOP321_DMA0_CSR   (volatile u32 *)IOP321_REG_ADDR(0x00000404)
+#define IOP321_DMA0_DAR   (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
+#define IOP321_DMA0_NDAR  (volatile u32 *)IOP321_REG_ADDR(0x00000410)
+#define IOP321_DMA0_PADR  (volatile u32 *)IOP321_REG_ADDR(0x00000414)
+#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
+#define IOP321_DMA0_LADR  (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
+#define IOP321_DMA0_BCR   (volatile u32 *)IOP321_REG_ADDR(0x00000420)
+#define IOP321_DMA0_DCR   (volatile u32 *)IOP321_REG_ADDR(0x00000424)
+/* Reserved 0x00000428 through 0x0000043C */
+#define IOP321_DMA1_CCR   (volatile u32 *)IOP321_REG_ADDR(0x00000440)
+#define IOP321_DMA1_CSR   (volatile u32 *)IOP321_REG_ADDR(0x00000444)
+#define IOP321_DMA1_DAR   (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
+#define IOP321_DMA1_NDAR  (volatile u32 *)IOP321_REG_ADDR(0x00000450)
+#define IOP321_DMA1_PADR  (volatile u32 *)IOP321_REG_ADDR(0x00000454)
+#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
+#define IOP321_DMA1_LADR  (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
+#define IOP321_DMA1_BCR   (volatile u32 *)IOP321_REG_ADDR(0x00000460)
+#define IOP321_DMA1_DCR   (volatile u32 *)IOP321_REG_ADDR(0x00000464)
+/* Reserved 0x00000468 through 0x000004FF */
+
+/* Memory controller 0x00000500 through 0x0005FF */
+
+/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
+#define IOP321_PBCR       (volatile u32 *)IOP321_REG_ADDR(0x00000680)
+#define IOP321_PBISR      (volatile u32 *)IOP321_REG_ADDR(0x00000684)
+#define IOP321_PBBAR0     (volatile u32 *)IOP321_REG_ADDR(0x00000688)
+#define IOP321_PBLR0      (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
+#define IOP321_PBBAR1     (volatile u32 *)IOP321_REG_ADDR(0x00000690)
+#define IOP321_PBLR1      (volatile u32 *)IOP321_REG_ADDR(0x00000694)
+#define IOP321_PBBAR2     (volatile u32 *)IOP321_REG_ADDR(0x00000698)
+#define IOP321_PBLR2      (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
+#define IOP321_PBBAR3     (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
+#define IOP321_PBLR3      (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
+#define IOP321_PBBAR4     (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
+#define IOP321_PBLR4      (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
+#define IOP321_PBBAR5     (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
+#define IOP321_PBLR5      (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
+#define IOP321_PBDSCR     (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
+/* Reserved 0x000006BC */
+#define IOP321_PMBR0      (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
+/* Reserved 0x000006C4 through 0x000006DC */
+#define IOP321_PMBR1      (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
+#define IOP321_PMBR2      (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
+
+#define IOP321_PBCR_EN    0x1
+
+#define IOP321_PBISR_BOOR_ERR 0x1
+
+/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
+#define IOP321_GTMR     (volatile u32 *)IOP321_REG_ADDR(0x00000700)
+#define IOP321_ESR      (volatile u32 *)IOP321_REG_ADDR(0x00000704)
+#define IOP321_EMISR    (volatile u32 *)IOP321_REG_ADDR(0x00000708)
+/* reserved 0x00000070c */
+#define IOP321_GTSR     (volatile u32 *)IOP321_REG_ADDR(0x00000710)
+/* PERC0 DOESN'T EXIST - index from 1! */
+#define IOP321_PERCR0   (volatile u32 *)IOP321_REG_ADDR(0x00000710)
+
+#define IOP321_GTMR_NGCE        0x04 /* (Not) Global Counter Enable */
+
+/* Internal arbitration unit 0x00000780 through 0x0007BF */
+#define IOP321_IACR     (volatile u32 *)IOP321_REG_ADDR(0x00000780)
+#define IOP321_MTTR1    (volatile u32 *)IOP321_REG_ADDR(0x00000784)
+#define IOP321_MTTR2    (volatile u32 *)IOP321_REG_ADDR(0x00000788)
+
+/* General Purpose I/O Registers */
+#define IOP321_GPOE       (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
+#define IOP321_GPID       (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
+#define IOP321_GPOD       (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
+
+/* Interrupt Controller */
+#define IOP321_INTCTL     (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
+#define IOP321_INTSTR     (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
+#define IOP321_IINTSRC    (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
+#define IOP321_FINTSRC    (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
+
+/* Timers */
+
+#define IOP321_TU_TMR0          (volatile u32 *)IOP321_REG_ADDR(0x000007E0)
+#define IOP321_TU_TMR1          (volatile u32 *)IOP321_REG_ADDR(0x000007E4)
+
+#ifdef CONFIG_ARCH_IQ80321
+#define IOP321_TICK_RATE        200000000       /* 200 MHz clock */
+#elif defined(CONFIG_ARCH_IQ31244)
+#define IOP321_TICK_RATE        198000000       /* 33.000 MHz crystal */
+#endif
+
+#ifdef CONFIG_ARCH_EP80219
+#undef IOP321_TICK_RATE
+#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
+#endif
+
+#define IOP321_TMR_TC           0x01
+#define IOP321_TMR_EN           0x02
+#define IOP321_TMR_RELOAD       0x04
+#define IOP321_TMR_PRIVILEGED   0x09
+
+#define IOP321_TMR_RATIO_1_1    0x00
+#define IOP321_TMR_RATIO_4_1    0x10
+#define IOP321_TMR_RATIO_8_1    0x20
+#define IOP321_TMR_RATIO_16_1   0x30
+
+#define IOP321_TU_TCR0    (volatile u32 *)IOP321_REG_ADDR(0x000007E8)
+#define IOP321_TU_TCR1    (volatile u32 *)IOP321_REG_ADDR(0x000007EC)
+#define IOP321_TU_TRR0    (volatile u32 *)IOP321_REG_ADDR(0x000007F0)
+#define IOP321_TU_TRR1    (volatile u32 *)IOP321_REG_ADDR(0x000007F4)
+#define IOP321_TU_TISR    (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
+#define IOP321_TU_WDTCR   (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
+
+/* Application accelerator unit 0x00000800 - 0x000008FF */
+#define IOP321_AAU_ACR     (volatile u32 *)IOP321_REG_ADDR(0x00000800)
+#define IOP321_AAU_ASR     (volatile u32 *)IOP321_REG_ADDR(0x00000804)
+#define IOP321_AAU_ADAR    (volatile u32 *)IOP321_REG_ADDR(0x00000808)
+#define IOP321_AAU_ANDAR   (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
+#define IOP321_AAU_SAR1    (volatile u32 *)IOP321_REG_ADDR(0x00000810)
+#define IOP321_AAU_SAR2    (volatile u32 *)IOP321_REG_ADDR(0x00000814)
+#define IOP321_AAU_SAR3    (volatile u32 *)IOP321_REG_ADDR(0x00000818)
+#define IOP321_AAU_SAR4    (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
+#define IOP321_AAU_SAR5    (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
+#define IOP321_AAU_SAR6    (volatile u32 *)IOP321_REG_ADDR(0x00000830)
+#define IOP321_AAU_SAR7    (volatile u32 *)IOP321_REG_ADDR(0x00000834)
+#define IOP321_AAU_SAR8    (volatile u32 *)IOP321_REG_ADDR(0x00000838)
+#define IOP321_AAU_SAR9    (volatile u32 *)IOP321_REG_ADDR(0x00000840)
+#define IOP321_AAU_SAR10   (volatile u32 *)IOP321_REG_ADDR(0x00000844)
+#define IOP321_AAU_SAR11   (volatile u32 *)IOP321_REG_ADDR(0x00000848)
+#define IOP321_AAU_SAR12   (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
+#define IOP321_AAU_SAR13   (volatile u32 *)IOP321_REG_ADDR(0x00000850)
+#define IOP321_AAU_SAR14   (volatile u32 *)IOP321_REG_ADDR(0x00000854)
+#define IOP321_AAU_SAR15   (volatile u32 *)IOP321_REG_ADDR(0x00000858)
+#define IOP321_AAU_SAR16   (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
+#define IOP321_AAU_SAR17   (volatile u32 *)IOP321_REG_ADDR(0x00000864)
+#define IOP321_AAU_SAR18   (volatile u32 *)IOP321_REG_ADDR(0x00000868)
+#define IOP321_AAU_SAR19   (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
+#define IOP321_AAU_SAR20   (volatile u32 *)IOP321_REG_ADDR(0x00000870)
+#define IOP321_AAU_SAR21   (volatile u32 *)IOP321_REG_ADDR(0x00000874)
+#define IOP321_AAU_SAR22   (volatile u32 *)IOP321_REG_ADDR(0x00000878)
+#define IOP321_AAU_SAR23   (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
+#define IOP321_AAU_SAR24   (volatile u32 *)IOP321_REG_ADDR(0x00000880)
+#define IOP321_AAU_SAR25   (volatile u32 *)IOP321_REG_ADDR(0x00000888)
+#define IOP321_AAU_SAR26   (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
+#define IOP321_AAU_SAR27   (volatile u32 *)IOP321_REG_ADDR(0x00000890)
+#define IOP321_AAU_SAR28   (volatile u32 *)IOP321_REG_ADDR(0x00000894)
+#define IOP321_AAU_SAR29   (volatile u32 *)IOP321_REG_ADDR(0x00000898)
+#define IOP321_AAU_SAR30   (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
+#define IOP321_AAU_SAR31   (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
+#define IOP321_AAU_SAR32   (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
+#define IOP321_AAU_DAR     (volatile u32 *)IOP321_REG_ADDR(0x00000820)
+#define IOP321_AAU_ABCR    (volatile u32 *)IOP321_REG_ADDR(0x00000824)
+#define IOP321_AAU_ADCR    (volatile u32 *)IOP321_REG_ADDR(0x00000828)
+#define IOP321_AAU_EDCR0   (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
+#define IOP321_AAU_EDCR1   (volatile u32 *)IOP321_REG_ADDR(0x00000860)
+#define IOP321_AAU_EDCR2   (volatile u32 *)IOP321_REG_ADDR(0x00000884)
+
+
+/* SSP serial port unit 0x00001600 - 0x0000167F */
+/* I2C bus interface unit 0x00001680 - 0x000016FF */
+#define IOP321_ICR0       (volatile u32 *)IOP321_REG_ADDR(0x00001680)
+#define IOP321_ISR0       (volatile u32 *)IOP321_REG_ADDR(0x00001684)
+#define IOP321_ISAR0      (volatile u32 *)IOP321_REG_ADDR(0x00001688)
+#define IOP321_IDBR0      (volatile u32 *)IOP321_REG_ADDR(0x0000168C)
+/* Reserved 0x00001690 */
+#define IOP321_IBMR0      (volatile u32 *)IOP321_REG_ADDR(0x00001694)
+/* Reserved 0x00001698 */
+/* Reserved 0x0000169C */
+#define IOP321_ICR1       (volatile u32 *)IOP321_REG_ADDR(0x000016A0)
+#define IOP321_ISR1       (volatile u32 *)IOP321_REG_ADDR(0x000016A4)
+#define IOP321_ISAR1      (volatile u32 *)IOP321_REG_ADDR(0x000016A8)
+#define IOP321_IDBR1      (volatile u32 *)IOP321_REG_ADDR(0x000016AC)
+#define IOP321_IBMR1      (volatile u32 *)IOP321_REG_ADDR(0x000016B4)
+/* Reserved 0x000016B8 through 0x000016FC */
+
+/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
+
+
+#ifndef __ASSEMBLY__
+extern void iop321_map_io(void);
+extern void iop321_init_irq(void);
+extern void iop321_time_init(void);
+#endif
+
+#endif // _IOP321_HW_H_
diff --git a/include/asm-arm/arch-iop3xx/iop331-irqs.h b/include/asm-arm/arch-iop3xx/iop331-irqs.h
new file mode 100644
index 000000000000..8ff73d487222
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop331-irqs.h
@@ -0,0 +1,136 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/irqs.h
+ *
+ * Author:      Dave Jiang (dave.jiang@intel.com)
+ * Copyright:   (C) 2003 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef _IOP331_IRQS_H_
+#define _IOP331_IRQS_H_
+
+/*
+ * IOP80331 chipset interrupts
+ */
+#define IOP331_IRQ_OFS          0
+#define IOP331_IRQ(x)           (IOP331_IRQ_OFS + (x))
+
+/*
+ * On IRQ or FIQ register
+ */
+#define IRQ_IOP331_DMA0_EOT     IOP331_IRQ(0)
+#define IRQ_IOP331_DMA0_EOC     IOP331_IRQ(1)
+#define IRQ_IOP331_DMA1_EOT     IOP331_IRQ(2)
+#define IRQ_IOP331_DMA1_EOC     IOP331_IRQ(3)
+#define IRQ_IOP331_RSVD_4       IOP331_IRQ(4)
+#define IRQ_IOP331_RSVD_5       IOP331_IRQ(5)
+#define IRQ_IOP331_AA_EOT       IOP331_IRQ(6)
+#define IRQ_IOP331_AA_EOC       IOP331_IRQ(7)
+#define IRQ_IOP331_TIMER0       IOP331_IRQ(8)
+#define IRQ_IOP331_TIMER1       IOP331_IRQ(9)
+#define IRQ_IOP331_I2C_0        IOP331_IRQ(10)
+#define IRQ_IOP331_I2C_1        IOP331_IRQ(11)
+#define IRQ_IOP331_MSG      IOP331_IRQ(12)
+#define IRQ_IOP331_MSGIBQ   IOP331_IRQ(13)
+#define IRQ_IOP331_ATU_BIST     IOP331_IRQ(14)
+#define IRQ_IOP331_PERFMON      IOP331_IRQ(15)
+#define IRQ_IOP331_CORE_PMU     IOP331_IRQ(16)
+#define IRQ_IOP331_RSVD_17      IOP331_IRQ(17)
+#define IRQ_IOP331_RSVD_18      IOP331_IRQ(18)
+#define IRQ_IOP331_RSVD_19      IOP331_IRQ(19)
+#define IRQ_IOP331_RSVD_20      IOP331_IRQ(20)
+#define IRQ_IOP331_RSVD_21      IOP331_IRQ(21)
+#define IRQ_IOP331_RSVD_22      IOP331_IRQ(22)
+#define IRQ_IOP331_RSVD_23      IOP331_IRQ(23)
+#define IRQ_IOP331_XINT0        IOP331_IRQ(24)
+#define IRQ_IOP331_XINT1        IOP331_IRQ(25)
+#define IRQ_IOP331_XINT2        IOP331_IRQ(26)
+#define IRQ_IOP331_XINT3        IOP331_IRQ(27)
+#define IRQ_IOP331_RSVD_28  IOP331_IRQ(28)
+#define IRQ_IOP331_RSVD_29  IOP331_IRQ(29)
+#define IRQ_IOP331_RSVD_30  IOP331_IRQ(30)
+#define IRQ_IOP331_RSVD_31  IOP331_IRQ(31)
+#define IRQ_IOP331_XINT8    IOP331_IRQ(32)  // 0
+#define IRQ_IOP331_XINT9    IOP331_IRQ(33)  // 1
+#define IRQ_IOP331_XINT10   IOP331_IRQ(34)  // 2
+#define IRQ_IOP331_XINT11   IOP331_IRQ(35)  // 3
+#define IRQ_IOP331_XINT12   IOP331_IRQ(36)  // 4
+#define IRQ_IOP331_XINT13   IOP331_IRQ(37)  // 5
+#define IRQ_IOP331_XINT14   IOP331_IRQ(38)  // 6
+#define IRQ_IOP331_XINT15   IOP331_IRQ(39)  // 7
+#define IRQ_IOP331_RSVD_40  IOP331_IRQ(40)  // 8
+#define IRQ_IOP331_RSVD_41  IOP331_IRQ(41)  // 9
+#define IRQ_IOP331_RSVD_42  IOP331_IRQ(42)  // 10
+#define IRQ_IOP331_RSVD_43  IOP331_IRQ(43)  // 11
+#define IRQ_IOP331_RSVD_44  IOP331_IRQ(44)  // 12
+#define IRQ_IOP331_RSVD_45  IOP331_IRQ(45)  // 13
+#define IRQ_IOP331_RSVD_46  IOP331_IRQ(46)  // 14
+#define IRQ_IOP331_RSVD_47  IOP331_IRQ(47)  // 15
+#define IRQ_IOP331_RSVD_48  IOP331_IRQ(48)  // 16
+#define IRQ_IOP331_RSVD_49  IOP331_IRQ(49)  // 17
+#define IRQ_IOP331_RSVD_50  IOP331_IRQ(50)  // 18
+#define IRQ_IOP331_UART0    IOP331_IRQ(51)  // 19
+#define IRQ_IOP331_UART1    IOP331_IRQ(52)  // 20
+#define IRQ_IOP331_PBIE     IOP331_IRQ(53)  // 21
+#define IRQ_IOP331_ATU_CRW  IOP331_IRQ(54)  // 22
+#define IRQ_IOP331_ATU_ERR      IOP331_IRQ(55)  // 23
+#define IRQ_IOP331_MCU_ERR      IOP331_IRQ(56)  // 24
+#define IRQ_IOP331_DMA0_ERR     IOP331_IRQ(57)  // 25
+#define IRQ_IOP331_DMA1_ERR     IOP331_IRQ(58)  // 26
+#define IRQ_IOP331_RSVD_59  IOP331_IRQ(59)  // 27
+#define IRQ_IOP331_AA_ERR       IOP331_IRQ(60)  // 28
+#define IRQ_IOP331_RSVD_61  IOP331_IRQ(61)  // 29
+#define IRQ_IOP331_MSG_ERR      IOP331_IRQ(62)  // 30
+#define IRQ_IOP331_HPI          IOP331_IRQ(63)  // 31
+
+#define NR_IOP331_IRQS          (IOP331_IRQ(63) + 1)
+
+#define NR_IRQS                 NR_IOP331_IRQS
+
+
+#if defined(CONFIG_ARCH_IQ80331)
+/*
+ * Interrupts available on the IQ80331 board
+ */
+
+/*
+ * On board devices
+ */
+#define IRQ_IQ80331_I82544      IRQ_IOP331_XINT0
+#define IRQ_IQ80331_UART0       IRQ_IOP331_UART0
+#define IRQ_IQ80331_UART1       IRQ_IOP331_UART1
+
+/*
+ * PCI interrupts
+ */
+#define IRQ_IQ80331_INTA        IRQ_IOP331_XINT0
+#define IRQ_IQ80331_INTB        IRQ_IOP331_XINT1
+#define IRQ_IQ80331_INTC        IRQ_IOP331_XINT2
+#define IRQ_IQ80331_INTD        IRQ_IOP331_XINT3
+
+#elif defined(CONFIG_MACH_IQ80332)
+/*
+ * Interrupts available on the IQ80332 board
+ */
+
+/*
+ * On board devices
+ */
+#define IRQ_IQ80332_I82544      IRQ_IOP331_XINT0
+#define IRQ_IQ80332_UART0       IRQ_IOP331_UART0
+#define IRQ_IQ80332_UART1       IRQ_IOP331_UART1
+
+/*
+ * PCI interrupts
+ */
+#define IRQ_IQ80332_INTA        IRQ_IOP331_XINT0
+#define IRQ_IQ80332_INTB        IRQ_IOP331_XINT1
+#define IRQ_IQ80332_INTC        IRQ_IOP331_XINT2
+#define IRQ_IQ80332_INTD        IRQ_IOP331_XINT3
+
+#endif
+
+#endif // _IOP331_IRQ_H_
diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h
new file mode 100644
index 000000000000..96adffd8bad2
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop331.h
@@ -0,0 +1,363 @@
+/*
+ * linux/include/asm/arch-iop3xx/iop331.h
+ *
+ * Intel IOP331 Chip definitions
+ *
+ * Author: Dave Jiang (dave.jiang@intel.com)
+ * Copyright (C) 2003, 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IOP331_HW_H_
+#define _IOP331_HW_H_
+
+
+/*
+ * This is needed for mixed drivers that need to work on all
+ * IOP3xx variants but behave slightly differently on each.
+ */
+#ifndef __ASSEMBLY__
+#ifdef  CONFIG_ARCH_IOP331
+/*#define       iop_is_331()    ((processor_id & 0xffffffb0) == 0x69054090) */
+#define iop_is_331()    ((processor_id & 0xffffff30) == 0x69054010)
+#else
+#define iop_is_331()    0
+#endif
+#endif
+
+/*
+ * IOP331 I/O and Mem space regions for PCI autoconfiguration
+ */
+#define IOP331_PCI_IO_WINDOW_SIZE   0x00010000
+#define IOP331_PCI_LOWER_IO_PA      0x90000000
+#define IOP331_PCI_LOWER_IO_VA      0xfe000000
+#define IOP331_PCI_LOWER_IO_BA      (*IOP331_OIOWTVR)
+#define IOP331_PCI_UPPER_IO_PA      (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
+#define IOP331_PCI_UPPER_IO_VA      (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
+#define IOP331_PCI_UPPER_IO_BA      (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
+#define IOP331_PCI_IO_OFFSET        (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
+
+/* this can be 128M if OMWTVR1 is set */
+#define IOP331_PCI_MEM_WINDOW_SIZE      0x04000000 /* 64M outbound window */
+//#define IOP331_PCI_MEM_WINDOW_SIZE  (~*IOP331_IALR1 + 1)
+#define IOP331_PCI_LOWER_MEM_PA     0x80000000
+#define IOP331_PCI_LOWER_MEM_BA     (*IOP331_OMWTVR0)
+#define IOP331_PCI_UPPER_MEM_PA     (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP331_PCI_UPPER_MEM_BA     (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP331_PCI_MEM_OFFSET       (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
+
+/*
+ * IOP331 chipset registers
+ */
+#define IOP331_VIRT_MEM_BASE  0xfeffe000  /* chip virtual mem address*/
+#define IOP331_PHYS_MEM_BASE  0xffffe000  /* chip physical memory address */
+#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
+
+/* Reserved 0x00000000 through 0x000000FF */
+
+/* Address Translation Unit 0x00000100 through 0x000001FF */
+#define IOP331_ATUVID     (volatile u16 *)IOP331_REG_ADDR(0x00000100)
+#define IOP331_ATUDID     (volatile u16 *)IOP331_REG_ADDR(0x00000102)
+#define IOP331_ATUCMD     (volatile u16 *)IOP331_REG_ADDR(0x00000104)
+#define IOP331_ATUSR      (volatile u16 *)IOP331_REG_ADDR(0x00000106)
+#define IOP331_ATURID     (volatile u8  *)IOP331_REG_ADDR(0x00000108)
+#define IOP331_ATUCCR     (volatile u32 *)IOP331_REG_ADDR(0x00000109)
+#define IOP331_ATUCLSR    (volatile u8  *)IOP331_REG_ADDR(0x0000010C)
+#define IOP331_ATULT      (volatile u8  *)IOP331_REG_ADDR(0x0000010D)
+#define IOP331_ATUHTR     (volatile u8  *)IOP331_REG_ADDR(0x0000010E)
+#define IOP331_ATUBIST    (volatile u8  *)IOP331_REG_ADDR(0x0000010F)
+#define IOP331_IABAR0     (volatile u32 *)IOP331_REG_ADDR(0x00000110)
+#define IOP331_IAUBAR0    (volatile u32 *)IOP331_REG_ADDR(0x00000114)
+#define IOP331_IABAR1     (volatile u32 *)IOP331_REG_ADDR(0x00000118)
+#define IOP331_IAUBAR1    (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
+#define IOP331_IABAR2     (volatile u32 *)IOP331_REG_ADDR(0x00000120)
+#define IOP331_IAUBAR2    (volatile u32 *)IOP331_REG_ADDR(0x00000124)
+#define IOP331_ASVIR      (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
+#define IOP331_ASIR       (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
+#define IOP331_ERBAR      (volatile u32 *)IOP331_REG_ADDR(0x00000130)
+#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
+/* Reserved 0x00000138 through 0x0000013B */
+#define IOP331_ATUILR     (volatile u8  *)IOP331_REG_ADDR(0x0000013C)
+#define IOP331_ATUIPR     (volatile u8  *)IOP331_REG_ADDR(0x0000013D)
+#define IOP331_ATUMGNT    (volatile u8  *)IOP331_REG_ADDR(0x0000013E)
+#define IOP331_ATUMLAT    (volatile u8  *)IOP331_REG_ADDR(0x0000013F)
+#define IOP331_IALR0      (volatile u32 *)IOP331_REG_ADDR(0x00000140)
+#define IOP331_IATVR0     (volatile u32 *)IOP331_REG_ADDR(0x00000144)
+#define IOP331_ERLR       (volatile u32 *)IOP331_REG_ADDR(0x00000148)
+#define IOP331_ERTVR      (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
+#define IOP331_IALR1      (volatile u32 *)IOP331_REG_ADDR(0x00000150)
+#define IOP331_IALR2      (volatile u32 *)IOP331_REG_ADDR(0x00000154)
+#define IOP331_IATVR2     (volatile u32 *)IOP331_REG_ADDR(0x00000158)
+#define IOP331_OIOWTVR    (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
+#define IOP331_OMWTVR0    (volatile u32 *)IOP331_REG_ADDR(0x00000160)
+#define IOP331_OUMWTVR0   (volatile u32 *)IOP331_REG_ADDR(0x00000164)
+#define IOP331_OMWTVR1    (volatile u32 *)IOP331_REG_ADDR(0x00000168)
+#define IOP331_OUMWTVR1   (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
+/* Reserved 0x00000170 through 0x00000177*/
+#define IOP331_OUDWTVR    (volatile u32 *)IOP331_REG_ADDR(0x00000178)
+/* Reserved 0x0000017C through 0x0000017F*/
+#define IOP331_ATUCR      (volatile u32 *)IOP331_REG_ADDR(0x00000180)
+#define IOP331_PCSR       (volatile u32 *)IOP331_REG_ADDR(0x00000184)
+#define IOP331_ATUISR     (volatile u32 *)IOP331_REG_ADDR(0x00000188)
+#define IOP331_ATUIMR     (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
+#define IOP331_IABAR3     (volatile u32 *)IOP331_REG_ADDR(0x00000190)
+#define IOP331_IAUBAR3    (volatile u32 *)IOP331_REG_ADDR(0x00000194)
+#define IOP331_IALR3      (volatile u32 *)IOP331_REG_ADDR(0x00000198)
+#define IOP331_IATVR3     (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
+/* Reserved 0x000001A0 through 0x000001A3*/
+#define IOP331_OCCAR      (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
+/* Reserved 0x000001A8 through 0x000001AB*/
+#define IOP331_OCCDR      (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
+/* Reserved 0x000001B0 through 0x000001BB*/
+#define IOP331_VPDCAPID   (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
+#define IOP331_VPDNXTP    (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
+#define IOP331_VPDAR      (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
+#define IOP331_VPDDR      (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
+#define IOP331_PMCAPID    (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
+#define IOP331_PMNEXT     (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
+#define IOP331_APMCR      (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
+#define IOP331_APMCSR     (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
+/* Reserved 0x000001C6 through 0x000001CF */
+#define IOP331_MSICAPID   (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
+#define IOP331_MSINXTP    (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
+#define IOP331_MSIMCR     (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
+#define IOP331_MSIMAR     (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
+#define IOP331_MSIMUAR    (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
+#define IOP331_MSIMDR     (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
+#define IOP331_PCIXCAPID  (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
+#define IOP331_PCIXNEXT   (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
+#define IOP331_PCIXCMD    (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
+#define IOP331_PCIXSR     (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
+#define IOP331_PCIIRSR    (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
+
+/* Messaging Unit 0x00000300 through 0x000003FF */
+
+/* Reserved 0x00000300 through 0x0000030c */
+#define IOP331_IMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000310)
+#define IOP331_IMR1       (volatile u32 *)IOP331_REG_ADDR(0x00000314)
+#define IOP331_OMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000318)
+#define IOP331_OMR1       (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
+#define IOP331_IDR        (volatile u32 *)IOP331_REG_ADDR(0x00000320)
+#define IOP331_IISR       (volatile u32 *)IOP331_REG_ADDR(0x00000324)
+#define IOP331_IIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000328)
+#define IOP331_ODR        (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
+#define IOP331_OISR       (volatile u32 *)IOP331_REG_ADDR(0x00000330)
+#define IOP331_OIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000334)
+/* Reserved 0x00000338 through 0x0000034F */
+#define IOP331_MUCR       (volatile u32 *)IOP331_REG_ADDR(0x00000350)
+#define IOP331_QBAR       (volatile u32 *)IOP331_REG_ADDR(0x00000354)
+/* Reserved 0x00000358 through 0x0000035C */
+#define IOP331_IFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000360)
+#define IOP331_IFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000364)
+#define IOP331_IPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000368)
+#define IOP331_IPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
+#define IOP331_OFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000370)
+#define IOP331_OFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000374)
+#define IOP331_OPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000378)
+#define IOP331_OPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
+#define IOP331_IAR        (volatile u32 *)IOP331_REG_ADDR(0x00000380)
+/* Reserved 0x00000384 through 0x000003FF */
+
+/* DMA Controller 0x00000400 through 0x000004FF */
+#define IOP331_DMA0_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000400)
+#define IOP331_DMA0_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000404)
+#define IOP331_DMA0_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
+#define IOP331_DMA0_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000410)
+#define IOP331_DMA0_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000414)
+#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
+#define IOP331_DMA0_LADR  (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
+#define IOP331_DMA0_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000420)
+#define IOP331_DMA0_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000424)
+/* Reserved 0x00000428 through 0x0000043C */
+#define IOP331_DMA1_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000440)
+#define IOP331_DMA1_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000444)
+#define IOP331_DMA1_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
+#define IOP331_DMA1_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000450)
+#define IOP331_DMA1_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000454)
+#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
+#define IOP331_DMA1_LADR  (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
+#define IOP331_DMA1_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000460)
+#define IOP331_DMA1_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000464)
+/* Reserved 0x00000468 through 0x000004FF */
+
+/* Memory controller 0x00000500 through 0x0005FF */
+
+/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
+#define IOP331_PBCR       (volatile u32 *)IOP331_REG_ADDR(0x00000680)
+#define IOP331_PBISR      (volatile u32 *)IOP331_REG_ADDR(0x00000684)
+#define IOP331_PBBAR0     (volatile u32 *)IOP331_REG_ADDR(0x00000688)
+#define IOP331_PBLR0      (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
+#define IOP331_PBBAR1     (volatile u32 *)IOP331_REG_ADDR(0x00000690)
+#define IOP331_PBLR1      (volatile u32 *)IOP331_REG_ADDR(0x00000694)
+#define IOP331_PBBAR2     (volatile u32 *)IOP331_REG_ADDR(0x00000698)
+#define IOP331_PBLR2      (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
+#define IOP331_PBBAR3     (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
+#define IOP331_PBLR3      (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
+#define IOP331_PBBAR4     (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
+#define IOP331_PBLR4      (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
+#define IOP331_PBBAR5     (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
+#define IOP331_PBLR5      (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
+#define IOP331_PBDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
+/* Reserved 0x000006BC */
+#define IOP331_PMBR0      (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
+/* Reserved 0x000006C4 through 0x000006DC */
+#define IOP331_PMBR1      (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
+#define IOP331_PMBR2      (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
+
+#define IOP331_PBCR_EN    0x1
+
+#define IOP331_PBISR_BOOR_ERR 0x1
+
+
+
+/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
+/* Internal arbitration unit 0x00000780 through 0x0007BF */
+
+/* Interrupt Controller */
+#define IOP331_INTCTL0    (volatile u32 *)IOP331_REG_ADDR(0x00000790)
+#define IOP331_INTCTL1    (volatile u32 *)IOP331_REG_ADDR(0x00000794)
+#define IOP331_INTSTR0    (volatile u32 *)IOP331_REG_ADDR(0x00000798)
+#define IOP331_INTSTR1    (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
+#define IOP331_IINTSRC0   (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
+#define IOP331_IINTSRC1   (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
+#define IOP331_FINTSRC0   (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
+#define IOP331_FINTSRC1   (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
+#define IOP331_IPR0       (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
+#define IOP331_IPR1       (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
+#define IOP331_IPR2       (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
+#define IOP331_IPR3       (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
+#define IOP331_INTBASE    (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
+#define IOP331_INTSIZE    (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
+#define IOP331_IINTVEC    (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
+#define IOP331_FINTVEC    (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
+
+
+/* Timers */
+
+#define IOP331_TU_TMR0          (volatile u32 *)IOP331_REG_ADDR(0x000007D0)
+#define IOP331_TU_TMR1          (volatile u32 *)IOP331_REG_ADDR(0x000007D4)
+
+#define IOP331_TMR_TC           0x01
+#define IOP331_TMR_EN           0x02
+#define IOP331_TMR_RELOAD       0x04
+#define IOP331_TMR_PRIVILEGED   0x09
+
+#define IOP331_TMR_RATIO_1_1    0x00
+#define IOP331_TMR_RATIO_4_1    0x10
+#define IOP331_TMR_RATIO_8_1    0x20
+#define IOP331_TMR_RATIO_16_1   0x30
+
+#define IOP331_TU_TCR0    (volatile u32 *)IOP331_REG_ADDR(0x000007D8)
+#define IOP331_TU_TCR1    (volatile u32 *)IOP331_REG_ADDR(0x000007DC)
+#define IOP331_TU_TRR0    (volatile u32 *)IOP331_REG_ADDR(0x000007E0)
+#define IOP331_TU_TRR1    (volatile u32 *)IOP331_REG_ADDR(0x000007E4)
+#define IOP331_TU_TISR    (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
+#define IOP331_TU_WDTCR   (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
+
+#if defined(CONFIG_ARCH_IOP331)
+#define IOP331_TICK_RATE        266000000       /* 266 MHz IB clock */
+#endif
+
+#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
+#undef IOP331_TICK_RATE
+#define IOP331_TICK_RATE        333000000       /* 333 Mhz IB clock */
+#endif
+
+/* Application accelerator unit 0x00000800 - 0x000008FF */
+#define IOP331_AAU_ACR     (volatile u32 *)IOP331_REG_ADDR(0x00000800)
+#define IOP331_AAU_ASR     (volatile u32 *)IOP331_REG_ADDR(0x00000804)
+#define IOP331_AAU_ADAR    (volatile u32 *)IOP331_REG_ADDR(0x00000808)
+#define IOP331_AAU_ANDAR   (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
+#define IOP331_AAU_SAR1    (volatile u32 *)IOP331_REG_ADDR(0x00000810)
+#define IOP331_AAU_SAR2    (volatile u32 *)IOP331_REG_ADDR(0x00000814)
+#define IOP331_AAU_SAR3    (volatile u32 *)IOP331_REG_ADDR(0x00000818)
+#define IOP331_AAU_SAR4    (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
+#define IOP331_AAU_SAR5    (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
+#define IOP331_AAU_SAR6    (volatile u32 *)IOP331_REG_ADDR(0x00000830)
+#define IOP331_AAU_SAR7    (volatile u32 *)IOP331_REG_ADDR(0x00000834)
+#define IOP331_AAU_SAR8    (volatile u32 *)IOP331_REG_ADDR(0x00000838)
+#define IOP331_AAU_SAR9    (volatile u32 *)IOP331_REG_ADDR(0x00000840)
+#define IOP331_AAU_SAR10   (volatile u32 *)IOP331_REG_ADDR(0x00000844)
+#define IOP331_AAU_SAR11   (volatile u32 *)IOP331_REG_ADDR(0x00000848)
+#define IOP331_AAU_SAR12   (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
+#define IOP331_AAU_SAR13   (volatile u32 *)IOP331_REG_ADDR(0x00000850)
+#define IOP331_AAU_SAR14   (volatile u32 *)IOP331_REG_ADDR(0x00000854)
+#define IOP331_AAU_SAR15   (volatile u32 *)IOP331_REG_ADDR(0x00000858)
+#define IOP331_AAU_SAR16   (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
+#define IOP331_AAU_SAR17   (volatile u32 *)IOP331_REG_ADDR(0x00000864)
+#define IOP331_AAU_SAR18   (volatile u32 *)IOP331_REG_ADDR(0x00000868)
+#define IOP331_AAU_SAR19   (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
+#define IOP331_AAU_SAR20   (volatile u32 *)IOP331_REG_ADDR(0x00000870)
+#define IOP331_AAU_SAR21   (volatile u32 *)IOP331_REG_ADDR(0x00000874)
+#define IOP331_AAU_SAR22   (volatile u32 *)IOP331_REG_ADDR(0x00000878)
+#define IOP331_AAU_SAR23   (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
+#define IOP331_AAU_SAR24   (volatile u32 *)IOP331_REG_ADDR(0x00000880)
+#define IOP331_AAU_SAR25   (volatile u32 *)IOP331_REG_ADDR(0x00000888)
+#define IOP331_AAU_SAR26   (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
+#define IOP331_AAU_SAR27   (volatile u32 *)IOP331_REG_ADDR(0x00000890)
+#define IOP331_AAU_SAR28   (volatile u32 *)IOP331_REG_ADDR(0x00000894)
+#define IOP331_AAU_SAR29   (volatile u32 *)IOP331_REG_ADDR(0x00000898)
+#define IOP331_AAU_SAR30   (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
+#define IOP331_AAU_SAR31   (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
+#define IOP331_AAU_SAR32   (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
+#define IOP331_AAU_DAR     (volatile u32 *)IOP331_REG_ADDR(0x00000820)
+#define IOP331_AAU_ABCR    (volatile u32 *)IOP331_REG_ADDR(0x00000824)
+#define IOP331_AAU_ADCR    (volatile u32 *)IOP331_REG_ADDR(0x00000828)
+#define IOP331_AAU_EDCR0   (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
+#define IOP331_AAU_EDCR1   (volatile u32 *)IOP331_REG_ADDR(0x00000860)
+#define IOP331_AAU_EDCR2   (volatile u32 *)IOP331_REG_ADDR(0x00000884)
+
+
+#define IOP331_SPDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
+#define IOP331_PPDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
+/* SSP serial port unit 0x00001600 - 0x0000167F */
+
+/* I2C bus interface unit 0x00001680 - 0x000016FF */
+/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
+
+#define IOP331_ICR0       (volatile u32 *)IOP331_REG_ADDR(0x00001680)
+#define IOP331_ISR0       (volatile u32 *)IOP331_REG_ADDR(0x00001684)
+#define IOP331_ISAR0      (volatile u32 *)IOP331_REG_ADDR(0x00001688)
+#define IOP331_IDBR0      (volatile u32 *)IOP331_REG_ADDR(0x0000168C)
+/* Reserved 0x00001690 */
+#define IOP331_IBMR0      (volatile u32 *)IOP331_REG_ADDR(0x00001694)
+/* Reserved 0x00001698 */
+/* Reserved 0x0000169C */
+#define IOP331_ICR1       (volatile u32 *)IOP331_REG_ADDR(0x000016A0)
+#define IOP331_ISR1       (volatile u32 *)IOP331_REG_ADDR(0x000016A4)
+#define IOP331_ISAR1      (volatile u32 *)IOP331_REG_ADDR(0x000016A8)
+#define IOP331_IDBR1      (volatile u32 *)IOP331_REG_ADDR(0x000016AC)
+#define IOP331_IBMR1      (volatile u32 *)IOP331_REG_ADDR(0x000016B4)
+/* Reserved 0x000016B8 through 0x000016FF */
+
+/* 0x00001700 through 0x0000172C  UART 0 */
+
+/* Reserved 0x00001730 through 0x0000173F */
+
+/* 0x00001740 through 0x0000176C UART 1 */
+
+#define IOP331_UART0_PHYS  (IOP331_PHYS_MEM_BASE | 0x00001700)  /* UART #1 physical */
+#define IOP331_UART1_PHYS  (IOP331_PHYS_MEM_BASE | 0x00001740)  /* UART #2 physical */
+#define IOP331_UART0_VIRT  (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
+#define IOP331_UART1_VIRT  (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
+
+/* Reserved 0x00001770 through 0x0000177F */
+
+/* General Purpose I/O Registers */
+#define IOP331_GPOE       (volatile u32 *)IOP331_REG_ADDR(0x00001780)
+#define IOP331_GPID       (volatile u32 *)IOP331_REG_ADDR(0x00001784)
+#define IOP331_GPOD       (volatile u32 *)IOP331_REG_ADDR(0x00001788)
+
+/* Reserved 0x0000178c through 0x000019ff */
+
+
+#ifndef __ASSEMBLY__
+extern void iop331_map_io(void);
+extern void iop331_init_irq(void);
+extern void iop331_time_init(void);
+#endif
+
+#endif // _IOP331_HW_H_
diff --git a/include/asm-arm/arch-iop3xx/iq31244.h b/include/asm-arm/arch-iop3xx/iq31244.h
new file mode 100644
index 000000000000..4177cfa8100f
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iq31244.h
@@ -0,0 +1,24 @@
+/*
+ * linux/include/asm/arch-iop3xx/iq31244.h
+ *
+ * Intel IQ31244 evaluation board registers
+ */
+
+#ifndef _IQ31244_H_
+#define _IQ31244_H_
+
+#define IQ31244_FLASHBASE       0xf0000000      /* Flash */
+#define IQ31244_FLASHSIZE       0x00800000
+#define IQ31244_FLASHWIDTH      2
+
+#define IQ31244_UART            0xfe800000      /* UART #1 */
+#define IQ31244_7SEG_1          0xfe840000      /* 7-Segment MSB */
+#define IQ31244_7SEG_0          0xfe850000      /* 7-Segment LSB (WO) */
+#define IQ31244_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
+#define IQ31244_BATT_STAT       0xfe8f0000      /* Battery Status */
+
+#ifndef __ASSEMBLY__
+extern void iq31244_map_io(void);
+#endif
+
+#endif  // _IQ31244_H_
diff --git a/include/asm-arm/arch-iop3xx/iq80321.h b/include/asm-arm/arch-iop3xx/iq80321.h
new file mode 100644
index 000000000000..cb8725979ffa
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iq80321.h
@@ -0,0 +1,24 @@
+/*
+ * linux/include/asm/arch-iop3xx/iq80321.h
+ *
+ * Intel IQ80321 evaluation board registers
+ */
+
+#ifndef _IQ80321_H_
+#define _IQ80321_H_
+
+#define IQ80321_FLASHBASE       0xf0000000      /* Flash */
+#define IQ80321_FLASHSIZE       0x00800000
+#define IQ80321_FLASHWIDTH      1
+
+#define IQ80321_UART            0xfe800000      /* UART #1 */
+#define IQ80321_7SEG_1          0xfe840000      /* 7-Segment MSB */
+#define IQ80321_7SEG_0          0xfe850000      /* 7-Segment LSB (WO) */
+#define IQ80321_ROTARY_SW       0xfe8d0000      /* Rotary Switch */
+#define IQ80321_BATT_STAT       0xfe8f0000      /* Battery Status */
+
+#ifndef __ASSEMBLY__
+extern void iq80321_map_io(void);
+#endif
+
+#endif  // _IQ80321_H_
diff --git a/include/asm-arm/arch-iop3xx/iq80331.h b/include/asm-arm/arch-iop3xx/iq80331.h
new file mode 100644
index 000000000000..0668e78d483e
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iq80331.h
@@ -0,0 +1,23 @@
+/*
+ * linux/include/asm/arch-iop3xx/iq80331.h
+ *
+ * Intel IQ80331 evaluation board registers
+ */
+
+#ifndef _IQ80331_H_
+#define _IQ80331_H_
+
+#define IQ80331_FLASHBASE       0xc0000000      /* Flash */
+#define IQ80331_FLASHSIZE       0x00800000
+#define IQ80331_FLASHWIDTH      1
+
+#define IQ80331_7SEG_1          0xce840000      /* 7-Segment MSB */
+#define IQ80331_7SEG_0          0xce850000      /* 7-Segment LSB (WO) */
+#define IQ80331_ROTARY_SW       0xce8d0000      /* Rotary Switch */
+#define IQ80331_BATT_STAT       0xce8f0000      /* Battery Status */
+
+#ifndef __ASSEMBLY__
+extern void iq80331_map_io(void);
+#endif
+
+#endif  // _IQ80331_H_
diff --git a/include/asm-arm/arch-iop3xx/iq80332.h b/include/asm-arm/arch-iop3xx/iq80332.h
new file mode 100644
index 000000000000..e5fff1775d1a
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iq80332.h
@@ -0,0 +1,23 @@
+/*
+ * linux/include/asm/arch-iop3xx/iq80332.h
+ *
+ * Intel IQ80332 evaluation board registers
+ */
+
+#ifndef _IQ80332_H_
+#define _IQ80332_H_
+
+#define IQ80332_FLASHBASE       0xc0000000      /* Flash */
+#define IQ80332_FLASHSIZE       0x00800000
+#define IQ80332_FLASHWIDTH      1
+
+#define IQ80332_7SEG_1          0xce840000      /* 7-Segment MSB */
+#define IQ80332_7SEG_0          0xce850000      /* 7-Segment LSB (WO) */
+#define IQ80332_ROTARY_SW       0xce8d0000      /* Rotary Switch */
+#define IQ80332_BATT_STAT       0xce8f0000      /* Battery Status */
+
+#ifndef __ASSEMBLY__
+extern void iq80332_map_io(void);
+#endif
+
+#endif  // _IQ80332_H_
diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h
new file mode 100644
index 000000000000..b2c03f4c269c
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/irqs.h
@@ -0,0 +1,21 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/irqs.h
+ *
+ * Copyright:   (C) 2001-2003 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*
+ * Chipset-specific bits
+ */
+#ifdef CONFIG_ARCH_IOP321
+#include "iop321-irqs.h"
+#endif
+
+#ifdef CONFIG_ARCH_IOP331
+#include "iop331-irqs.h"
+#endif
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
new file mode 100644
index 000000000000..dc4735cb0c10
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/memory.h
@@ -0,0 +1,41 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <linux/config.h>
+#include <asm/hardware.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#ifndef CONFIG_ARCH_IOP331
+#define PHYS_OFFSET     (0xa0000000UL)
+#else
+#define PHYS_OFFSET     (0x00000000UL)
+#endif
+
+/*
+ * Virtual view <-> PCI DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#if defined(CONFIG_ARCH_IOP321)
+
+#define __virt_to_bus(x)        (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
+#define __bus_to_virt(x)    (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
+
+#elif defined(CONFIG_ARCH_IOP331)
+
+#define __virt_to_bus(x)        (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0))
+#define __bus_to_virt(x)    (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2)))
+
+#endif
+
+#define PFN_TO_NID(addr)        (0)
+
+#endif
diff --git a/include/asm-arm/arch-iop3xx/param.h b/include/asm-arm/arch-iop3xx/param.h
new file mode 100644
index 000000000000..acf404e87358
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/param.h
@@ -0,0 +1,3 @@
+/*
+ *  linux/include/asm-arm/arch-iop3xx/param.h
+ */
diff --git a/include/asm-arm/arch-iop3xx/system.h b/include/asm-arm/arch-iop3xx/system.h
new file mode 100644
index 000000000000..af6ae8cd36c9
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/system.h
@@ -0,0 +1,35 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/system.h
+ *
+ *  Copyright (C) 2001 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+
+static inline void arch_reset(char mode)
+{
+#ifdef CONFIG_ARCH_IOP321
+    *IOP321_PCSR = 0x30;
+#endif
+
+#ifdef CONFIG_ARCH_IOP331
+    *IOP331_PCSR = 0x30;
+#endif
+
+        if ( 1 && mode == 's') {
+                /* Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                /* No on-chip reset capability */
+                cpu_reset(0);
+        }
+}
+
diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h
new file mode 100644
index 000000000000..d4187fe9a85a
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/timex.h
@@ -0,0 +1,21 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/timex.h
+ *
+ * IOP3xx architecture timex specifications
+ */
+#include <linux/config.h>
+
+
+#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
+
+#define CLOCK_TICK_RATE IOP321_TICK_RATE
+
+#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332)
+
+#define CLOCK_TICK_RATE IOP331_TICK_RATE
+
+#else
+
+#error "No IOP3xx timex information for this architecture"
+
+#endif
diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h
new file mode 100644
index 000000000000..82b88762c3cc
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/uncompress.h
@@ -0,0 +1,57 @@
+/*
+ *  linux/include/asm-arm/arch-iop3xx/uncompress.h
+ */
+#include <linux/config.h>
+#include <asm/types.h>
+#include <asm/mach-types.h>
+#include <linux/serial_reg.h>
+#include <asm/hardware.h>
+
+#ifdef CONFIG_ARCH_IOP321
+#define UTYPE unsigned char *
+#elif defined(CONFIG_ARCH_IOP331)
+#define UTYPE u32 *
+#else
+#error "Missing IOP3xx arch type def"
+#endif
+
+static volatile UTYPE uart_base;
+
+#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
+
+static __inline__ void putc(char c)
+{
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE);
+        *uart_base = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                putc(*s);
+                if (*s == '\n')
+                        putc('\r');
+                s++;
+        }
+}
+
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        if(machine_is_iq80321())
+                        uart_base = (volatile UTYPE)IQ80321_UART;
+                else if(machine_is_iq31244())
+                        uart_base = (volatile UTYPE)IQ31244_UART;
+                else if(machine_is_iq80331() || machine_is_iq80332())
+                        uart_base = (volatile UTYPE)IOP331_UART0_PHYS;
+                else
+                        uart_base = (volatile UTYPE)0xfe800000;
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop3xx/vmalloc.h b/include/asm-arm/arch-iop3xx/vmalloc.h
new file mode 100644
index 000000000000..dc1d2a957164
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/vmalloc.h
@@ -0,0 +1,19 @@
+/*
+ * linux/include/asm-arm/arch-iop3xx/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+//#define VMALLOC_END       (0xe8000000)
+/* increase usable physical RAM to ~992M per RMK */
+#define VMALLOC_END       (0xfe000000)
+
diff --git a/include/asm-arm/arch-ixp2000/debug-macro.S b/include/asm-arm/arch-ixp2000/debug-macro.S
new file mode 100644
index 000000000000..5631e0889861
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/debug-macro.S
@@ -0,0 +1,40 @@
+/* linux/include/asm-arm/arch-ixp2000/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0xc0000000        @ Physical base
+                movne   \rx, #0xfe000000        @ virtual base
+                orrne   \rx, \rx, #0x00f00000
+                orr     \rx, \rx, #0x00030000
+#ifdef  __ARMEB__
+                orr     \rx, \rx, #0x00000003
+#endif
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldrb    \rd, [\rx, #0x14]
+                tst     \rd, #0x20
+                beq     1002b
+                .endm
+
+                .macro  waituart,rd,rx
+                nop
+                nop
+                nop
+                .endm
diff --git a/include/asm-arm/arch-ixp2000/dma.h b/include/asm-arm/arch-ixp2000/dma.h
new file mode 100644
index 000000000000..0fb3568a98dd
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/dma.h
@@ -0,0 +1,18 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/dma.h
+ *
+ * Copyright (C) 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+
+/* No DMA */
+#define MAX_DMA_CHANNELS        0
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ixp2000/enp2611.h b/include/asm-arm/arch-ixp2000/enp2611.h
new file mode 100644
index 000000000000..31ae88674968
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/enp2611.h
@@ -0,0 +1,28 @@
+/*
+ * include/asm-arm/arch-ixp2000/enp2611.h
+ *
+ * Register and other defines for Radisys ENP-2611
+ *
+ * Created 2004 by Lennert Buytenhek from the ixdp2x01 code.  The
+ * original version carries the following notices:
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ENP2611_H
+#define __ENP2611_H
+
+#define ENP2611_GPIO_SCL        0x07
+#define ENP2611_GPIO_SDA        0x06
+
+
+#endif
diff --git a/include/asm-arm/arch-ixp2000/entry-macro.S b/include/asm-arm/arch-ixp2000/entry-macro.S
new file mode 100644
index 000000000000..e3a4e4121298
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/entry-macro.S
@@ -0,0 +1,53 @@
+/*
+ * include/asm-arm/arch-ixp2000/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IXP2000-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                mov     \irqnr, #0x0              @clear out irqnr as default
+                mov     \base, #0xfe000000
+                orr     \base, \base, #0x00e00000
+                orr     \base, \base, #0x08
+                ldr     \irqstat, [\base]         @ get interrupts
+
+                cmp     \irqstat, #0
+                beq     1001f
+
+                clz     \irqnr, \irqstat
+                mov     \base, #31
+                subs    \irqnr, \base, \irqnr
+
+                /*
+                 * We handle PCIA and PCIB here so we don't have an
+                 * extra layer of code just to check these two bits.
+                 */
+                cmp     \irqnr, #IRQ_IXP2000_PCI
+                bne     1001f
+
+                mov     \base, #0xfe000000
+                orr     \base, \base, #0x00c00000
+                orr     \base, \base, #0x00000100
+                orr     \base, \base, #0x00000058
+                ldr     \irqstat, [\base]
+
+                mov     \tmp, #(1<<26)
+                tst     \irqstat, \tmp
+                movne   \irqnr, #IRQ_IXP2000_PCIA
+                bne     1001f
+
+                mov     \tmp, #(1<<27)
+                tst     \irqstat, \tmp
+                movne   \irqnr, #IRQ_IXP2000_PCIB
+
+1001:
+                .endm
+
diff --git a/include/asm-arm/arch-ixp2000/gpio.h b/include/asm-arm/arch-ixp2000/gpio.h
new file mode 100644
index 000000000000..84634af5cc64
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/gpio.h
@@ -0,0 +1,55 @@
+/*
+ * include/asm-arm/arch-ixp2000/ixp2000-gpio.h
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software, you can redistribute it and/or modify 
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * IXP2000 GPIO in/out, edge/level detection for IRQs:
+ * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High
+ * or both Falling-edge and Rising-edge.  
+ * This must be called *before* the corresponding IRQ is registerd.
+ * Use this instead of directly setting the GPIO registers.
+ * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb)
+ */
+#ifndef _ASM_ARCH_IXP2000_GPIO_H_
+#define _ASM_ARCH_IXP2000_GPIO_H_
+
+#ifndef __ASSEMBLY__
+#define GPIO_OUT                        0x0
+#define GPIO_IN                         0x80
+
+#define IXP2000_GPIO_LOW                0
+#define IXP2000_GPIO_HIGH               1
+
+#define GPIO_NO_EDGES                   0
+#define GPIO_FALLING_EDGE               1
+#define GPIO_RISING_EDGE                2
+#define GPIO_BOTH_EDGES                 3
+#define GPIO_LEVEL_LOW                  4
+#define GPIO_LEVEL_HIGH                 8
+
+extern void set_GPIO_IRQ_edge(int gpio_nr, int edge);
+extern void set_GPIO_IRQ_level(int gpio_nr, int level);
+extern void gpio_line_config(int line, int style);
+
+static inline int gpio_line_get(int line)
+{
+        return (((*IXP2000_GPIO_PLR) >> line) & 1);
+}
+
+static inline void gpio_line_set(int line, int value)
+{
+        if (value == IXP2000_GPIO_HIGH) {
+                ixp_reg_write(IXP2000_GPIO_POSR, BIT(line));
+        } else if (value == IXP2000_GPIO_LOW)
+                ixp_reg_write(IXP2000_GPIO_POCR, BIT(line));
+}
+
+#endif /* !__ASSEMBLY__ */
+#endif /* ASM_ARCH_IXP2000_GPIO_H_ */
+
diff --git a/include/asm-arm/arch-ixp2000/hardware.h b/include/asm-arm/arch-ixp2000/hardware.h
new file mode 100644
index 000000000000..e7ea781c48aa
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/hardware.h
@@ -0,0 +1,44 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/hardware.h
+ *
+ * Hardware definitions for IXP2400/2800 based systems
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ *
+ * Maintainer: Deepak Saxena <dsaxena@mvista.com>
+ *
+ * Copyright (C) 2001-2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H__
+
+/*
+ * This needs to be platform-specific?
+ */
+#define PCIBIOS_MIN_IO          0x00000000
+#define PCIBIOS_MIN_MEM         0x00000000
+
+#include "ixp2000-regs.h"       /* Chipset Registers */
+
+#define pcibios_assign_all_busses() 0
+
+/*
+ * Platform helper functions
+ */
+#include "platform.h"
+
+/*
+ * Platform-specific bits
+ */
+#include "enp2611.h"            /* ENP-2611 */
+#include "ixdp2x00.h"           /* IXDP2400/2800 */
+#include "ixdp2x01.h"           /* IXDP2401/2801 */
+
+#endif  /* _ASM_ARCH_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-ixp2000/io.h b/include/asm-arm/arch-ixp2000/io.h
new file mode 100644
index 000000000000..a8e3c2daefd6
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/io.h
@@ -0,0 +1,150 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/io.h
+ *
+ * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002  Intel Corp.
+ * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT          0xffffffff
+#define __mem_pci(a)            (a)
+#define ___io(p)                ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
+
+/*
+ * The IXP2400 before revision B0 asserts byte lanes for PCI I/O
+ * transactions the other way round (MEM transactions don't have this
+ * issue), so we need to override the standard functions.  B0 and later
+ * have a bit that can be set to 1 to get the 'proper' behavior, but
+ * since that isn't available on the A? revisions we just keep doing
+ * things manually.
+ */
+#define alignb(addr)            (void __iomem *)((unsigned long)addr ^ 3)
+#define alignw(addr)            (void __iomem *)((unsigned long)addr ^ 2)
+
+#define outb(v,p)               __raw_writeb((v),alignb(___io(p)))
+#define outw(v,p)               __raw_writew((v),alignw(___io(p)))
+#define outl(v,p)               __raw_writel((v),___io(p))
+
+#define inb(p)          ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
+#define inw(p)          \
+        ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
+#define inl(p)          \
+        ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
+
+#define outsb(p,d,l)            __raw_writesb(alignb(___io(p)),d,l)
+#define outsw(p,d,l)            __raw_writesw(alignw(___io(p)),d,l)
+#define outsl(p,d,l)            __raw_writesl(___io(p),d,l)
+
+#define insb(p,d,l)             __raw_readsb(alignb(___io(p)),d,l)
+#define insw(p,d,l)             __raw_readsw(alignw(___io(p)),d,l)
+#define insl(p,d,l)             __raw_readsl(___io(p),d,l)
+
+
+#ifdef CONFIG_ARCH_IXDP2X01
+/*
+ * This is an ugly hack but the CS8900 on the 2x01's does not sit in any sort
+ * of "I/O space" and is just direct mapped into a 32-bit-only addressable
+ * bus. The address space for this bus is such that we can't really easily
+ * make it contiguous to the PCI I/O address range, and it also does not
+ * need swapping like PCI addresses do (IXDP2x01 is a BE platform).
+ * B/C of this we can't use the standard in/out functions and need to
+ * runtime check if the incoming address is a PCI address or for
+ * the CS89x0.
+ */
+#undef inw
+#undef outw
+#undef insw
+#undef outsw
+
+#include <asm/mach-types.h>
+
+static inline void insw(u32 ptr, void *buf, int length)
+{
+        register volatile u32 *port = (volatile u32 *)ptr;
+
+        /*
+         * Is this cycle meant for the CS8900?
+         */
+        if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
+                ((port >= IXDP2X01_CS8900_VIRT_BASE) && 
+                 (port <= IXDP2X01_CS8900_VIRT_END))) {
+                u8 *buf8 = (u8*)buf;
+                register u32 tmp32;
+
+                do {
+                        tmp32 = *port;
+                        *buf8++ = (u8)tmp32;
+                        *buf8++ = (u8)(tmp32 >> 8);
+                } while(--length);
+
+                return;
+        }
+
+        __raw_readsw(alignw(___io(ptr)),buf,length);
+}
+
+static inline void outsw(u32 ptr, void *buf, int length)
+{
+        register volatile u32 *port = (volatile u32 *)ptr;
+
+        /*
+         * Is this cycle meant for the CS8900?
+         */
+        if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
+                ((port >= IXDP2X01_CS8900_VIRT_BASE) && 
+                 (port <= IXDP2X01_CS8900_VIRT_END))) {
+                register u32 tmp32;
+                u8 *buf8 = (u8*)buf;
+                do {
+                        tmp32 = *buf8++;
+                        tmp32 |= (*buf8++) << 8;
+                        *port = tmp32;
+                } while(--length);
+                return;
+        }
+
+        __raw_writesw(alignw(___io(ptr)),buf,length);
+}
+
+
+static inline u16 inw(u32 ptr)
+{
+        register volatile u32 *port = (volatile u32 *)ptr;
+
+        /*
+         * Is this cycle meant for the CS8900?
+         */
+        if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
+                ((port >= IXDP2X01_CS8900_VIRT_BASE) && 
+                 (port <= IXDP2X01_CS8900_VIRT_END))) {
+                return (u16)(*port);  
+        }
+
+        return __raw_readw(alignw(___io(ptr)));
+}
+
+static inline void outw(u16 value, u32 ptr)
+{
+        register volatile u32 *port = (volatile u32 *)ptr;
+
+        if ((machine_is_ixdp2401() || machine_is_ixdp2801()) && 
+                ((port >= IXDP2X01_CS8900_VIRT_BASE) && 
+                 (port <= IXDP2X01_CS8900_VIRT_END))) {
+                *port = value;  
+                return;
+        }
+
+        __raw_writew((value),alignw(___io(ptr)));
+}
+#endif  /* IXDP2x01 */
+
+#endif
diff --git a/include/asm-arm/arch-ixp2000/irq.h b/include/asm-arm/arch-ixp2000/irq.h
new file mode 100644
index 000000000000..ba00b23f9828
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/irq.h
@@ -0,0 +1,13 @@
+/*
+ *  linux/include/asm-arm/arch-ixp2000/irq.h
+ *
+ *  Copyright (C) 2002 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define fixup_irq(irq)  (irq)
+
+
diff --git a/include/asm-arm/arch-ixp2000/irqs.h b/include/asm-arm/arch-ixp2000/irqs.h
new file mode 100644
index 000000000000..0deb96c12adb
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/irqs.h
@@ -0,0 +1,174 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/irqs.h
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ * 
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _IRQS_H
+#define _IRQS_H
+
+/*
+ * Do NOT add #ifdef MACHINE_FOO in here.
+ * Simpy add your machine IRQs here and increase NR_IRQS if needed to
+ * hold your machine's IRQ table.
+ */
+
+/*
+ * Some interrupt numbers go unused b/c the IRQ mask/ummask/status
+ * register has those bit reserved. We just mark those interrupts
+ * as invalid and this allows us to do mask/unmask with a single
+ * shift operation instead of having to map the IRQ number to
+ * a HW IRQ number.
+ */
+#define IRQ_IXP2000_SOFT_INT            0 /* soft interrupt */
+#define IRQ_IXP2000_ERRSUM              1 /* OR of all bits in ErrorStatus reg*/
+#define IRQ_IXP2000_UART                2
+#define IRQ_IXP2000_GPIO                3
+#define IRQ_IXP2000_TIMER1              4
+#define IRQ_IXP2000_TIMER2              5
+#define IRQ_IXP2000_TIMER3              6
+#define IRQ_IXP2000_TIMER4              7
+#define IRQ_IXP2000_PMU                 8               
+#define IRQ_IXP2000_SPF                 9  /* Slow port framer IRQ */
+#define IRQ_IXP2000_DMA1                10
+#define IRQ_IXP2000_DMA2                11
+#define IRQ_IXP2000_DMA3                12
+#define IRQ_IXP2000_PCI_DOORBELL        13
+#define IRQ_IXP2000_ME_ATTN             14 
+#define IRQ_IXP2000_PCI                 15 /* PCI INTA or INTB */
+#define IRQ_IXP2000_THDA0               16 /* thread 0-31A */
+#define IRQ_IXP2000_THDA1               17 /* thread 32-63A, IXP2800 only */
+#define IRQ_IXP2000_THDA2               18 /* thread 64-95A */
+#define IRQ_IXP2000_THDA3               19 /* thread 96-127A, IXP2800 only */
+#define IRQ_IXP2000_THDB0               24 /* thread 0-31B */
+#define IRQ_IXP2000_THDB1               25 /* thread 32-63B, IXP2800 only */
+#define IRQ_IXP2000_THDB2               26 /* thread 64-95B */
+#define IRQ_IXP2000_THDB3               27 /* thread 96-127B, IXP2800 only */
+
+/* define generic GPIOs */
+#define IRQ_IXP2000_GPIO0               32
+#define IRQ_IXP2000_GPIO1               33
+#define IRQ_IXP2000_GPIO2               34
+#define IRQ_IXP2000_GPIO3               35
+#define IRQ_IXP2000_GPIO4               36
+#define IRQ_IXP2000_GPIO5               37
+#define IRQ_IXP2000_GPIO6               38
+#define IRQ_IXP2000_GPIO7               39
+
+/* split off the 2 PCI sources */
+#define IRQ_IXP2000_PCIA                40
+#define IRQ_IXP2000_PCIB                41
+
+#define NR_IXP2000_IRQS                 42
+
+#define IXP2000_BOARD_IRQ(x)            (NR_IXP2000_IRQS + (x))
+
+#define IXP2000_BOARD_IRQ_MASK(irq)     (1 << (irq - NR_IXP2000_IRQS))  
+
+/*
+ * This allows for all the on-chip sources plus up to 32 CPLD based
+ * IRQs. Should be more than enough.
+ */
+#define IXP2000_BOARD_IRQS              32
+#define NR_IRQS                         (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS)
+
+
+/* 
+ * IXDP2400 specific IRQs
+ */
+#define IRQ_IXDP2400_INGRESS_NPU        IXP2000_BOARD_IRQ(0) 
+#define IRQ_IXDP2400_ENET               IXP2000_BOARD_IRQ(1) 
+#define IRQ_IXDP2400_MEDIA_PCI          IXP2000_BOARD_IRQ(2) 
+#define IRQ_IXDP2400_MEDIA_SP           IXP2000_BOARD_IRQ(3) 
+#define IRQ_IXDP2400_SF_PCI             IXP2000_BOARD_IRQ(4) 
+#define IRQ_IXDP2400_SF_SP              IXP2000_BOARD_IRQ(5) 
+#define IRQ_IXDP2400_PMC                IXP2000_BOARD_IRQ(6) 
+#define IRQ_IXDP2400_TVM                IXP2000_BOARD_IRQ(7) 
+
+#define NR_IXDP2400_IRQS                ((IRQ_IXDP2400_TVM)+1)  
+#define IXDP2400_NR_IRQS                NR_IXDP2400_IRQS - NR_IXP2000_IRQS
+
+/* IXDP2800 specific IRQs */
+#define IRQ_IXDP2800_EGRESS_ENET        IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2800_INGRESS_NPU        IXP2000_BOARD_IRQ(1)
+#define IRQ_IXDP2800_PMC                IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2800_FABRIC_PCI         IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2800_FABRIC             IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2800_MEDIA              IXP2000_BOARD_IRQ(5)
+
+#define NR_IXDP2800_IRQS                ((IRQ_IXDP2800_MEDIA)+1)
+#define IXDP2800_NR_IRQS                NR_IXDP2800_IRQS - NR_IXP2000_IRQS
+
+/* 
+ * IRQs on both IXDP2x01 boards
+ */
+#define IRQ_IXDP2X01_SPCI_DB_0          IXP2000_BOARD_IRQ(2)
+#define IRQ_IXDP2X01_SPCI_DB_1          IXP2000_BOARD_IRQ(3)
+#define IRQ_IXDP2X01_SPCI_PMC_INTA      IXP2000_BOARD_IRQ(4)
+#define IRQ_IXDP2X01_SPCI_PMC_INTB      IXP2000_BOARD_IRQ(5)
+#define IRQ_IXDP2X01_SPCI_PMC_INTC      IXP2000_BOARD_IRQ(6)
+#define IRQ_IXDP2X01_SPCI_PMC_INTD      IXP2000_BOARD_IRQ(7)
+#define IRQ_IXDP2X01_SPCI_FIC_INT       IXP2000_BOARD_IRQ(8)
+#define IRQ_IXDP2X01_IPMI_FROM          IXP2000_BOARD_IRQ(16)
+#define IRQ_IXDP2X01_125US              IXP2000_BOARD_IRQ(17)
+#define IRQ_IXDP2X01_DB_0_ADD           IXP2000_BOARD_IRQ(18)
+#define IRQ_IXDP2X01_DB_1_ADD           IXP2000_BOARD_IRQ(19)
+#define IRQ_IXDP2X01_UART1              IXP2000_BOARD_IRQ(21)
+#define IRQ_IXDP2X01_UART2              IXP2000_BOARD_IRQ(22)
+#define IRQ_IXDP2X01_FIC_ADD_INT        IXP2000_BOARD_IRQ(24)
+#define IRQ_IXDP2X01_CS8900             IXP2000_BOARD_IRQ(25)
+#define IRQ_IXDP2X01_BBSRAM             IXP2000_BOARD_IRQ(26)
+
+#define IXDP2X01_VALID_IRQ_MASK ( \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) )
+
+/* 
+ * IXDP2401 specific IRQs
+ */
+#define IRQ_IXDP2401_INTA_82546         IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2401_INTB_82546         IXP2000_BOARD_IRQ(1)
+
+#define IXDP2401_VALID_IRQ_MASK ( \
+                IXDP2X01_VALID_IRQ_MASK | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546))
+
+/*
+ * IXDP2801-specific IRQs
+ */
+#define IRQ_IXDP2801_RIV                IXP2000_BOARD_IRQ(0)
+#define IRQ_IXDP2801_CNFG_MEDIA         IXP2000_BOARD_IRQ(27)
+#define IRQ_IXDP2801_CLOCK_REF          IXP2000_BOARD_IRQ(28)
+
+#define IXDP2801_VALID_IRQ_MASK ( \
+                IXDP2X01_VALID_IRQ_MASK | \
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\
+                IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF))
+
+#define NR_IXDP2X01_IRQS                ((IRQ_IXDP2801_CLOCK_REF) + 1)
+
+#endif /*_IRQS_H*/
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x00.h b/include/asm-arm/arch-ixp2000/ixdp2x00.h
new file mode 100644
index 000000000000..3a398dfbf125
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/ixdp2x00.h
@@ -0,0 +1,93 @@
+/*
+ * include/asm-arm/arch-ixp2000/ixdp2x00.h
+ *
+ * Register and other defines for IXDP2[48]00 platforms
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef _IXDP2X00_H_
+#define _IXDP2X00_H_
+
+/*
+ * On board CPLD memory map
+ */
+#define IXDP2X00_PHYS_CPLD_BASE         0xc7000000
+#define IXDP2X00_VIRT_CPLD_BASE         0xfafff000
+#define IXDP2X00_CPLD_SIZE              0x00001000
+
+
+#define IXDP2X00_CPLD_REG(x)    \
+        (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x)
+
+/*
+ * IXDP2400 CPLD registers
+ */
+#define IXDP2400_CPLD_SYSLED            IXDP2X00_CPLD_REG(0x0)  
+#define IXDP2400_CPLD_DISP_DATA         IXDP2X00_CPLD_REG(0x4)
+#define IXDP2400_CPLD_CLOCK_SPEED       IXDP2X00_CPLD_REG(0x8)
+#define IXDP2400_CPLD_INT_STAT          IXDP2X00_CPLD_REG(0xc)
+#define IXDP2400_CPLD_REV               IXDP2X00_CPLD_REG(0x10)
+#define IXDP2400_CPLD_SYS_CLK_M         IXDP2X00_CPLD_REG(0x14)
+#define IXDP2400_CPLD_SYS_CLK_N         IXDP2X00_CPLD_REG(0x18)
+#define IXDP2400_CPLD_INT_MASK          IXDP2X00_CPLD_REG(0x48)
+
+/*
+ * IXDP2800 CPLD registers
+ */
+#define IXDP2800_CPLD_INT_STAT          IXDP2X00_CPLD_REG(0x0)
+#define IXDP2800_CPLD_INT_MASK          IXDP2X00_CPLD_REG(0x140)
+
+
+#define IXDP2X00_GPIO_I2C_ENABLE        0x02
+#define IXDP2X00_GPIO_SCL               0x07
+#define IXDP2X00_GPIO_SDA               0x06
+
+/*
+ * PCI devfns for on-board devices. We need these to be able to
+ * properly translate IRQs and for device removal.
+ */
+#define IXDP2400_SLAVE_ENET_DEVFN       0x18    /* Bus 1 */
+#define IXDP2400_MASTER_ENET_DEVFN      0x20    /* Bus 1 */
+#define IXDP2400_MEDIA_DEVFN            0x28    /* Bus 1 */
+#define IXDP2400_SWITCH_FABRIC_DEVFN    0x30    /* Bus 1 */
+
+#define IXDP2800_SLAVE_ENET_DEVFN       0x20    /* Bus 1 */
+#define IXDP2800_MASTER_ENET_DEVFN      0x18    /* Bus 1 */
+#define IXDP2800_SWITCH_FABRIC_DEVFN    0x30    /* Bus 1 */
+
+#define IXDP2X00_P2P_DEVFN              0x20    /* Bus 0 */
+#define IXDP2X00_21555_DEVFN            0x30    /* Bus 0 */
+#define IXDP2X00_SLAVE_NPU_DEVFN        0x28    /* Bus 1 */
+#define IXDP2X00_PMC_DEVFN              0x38    /* Bus 1 */
+#define IXDP2X00_MASTER_NPU_DEVFN       0x38    /* Bus 1 */
+
+#ifndef __ASSEMBLY__
+/*
+ * Master NPU will always have flash and be PCI master.
+ * Slave NPU may or may not have flash but will never be PCI master.
+ */
+static inline unsigned int ixdp2x00_master_npu(void)
+{
+        return ((ixp2000_has_flash()) && (ixp2000_is_pcimaster()));
+}
+
+/*
+ * Helper functions used by ixdp2400 and ixdp2800 specific code
+ */
+void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long);
+void ixdp2x00_slave_pci_postinit(void);
+void ixdp2x00_init_machine(void);
+void ixdp2x00_map_io(void);
+
+#endif
+
+#endif /*_IXDP2X00_H_ */
diff --git a/include/asm-arm/arch-ixp2000/ixdp2x01.h b/include/asm-arm/arch-ixp2000/ixdp2x01.h
new file mode 100644
index 000000000000..b3a1bcda8d01
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/ixdp2x01.h
@@ -0,0 +1,57 @@
+/*
+ * include/asm-arm/arch-ixp2000/ixdp2x01.h
+ *
+ * Platform definitions for IXDP2X01 && IXDP2801 systems
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista Software, Inc. 
+ *
+ * Based on original code Copyright (c) 2002-2003 Intel Corporation
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __IXDP2X01_H__
+#define __IXDP2X01_H__
+
+#define IXDP2X01_PHYS_CPLD_BASE         0xc6024000
+#define IXDP2X01_VIRT_CPLD_BASE         0xfafff000
+#define IXDP2X01_CPLD_REGION_SIZE       0x00001000
+
+#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg)
+#define IXDP2X01_CPLD_PHYS_REG(reg) (volatile u32*)(IXDP2X01_PHYS_CPLD_BASE | reg)
+
+#define IXDP2X01_UART1_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x40)
+#define IXDP2X01_UART1_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x40)
+
+#define IXDP2X01_UART2_VIRT_BASE        IXDP2X01_CPLD_VIRT_REG(0x60)
+#define IXDP2X01_UART2_PHYS_BASE        IXDP2X01_CPLD_PHYS_REG(0x60)
+
+#define IXDP2X01_CS8900_VIRT_BASE       IXDP2X01_CPLD_VIRT_REG(0x80)
+#define IXDP2X01_CS8900_VIRT_END        (IXDP2X01_CS8900_VIRT_BASE + 16)
+
+#define IXDP2X01_CPLD_RESET_REG         IXDP2X01_CPLD_VIRT_REG(0x00)
+#define IXDP2X01_INT_MASK_SET_REG       IXDP2X01_CPLD_VIRT_REG(0x08)
+#define IXDP2X01_INT_STAT_REG           IXDP2X01_CPLD_VIRT_REG(0x0C)
+#define IXDP2X01_INT_RAW_REG            IXDP2X01_CPLD_VIRT_REG(0x10) 
+#define IXDP2X01_INT_MASK_CLR_REG       IXDP2X01_INT_RAW_REG
+#define IXDP2X01_INT_SIM_REG            IXDP2X01_CPLD_VIRT_REG(0x14)
+
+#define IXDP2X01_CPLD_FLASH_REG         IXDP2X01_CPLD_VIRT_REG(0x20)
+
+#define IXDP2X01_CPLD_FLASH_INTERN      0x8000
+#define IXDP2X01_CPLD_FLASH_BANK_MASK   0xF
+#define IXDP2X01_FLASH_WINDOW_BITS      25
+#define IXDP2X01_FLASH_WINDOW_SIZE      (1 << IXDP2X01_FLASH_WINDOW_BITS)
+#define IXDP2X01_FLASH_WINDOW_MASK      (IXDP2X01_FLASH_WINDOW_SIZE - 1)
+
+#define IXDP2X01_UART_CLK               1843200
+
+#define IXDP2X01_GPIO_I2C_ENABLE        0x02
+#define IXDP2X01_GPIO_SCL               0x07
+#define IXDP2X01_GPIO_SDA               0x06
+
+#endif /* __IXDP2x01_H__ */
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
new file mode 100644
index 000000000000..6c56708d0ff0
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -0,0 +1,377 @@
+/*
+ * include/asm-arm/arch-ixp2000/ixp2000-regs.h
+ *
+ * Chipset register definitions for IXP2400/2800 based systems.
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+#ifndef _IXP2000_REGS_H_
+#define _IXP2000_REGS_H_
+
+/* 
+ * Static I/O regions.
+ *
+ * Most of the registers are clumped in 4K regions spread throughout
+ * the 0xc0000000 -> 0xc0100000 address range, but we just map in
+ * the whole range using a single 1 MB section instead of small
+ * 4K pages.  This has two advantages for us:
+ *
+ * 1) We use only one TLB entry for large number of on-chip I/O devices.
+ *
+ * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
+ *    as required per erratum #66.  We accomplish this by using a
+ *    new MT_IXP2000_DEVICE memory type with the bits set as required.
+ *
+ * CAP stands for CSR Access Proxy.
+ *
+ * If you change the virtual address of this mapping, please propagate
+ * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
+ * address of the UART located in this region.
+ */
+
+#define IXP2000_CAP_PHYS_BASE           0xc0000000
+#define IXP2000_CAP_VIRT_BASE           0xfef00000
+#define IXP2000_CAP_SIZE                0x00100000
+
+/*
+ * Addresses for specific on-chip peripherals
+ */
+#define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
+#define IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
+#define IXP2000_UART_PHYS_BASE          0xc0030000
+#define IXP2000_UART_VIRT_BASE          0xfef30000
+#define IXP2000_TIMER_VIRT_BASE         0xfef20000
+#define IXP2000_GPIO_VIRT_BASE          0Xfef10000
+
+/*
+ * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
+ * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
+ * entry-macro.S, so if you ever change these please propagate
+ * the change.
+ */
+#define IXP2000_INTCTL_PHYS_BASE        0xd6000000
+#define IXP2000_INTCTL_VIRT_BASE        0xfee00000
+#define IXP2000_INTCTL_SIZE             0x00100000
+
+#define IXP2000_PCI_CREG_PHYS_BASE      0xde000000
+#define IXP2000_PCI_CREG_VIRT_BASE      0xfed00000
+#define IXP2000_PCI_CREG_SIZE           0x00100000
+
+#define IXP2000_PCI_CSR_PHYS_BASE       0xdf000000
+#define IXP2000_PCI_CSR_VIRT_BASE       0xfec00000
+#define IXP2000_PCI_CSR_SIZE            0x00100000
+
+#define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
+#define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
+#define IXP2000_PCI_IO_SIZE             0x01000000
+
+#define IXP2000_PCI_CFG0_PHYS_BASE      0xda000000
+#define IXP2000_PCI_CFG0_VIRT_BASE      0xfc000000
+#define IXP2000_PCI_CFG0_SIZE           0x01000000
+
+#define IXP2000_PCI_CFG1_PHYS_BASE      0xdb000000
+#define IXP2000_PCI_CFG1_VIRT_BASE      0xfb000000
+#define IXP2000_PCI_CFG1_SIZE           0x01000000
+
+/* 
+ * Timers
+ */
+#define IXP2000_TIMER_REG(x)            ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
+/* Timer control */
+#define IXP2000_T1_CTL                  IXP2000_TIMER_REG(0x00)
+#define IXP2000_T2_CTL                  IXP2000_TIMER_REG(0x04)
+#define IXP2000_T3_CTL                  IXP2000_TIMER_REG(0x08)
+#define IXP2000_T4_CTL                  IXP2000_TIMER_REG(0x0c)
+/* Store initial value */
+#define IXP2000_T1_CLD                  IXP2000_TIMER_REG(0x10)
+#define IXP2000_T2_CLD                  IXP2000_TIMER_REG(0x14)
+#define IXP2000_T3_CLD                  IXP2000_TIMER_REG(0x18)
+#define IXP2000_T4_CLD                  IXP2000_TIMER_REG(0x1c)
+/* Read current value */
+#define IXP2000_T1_CSR                  IXP2000_TIMER_REG(0x20)
+#define IXP2000_T2_CSR                  IXP2000_TIMER_REG(0x24)
+#define IXP2000_T3_CSR                  IXP2000_TIMER_REG(0x28)
+#define IXP2000_T4_CSR                  IXP2000_TIMER_REG(0x2c)
+/* Clear associated timer interrupt */
+#define IXP2000_T1_CLR                  IXP2000_TIMER_REG(0x30)
+#define IXP2000_T2_CLR                  IXP2000_TIMER_REG(0x34)
+#define IXP2000_T3_CLR                  IXP2000_TIMER_REG(0x38)
+#define IXP2000_T4_CLR                  IXP2000_TIMER_REG(0x3c)
+/* Timer watchdog enable for T4 */
+#define IXP2000_TWDE                    IXP2000_TIMER_REG(0x40)
+
+#define WDT_ENABLE                      0x00000001
+#define TIMER_DIVIDER_256               0x00000008
+#define TIMER_ENABLE                    0x00000080
+#define IRQ_MASK_TIMER1                 (1 << 4)
+
+/*
+ * Interrupt controller registers
+ */
+#define IXP2000_INTCTL_REG(x)           (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
+#define IXP2000_IRQ_STATUS              IXP2000_INTCTL_REG(0x08)
+#define IXP2000_IRQ_ENABLE              IXP2000_INTCTL_REG(0x10)
+#define IXP2000_IRQ_ENABLE_SET          IXP2000_INTCTL_REG(0x10)
+#define IXP2000_IRQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x18)
+#define IXP2000_FIQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x14)
+#define IXP2000_IRQ_ERR_STATUS          IXP2000_INTCTL_REG(0x24)
+#define IXP2000_IRQ_ERR_ENABLE_SET      IXP2000_INTCTL_REG(0x2c)
+#define IXP2000_FIQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x30)
+#define IXP2000_IRQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x34)
+#define IXP2000_IRQ_THD_RAW_STATUS_A_0  IXP2000_INTCTL_REG(0x60)
+#define IXP2000_IRQ_THD_RAW_STATUS_A_1  IXP2000_INTCTL_REG(0x64)
+#define IXP2000_IRQ_THD_RAW_STATUS_A_2  IXP2000_INTCTL_REG(0x68)
+#define IXP2000_IRQ_THD_RAW_STATUS_A_3  IXP2000_INTCTL_REG(0x6c)
+#define IXP2000_IRQ_THD_RAW_STATUS_B_0  IXP2000_INTCTL_REG(0x80)
+#define IXP2000_IRQ_THD_RAW_STATUS_B_1  IXP2000_INTCTL_REG(0x84)
+#define IXP2000_IRQ_THD_RAW_STATUS_B_2  IXP2000_INTCTL_REG(0x88)
+#define IXP2000_IRQ_THD_RAW_STATUS_B_3  IXP2000_INTCTL_REG(0x8c)
+#define IXP2000_IRQ_THD_ENABLE_SET_A_0  IXP2000_INTCTL_REG(0x160)
+#define IXP2000_IRQ_THD_ENABLE_SET_A_1  IXP2000_INTCTL_REG(0x164)
+#define IXP2000_IRQ_THD_ENABLE_SET_A_2  IXP2000_INTCTL_REG(0x168)
+#define IXP2000_IRQ_THD_ENABLE_SET_A_3  IXP2000_INTCTL_REG(0x16c)
+#define IXP2000_IRQ_THD_ENABLE_SET_B_0  IXP2000_INTCTL_REG(0x180)
+#define IXP2000_IRQ_THD_ENABLE_SET_B_1  IXP2000_INTCTL_REG(0x184)
+#define IXP2000_IRQ_THD_ENABLE_SET_B_2  IXP2000_INTCTL_REG(0x188)
+#define IXP2000_IRQ_THD_ENABLE_SET_B_3  IXP2000_INTCTL_REG(0x18c)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0        IXP2000_INTCTL_REG(0x1e0)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1        IXP2000_INTCTL_REG(0x1e4)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2        IXP2000_INTCTL_REG(0x1e8)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3        IXP2000_INTCTL_REG(0x1ec)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0        IXP2000_INTCTL_REG(0x200)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1        IXP2000_INTCTL_REG(0x204)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2        IXP2000_INTCTL_REG(0x208)
+#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3        IXP2000_INTCTL_REG(0x20c)
+
+/*
+ * Mask of valid IRQs in the 32-bit IRQ register. We use
+ * this to mark certain IRQs as being invalid.
+ */
+#define IXP2000_VALID_IRQ_MASK  0x0f0fffff
+
+/*
+ * PCI config register access from core
+ */
+#define IXP2000_PCI_CREG(x)             (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
+#define IXP2000_PCI_CMDSTAT             IXP2000_PCI_CREG(0x04)
+#define IXP2000_PCI_CSR_BAR             IXP2000_PCI_CREG(0x10)
+#define IXP2000_PCI_SRAM_BAR            IXP2000_PCI_CREG(0x14)
+#define IXP2000_PCI_SDRAM_BAR           IXP2000_PCI_CREG(0x18)
+
+/*
+ * PCI CSRs
+ */
+#define IXP2000_PCI_CSR(x)              (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
+
+/*
+ * PCI outbound interrupts
+ */
+#define IXP2000_PCI_OUT_INT_STATUS      IXP2000_PCI_CSR(0x30)
+#define IXP2000_PCI_OUT_INT_MASK        IXP2000_PCI_CSR(0x34)
+/*
+ * PCI communications
+ */
+#define IXP2000_PCI_MAILBOX0            IXP2000_PCI_CSR(0x50)
+#define IXP2000_PCI_MAILBOX1            IXP2000_PCI_CSR(0x54)
+#define IXP2000_PCI_MAILBOX2            IXP2000_PCI_CSR(0x58)
+#define IXP2000_PCI_MAILBOX3            IXP2000_PCI_CSR(0x5C)
+#define IXP2000_XSCALE_DOORBELL         IXP2000_PCI_CSR(0x60)
+#define IXP2000_XSCALE_DOORBELL_SETUP   IXP2000_PCI_CSR(0x64)
+#define IXP2000_PCI_DOORBELL            IXP2000_PCI_CSR(0x70)
+#define IXP2000_PCI_DOORBELL_SETUP      IXP2000_PCI_CSR(0x74)
+
+/*
+ * DMA engines
+ */
+#define IXP2000_PCI_CH1_BYTE_CNT        IXP2000_PCI_CSR(0x80)
+#define IXP2000_PCI_CH1_ADDR            IXP2000_PCI_CSR(0x84)
+#define IXP2000_PCI_CH1_DRAM_ADDR       IXP2000_PCI_CSR(0x88)
+#define IXP2000_PCI_CH1_DESC_PTR        IXP2000_PCI_CSR(0x8C)
+#define IXP2000_PCI_CH1_CNTRL           IXP2000_PCI_CSR(0x90)
+#define IXP2000_PCI_CH1_ME_PARAM        IXP2000_PCI_CSR(0x94)
+#define IXP2000_PCI_CH2_BYTE_CNT        IXP2000_PCI_CSR(0xA0)
+#define IXP2000_PCI_CH2_ADDR            IXP2000_PCI_CSR(0xA4)
+#define IXP2000_PCI_CH2_DRAM_ADDR       IXP2000_PCI_CSR(0xA8)
+#define IXP2000_PCI_CH2_DESC_PTR        IXP2000_PCI_CSR(0xAC)
+#define IXP2000_PCI_CH2_CNTRL           IXP2000_PCI_CSR(0xB0)
+#define IXP2000_PCI_CH2_ME_PARAM        IXP2000_PCI_CSR(0xB4)
+#define IXP2000_PCI_CH3_BYTE_CNT        IXP2000_PCI_CSR(0xC0)
+#define IXP2000_PCI_CH3_ADDR            IXP2000_PCI_CSR(0xC4)
+#define IXP2000_PCI_CH3_DRAM_ADDR       IXP2000_PCI_CSR(0xC8)
+#define IXP2000_PCI_CH3_DESC_PTR        IXP2000_PCI_CSR(0xCC)
+#define IXP2000_PCI_CH3_CNTRL           IXP2000_PCI_CSR(0xD0)
+#define IXP2000_PCI_CH3_ME_PARAM        IXP2000_PCI_CSR(0xD4)
+#define IXP2000_DMA_INF_MODE            IXP2000_PCI_CSR(0xE0)
+/*
+ * Size masks for BARs
+ */
+#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
+#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
+/*
+ * Control and uEngine related
+ */
+#define IXP2000_PCI_CONTROL             IXP2000_PCI_CSR(0x13C)
+#define IXP2000_PCI_ADDR_EXT            IXP2000_PCI_CSR(0x140)
+#define IXP2000_PCI_ME_PUSH_STATUS      IXP2000_PCI_CSR(0x148)
+#define IXP2000_PCI_ME_PUSH_EN          IXP2000_PCI_CSR(0x14C)
+#define IXP2000_PCI_ERR_STATUS          IXP2000_PCI_CSR(0x150)
+#define IXP2000_PCI_ERR_ENABLE          IXP2000_PCI_CSR(0x154)
+/*
+ * Inbound PCI interrupt control
+ */
+#define IXP2000_PCI_XSCALE_INT_STATUS   IXP2000_PCI_CSR(0x158)
+#define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
+
+#define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
+#define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Centrolfunction bit */
+#define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from XScale to PCI */
+
+/* These are from the IRQ register in the PCI ISR register */
+#define PCI_CONTROL_BE_DEO              (1 << 22)       /* Big Endian Data Enable Out */
+#define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
+#define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
+#define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
+#define PCI_CONTROL_PNR                 (1 << 17)       /* PCI Not Reset bit */
+
+#define IXP2000_PCI_RST_REL             (1 << 2)
+#define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
+#define CFG_PCI_BOOT_HOST               (1 << 2)
+#define CFG_BOOT_PROM                   (1 << 1)
+
+/*
+ * SlowPort CSRs
+ *
+ * The slowport is used to access things like flash, SONET framer control
+ * ports, slave microprocessors, CPLDs, and others of chip memory mapped
+ * peripherals.
+ */
+#define SLOWPORT_CSR(x)         (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
+
+#define IXP2000_SLOWPORT_CCR            SLOWPORT_CSR(0x00)
+#define IXP2000_SLOWPORT_WTC1           SLOWPORT_CSR(0x04)
+#define IXP2000_SLOWPORT_WTC2           SLOWPORT_CSR(0x08)
+#define IXP2000_SLOWPORT_RTC1           SLOWPORT_CSR(0x0c)
+#define IXP2000_SLOWPORT_RTC2           SLOWPORT_CSR(0x10)
+#define IXP2000_SLOWPORT_FSR            SLOWPORT_CSR(0x14)
+#define IXP2000_SLOWPORT_PCR            SLOWPORT_CSR(0x18)
+#define IXP2000_SLOWPORT_ADC            SLOWPORT_CSR(0x1C)
+#define IXP2000_SLOWPORT_FAC            SLOWPORT_CSR(0x20)
+#define IXP2000_SLOWPORT_FRM            SLOWPORT_CSR(0x24)
+#define IXP2000_SLOWPORT_FIN            SLOWPORT_CSR(0x28)
+
+/*
+ * CCR values.  
+ * The CCR configures the clock division for the slowport interface.
+ */
+#define SLOWPORT_CCR_DIV_1              0x00
+#define SLOWPORT_CCR_DIV_2              0x01
+#define SLOWPORT_CCR_DIV_4              0x02
+#define SLOWPORT_CCR_DIV_6              0x03
+#define SLOWPORT_CCR_DIV_8              0x04
+#define SLOWPORT_CCR_DIV_10             0x05
+#define SLOWPORT_CCR_DIV_12             0x06
+#define SLOWPORT_CCR_DIV_14             0x07
+#define SLOWPORT_CCR_DIV_16             0x08
+#define SLOWPORT_CCR_DIV_18             0x09
+#define SLOWPORT_CCR_DIV_20             0x0a
+#define SLOWPORT_CCR_DIV_22             0x0b
+#define SLOWPORT_CCR_DIV_24             0x0c
+#define SLOWPORT_CCR_DIV_26             0x0d
+#define SLOWPORT_CCR_DIV_28             0x0e
+#define SLOWPORT_CCR_DIV_30             0x0f
+
+/*
+ * PCR values.  PCR configure the mode of the interface.
+ */
+#define SLOWPORT_MODE_FLASH             0x00
+#define SLOWPORT_MODE_LUCENT            0x01
+#define SLOWPORT_MODE_PMC_SIERRA        0x02
+#define SLOWPORT_MODE_INTEL_UP          0x03
+#define SLOWPORT_MODE_MOTOROLA_UP       0x04
+
+/*
+ * ADC values.  Defines data and address bus widths.
+ */
+#define SLOWPORT_ADDR_WIDTH_8           0x00
+#define SLOWPORT_ADDR_WIDTH_16          0x01
+#define SLOWPORT_ADDR_WIDTH_24          0x02
+#define SLOWPORT_ADDR_WIDTH_32          0x03
+#define SLOWPORT_DATA_WIDTH_8           0x00
+#define SLOWPORT_DATA_WIDTH_16          0x10
+#define SLOWPORT_DATA_WIDTH_24          0x20
+#define SLOWPORT_DATA_WIDTH_32          0x30
+
+/*
+ * Masks and shifts for various fields in the WTC and RTC registers.
+ */
+#define SLOWPORT_WRTC_MASK_HD           0x0003
+#define SLOWPORT_WRTC_MASK_SU           0x003c
+#define SLOWPORT_WRTC_MASK_PW           0x03c0
+
+#define SLOWPORT_WRTC_SHIFT_HD          0x00
+#define SLOWPORT_WRTC_SHIFT_SU          0x02
+#define SLOWPORT_WRTC_SHFIT_PW          0x06
+
+
+/*
+ * GPIO registers & GPIO interface.
+ */
+#define IXP2000_GPIO_REG(x)             ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
+#define IXP2000_GPIO_PLR                IXP2000_GPIO_REG(0x00)
+#define IXP2000_GPIO_PDPR               IXP2000_GPIO_REG(0x04)
+#define IXP2000_GPIO_PDSR               IXP2000_GPIO_REG(0x08)
+#define IXP2000_GPIO_PDCR               IXP2000_GPIO_REG(0x0c)
+#define IXP2000_GPIO_POPR               IXP2000_GPIO_REG(0x10)
+#define IXP2000_GPIO_POSR               IXP2000_GPIO_REG(0x14)
+#define IXP2000_GPIO_POCR               IXP2000_GPIO_REG(0x18)
+#define IXP2000_GPIO_REDR               IXP2000_GPIO_REG(0x1c)
+#define IXP2000_GPIO_FEDR               IXP2000_GPIO_REG(0x20)
+#define IXP2000_GPIO_EDSR               IXP2000_GPIO_REG(0x24)
+#define IXP2000_GPIO_LSHR               IXP2000_GPIO_REG(0x28)
+#define IXP2000_GPIO_LSLR               IXP2000_GPIO_REG(0x2c)
+#define IXP2000_GPIO_LDSR               IXP2000_GPIO_REG(0x30)
+#define IXP2000_GPIO_INER               IXP2000_GPIO_REG(0x34)
+#define IXP2000_GPIO_INSR               IXP2000_GPIO_REG(0x38)
+#define IXP2000_GPIO_INCR               IXP2000_GPIO_REG(0x3c)
+#define IXP2000_GPIO_INST               IXP2000_GPIO_REG(0x40)
+
+/*
+ * "Global" registers...whatever that's supposed to mean.
+ */
+#define GLOBAL_REG_BASE                 (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
+#define GLOBAL_REG(x)                   (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
+
+#define IXP2000_PROD_ID                 GLOBAL_REG(0x00)
+
+#define IXP2000_MAJ_PROD_TYPE_MASK      0x001F0000
+#define IXP2000_MAJ_PROD_TYPE_IXP2000   0x00000000
+#define IXP2000_MIN_PROD_TYPE_MASK      0x0000FF00
+#define IXP2000_MIN_PROD_TYPE_IXP2400   0x00000200
+#define IXP2000_MIN_PROD_TYPE_IXP2850   0x00000100
+#define IXP2000_MIN_PROD_TYPE_IXP2800   0x00000000
+#define IXP2000_MAJ_REV_MASK            0x000000F0
+#define IXP2000_MIN_REV_MASK            0x0000000F
+#define IXP2000_PROD_ID_MASK            0xFFFFFFFF
+
+#define IXP2000_MISC_CONTROL            GLOBAL_REG(0x04)
+#define IXP2000_MSF_CLK_CNTRL           GLOBAL_REG(0x08)
+#define IXP2000_RESET0                  GLOBAL_REG(0x0c)
+#define IXP2000_RESET1                  GLOBAL_REG(0x10)
+#define IXP2000_CCR                     GLOBAL_REG(0x14)
+#define IXP2000_STRAP_OPTIONS           GLOBAL_REG(0x18)
+
+#define RSTALL                          (1 << 16)
+#define WDT_RESET_ENABLE                0x01000000
+
+
+#endif                          /* _IXP2000_H_ */
diff --git a/include/asm-arm/arch-ixp2000/memory.h b/include/asm-arm/arch-ixp2000/memory.h
new file mode 100644
index 000000000000..d0f415c6dae9
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/memory.h
@@ -0,0 +1,34 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/memory.h
+ *
+ * Copyright (c) 2002 Intel Corp.
+ * Copyright (c) 2003-2004 MontaVista Software, Inc.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     (0x00000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#include <asm/arch/ixp2000-regs.h>
+
+#define __virt_to_bus(v) \
+        (((__virt_to_phys(v) - 0x0) + (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)))
+
+#define __bus_to_virt(b) \
+        __phys_to_virt((((b - (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0)) + 0x0)))
+
+#endif
+
diff --git a/include/asm-arm/arch-ixp2000/param.h b/include/asm-arm/arch-ixp2000/param.h
new file mode 100644
index 000000000000..2646d9e5919d
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/param.h
@@ -0,0 +1,3 @@
+/*
+ *  linux/include/asm-arm/arch-ixp2000/param.h
+ */
diff --git a/include/asm-arm/arch-ixp2000/platform.h b/include/asm-arm/arch-ixp2000/platform.h
new file mode 100644
index 000000000000..509e44d528d8
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/platform.h
@@ -0,0 +1,166 @@
+/*
+ * include/asm-arm/arch-ixp2000/platform.h
+ *
+ * Various bits of code used by platform-level code.
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+
+#ifndef __ASSEMBLY__
+
+/*
+ * The IXP2400 B0 silicon contains an erratum (#66) that causes writes
+ * to on-chip I/O register to not complete fully. What this means is
+ * that if you have a write to on-chip I/O followed by a back-to-back
+ * read or write, the first write will happen twice. OR...if it's
+ * not a back-to-back transaction, the read or write will generate
+ * incorrect data.
+ *
+ * The official work around for this is to set the on-chip I/O regions
+ * as XCB=101 and then force a read-back from the register.
+ *
+ */
+#if defined(CONFIG_ARCH_ENP2611) || defined(CONFIG_ARCH_IXDP2400) || defined(CONFIG_ARCH_IXDP2401)
+
+#include <asm/system.h>         /* Pickup local_irq_ functions */
+
+static inline void ixp2000_reg_write(volatile unsigned long *reg, unsigned long val)
+{
+        volatile unsigned long dummy;
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *reg = val;
+        barrier();
+        dummy = *reg;
+        local_irq_restore(flags);
+}
+#else
+#define ixp2000_reg_write(reg, val) (*reg = val)
+#endif  /* IXDP2400 || IXDP2401 */
+
+/*
+ * Boards may multiplex different devices on the 2nd channel of 
+ * the slowport interface that each need different configuration 
+ * settings.  For example, the IXDP2400 uses channel 2 on the interface 
+ * to access the CPLD, the switch fabric card, and the media card.  Each
+ * one needs a different mode so drivers must save/restore the mode 
+ * before and after each operation.  
+ *
+ * acquire_slowport(&your_config);
+ * ...
+ * do slowport operations
+ * ...
+ * release_slowport();
+ *
+ * Note that while you have the slowport, you are holding a spinlock,
+ * so your code should be written as if you explicitly acquired a lock.
+ *
+ * The configuration only affects device 2 on the slowport, so the
+ * MTD map driver does not acquire/release the slowport.  
+ */
+struct slowport_cfg {
+        unsigned long CCR;      /* Clock divide */
+        unsigned long WTC;      /* Write Timing Control */
+        unsigned long RTC;      /* Read Timing Control */
+        unsigned long PCR;      /* Protocol Control Register */
+        unsigned long ADC;      /* Address/Data Width Control */
+};
+
+
+void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *);
+void ixp2000_release_slowport(struct slowport_cfg *);
+
+/*
+ * IXP2400 A0/A1 and  IXP2800 A0/A1/A2 have broken slowport that requires
+ * tweaking of addresses in the MTD driver.
+ */
+static inline unsigned ixp2000_has_broken_slowport(void)
+{
+        unsigned long id = *IXP2000_PROD_ID;
+        unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK |
+                                      IXP2000_MIN_PROD_TYPE_MASK);
+        return (((id_prod ==
+                  /* fixed in IXP2400-B0 */
+                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+                   IXP2000_MIN_PROD_TYPE_IXP2400)) &&
+                 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
+                ((id_prod ==
+                  /* fixed in IXP2800-B0 */
+                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+                   IXP2000_MIN_PROD_TYPE_IXP2800)) &&
+                 ((id & IXP2000_MAJ_REV_MASK) == 0)) ||
+                ((id_prod ==
+                  /* fixed in IXP2850-B0 */
+                  (IXP2000_MAJ_PROD_TYPE_IXP2000 |
+                   IXP2000_MIN_PROD_TYPE_IXP2850)) &&
+                 ((id & IXP2000_MAJ_REV_MASK) == 0)));
+}
+
+static inline unsigned int ixp2000_has_flash(void)
+{
+        return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM));
+}
+
+static inline unsigned int ixp2000_is_pcimaster(void)
+{
+        return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST));
+}
+
+void ixp2000_map_io(void);
+void ixp2000_init_irq(void);
+void ixp2000_init_time(unsigned long);
+unsigned long ixp2000_gettimeoffset(void);
+
+struct pci_sys_data;
+
+void ixp2000_pci_preinit(void);
+int ixp2000_pci_setup(int, struct pci_sys_data*);
+struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
+int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *);
+int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32);
+
+/*
+ * Several of the IXP2000 systems have banked flash so we need to extend the
+ * flash_platform_data structure with some private pointers
+ */
+struct ixp2000_flash_data {
+        struct flash_platform_data *platform_data;
+        int nr_banks;
+        unsigned long (*bank_setup)(unsigned long);
+};
+
+/*
+ * GPIO helper functions
+ */
+#define GPIO_IN         0
+#define GPIO_OUT        1
+
+extern void gpio_line_config(int line, int style);
+
+static inline int gpio_line_get(int line)
+{
+        return (((*IXP2000_GPIO_PLR) >> line) & 1);
+}
+
+static inline void gpio_line_set(int line, int value)
+{
+        if (value) 
+                ixp2000_reg_write(IXP2000_GPIO_POSR, (1 << line));
+        else 
+                ixp2000_reg_write(IXP2000_GPIO_POCR, (1 << line));
+}
+
+struct ixp2000_i2c_pins {
+        unsigned long sda_pin;
+        unsigned long scl_pin;
+};
+
+#endif /*  !__ASSEMBLY__ */
diff --git a/include/asm-arm/arch-ixp2000/system.h b/include/asm-arm/arch-ixp2000/system.h
new file mode 100644
index 000000000000..4f489cc0dfa5
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/system.h
@@ -0,0 +1,54 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/system.h
+ *
+ * Copyright (C) 2002 Intel Corp.
+ * Copyricht (C) 2003-2005 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        local_irq_disable();
+
+        /*
+         * Reset flash banking register so that we are pointing at
+         * RedBoot bank.
+         */
+        if (machine_is_ixdp2401()) {
+                *IXDP2X01_CPLD_FLASH_REG = ((0 >> IXDP2X01_FLASH_WINDOW_BITS)
+                                                | IXDP2X01_CPLD_FLASH_INTERN);
+                *IXDP2X01_CPLD_RESET_REG = 0xffffffff;
+        }
+
+        /*
+         * On IXDP2801 we need to write this magic sequence to the CPLD
+         * to cause a complete reset of the CPU and all external devices
+         * and moves the flash bank register back to 0.
+         */
+        if (machine_is_ixdp2801()) {
+                unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG;
+                reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF);
+                *IXDP2X01_CPLD_RESET_REG = reset_reg;
+                mb();
+                *IXDP2X01_CPLD_RESET_REG = 0x80000000;
+        }
+
+        /*
+         * We do a reset all if we are PCI master. We could be a slave and we
+         * don't want to do anything funky on the PCI bus.
+         */
+        if (*IXP2000_STRAP_OPTIONS & CFG_PCI_BOOT_HOST) {
+                *(IXP2000_RESET0) |= (RSTALL);
+        }
+}
diff --git a/include/asm-arm/arch-ixp2000/timex.h b/include/asm-arm/arch-ixp2000/timex.h
new file mode 100644
index 000000000000..b78a183d4698
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/timex.h
@@ -0,0 +1,13 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/timex.h
+ *
+ * IXP2000 architecture timex specifications
+ */
+
+
+/*
+ * Default clock is 50MHz APB, but platform code can override this
+ */
+#define CLOCK_TICK_RATE 50000000
+
+
diff --git a/include/asm-arm/arch-ixp2000/uncompress.h b/include/asm-arm/arch-ixp2000/uncompress.h
new file mode 100644
index 000000000000..3d3d5b2ed6e9
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/uncompress.h
@@ -0,0 +1,52 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/uncompress.h
+ *
+ *
+ * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ * Maintainer: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2002 Intel Corp.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#include <linux/serial_reg.h>
+
+#define UART_BASE       0xc0030000
+
+#define PHYS(x)          ((volatile unsigned long *)(UART_BASE + x))
+
+#define UARTDR          PHYS(0x00)      /* Transmit reg dlab=0 */
+#define UARTDLL         PHYS(0x00)      /* Divisor Latch reg dlab=1*/
+#define UARTDLM         PHYS(0x04)      /* Divisor Latch reg dlab=1*/
+#define UARTIER         PHYS(0x04)      /* Interrupt enable reg */
+#define UARTFCR         PHYS(0x08)      /* FIFO control reg dlab =0*/
+#define UARTLCR         PHYS(0x0c)      /* Control reg */
+#define UARTSR          PHYS(0x14)      /* Status reg */
+
+
+static __inline__ void putc(char c)
+{
+        int j = 0x1000;
+
+        while (--j && !(*UARTSR & UART_LSR_THRE)); 
+        *UARTDR = c;
+}
+
+static void putstr(const char *s)
+{
+        while (*s)
+        {
+                putc(*s);
+                if (*s == '\n')
+                        putc('\r');
+                s++;
+        }
+}
+
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-ixp2000/vmalloc.h b/include/asm-arm/arch-ixp2000/vmalloc.h
new file mode 100644
index 000000000000..2e4bcbcf31f0
--- /dev/null
+++ b/include/asm-arm/arch-ixp2000/vmalloc.h
@@ -0,0 +1,23 @@
+/*
+ * linux/include/asm-arm/arch-ixp2000/vmalloc.h
+ *
+ * Author: Naeem Afzal <naeem.m.afzal@intel.com>
+ *
+ * Copyright 2002 Intel Corp.
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET      (8*1024*1024)
+#define VMALLOC_START       (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x)   ((unsigned long)(x))
+#define VMALLOC_END         0xfaffefff
diff --git a/include/asm-arm/arch-ixp4xx/coyote.h b/include/asm-arm/arch-ixp4xx/coyote.h
new file mode 100644
index 000000000000..dd0c2d2d8503
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/coyote.h
@@ -0,0 +1,36 @@
+/*
+ * include/asm-arm/arch-ixp4xx/coyote.h
+ *
+ * ADI Engineering platform specific definitions
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista, Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+
+#define COYOTE_FLASH_BASE       IXP4XX_EXP_BUS_CS0_BASE_PHYS
+#define COYOTE_FLASH_SIZE       IXP4XX_EXP_BUS_CSX_REGION_SIZE * 2
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define COYOTE_PCI_SLOT0_PIN    6
+#define COYOTE_PCI_SLOT1_PIN    11
+
+#define COYOTE_PCI_SLOT0_DEVID  14
+#define COYOTE_PCI_SLOT1_DEVID  15
+
+#define COYOTE_IDE_BASE_PHYS    IXP4XX_EXP_BUS_CS3_BASE_PHYS
+#define COYOTE_IDE_BASE_VIRT    0xFFFE1000
+#define COYOTE_IDE_REGION_SIZE  0x1000
+
+#define COYOTE_IDE_DATA_PORT    0xFFFE10E0
+#define COYOTE_IDE_CTRL_PORT    0xFFFE10FC
+#define COYOTE_IDE_ERROR_PORT   0xFFFE10E2
+
diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S
new file mode 100644
index 000000000000..4499ae8e4b44
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/debug-macro.S
@@ -0,0 +1,34 @@
+/* linux/include/asm-arm/arch-ixp4xx/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0xc8000000
+                movne   \rx, #0xff000000
+                add     \rx,\rx,#3              @ Uart regs are at off set of 3 if
+                                                @ byte writes used - Big Endian.
+                .endm
+
+               .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  waituart,rd,rx
+1002:           ldrb    \rd, [\rx, #0x14]
+                and     \rd, \rd, #0x60         @ check THRE and TEMT bits
+                teq     \rd, #0x60
+                bne     1002b
+                .endm
+
+                .macro  busyuart,rd,rx
+                .endm
diff --git a/include/asm-arm/arch-ixp4xx/dma.h b/include/asm-arm/arch-ixp4xx/dma.h
new file mode 100644
index 000000000000..312065dc0e7a
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/dma.h
@@ -0,0 +1,26 @@
+/*
+ * include/asm-arm/arch-ixp4xx/dma.h
+ *
+ * Copyright (C) 2001-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#include <linux/config.h>
+#include <linux/device.h>
+#include <linux/pci.h>
+#include <asm/page.h>
+#include <asm/sizes.h>
+#include <asm/hardware.h>
+
+#define MAX_DMA_ADDRESS         (PAGE_OFFSET + SZ_64M)
+
+/* No DMA */
+#define MAX_DMA_CHANNELS        0
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S
new file mode 100644
index 000000000000..455da64832de
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ * include/asm-arm/arch-ixp4xx/entry-macro.S
+ *
+ * Low-level IRQ helper macros for IXP4xx-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
+                ldr     \irqstat, [\irqstat]            @ get interrupts
+                cmp     \irqstat, #0
+                beq     1001f
+                clz     \irqnr, \irqstat
+                mov     \base, #31
+                subs    \irqnr, \base, \irqnr
+
+1001:
+                /*
+                 * IXP465 has an upper IRQ status register
+                 */
+#if defined(CONFIG_CPU_IXP46X)
+                bne     1002f
+                ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
+                ldr     \irqstat, [\irqstat]            @ get upper interrupts
+                mov     \irqnr, #63
+                clz     \irqstat, \irqstat
+                cmp     \irqstat, #32
+                subne   \irqnr, \irqnr, \irqstat
+1002:
+#endif
+                .endm
+
+
diff --git a/include/asm-arm/arch-ixp4xx/gtwx5715.h b/include/asm-arm/arch-ixp4xx/gtwx5715.h
new file mode 100644
index 000000000000..fc460af70627
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/gtwx5715.h
@@ -0,0 +1,120 @@
+/*
+ * include/asm-arm/arch-ixp4xx/gtwx5715.h
+ *
+ * Gemtek GTWX5715 Gateway (Linksys WRV54G)
+ *
+ * Copyright 2004 (c) George T. Joseph
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+#include "irqs.h"
+
+#define GTWX5715_GPIO0  0
+#define GTWX5715_GPIO1  1
+#define GTWX5715_GPIO2  2
+#define GTWX5715_GPIO3  3
+#define GTWX5715_GPIO4  4
+#define GTWX5715_GPIO5  5
+#define GTWX5715_GPIO6  6
+#define GTWX5715_GPIO7  7
+#define GTWX5715_GPIO8  8
+#define GTWX5715_GPIO9  9
+#define GTWX5715_GPIO10 10
+#define GTWX5715_GPIO11 11
+#define GTWX5715_GPIO12 12
+#define GTWX5715_GPIO13 13
+#define GTWX5715_GPIO14 14
+
+#define GTWX5715_GPIO0_IRQ                      IRQ_IXP4XX_GPIO0
+#define GTWX5715_GPIO1_IRQ                      IRQ_IXP4XX_GPIO1
+#define GTWX5715_GPIO2_IRQ                      IRQ_IXP4XX_GPIO2
+#define GTWX5715_GPIO3_IRQ                      IRQ_IXP4XX_GPIO3
+#define GTWX5715_GPIO4_IRQ                      IRQ_IXP4XX_GPIO4
+#define GTWX5715_GPIO5_IRQ                      IRQ_IXP4XX_GPIO5
+#define GTWX5715_GPIO6_IRQ                      IRQ_IXP4XX_GPIO6
+#define GTWX5715_GPIO7_IRQ                      IRQ_IXP4XX_GPIO7
+#define GTWX5715_GPIO8_IRQ                      IRQ_IXP4XX_GPIO8
+#define GTWX5715_GPIO9_IRQ                      IRQ_IXP4XX_GPIO9
+#define GTWX5715_GPIO10_IRQ             IRQ_IXP4XX_GPIO10
+#define GTWX5715_GPIO11_IRQ             IRQ_IXP4XX_GPIO11
+#define GTWX5715_GPIO12_IRQ             IRQ_IXP4XX_GPIO12
+#define GTWX5715_GPIO13_IRQ             IRQ_IXP4XX_SW_INT1
+#define GTWX5715_GPIO14_IRQ             IRQ_IXP4XX_SW_INT2
+
+
+#define GTWX5715_FLASH_BASE     IXP4XX_EXP_BUS_CS0_BASE_PHYS
+#define GTWX5715_FLASH_SIZE     (0x00800000)
+
+/* PCI controller GPIO to IRQ pin mappings
+
+                        INTA    INTB
+SLOT 0  10              11
+SLOT 1  11              10
+
+*/
+
+#define GTWX5715_PCI_SLOT0_DEVID        0
+#define GTWX5715_PCI_SLOT0_INTA_GPIO    GTWX5715_GPIO10
+#define GTWX5715_PCI_SLOT0_INTB_GPIO    GTWX5715_GPIO11
+#define GTWX5715_PCI_SLOT0_INTA_IRQ     GTWX5715_GPIO10_IRQ
+#define GTWX5715_PCI_SLOT0_INTB_IRQ     GTWX5715_GPIO11_IRQ
+
+#define GTWX5715_PCI_SLOT1_DEVID        1
+#define GTWX5715_PCI_SLOT1_INTA_GPIO    GTWX5715_GPIO11
+#define GTWX5715_PCI_SLOT1_INTB_GPIO    GTWX5715_GPIO10
+#define GTWX5715_PCI_SLOT1_INTA_IRQ     GTWX5715_GPIO11_IRQ
+#define GTWX5715_PCI_SLOT1_INTB_IRQ     GTWX5715_GPIO10_IRQ
+
+#define GTWX5715_PCI_SLOT_COUNT                 2
+#define GTWX5715_PCI_INT_PIN_COUNT              2
+
+/*
+ * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
+ * and operate as an SPI type interface.  The details of the interface
+ * are available on Kendin/Micrel's web site.
+ */
+
+#define GTWX5715_KSSPI_SELECT   GTWX5715_GPIO5
+#define GTWX5715_KSSPI_TXD              GTWX5715_GPIO6
+#define GTWX5715_KSSPI_CLOCK    GTWX5715_GPIO7
+#define GTWX5715_KSSPI_RXD              GTWX5715_GPIO12
+
+/*
+ * The "reset" button is wired to GPIO 3.
+ * The GPIO is brought "low" when the button is pushed.
+ */
+
+#define GTWX5715_BUTTON_GPIO    GTWX5715_GPIO3
+#define GTWX5715_BUTTON_IRQ     GTWX5715_GPIO3_IRQ
+
+/*
+ *  Board Label      Front Label
+ *  LED1             Power
+ *  LED2             Wireless-G
+ *  LED3             not populated but could be
+ *  LED4             Internet
+ *  LED5 - LED8      Controlled by KS8995M Switch
+ *  LED9             DMZ
+ */
+
+#define GTWX5715_LED1_GPIO              GTWX5715_GPIO2
+#define GTWX5715_LED2_GPIO              GTWX5715_GPIO9
+#define GTWX5715_LED3_GPIO              GTWX5715_GPIO8
+#define GTWX5715_LED4_GPIO              GTWX5715_GPIO1
+#define GTWX5715_LED9_GPIO              GTWX5715_GPIO4
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
new file mode 100644
index 000000000000..4ac964b9078a
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -0,0 +1,48 @@
+/*
+ * include/asm-arm/arch-ixp4xx/hardware.h 
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+/*
+ * Hardware definitions for IXP4xx based systems
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#define __ASM_ARCH_HARDWARE_H__
+
+#define PCIBIOS_MIN_IO                  0x00001000
+#define PCIBIOS_MIN_MEM                 0x48000000
+
+/*
+ * We override the standard dma-mask routines for bouncing.
+ */
+#define HAVE_ARCH_PCI_SET_DMA_MASK
+
+#define pcibios_assign_all_busses()     1
+
+#if defined(CONFIG_CPU_IXP465) && !defined(__ASSEMBLY__)
+extern unsigned int processor_id;
+#define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200)
+#else
+#define cpu_is_ixp465() (0)
+#endif
+
+/* Register locations and bits */
+#include "ixp4xx-regs.h"
+
+/* Platform helper functions and definitions */
+#include "platform.h"
+
+/* Platform specific details */
+#include "ixdp425.h"
+#include "coyote.h"
+#include "prpmc1100.h"
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
new file mode 100644
index 000000000000..c27b9d3079a7
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -0,0 +1,388 @@
+/*
+ * linux/include/asm-arm/arch-ixp4xx/io.h
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright (C) 2002-2004  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <asm/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffff0000
+
+#define BIT(x)  ((1)<<(x))
+
+
+extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
+extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
+
+
+/*
+ * IXP4xx provides two methods of accessing PCI memory space:
+ *
+ * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
+ *    To access PCI via this space, we simply ioremap() the BAR
+ *    into the kernel and we can use the standard read[bwl]/write[bwl]
+ *    macros. This is the preffered method due to speed but it
+ *    limits the system to just 64MB of PCI memory. This can be 
+ *    problamatic if using video cards and other memory-heavy
+ *    targets.
+ *
+ * 2) If > 64MB of memory space is required, the IXP4xx can be configured
+ *    to use indirect registers to access PCI (as we do below for I/O
+ *    transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
+ *    of memory on the bus. The disadvantadge of this is that every 
+ *    PCI access requires three local register accesses plus a spinlock,
+ *    but in some cases the performance hit is acceptable. In addition,
+ *    you cannot mmap() PCI devices in this case.
+ *
+ */
+#ifndef CONFIG_IXP4XX_INDIRECT_PCI
+
+#define __mem_pci(a)            (a)
+
+#else
+
+#include <linux/mm.h>
+
+/*
+ * In the case of using indirect PCI, we simply return the actual PCI
+ * address and our read/write implementation use that to drive the 
+ * access registers. If something outside of PCI is ioremap'd, we
+ * fallback to the default.
+ */
+static inline void __iomem *
+__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned long align)
+{
+        extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
+        if((addr < 0x48000000) || (addr > 0x4fffffff))
+                return __ioremap(addr, size, flags, align);
+
+        return (void *)addr;
+}
+
+static inline void
+__ixp4xx_iounmap(void __iomem *addr)
+{
+        extern void __iounmap(void __iomem *addr);
+
+        if ((u32)addr >= VMALLOC_START)
+                __iounmap(addr);
+}
+
+#define __arch_ioremap(a, s, f, x)      __ixp4xx_ioremap(a, s, f, x)
+#define __arch_iounmap(a)               __ixp4xx_iounmap(a)
+
+#define writeb(p, v)                    __ixp4xx_writeb(p, v)
+#define writew(p, v)                    __ixp4xx_writew(p, v)
+#define writel(p, v)                    __ixp4xx_writel(p, v)
+
+#define writesb(p, v, l)                __ixp4xx_writesb(p, v, l)
+#define writesw(p, v, l)                __ixp4xx_writesw(p, v, l)
+#define writesl(p, v, l)                __ixp4xx_writesl(p, v, l)
+        
+#define readb(p)                        __ixp4xx_readb(p)
+#define readw(p)                        __ixp4xx_readw(p)
+#define readl(p)                        __ixp4xx_readl(p)
+        
+#define readsb(p, v, l)                 __ixp4xx_readsb(p, v, l)
+#define readsw(p, v, l)                 __ixp4xx_readsw(p, v, l)
+#define readsl(p, v, l)                 __ixp4xx_readsl(p, v, l)
+
+static inline void 
+__ixp4xx_writeb(u8 value, u32 addr)
+{
+        u32 n, byte_enables, data;
+
+        if (addr >= VMALLOC_START) {
+                __raw_writeb(value, addr);
+                return;
+        }
+
+        n = addr % 4;
+        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+        data = value << (8*n);
+        ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
+}
+
+static inline void
+__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
+{
+        while (count--)
+                writeb(*vaddr++, bus_addr);
+}
+
+static inline void 
+__ixp4xx_writew(u16 value, u32 addr)
+{
+        u32 n, byte_enables, data;
+
+        if (addr >= VMALLOC_START) {
+                __raw_writew(value, addr);
+                return;
+        }
+
+        n = addr % 4;
+        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+        data = value << (8*n);
+        ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
+}
+
+static inline void
+__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
+{
+        while (count--)
+                writew(*vaddr++, bus_addr);
+}
+
+static inline void 
+__ixp4xx_writel(u32 value, u32 addr)
+{
+        if (addr >= VMALLOC_START) {
+                __raw_writel(value, addr);
+                return;
+        }
+
+        ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
+}
+
+static inline void
+__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
+{
+        while (count--)
+                writel(*vaddr++, bus_addr);
+}
+
+static inline unsigned char 
+__ixp4xx_readb(u32 addr)
+{
+        u32 n, byte_enables, data;
+
+        if (addr >= VMALLOC_START)
+                return __raw_readb(addr);
+
+        n = addr % 4;
+        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
+                return 0xff;
+
+        return data >> (8*n);
+}
+
+static inline void
+__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = readb(bus_addr);
+}
+
+static inline unsigned short 
+__ixp4xx_readw(u32 addr)
+{
+        u32 n, byte_enables, data;
+
+        if (addr >= VMALLOC_START)
+                return __raw_readw(addr);
+
+        n = addr % 4;
+        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
+                return 0xffff;
+
+        return data>>(8*n);
+}
+
+static inline void 
+__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = readw(bus_addr);
+}
+
+static inline unsigned long 
+__ixp4xx_readl(u32 addr)
+{
+        u32 data;
+
+        if (addr >= VMALLOC_START)
+                return __raw_readl(addr);
+
+        if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
+                return 0xffffffff;
+
+        return data;
+}
+
+static inline void 
+__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = readl(bus_addr);
+}
+
+
+/*
+ * We can use the built-in functions b/c they end up calling writeb/readb
+ */
+#define memset_io(c,v,l)                _memset_io((c),(v),(l))
+#define memcpy_fromio(a,c,l)            _memcpy_fromio((a),(c),(l))
+#define memcpy_toio(c,a,l)              _memcpy_toio((c),(a),(l))
+
+#define eth_io_copy_and_sum(s,c,l,b) \
+                                eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+
+static inline int
+check_signature(unsigned long bus_addr, const unsigned char *signature,
+                int length)
+{
+        int retval = 0;
+        do {
+                if (readb(bus_addr) != *signature)
+                        goto out;
+                bus_addr++;
+                signature++;
+                length--;
+        } while (length);
+        retval = 1;
+out:
+        return retval;
+}
+
+#endif
+
+/*
+ * IXP4xx does not have a transparent cpu -> PCI I/O translation
+ * window.  Instead, it has a set of registers that must be tweaked
+ * with the proper byte lanes, command types, and address for the
+ * transaction.  This means that we need to override the default
+ * I/O functions.
+ */
+#define outb(p, v)                      __ixp4xx_outb(p, v)
+#define outw(p, v)                      __ixp4xx_outw(p, v)
+#define outl(p, v)                      __ixp4xx_outl(p, v)
+        
+#define outsb(p, v, l)                  __ixp4xx_outsb(p, v, l)
+#define outsw(p, v, l)                  __ixp4xx_outsw(p, v, l)
+#define outsl(p, v, l)                  __ixp4xx_outsl(p, v, l)
+
+#define inb(p)                          __ixp4xx_inb(p)
+#define inw(p)                          __ixp4xx_inw(p)
+#define inl(p)                          __ixp4xx_inl(p)
+
+#define insb(p, v, l)                   __ixp4xx_insb(p, v, l)
+#define insw(p, v, l)                   __ixp4xx_insw(p, v, l)
+#define insl(p, v, l)                   __ixp4xx_insl(p, v, l)
+
+
+static inline void 
+__ixp4xx_outb(u8 value, u32 addr)
+{
+        u32 n, byte_enables, data;
+        n = addr % 4;
+        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+        data = value << (8*n);
+        ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
+}
+
+static inline void 
+__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
+{
+        while (count--)
+                outb(*vaddr++, io_addr);
+}
+
+static inline void 
+__ixp4xx_outw(u16 value, u32 addr)
+{
+        u32 n, byte_enables, data;
+        n = addr % 4;
+        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+        data = value << (8*n);
+        ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
+}
+
+static inline void 
+__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
+{
+        while (count--)
+                outw(cpu_to_le16(*vaddr++), io_addr);
+}
+
+static inline void 
+__ixp4xx_outl(u32 value, u32 addr)
+{
+        ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
+}
+
+static inline void 
+__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
+{
+        while (count--)
+                outl(*vaddr++, io_addr);
+}
+
+static inline u8 
+__ixp4xx_inb(u32 addr)
+{
+        u32 n, byte_enables, data;
+        n = addr % 4;
+        byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
+        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
+                return 0xff;
+
+        return data >> (8*n);
+}
+
+static inline void 
+__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = inb(io_addr);
+}
+
+static inline u16 
+__ixp4xx_inw(u32 addr)
+{
+        u32 n, byte_enables, data;
+        n = addr % 4;
+        byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
+        if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
+                return 0xffff;
+
+        return data>>(8*n);
+}
+
+static inline void 
+__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = le16_to_cpu(inw(io_addr));
+}
+
+static inline u32 
+__ixp4xx_inl(u32 addr)
+{
+        u32 data;
+        if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
+                return 0xffffffff;
+
+        return data;
+}
+
+static inline void 
+__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
+{
+        while (count--)
+                *vaddr++ = inl(io_addr);
+}
+
+
+#endif  //  __ASM_ARM_ARCH_IO_H
+
diff --git a/include/asm-arm/arch-ixp4xx/irq.h b/include/asm-arm/arch-ixp4xx/irq.h
new file mode 100644
index 000000000000..87da70695f0a
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/irq.h
@@ -0,0 +1,13 @@
+/*
+ * irq.h 
+ *
+ *  Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#define fixup_irq(irq)  (irq)
+
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
new file mode 100644
index 000000000000..ca808281c7f9
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -0,0 +1,96 @@
+/*
+ * include/asm-arm/arch-ixp4xx/irqs.h 
+ *
+ * IRQ definitions for IXP4XX based systems
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ARCH_IXP4XX_IRQS_H_
+#define _ARCH_IXP4XX_IRQS_H_
+
+
+#define IRQ_IXP4XX_NPEA         0
+#define IRQ_IXP4XX_NPEB         1
+#define IRQ_IXP4XX_NPEC         2
+#define IRQ_IXP4XX_QM1          3
+#define IRQ_IXP4XX_QM2          4
+#define IRQ_IXP4XX_TIMER1       5
+#define IRQ_IXP4XX_GPIO0        6
+#define IRQ_IXP4XX_GPIO1        7
+#define IRQ_IXP4XX_PCI_INT      8
+#define IRQ_IXP4XX_PCI_DMA1     9
+#define IRQ_IXP4XX_PCI_DMA2     10
+#define IRQ_IXP4XX_TIMER2       11
+#define IRQ_IXP4XX_USB          12
+#define IRQ_IXP4XX_UART2        13
+#define IRQ_IXP4XX_TIMESTAMP    14
+#define IRQ_IXP4XX_UART1        15
+#define IRQ_IXP4XX_WDOG         16
+#define IRQ_IXP4XX_AHB_PMU      17
+#define IRQ_IXP4XX_XSCALE_PMU   18
+#define IRQ_IXP4XX_GPIO2        19
+#define IRQ_IXP4XX_GPIO3        20
+#define IRQ_IXP4XX_GPIO4        21
+#define IRQ_IXP4XX_GPIO5        22
+#define IRQ_IXP4XX_GPIO6        23
+#define IRQ_IXP4XX_GPIO7        24
+#define IRQ_IXP4XX_GPIO8        25
+#define IRQ_IXP4XX_GPIO9        26
+#define IRQ_IXP4XX_GPIO10       27
+#define IRQ_IXP4XX_GPIO11       28
+#define IRQ_IXP4XX_GPIO12       29
+#define IRQ_IXP4XX_SW_INT1      30
+#define IRQ_IXP4XX_SW_INT2      31
+#define IRQ_IXP4XX_USB_HOST     32
+#define IRQ_IXP4XX_I2C          33
+#define IRQ_IXP4XX_SSP          34
+#define IRQ_IXP4XX_TSYNC        35
+#define IRQ_IXP4XX_EAU_DONE     36
+#define IRQ_IXP4XX_SHA_DONE     37
+#define IRQ_IXP4XX_SWCP_PE      58
+#define IRQ_IXP4XX_QM_PE        60
+#define IRQ_IXP4XX_MCU_ECC      61
+#define IRQ_IXP4XX_EXP_PE       62
+
+/*
+ * Only first 32 sources are valid if running on IXP42x systems
+ */
+#ifndef CONFIG_CPU_IXP46X
+#define NR_IRQS                 32
+#else
+#define NR_IRQS                 64
+#endif
+
+#define XSCALE_PMU_IRQ          (IRQ_IXP4XX_XSCALE_PMU)
+
+/*
+ * IXDP425 board IRQs
+ */
+#define IRQ_IXDP425_PCI_INTA    IRQ_IXP4XX_GPIO11
+#define IRQ_IXDP425_PCI_INTB    IRQ_IXP4XX_GPIO10
+#define IRQ_IXDP425_PCI_INTC    IRQ_IXP4XX_GPIO9
+#define IRQ_IXDP425_PCI_INTD    IRQ_IXP4XX_GPIO8
+
+/*
+ * PrPMC1100 Board IRQs
+ */
+#define IRQ_PRPMC1100_PCI_INTA  IRQ_IXP4XX_GPIO11
+#define IRQ_PRPMC1100_PCI_INTB  IRQ_IXP4XX_GPIO10
+#define IRQ_PRPMC1100_PCI_INTC  IRQ_IXP4XX_GPIO9
+#define IRQ_PRPMC1100_PCI_INTD  IRQ_IXP4XX_GPIO8
+
+/*
+ * ADI Coyote Board IRQs
+ */
+#define IRQ_COYOTE_PCI_SLOT0    IRQ_IXP4XX_GPIO6
+#define IRQ_COYOTE_PCI_SLOT1    IRQ_IXP4XX_GPIO11
+#define IRQ_COYOTE_IDE          IRQ_IXP4XX_GPIO5
+
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h
new file mode 100644
index 000000000000..7d21bf941379
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/ixdp425.h
@@ -0,0 +1,38 @@
+/*
+ * include/asm-arm/arch-ixp4xx/ixdp425.h
+ *
+ * IXDP425 platform specific definitions
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista, Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+
+#define IXDP425_FLASH_BASE      IXP4XX_EXP_BUS_CS0_BASE_PHYS
+#define IXDP425_FLASH_SIZE      IXP4XX_EXP_BUS_CSX_REGION_SIZE
+
+#define IXDP425_SDA_PIN         7
+#define IXDP425_SCL_PIN         6
+
+/*
+ * IXDP425 PCI IRQs
+ */
+#define IXDP425_PCI_MAX_DEV     4
+#define IXDP425_PCI_IRQ_LINES   4
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define IXDP425_PCI_INTA_PIN    11
+#define IXDP425_PCI_INTB_PIN    10
+#define IXDP425_PCI_INTC_PIN    9
+#define IXDP425_PCI_INTD_PIN    8
+
+
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
new file mode 100644
index 000000000000..8eeb1db6309d
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -0,0 +1,591 @@
+/*
+ * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+ *
+ * Register definitions for IXP4xx chipset. This file contains 
+ * register location and bit definitions only. Platform specific 
+ * definitions and helper function declarations are in platform.h 
+ * and machine-name.h.
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+
+#ifndef _ASM_ARM_IXP4XX_H_
+#define _ASM_ARM_IXP4XX_H_
+
+/*
+ * IXP4xx Linux Memory Map:
+ *
+ * Phy          Size            Virt            Description
+ * =========================================================================
+ *
+ * 0x00000000   0x10000000(max) PAGE_OFFSET     System RAM
+ *
+ * 0x48000000   0x04000000      ioremap'd       PCI Memory Space
+ *
+ * 0x50000000   0x10000000      ioremap'd       EXP BUS
+ *
+ * 0x6000000    0x00004000      ioremap'd       QMgr
+ *
+ * 0xC0000000   0x00001000      0xffbfe000      PCI CFG 
+ *
+ * 0xC4000000   0x00001000      0xffbfd000      EXP CFG 
+ *
+ * 0xC8000000   0x0000C000      0xffbf2000      On-Chip Peripherals
+ */
+
+/*
+ * Queue Manager
+ */
+#define IXP4XX_QMGR_BASE_PHYS           (0x60000000)
+
+/*
+ * Expansion BUS Configuration registers
+ */
+#define IXP4XX_EXP_CFG_BASE_PHYS        (0xC4000000)
+#define IXP4XX_EXP_CFG_BASE_VIRT        (0xFFBFD000)
+#define IXP4XX_EXP_CFG_REGION_SIZE      (0x00001000)
+
+/*
+ * PCI Config registers
+ */
+#define IXP4XX_PCI_CFG_BASE_PHYS        (0xC0000000)
+#define IXP4XX_PCI_CFG_BASE_VIRT        (0xFFBFE000)
+#define IXP4XX_PCI_CFG_REGION_SIZE      (0x00001000)
+
+/*
+ * Peripheral space
+ */
+#define IXP4XX_PERIPHERAL_BASE_PHYS     (0xC8000000)
+#define IXP4XX_PERIPHERAL_BASE_VIRT     (0xFFBF2000)
+#define IXP4XX_PERIPHERAL_REGION_SIZE   (0x0000C000)
+
+#define IXP4XX_EXP_CS0_OFFSET   0x00
+#define IXP4XX_EXP_CS1_OFFSET   0x04
+#define IXP4XX_EXP_CS2_OFFSET   0x08
+#define IXP4XX_EXP_CS3_OFFSET   0x0C
+#define IXP4XX_EXP_CS4_OFFSET   0x10
+#define IXP4XX_EXP_CS5_OFFSET   0x14
+#define IXP4XX_EXP_CS6_OFFSET   0x18
+#define IXP4XX_EXP_CS7_OFFSET   0x1C
+#define IXP4XX_EXP_CFG0_OFFSET  0x20
+#define IXP4XX_EXP_CFG1_OFFSET  0x24
+#define IXP4XX_EXP_CFG2_OFFSET  0x28
+#define IXP4XX_EXP_CFG3_OFFSET  0x2C
+
+/*
+ * Expansion Bus Controller registers.
+ */
+#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
+
+#define IXP4XX_EXP_CS0      IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
+#define IXP4XX_EXP_CS1      IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
+#define IXP4XX_EXP_CS2      IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET) 
+#define IXP4XX_EXP_CS3      IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
+#define IXP4XX_EXP_CS4      IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
+#define IXP4XX_EXP_CS5      IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
+#define IXP4XX_EXP_CS6      IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)     
+#define IXP4XX_EXP_CS7      IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
+
+#define IXP4XX_EXP_CFG0     IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET) 
+#define IXP4XX_EXP_CFG1     IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET) 
+#define IXP4XX_EXP_CFG2     IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET) 
+#define IXP4XX_EXP_CFG3     IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
+
+
+/*
+ * Peripheral Space Register Region Base Addresses
+ */
+#define IXP4XX_UART1_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
+#define IXP4XX_UART2_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
+#define IXP4XX_PMU_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
+#define IXP4XX_INTC_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
+#define IXP4XX_GPIO_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
+#define IXP4XX_TIMER_BASE_PHYS  (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
+#define IXP4XX_EthA_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
+#define IXP4XX_EthB_BASE_PHYS   (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
+#define IXP4XX_USB_BASE_PHYS    (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
+
+#define IXP4XX_UART1_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
+#define IXP4XX_UART2_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
+#define IXP4XX_PMU_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
+#define IXP4XX_INTC_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
+#define IXP4XX_GPIO_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
+#define IXP4XX_TIMER_BASE_VIRT  (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
+#define IXP4XX_EthA_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
+#define IXP4XX_EthB_BASE_VIRT   (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
+#define IXP4XX_USB_BASE_VIRT    (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
+
+/*
+ * Constants to make it easy to access  Interrupt Controller registers
+ */
+#define IXP4XX_ICPR_OFFSET      0x00 /* Interrupt Status */
+#define IXP4XX_ICMR_OFFSET      0x04 /* Interrupt Enable */
+#define IXP4XX_ICLR_OFFSET      0x08 /* Interrupt IRQ/FIQ Select */
+#define IXP4XX_ICIP_OFFSET      0x0C /* IRQ Status */
+#define IXP4XX_ICFP_OFFSET      0x10 /* FIQ Status */
+#define IXP4XX_ICHR_OFFSET      0x14 /* Interrupt Priority */
+#define IXP4XX_ICIH_OFFSET      0x18 /* IRQ Highest Pri Int */
+#define IXP4XX_ICFH_OFFSET      0x1C /* FIQ Highest Pri Int */
+
+/*
+ * IXP465-only
+ */
+#define IXP4XX_ICPR2_OFFSET     0x20 /* Interrupt Status 2 */
+#define IXP4XX_ICMR2_OFFSET     0x24 /* Interrupt Enable 2 */
+#define IXP4XX_ICLR2_OFFSET     0x28 /* Interrupt IRQ/FIQ Select 2 */
+#define IXP4XX_ICIP2_OFFSET     0x2C /* IRQ Status */
+#define IXP4XX_ICFP2_OFFSET     0x30 /* FIQ Status */
+#define IXP4XX_ICEEN_OFFSET     0x34 /* Error High Pri Enable */
+
+
+/*
+ * Interrupt Controller Register Definitions.
+ */
+
+#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
+
+#define IXP4XX_ICPR     IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
+#define IXP4XX_ICMR     IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
+#define IXP4XX_ICLR     IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
+#define IXP4XX_ICIP     IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
+#define IXP4XX_ICFP     IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
+#define IXP4XX_ICHR     IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
+#define IXP4XX_ICIH     IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET) 
+#define IXP4XX_ICFH     IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
+#define IXP4XX_ICPR2    IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
+#define IXP4XX_ICMR2    IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
+#define IXP4XX_ICLR2    IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
+#define IXP4XX_ICIP2    IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
+#define IXP4XX_ICFP2    IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
+#define IXP4XX_ICEEN    IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
+                                                                                
+/*
+ * Constants to make it easy to access GPIO registers
+ */
+#define IXP4XX_GPIO_GPOUTR_OFFSET       0x00
+#define IXP4XX_GPIO_GPOER_OFFSET        0x04
+#define IXP4XX_GPIO_GPINR_OFFSET        0x08
+#define IXP4XX_GPIO_GPISR_OFFSET        0x0C
+#define IXP4XX_GPIO_GPIT1R_OFFSET       0x10
+#define IXP4XX_GPIO_GPIT2R_OFFSET       0x14
+#define IXP4XX_GPIO_GPCLKR_OFFSET       0x18
+#define IXP4XX_GPIO_GPDBSELR_OFFSET     0x1C
+
+/* 
+ * GPIO Register Definitions.
+ * [Only perform 32bit reads/writes]
+ */
+#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
+
+#define IXP4XX_GPIO_GPOUTR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
+#define IXP4XX_GPIO_GPOER       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
+#define IXP4XX_GPIO_GPINR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
+#define IXP4XX_GPIO_GPISR       IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
+#define IXP4XX_GPIO_GPIT1R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
+#define IXP4XX_GPIO_GPIT2R      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
+#define IXP4XX_GPIO_GPCLKR      IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
+#define IXP4XX_GPIO_GPDBSELR    IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
+
+/*
+ * GPIO register bit definitions
+ */
+
+/* Interrupt styles
+ */
+#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH   0x0
+#define IXP4XX_GPIO_STYLE_ACTIVE_LOW    0x1
+#define IXP4XX_GPIO_STYLE_RISING_EDGE   0x2
+#define IXP4XX_GPIO_STYLE_FALLING_EDGE  0x3
+#define IXP4XX_GPIO_STYLE_TRANSITIONAL  0x4
+
+/* 
+ * Mask used to clear interrupt styles 
+ */
+#define IXP4XX_GPIO_STYLE_CLEAR         0x7
+#define IXP4XX_GPIO_STYLE_SIZE          3
+
+/*
+ * Constants to make it easy to access Timer Control/Status registers
+ */
+#define IXP4XX_OSTS_OFFSET      0x00  /* Continious TimeStamp */
+#define IXP4XX_OST1_OFFSET      0x04  /* Timer 1 Timestamp */
+#define IXP4XX_OSRT1_OFFSET     0x08  /* Timer 1 Reload */
+#define IXP4XX_OST2_OFFSET      0x0C  /* Timer 2 Timestamp */
+#define IXP4XX_OSRT2_OFFSET     0x10  /* Timer 2 Reload */
+#define IXP4XX_OSWT_OFFSET      0x14  /* Watchdog Timer */
+#define IXP4XX_OSWE_OFFSET      0x18  /* Watchdog Enable */
+#define IXP4XX_OSWK_OFFSET      0x1C  /* Watchdog Key */
+#define IXP4XX_OSST_OFFSET      0x20  /* Timer Status */
+
+/*
+ * Operating System Timer Register Definitions.
+ */
+
+#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
+
+#define IXP4XX_OSTS     IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
+#define IXP4XX_OST1     IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
+#define IXP4XX_OSRT1    IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
+#define IXP4XX_OST2     IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
+#define IXP4XX_OSRT2    IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
+#define IXP4XX_OSWT     IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
+#define IXP4XX_OSWE     IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
+#define IXP4XX_OSWK     IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
+#define IXP4XX_OSST     IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
+
+/*
+ * Timer register values and bit definitions 
+ */
+#define IXP4XX_OST_ENABLE               0x00000001
+#define IXP4XX_OST_ONE_SHOT             0x00000002
+/* Low order bits of reload value ignored */
+#define IXP4XX_OST_RELOAD_MASK          0x00000003
+#define IXP4XX_OST_DISABLED             0x00000000
+#define IXP4XX_OSST_TIMER_1_PEND        0x00000001
+#define IXP4XX_OSST_TIMER_2_PEND        0x00000002
+#define IXP4XX_OSST_TIMER_TS_PEND       0x00000004
+#define IXP4XX_OSST_TIMER_WDOG_PEND     0x00000008
+#define IXP4XX_OSST_TIMER_WARM_RESET    0x00000010
+
+#define IXP4XX_WDT_KEY                  0x0000482E
+
+#define IXP4XX_WDT_RESET_ENABLE         0x00000001
+#define IXP4XX_WDT_IRQ_ENABLE           0x00000002
+#define IXP4XX_WDT_COUNT_ENABLE         0x00000004
+
+
+/*
+ * Constants to make it easy to access PCI Control/Status registers
+ */
+#define PCI_NP_AD_OFFSET            0x00
+#define PCI_NP_CBE_OFFSET           0x04
+#define PCI_NP_WDATA_OFFSET         0x08
+#define PCI_NP_RDATA_OFFSET         0x0c
+#define PCI_CRP_AD_CBE_OFFSET       0x10
+#define PCI_CRP_WDATA_OFFSET        0x14
+#define PCI_CRP_RDATA_OFFSET        0x18
+#define PCI_CSR_OFFSET              0x1c
+#define PCI_ISR_OFFSET              0x20
+#define PCI_INTEN_OFFSET            0x24
+#define PCI_DMACTRL_OFFSET          0x28
+#define PCI_AHBMEMBASE_OFFSET       0x2c
+#define PCI_AHBIOBASE_OFFSET        0x30
+#define PCI_PCIMEMBASE_OFFSET       0x34
+#define PCI_AHBDOORBELL_OFFSET      0x38
+#define PCI_PCIDOORBELL_OFFSET      0x3C
+#define PCI_ATPDMA0_AHBADDR_OFFSET  0x40
+#define PCI_ATPDMA0_PCIADDR_OFFSET  0x44
+#define PCI_ATPDMA0_LENADDR_OFFSET  0x48
+#define PCI_ATPDMA1_AHBADDR_OFFSET  0x4C
+#define PCI_ATPDMA1_PCIADDR_OFFSET  0x50
+#define PCI_ATPDMA1_LENADDR_OFFSET      0x54
+
+/*
+ * PCI Control/Status Registers
+ */
+#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
+
+#define PCI_NP_AD               IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
+#define PCI_NP_CBE              IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
+#define PCI_NP_WDATA            IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
+#define PCI_NP_RDATA            IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
+#define PCI_CRP_AD_CBE          IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
+#define PCI_CRP_WDATA           IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
+#define PCI_CRP_RDATA           IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
+#define PCI_CSR                 IXP4XX_PCI_CSR(PCI_CSR_OFFSET) 
+#define PCI_ISR                 IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
+#define PCI_INTEN               IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
+#define PCI_DMACTRL             IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
+#define PCI_AHBMEMBASE          IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
+#define PCI_AHBIOBASE           IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
+#define PCI_PCIMEMBASE          IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
+#define PCI_AHBDOORBELL         IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
+#define PCI_PCIDOORBELL         IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
+#define PCI_ATPDMA0_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
+#define PCI_ATPDMA0_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
+#define PCI_ATPDMA0_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
+#define PCI_ATPDMA1_AHBADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
+#define PCI_ATPDMA1_PCIADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
+#define PCI_ATPDMA1_LENADDR     IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
+
+/*
+ * PCI register values and bit definitions 
+ */
+
+/* CSR bit definitions */
+#define PCI_CSR_HOST            0x00000001
+#define PCI_CSR_ARBEN           0x00000002
+#define PCI_CSR_ADS             0x00000004
+#define PCI_CSR_PDS             0x00000008
+#define PCI_CSR_ABE             0x00000010
+#define PCI_CSR_DBT             0x00000020
+#define PCI_CSR_ASE             0x00000100
+#define PCI_CSR_IC              0x00008000
+
+/* ISR (Interrupt status) Register bit definitions */
+#define PCI_ISR_PSE             0x00000001
+#define PCI_ISR_PFE             0x00000002
+#define PCI_ISR_PPE             0x00000004
+#define PCI_ISR_AHBE            0x00000008
+#define PCI_ISR_APDC            0x00000010
+#define PCI_ISR_PADC            0x00000020
+#define PCI_ISR_ADB             0x00000040
+#define PCI_ISR_PDB             0x00000080
+
+/* INTEN (Interrupt Enable) Register bit definitions */
+#define PCI_INTEN_PSE           0x00000001
+#define PCI_INTEN_PFE           0x00000002
+#define PCI_INTEN_PPE           0x00000004
+#define PCI_INTEN_AHBE          0x00000008
+#define PCI_INTEN_APDC          0x00000010
+#define PCI_INTEN_PADC          0x00000020
+#define PCI_INTEN_ADB           0x00000040
+#define PCI_INTEN_PDB           0x00000080
+
+/*
+ * Shift value for byte enable on NP cmd/byte enable register
+ */
+#define IXP4XX_PCI_NP_CBE_BESL          4
+
+/*
+ * PCI commands supported by NP access unit
+ */
+#define NP_CMD_IOREAD                   0x2
+#define NP_CMD_IOWRITE                  0x3
+#define NP_CMD_CONFIGREAD               0xa
+#define NP_CMD_CONFIGWRITE              0xb
+#define NP_CMD_MEMREAD                  0x6
+#define NP_CMD_MEMWRITE                 0x7
+
+/*
+ * Constants for CRP access into local config space
+ */
+#define CRP_AD_CBE_BESL         20
+#define CRP_AD_CBE_WRITE        0x00010000
+
+
+/*
+ * USB Device Controller
+ *
+ * These are used by the USB gadget driver, so they don't follow the
+ * IXP4XX_ naming convetions.
+ *
+ */
+# define IXP4XX_USB_REG(x)       (*((volatile u32 *)(x)))
+
+/* UDC Undocumented - Reserved1 */
+#define UDC_RES1        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)  
+/* UDC Undocumented - Reserved2 */
+#define UDC_RES2        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)  
+/* UDC Undocumented - Reserved3 */
+#define UDC_RES3        IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)  
+/* UDC Control Register */
+#define UDCCR           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)  
+/* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)  
+/* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS1          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)  
+/* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS2          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)  
+/* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS3          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)  
+/* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS4          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)  
+/* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS5          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)  
+/* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS6          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)  
+/* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS7          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)  
+/* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS8          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)  
+/* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS9          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)  
+/* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS10         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)  
+/* UDC Endpoint 11 (IN) Control/Status Register */
+#define UDCCS11         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)  
+/* UDC Endpoint 12 (OUT) Control/Status Register */
+#define UDCCS12         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)  
+/* UDC Endpoint 13 (IN) Control/Status Register */
+#define UDCCS13         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)  
+/* UDC Endpoint 14 (OUT) Control/Status Register */
+#define UDCCS14         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)  
+/* UDC Endpoint 15 (Interrupt) Control/Status Register */
+#define UDCCS15         IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)  
+/* UDC Frame Number Register High */
+#define UFNRH           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)  
+/* UDC Frame Number Register Low */
+#define UFNRL           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)  
+/* UDC Byte Count Reg 2 */
+#define UBCR2           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)  
+/* UDC Byte Count Reg 4 */
+#define UBCR4           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)  
+/* UDC Byte Count Reg 7 */
+#define UBCR7           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)  
+/* UDC Byte Count Reg 9 */
+#define UBCR9           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)  
+/* UDC Byte Count Reg 12 */
+#define UBCR12          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)  
+/* UDC Byte Count Reg 14 */
+#define UBCR14          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)  
+/* UDC Endpoint 0 Data Register */
+#define UDDR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)  
+/* UDC Endpoint 1 Data Register */
+#define UDDR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)  
+/* UDC Endpoint 2 Data Register */
+#define UDDR2           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)  
+/* UDC Endpoint 3 Data Register */
+#define UDDR3           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)  
+/* UDC Endpoint 4 Data Register */
+#define UDDR4           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)  
+/* UDC Endpoint 5 Data Register */
+#define UDDR5           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)  
+/* UDC Endpoint 6 Data Register */
+#define UDDR6           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)  
+/* UDC Endpoint 7 Data Register */
+#define UDDR7           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)  
+/* UDC Endpoint 8 Data Register */
+#define UDDR8           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)  
+/* UDC Endpoint 9 Data Register */
+#define UDDR9           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)  
+/* UDC Endpoint 10 Data Register */
+#define UDDR10          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)  
+/* UDC Endpoint 11 Data Register */
+#define UDDR11          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)  
+/* UDC Endpoint 12 Data Register */
+#define UDDR12          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)  
+/* UDC Endpoint 13 Data Register */
+#define UDDR13          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)  
+/* UDC Endpoint 14 Data Register */
+#define UDDR14          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)  
+/* UDC Endpoint 15 Data Register */
+#define UDDR15          IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)  
+/* UDC Interrupt Control Register 0 */
+#define UICR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)  
+/* UDC Interrupt Control Register 1 */
+#define UICR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)  
+/* UDC Status Interrupt Register 0 */
+#define USIR0           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)  
+/* UDC Status Interrupt Register 1 */
+#define USIR1           IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)  
+
+#define UDCCR_UDE       (1 << 0)        /* UDC enable */
+#define UDCCR_UDA       (1 << 1)        /* UDC active */
+#define UDCCR_RSM       (1 << 2)        /* Device resume */
+#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
+#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
+#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
+#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
+#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
+
+#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
+#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
+#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
+#define UDCCS0_SST      (1 << 4)        /* Sent stall */
+#define UDCCS0_FST      (1 << 5)        /* Force stall */
+#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
+#define UDCCS0_SA       (1 << 7)        /* Setup active */
+
+#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
+
+#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
+
+#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
+
+#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_IO_ROF    (1 << 3)        /* Receive overflow */
+#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
+
+#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
+#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
+#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
+#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
+
+#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
+#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
+#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
+#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
+#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
+#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
+#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
+#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
+
+#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
+#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
+#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
+#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
+#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
+#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
+#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
+#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
+
+#define USIR0_IR0       (1 << 0)        /* Interrup request ep 0 */
+#define USIR0_IR1       (1 << 1)        /* Interrup request ep 1 */
+#define USIR0_IR2       (1 << 2)        /* Interrup request ep 2 */
+#define USIR0_IR3       (1 << 3)        /* Interrup request ep 3 */
+#define USIR0_IR4       (1 << 4)        /* Interrup request ep 4 */
+#define USIR0_IR5       (1 << 5)        /* Interrup request ep 5 */
+#define USIR0_IR6       (1 << 6)        /* Interrup request ep 6 */
+#define USIR0_IR7       (1 << 7)        /* Interrup request ep 7 */
+
+#define USIR1_IR8       (1 << 0)        /* Interrup request ep 8 */
+#define USIR1_IR9       (1 << 1)        /* Interrup request ep 9 */
+#define USIR1_IR10      (1 << 2)        /* Interrup request ep 10 */
+#define USIR1_IR11      (1 << 3)        /* Interrup request ep 11 */
+#define USIR1_IR12      (1 << 4)        /* Interrup request ep 12 */
+#define USIR1_IR13      (1 << 5)        /* Interrup request ep 13 */
+#define USIR1_IR14      (1 << 6)        /* Interrup request ep 14 */
+#define USIR1_IR15      (1 << 7)        /* Interrup request ep 15 */
+
+#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
+
+#ifndef __ASSEMBLY__
+static inline int cpu_is_ixp46x(void)
+{
+#ifdef CONFIG_CPU_IXP46X
+        unsigned int processor_id;
+
+        asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
+
+        if ((processor_id & 0xffffff00) == 0x69054200)
+                return 1;
+#endif
+        return 0;
+}
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h
new file mode 100644
index 000000000000..d348548b592b
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/memory.h
@@ -0,0 +1,61 @@
+/*
+ * linux/include/asm-arm/arch-ixp4xx/memory.h
+ *
+ * Copyright (c) 2001-2004 MontaVista Software, Inc.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/sizes.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x00000000UL)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Only first 64MB of memory can be accessed via PCI.
+ * We use GFP_DMA to allocate safe buffers to do map/unmap.
+ * This is really ugly and we need a better way of specifying
+ * DMA-capable regions of memory.
+ */
+static inline void __arch_adjust_zones(int node, unsigned long *zone_size, 
+        unsigned long *zhole_size) 
+{
+        unsigned int sz = SZ_64M >> PAGE_SHIFT;
+
+        /*
+         * Only adjust if > 64M on current system
+         */
+        if (node || (zone_size[0] <= sz))
+                return;
+
+        zone_size[1] = zone_size[0] - sz;
+        zone_size[0] = sz;
+        zhole_size[1] = zhole_size[0];
+        zhole_size[0] = 0;
+}
+
+#define arch_adjust_zones(node, size, holes) \
+        __arch_adjust_zones(node, size, holes)
+
+#define ISA_DMA_THRESHOLD (SZ_64M - 1)
+
+#endif
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ *
+ * These are dummies for now.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/param.h b/include/asm-arm/arch-ixp4xx/param.h
new file mode 100644
index 000000000000..8a757125e5e7
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/param.h
@@ -0,0 +1,3 @@
+/*
+ * linux/include/asm-arm/arch-ixp4xx/param.h
+ */
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
new file mode 100644
index 000000000000..3a626c03ea26
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -0,0 +1,126 @@
+/*
+ * include/asm-arm/arch-ixp4xx/platform.h
+ *
+ * Constants and functions that are useful to IXP4xx platform-specific code
+ * and device drivers.
+ *
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+
+#ifndef __ASSEMBLY__
+
+#include <asm/types.h>
+
+#ifndef __ARMEB__
+#define REG_OFFSET      0
+#else
+#define REG_OFFSET      3
+#endif
+
+/*
+ * Expansion bus memory regions
+ */
+#define IXP4XX_EXP_BUS_BASE_PHYS        (0x50000000)
+
+#define IXP4XX_EXP_BUS_CSX_REGION_SIZE  (0x01000000)
+
+#define IXP4XX_EXP_BUS_CS0_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x00000000)
+#define IXP4XX_EXP_BUS_CS1_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x01000000)
+#define IXP4XX_EXP_BUS_CS2_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x02000000)
+#define IXP4XX_EXP_BUS_CS3_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x03000000)
+#define IXP4XX_EXP_BUS_CS4_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x04000000)
+#define IXP4XX_EXP_BUS_CS5_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x05000000)
+#define IXP4XX_EXP_BUS_CS6_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x06000000)
+#define IXP4XX_EXP_BUS_CS7_BASE_PHYS    (IXP4XX_EXP_BUS_BASE_PHYS + 0x07000000)
+
+#define IXP4XX_FLASH_WRITABLE   (0x2)
+#define IXP4XX_FLASH_DEFAULT    (0xbcd23c40)
+#define IXP4XX_FLASH_WRITE      (0xbcd23c42)
+
+/*
+ * Clock Speed Definitions.
+ */
+#define IXP4XX_PERIPHERAL_BUS_CLOCK     (66) /* 66Mhzi APB BUS   */ 
+#define IXP4XX_UART_XTAL                14745600
+
+/*
+ * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
+ * used to 
+ * Used as platform_data to provide GPIO pin information to the ixp42x
+ * I2C driver.
+ */
+struct ixp4xx_i2c_pins {
+        unsigned long sda_pin;
+        unsigned long scl_pin;
+};
+
+
+struct sys_timer;
+
+/*
+ * Functions used by platform-level setup code
+ */
+extern void ixp4xx_map_io(void);
+extern void ixp4xx_init_irq(void);
+extern void ixp4xx_sys_init(void);
+extern struct sys_timer ixp4xx_timer;
+extern void ixp4xx_pci_preinit(void);
+struct pci_sys_data;
+extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
+extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
+
+/*
+ * GPIO-functions
+ */
+/*
+ * The following converted to the real HW bits the gpio_line_config
+ */
+/* GPIO pin types */
+#define IXP4XX_GPIO_OUT                 0x1
+#define IXP4XX_GPIO_IN                  0x2
+
+#define IXP4XX_GPIO_INTSTYLE_MASK       0x7C  /* Bits [6:2] define interrupt style */
+
+/* 
+ * GPIO interrupt types.
+ */
+#define IXP4XX_GPIO_ACTIVE_HIGH         0x4 /* Default */
+#define IXP4XX_GPIO_ACTIVE_LOW          0x8
+#define IXP4XX_GPIO_RISING_EDGE         0x10
+#define IXP4XX_GPIO_FALLING_EDGE        0x20
+#define IXP4XX_GPIO_TRANSITIONAL        0x40
+
+/* GPIO signal types */
+#define IXP4XX_GPIO_LOW                 0
+#define IXP4XX_GPIO_HIGH                1
+
+/* GPIO Clocks */
+#define IXP4XX_GPIO_CLK_0               14
+#define IXP4XX_GPIO_CLK_1               15
+
+extern void gpio_line_config(u8 line, u32 style);
+
+static inline void gpio_line_get(u8 line, int *value)
+{
+        *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
+}
+
+static inline void gpio_line_set(u8 line, int value)
+{
+        if (value == IXP4XX_GPIO_HIGH)
+            *IXP4XX_GPIO_GPOUTR |= (1 << line);
+        else if (value == IXP4XX_GPIO_LOW)
+            *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
+}
+
+static inline void gpio_line_isr_clear(u8 line)
+{
+        *IXP4XX_GPIO_GPISR = (1 << line);
+}
+
+#endif // __ASSEMBLY__
+
diff --git a/include/asm-arm/arch-ixp4xx/prpmc1100.h b/include/asm-arm/arch-ixp4xx/prpmc1100.h
new file mode 100644
index 000000000000..e2532ab7f48f
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/prpmc1100.h
@@ -0,0 +1,33 @@
+/*
+ * include/asm-arm/arch-ixp4xx/prpmc1100.h
+ *
+ * Motorolla PrPMC1100 platform specific definitions
+ *
+ * Author: Deepak Saxena <dsaxena@plexity.net>
+ *
+ * Copyright 2004 (c) MontaVista, Software, Inc. 
+ * 
+ * This file is licensed under  the terms of the GNU General Public 
+ * License version 2. This program is licensed "as is" without any 
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+
+#define PRPMC1100_FLASH_BASE    IXP4XX_EXP_BUS_CS0_BASE_PHYS
+#define PRPMC1100_FLASH_SIZE    IXP4XX_EXP_BUS_CSX_REGION_SIZE
+
+#define PRPMC1100_PCI_MIN_DEVID 10
+#define PRPMC1100_PCI_MAX_DEVID 16
+#define PRPMC1100_PCI_IRQ_LINES 4
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define PRPMC1100_PCI_INTA_PIN  11
+#define PRPMC1100_PCI_INTB_PIN  10
+#define PRPMC1100_PCI_INTC_PIN  9
+#define PRPMC1100_PCI_INTD_PIN  8
+
+
diff --git a/include/asm-arm/arch-ixp4xx/system.h b/include/asm-arm/arch-ixp4xx/system.h
new file mode 100644
index 000000000000..73589aad8dd6
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/system.h
@@ -0,0 +1,42 @@
+/*
+ * include/asm-arm/arch-ixp4x//system.h 
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/hardware.h>
+
+static inline void arch_idle(void)
+{
+#if 0
+        if (!hlt_counter)
+                cpu_do_idle(0);
+#endif
+}
+
+
+static inline void arch_reset(char mode)
+{
+        if ( 1 && mode == 's') {
+                /* Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                /* Use on-chip reset capability */
+
+                /* set the "key" register to enable access to
+                 * "timer" and "enable" registers
+                 */
+                *IXP4XX_OSWK = IXP4XX_WDT_KEY;
+
+                /* write 0 to the timer register for an immediate reset */
+                *IXP4XX_OSWT = 0;
+
+                *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
+        }
+}
+
diff --git a/include/asm-arm/arch-ixp4xx/timex.h b/include/asm-arm/arch-ixp4xx/timex.h
new file mode 100644
index 000000000000..38c9d77d3727
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/timex.h
@@ -0,0 +1,13 @@
+/*
+ * linux/include/asm-arm/arch-ixp4xx/timex.h
+ * 
+ */
+
+#include <asm/hardware.h>
+
+/*
+ * We use IXP425 General purpose timer for our timer needs, it runs at 
+ * 66.66... MHz
+ */
+#define CLOCK_TICK_RATE (66666666)
+
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
new file mode 100644
index 000000000000..960c35810a22
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
@@ -0,0 +1,64 @@
+/*
+ * include/asm-arm/arch-ixp4xx/uncompress.h 
+ *
+ * Copyright (C) 2002 Intel Corporation.
+ * Copyright (C) 2003-2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef _ARCH_UNCOMPRESS_H_
+#define _ARCH_UNCOMPRESS_H_
+
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+#include <linux/serial_reg.h>
+
+#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
+
+static volatile u32* uart_base;
+
+static __inline__ void putc(char c)
+{
+        /* Check THRE and TEMT bits before we transmit the character.
+         */
+        while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE); 
+        *uart_base = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s)
+        {
+                putc(*s);
+                if (*s == '\n')
+                        putc('\r');
+                s++;
+        }
+}
+
+static __inline__ void __arch_decomp_setup(unsigned long arch_id)
+{
+        /*
+         * Coyote and gtwx5715 only have UART2 connected
+         */
+        if (machine_is_adi_coyote() || machine_is_gtwx5715())
+                uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
+        else
+                uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
+}
+
+/*
+ * arch_id is a variable in decompress_kernel()
+ */
+#define arch_decomp_setup()     __arch_decomp_setup(arch_id)
+
+#define arch_decomp_wdog()
+
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/vmalloc.h b/include/asm-arm/arch-ixp4xx/vmalloc.h
new file mode 100644
index 000000000000..da46e560ad6f
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/vmalloc.h
@@ -0,0 +1,17 @@
+/*
+ * linux/include/asm-arm/arch-ixp4xx/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (0xFF000000)
+
diff --git a/include/asm-arm/arch-l7200/aux_reg.h b/include/asm-arm/arch-l7200/aux_reg.h
new file mode 100644
index 000000000000..762cbc76c501
--- /dev/null
+++ b/include/asm-arm/arch-l7200/aux_reg.h
@@ -0,0 +1,28 @@
+/*
+ * linux/include/asm-arm/arch-l7200/aux_reg.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   08-02-2000 SJH     Created file
+ */
+#ifndef _ASM_ARCH_AUXREG_H
+#define _ASM_ARCH_AUXREG_H
+
+#include <asm/arch/hardware.h>
+
+#define l7200aux_reg    *((volatile unsigned int *) (AUX_BASE))
+
+/*
+ * Auxillary register values
+ */
+#define AUX_CLEAR               0x00000000
+#define AUX_DIAG_LED_ON         0x00000002
+#define AUX_RTS_UART1           0x00000004
+#define AUX_DTR_UART1           0x00000008
+#define AUX_KBD_COLUMN_12_HIGH  0x00000010
+#define AUX_KBD_COLUMN_12_OFF   0x00000020
+#define AUX_KBD_COLUMN_13_HIGH  0x00000040
+#define AUX_KBD_COLUMN_13_OFF   0x00000080
+
+#endif
diff --git a/include/asm-arm/arch-l7200/debug-macro.S b/include/asm-arm/arch-l7200/debug-macro.S
new file mode 100644
index 000000000000..846473318e8b
--- /dev/null
+++ b/include/asm-arm/arch-l7200/debug-macro.S
@@ -0,0 +1,40 @@
+/* linux/include/asm-arm/arch-l7200/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .equ    io_virt, IO_BASE
+                .equ    io_phys, IO_START
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #io_phys           @ physical base address
+                movne   \rx, #io_virt           @ virtual address
+                add     \rx, \rx, #0x00044000   @ UART1
+@               add     \rx, \rx, #0x00045000   @ UART2
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0x0]        @ UARTDR
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-l7200/dma.h b/include/asm-arm/arch-l7200/dma.h
new file mode 100644
index 000000000000..6595b386cfc9
--- /dev/null
+++ b/include/asm-arm/arch-l7200/dma.h
@@ -0,0 +1,24 @@
+/*
+ * linux/include/asm-arm/arch-l7200/dma.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  08-29-2000  SJH     Created
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/* DMA is not yet implemented! It should be the same as acorn, copy over.. */
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS         0xd0000000
+#define MAX_DMA_CHANNELS        0
+
+#define DMA_S0                  0
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-l7200/entry-macro.S b/include/asm-arm/arch-l7200/entry-macro.S
new file mode 100644
index 000000000000..8b6342dc4be2
--- /dev/null
+++ b/include/asm-arm/arch-l7200/entry-macro.S
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-l7200/entry-macro.S
+ *
+ * Low-level IRQ helper macros for L7200-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <asm/hardware.h>
+
+                .equ    irq_base_addr,  IO_BASE_2
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \irqstat, #irq_base_addr                @ Virt addr IRQ regs
+                add     \irqstat, \irqstat, #0x00001000         @ Status reg
+                ldr     \irqstat, [\irqstat, #0]                @ get interrupts
+                mov     \irqnr, #0
+1001:           tst     \irqstat, #1
+                addeq   \irqnr, \irqnr, #1
+                moveq   \irqstat, \irqstat, lsr #1
+                tsteq   \irqnr, #32
+                beq     1001b
+                teq     \irqnr, #32
+                .endm
+
diff --git a/include/asm-arm/arch-l7200/gp_timers.h b/include/asm-arm/arch-l7200/gp_timers.h
new file mode 100644
index 000000000000..6f20962df248
--- /dev/null
+++ b/include/asm-arm/arch-l7200/gp_timers.h
@@ -0,0 +1,42 @@
+/*
+ * linux/include/asm-arm/arch-l7200/gp_timers.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   07-28-2000 SJH     Created file
+ *   08-02-2000 SJH     Used structure for registers
+ */
+#ifndef _ASM_ARCH_GPTIMERS_H
+#define _ASM_ARCH_GPTIMERS_H
+
+#include <asm/arch/hardware.h>
+
+/*
+ * Layout of L7200 general purpose timer registers
+ */
+struct GPT_Regs {
+        unsigned int TIMERLOAD;
+        unsigned int TIMERVALUE;
+        unsigned int TIMERCONTROL;
+        unsigned int TIMERCLEAR;
+};
+
+#define GPT_BASE                (IO_BASE_2 + 0x3000)
+#define l7200_timer1_regs       ((volatile struct GPT_Regs *) (GPT_BASE))
+#define l7200_timer2_regs       ((volatile struct GPT_Regs *) (GPT_BASE + 0x20))
+
+/*
+ * General register values
+ */
+#define GPT_PRESCALE_1          0x00000000
+#define GPT_PRESCALE_16         0x00000004
+#define GPT_PRESCALE_256        0x00000008
+#define GPT_MODE_FREERUN        0x00000000
+#define GPT_MODE_PERIODIC       0x00000040
+#define GPT_ENABLE              0x00000080
+#define GPT_BZTOG               0x00000100
+#define GPT_BZMOD               0x00000200
+#define GPT_LOAD_MASK           0x0000ffff
+
+#endif
diff --git a/include/asm-arm/arch-l7200/gpio.h b/include/asm-arm/arch-l7200/gpio.h
new file mode 100644
index 000000000000..0b63e4239bdd
--- /dev/null
+++ b/include/asm-arm/arch-l7200/gpio.h
@@ -0,0 +1,105 @@
+/****************************************************************************/
+/*
+ *      linux/include/asm-arm/arch-l7200/gpio.h
+ *
+ *      Registers and  helper functions for the L7200 Link-Up Systems
+ *      GPIO.
+ *
+ *      (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define GPIO_OFF   0x00005000  /* Offset from IO_START to the GPIO reg's. */
+
+/* IO_START and IO_BASE are defined in hardware.h */
+
+#define GPIO_START (IO_START_2 + GPIO_OFF) /* Physical addr of the GPIO reg. */
+#define GPIO_BASE  (IO_BASE_2  + GPIO_OFF) /* Virtual addr of the GPIO reg. */
+
+/* Offsets from the start of the GPIO for all the registers. */
+#define PADR_OFF     0x000
+#define PADDR_OFF    0x004
+#define PASBSR_OFF   0x008
+#define PAEENR_OFF   0x00c
+#define PAESNR_OFF   0x010
+#define PAESTR_OFF   0x014
+#define PAIMR_OFF    0x018
+#define PAINT_OFF    0x01c
+
+#define PBDR_OFF     0x020
+#define PBDDR_OFF    0x024
+#define PBSBSR_OFF   0x028
+#define PBIMR_OFF    0x038
+#define PBINT_OFF    0x03c
+
+#define PCDR_OFF     0x040
+#define PCDDR_OFF    0x044
+#define PCSBSR_OFF   0x048
+#define PCIMR_OFF    0x058
+#define PCINT_OFF    0x05c
+
+#define PDDR_OFF     0x060
+#define PDDDR_OFF    0x064
+#define PDSBSR_OFF   0x068
+#define PDEENR_OFF   0x06c
+#define PDESNR_OFF   0x070
+#define PDESTR_OFF   0x074
+#define PDIMR_OFF    0x078
+#define PDINT_OFF    0x07c
+
+#define PEDR_OFF     0x080
+#define PEDDR_OFF    0x084
+#define PESBSR_OFF   0x088
+#define PEEENR_OFF   0x08c
+#define PEESNR_OFF   0x090
+#define PEESTR_OFF   0x094
+#define PEIMR_OFF    0x098
+#define PEINT_OFF    0x09c
+
+/* Define the GPIO registers for use by device drivers and the kernel. */
+#define PADR   (*(volatile unsigned long *)(GPIO_BASE+PADR_OFF))
+#define PADDR  (*(volatile unsigned long *)(GPIO_BASE+PADDR_OFF))
+#define PASBSR (*(volatile unsigned long *)(GPIO_BASE+PASBSR_OFF))
+#define PAEENR (*(volatile unsigned long *)(GPIO_BASE+PAEENR_OFF))
+#define PAESNR (*(volatile unsigned long *)(GPIO_BASE+PAESNR_OFF))
+#define PAESTR (*(volatile unsigned long *)(GPIO_BASE+PAESTR_OFF))
+#define PAIMR  (*(volatile unsigned long *)(GPIO_BASE+PAIMR_OFF))
+#define PAINT  (*(volatile unsigned long *)(GPIO_BASE+PAINT_OFF))
+
+#define PBDR   (*(volatile unsigned long *)(GPIO_BASE+PBDR_OFF))
+#define PBDDR  (*(volatile unsigned long *)(GPIO_BASE+PBDDR_OFF))
+#define PBSBSR (*(volatile unsigned long *)(GPIO_BASE+PBSBSR_OFF))
+#define PBIMR  (*(volatile unsigned long *)(GPIO_BASE+PBIMR_OFF))
+#define PBINT  (*(volatile unsigned long *)(GPIO_BASE+PBINT_OFF))
+
+#define PCDR   (*(volatile unsigned long *)(GPIO_BASE+PCDR_OFF))
+#define PCDDR  (*(volatile unsigned long *)(GPIO_BASE+PCDDR_OFF))
+#define PCSBSR (*(volatile unsigned long *)(GPIO_BASE+PCSBSR_OFF))
+#define PCIMR  (*(volatile unsigned long *)(GPIO_BASE+PCIMR_OFF))
+#define PCINT  (*(volatile unsigned long *)(GPIO_BASE+PCINT_OFF))
+
+#define PDDR   (*(volatile unsigned long *)(GPIO_BASE+PDDR_OFF))
+#define PDDDR  (*(volatile unsigned long *)(GPIO_BASE+PDDDR_OFF))
+#define PDSBSR (*(volatile unsigned long *)(GPIO_BASE+PDSBSR_OFF))
+#define PDEENR (*(volatile unsigned long *)(GPIO_BASE+PDEENR_OFF))
+#define PDESNR (*(volatile unsigned long *)(GPIO_BASE+PDESNR_OFF))
+#define PDESTR (*(volatile unsigned long *)(GPIO_BASE+PDESTR_OFF))
+#define PDIMR  (*(volatile unsigned long *)(GPIO_BASE+PDIMR_OFF))
+#define PDINT  (*(volatile unsigned long *)(GPIO_BASE+PDINT_OFF))
+
+#define PEDR   (*(volatile unsigned long *)(GPIO_BASE+PEDR_OFF))
+#define PEDDR  (*(volatile unsigned long *)(GPIO_BASE+PEDDR_OFF))
+#define PESBSR (*(volatile unsigned long *)(GPIO_BASE+PESBSR_OFF))
+#define PEEENR (*(volatile unsigned long *)(GPIO_BASE+PEEENR_OFF))
+#define PEESNR (*(volatile unsigned long *)(GPIO_BASE+PEESNR_OFF))
+#define PEESTR (*(volatile unsigned long *)(GPIO_BASE+PEESTR_OFF))
+#define PEIMR  (*(volatile unsigned long *)(GPIO_BASE+PEIMR_OFF))
+#define PEINT  (*(volatile unsigned long *)(GPIO_BASE+PEINT_OFF))
+
+#define VEE_EN         0x02
+#define BACKLIGHT_EN   0x04
diff --git a/include/asm-arm/arch-l7200/hardware.h b/include/asm-arm/arch-l7200/hardware.h
new file mode 100644
index 000000000000..b755079befab
--- /dev/null
+++ b/include/asm-arm/arch-l7200/hardware.h
@@ -0,0 +1,60 @@
+/*
+ * linux/include/asm-arm/arch-l7200/hardware.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * This file contains the hardware definitions for the 
+ * LinkUp Systems L7200 SOC development board.
+ *
+ * Changelog:
+ *   02-01-2000  RS     Created L7200 version, derived from rpc code
+ *   03-21-2000 SJH     Cleaned up file
+ *   04-21-2000  RS     Changed mapping of I/O in virtual space
+ *   04-25-2000 SJH     Removed unused symbols and such
+ *   05-05-2000 SJH     Complete rewrite
+ *   07-31-2000 SJH     Added undocumented debug auxillary port to
+ *                      get at last two columns for keyboard driver
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+#define RAM_START               0xf0000000
+#define RAM_SIZE                0x02000000
+#define RAM_BASE                0xc0000000
+
+#define IO_START                0x80000000      /* I/O */
+#define IO_SIZE                 0x01000000
+#define IO_BASE                 0xd0000000
+
+#define IO_START_2              0x90000000      /* I/O */
+#define IO_SIZE_2               0x01000000
+#define IO_BASE_2               0xd1000000
+
+#define AUX_START               0x1a000000      /* AUX PORT */
+#define AUX_SIZE                0x01000000
+#define AUX_BASE                0xd2000000
+
+#define FLASH1_START            0x00000000      /* FLASH BANK 1 */
+#define FLASH1_SIZE             0x01000000
+#define FLASH1_BASE             0xd3000000
+
+#define FLASH2_START            0x10000000      /* FLASH BANK 2 */
+#define FLASH2_SIZE             0x01000000
+#define FLASH2_BASE             0xd4000000
+
+#define ISA_START               0x20000000      /* ISA */
+#define ISA_SIZE                0x20000000
+#define ISA_BASE                0xe0000000
+
+#define FLUSH_BASE_PHYS         0x40000000      /* ROM */
+#define FLUSH_BASE              0xdf000000
+
+#define PCIO_BASE               IO_BASE
+
+#endif
diff --git a/include/asm-arm/arch-l7200/io.h b/include/asm-arm/arch-l7200/io.h
new file mode 100644
index 000000000000..fc012a39e2cb
--- /dev/null
+++ b/include/asm-arm/arch-l7200/io.h
@@ -0,0 +1,76 @@
+/*
+ * linux/include/asm-arm/arch-l7200/io.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  03-21-2000  SJH     Created from linux/include/asm-arm/arch-nexuspci/io.h
+ *  08-31-2000  SJH     Added in IO functions necessary for new drivers
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#include <asm/arch/hardware.h>
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * There are not real ISA nor PCI buses, so we fake it.
+ */
+#define __io_pci(a)             ((void __iomem *)(PCIO_BASE + (a)))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+#define __ioaddr(p)             __io_pci(p)
+
+/*
+ * Generic virtual read/write
+ */
+#define __arch_getb(a)          (*(volatile unsigned char *)(a))
+#define __arch_getl(a)          (*(volatile unsigned int  *)(a))
+
+static inline unsigned int __arch_getw(unsigned long a)
+{
+        unsigned int value;
+        __asm__ __volatile__("ldr%?h    %0, [%1, #0]    @ getw"
+                : "=&r" (value)
+                : "r" (a));
+        return value;
+}
+
+#define __arch_putb(v,a)        (*(volatile unsigned char *)(a) = (v))
+#define __arch_putl(v,a)        (*(volatile unsigned int  *)(a) = (v))
+
+static inline void __arch_putw(unsigned int value, unsigned long a)
+{
+        __asm__ __volatile__("str%?h    %0, [%1, #0]    @ putw"
+                : : "r" (value), "r" (a));
+}
+
+/*
+ * Translated address IO functions
+ *
+ * IO address has already been translated to a virtual address
+ */
+#define outb_t(v,p)             (*(volatile unsigned char *)(p) = (v))
+#define inb_t(p)                (*(volatile unsigned char *)(p))
+#define outw_t(v,p)             (*(volatile unsigned int *)(p) = (v))
+#define inw_t(p)                (*(volatile unsigned int *)(p))
+#define outl_t(v,p)             (*(volatile unsigned long *)(p) = (v))
+#define inl_t(p)                (*(volatile unsigned long *)(p))
+
+/*
+ * FIXME - These are to allow for linking. On all the other
+ *         ARM platforms, the entire IO space is contiguous.
+ *         The 7200 has three separate IO spaces. The below
+ *         macros will eventually become more involved. Use
+ *         with caution and don't be surprised by kernel oopses!!!
+ */
+#define inb(p)                  inb_t(p)
+#define inw(p)                  inw_t(p)
+#define inl(p)                  inl_t(p)
+#define outb(v,p)               outb_t(v,p)
+#define outw(v,p)               outw_t(v,p)
+#define outl(v,p)               outl_t(v,p)
+
+#endif
diff --git a/include/asm-arm/arch-l7200/irqs.h b/include/asm-arm/arch-l7200/irqs.h
new file mode 100644
index 000000000000..7120c016e29e
--- /dev/null
+++ b/include/asm-arm/arch-l7200/irqs.h
@@ -0,0 +1,56 @@
+/*
+ * include/asm-arm/arch-l7200/irqs.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   01-02-2000 RS      Create l7200 version
+ *   03-28-2000 SJH     Removed unused interrupt
+ *   07-28-2000 SJH     Added pseudo-keyboard interrupt
+ */
+
+/*
+ * NOTE: The second timer (Timer 2) is used as the keyboard
+ *       interrupt when the keyboard driver is enabled.
+ */
+
+#define NR_IRQS          32
+
+#define IRQ_STWDOG        0   /* Watchdog timer */
+#define IRQ_PROG          1   /* Programmable interrupt */
+#define IRQ_DEBUG_RX      2   /* Comm Rx debug */
+#define IRQ_DEBUG_TX      3   /* Comm Tx debug */
+#define IRQ_GCTC1         4   /* Timer 1 */
+#define IRQ_GCTC2         5   /* Timer 2 / Keyboard */
+#define IRQ_DMA           6   /* DMA controller */
+#define IRQ_CLCD          7   /* Color LCD controller */
+#define IRQ_SM_RX         8   /* Smart card */
+#define IRQ_SM_TX         9   /* Smart cart */
+#define IRQ_SM_RST       10   /* Smart card */
+#define IRQ_SIB          11   /* Serial Interface Bus */
+#define IRQ_MMC          12   /* MultiMediaCard */
+#define IRQ_SSP1         13   /* Synchronous Serial Port 1 */
+#define IRQ_SSP2         14   /* Synchronous Serial Port 1 */
+#define IRQ_SPI          15   /* SPI slave */
+#define IRQ_UART_1       16   /* UART 1 */
+#define IRQ_UART_2       17   /* UART 2 */
+#define IRQ_IRDA         18   /* IRDA */
+#define IRQ_RTC_TICK     19   /* Real Time Clock tick */
+#define IRQ_RTC_ALARM    20   /* Real Time Clock alarm */
+#define IRQ_GPIO         21   /* General Purpose IO */
+#define IRQ_GPIO_DMA     22   /* General Purpose IO, DMA */
+#define IRQ_M2M          23   /* Memory to memory DMA  */
+#define IRQ_RESERVED     24   /* RESERVED, don't use */
+#define IRQ_INTF         25   /* External active low interrupt */
+#define IRQ_INT0         26   /* External active low interrupt */
+#define IRQ_INT1         27   /* External active low interrupt */
+#define IRQ_INT2         28   /* External active low interrupt */
+#define IRQ_UCB1200      29   /* Interrupt generated by UCB1200*/
+#define IRQ_BAT_LO       30   /* Low batery or external power */
+#define IRQ_MEDIA_CHG    31   /* Media change interrupt */
+
+/*
+ * This is the offset of the FIQ "IRQ" numbers
+ */
+#define FIQ_START       64
diff --git a/include/asm-arm/arch-l7200/memory.h b/include/asm-arm/arch-l7200/memory.h
new file mode 100644
index 000000000000..c5b9608cb137
--- /dev/null
+++ b/include/asm-arm/arch-l7200/memory.h
@@ -0,0 +1,23 @@
+/*
+ * linux/include/asm-arm/arch-l7200/memory.h
+ *
+ * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
+ * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *
+ * Changelog:
+ *  03-13-2000  SJH     Created
+ *  04-13-2000  RS      Changed bus macros for new addr
+ *  05-03-2000  SJH     Removed bus macros and fixed virt_to_phys macro
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset on the L7200 SDB.
+ */
+#define PHYS_OFFSET     (0xf0000000UL)
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-l7200/param.h b/include/asm-arm/arch-l7200/param.h
new file mode 100644
index 000000000000..9962a12ab158
--- /dev/null
+++ b/include/asm-arm/arch-l7200/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-l7200/param.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * This file contains the hardware definitions for the
+ * LinkUp Systems L7200 SOC development board.
+ *
+ * Changelog:
+ *   04-21-2000 RS      Created L7200 version
+ *   04-25-2000 SJH     Cleaned up file
+ *   05-03-2000 SJH     Change comments and rate
+ */
+
+/*
+ * See 'time.h' for how the RTC HZ rate is set
+ */
+#define HZ 128
diff --git a/include/asm-arm/arch-l7200/pmpcon.h b/include/asm-arm/arch-l7200/pmpcon.h
new file mode 100644
index 000000000000..730056c194be
--- /dev/null
+++ b/include/asm-arm/arch-l7200/pmpcon.h
@@ -0,0 +1,46 @@
+/****************************************************************************/
+/*
+ *  linux/include/asm-arm/arch-l7200/pmpcon.h
+ *
+ *   Registers and  helper functions for the L7200 Link-Up Systems
+ *   DC/DC converter register.
+ *
+ *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define PMPCON_OFF 0x00006000  /* Offset from IO_START_2. */
+
+/* IO_START_2 and IO_BASE_2 are defined in hardware.h */
+
+#define PMPCON_START (IO_START_2 + PMPCON_OFF)  /* Physical address of reg. */
+#define PMPCON_BASE  (IO_BASE_2  + PMPCON_OFF)  /* Virtual address of reg. */
+
+
+#define PMPCON (*(volatile unsigned int *)(PMPCON_BASE))
+
+#define PWM2_50CYCLE 0x800
+#define CONTRAST     0x9
+
+#define PWM1H (CONTRAST)
+#define PWM1L (CONTRAST << 4)
+
+#define PMPCON_VALUE  (PWM2_50CYCLE | PWM1L | PWM1H) 
+        
+/* PMPCON = 0x811;   // too light and fuzzy
+ * PMPCON = 0x844;   
+ * PMPCON = 0x866;   // better color poor depth
+ * PMPCON = 0x888;   // Darker but better depth 
+ * PMPCON = 0x899;   // Darker even better depth
+ * PMPCON = 0x8aa;   // too dark even better depth
+ * PMPCON = 0X8cc;   // Way too dark
+ */
+
+/* As CONTRAST value increases the greater the depth perception and
+ * the darker the colors.
+ */
diff --git a/include/asm-arm/arch-l7200/pmu.h b/include/asm-arm/arch-l7200/pmu.h
new file mode 100644
index 000000000000..57faea76d1b3
--- /dev/null
+++ b/include/asm-arm/arch-l7200/pmu.h
@@ -0,0 +1,125 @@
+/****************************************************************************/
+/*
+ *  linux/include/asm-arm/arch-l7200/pmu.h
+ *
+ *   Registers and  helper functions for the L7200 Link-Up Systems
+ *   Power Management Unit (PMU).
+ *
+ *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define PMU_OFF   0x00050000  /* Offset from IO_START to the PMU registers. */
+
+/* IO_START and IO_BASE are defined in hardware.h */
+
+#define PMU_START (IO_START + PMU_OFF)  /* Physical addr. of the PMU reg. */
+#define PMU_BASE  (IO_BASE  + PMU_OFF)  /* Virtual addr. of the PMU reg. */
+
+
+/* Define the PMU registers for use by device drivers and the kernel. */
+
+typedef struct {
+     unsigned int CURRENT;  /* Current configuration register */
+     unsigned int NEXT;     /* Next configuration register */
+     unsigned int reserved;
+     unsigned int RUN;      /* Run configuration register */
+     unsigned int COMM;     /* Configuration command register */
+     unsigned int SDRAM;    /* SDRAM configuration bypass register */
+} pmu_interface;
+
+#define PMU ((volatile pmu_interface *)(PMU_BASE))
+
+
+/* Macro's for reading the common register fields. */
+
+#define GET_TRANSOP(reg)  ((reg >> 25) & 0x03) /* Bits 26-25 */
+#define GET_OSCEN(reg)    ((reg >> 16) & 0x01)
+#define GET_OSCMUX(reg)   ((reg >> 15) & 0x01)
+#define GET_PLLMUL(reg)   ((reg >>  9) & 0x3f) /* Bits 14-9 */
+#define GET_PLLEN(reg)    ((reg >>  8) & 0x01)
+#define GET_PLLMUX(reg)   ((reg >>  7) & 0x01)
+#define GET_BCLK_DIV(reg) ((reg >>  3) & 0x03) /* Bits 4-3 */
+#define GET_SDRB_SEL(reg) ((reg >>  2) & 0x01)
+#define GET_SDRF_SEL(reg) ((reg >>  1) & 0x01)
+#define GET_FASTBUS(reg)  (reg & 0x1)
+
+/* CFG_NEXT register */
+
+#define CFG_NEXT_CLOCKRECOVERY ((PMU->NEXT >> 18) & 0x7f)   /* Bits 24-18 */
+#define CFG_NEXT_INTRET        ((PMU->NEXT >> 17) & 0x01)
+#define CFG_NEXT_SDR_STOP      ((PMU->NEXT >>  6) & 0x01)
+#define CFG_NEXT_SYSCLKEN      ((PMU->NEXT >>  5) & 0x01)
+
+/* Useful field values that can be used to construct the
+ * CFG_NEXT and CFG_RUN registers.
+ */
+
+#define TRANSOP_NOP      0<<25  /* NOCHANGE_NOSTALL */
+#define NOCHANGE_STALL   1<<25
+#define CHANGE_NOSTALL   2<<25
+#define CHANGE_STALL     3<<25
+
+#define INTRET           1<<17
+#define OSCEN            1<<16
+#define OSCMUX           1<<15
+
+/* PLL frequencies */
+
+#define PLLMUL_0         0<<9         /*  3.6864 MHz */
+#define PLLMUL_1         1<<9         /*  ?????? MHz */
+#define PLLMUL_5         5<<9         /*  18.432 MHz */
+#define PLLMUL_10       10<<9         /*  36.864 MHz */
+#define PLLMUL_18       18<<9         /*  ?????? MHz */
+#define PLLMUL_20       20<<9         /*  73.728 MHz */
+#define PLLMUL_32       32<<9         /*  ?????? MHz */
+#define PLLMUL_35       35<<9         /* 129.024 MHz */
+#define PLLMUL_36       36<<9         /*  ?????? MHz */
+#define PLLMUL_39       39<<9         /*  ?????? MHz */
+#define PLLMUL_40       40<<9         /* 147.456 MHz */
+
+/* Clock recovery times */
+
+#define CRCLOCK_1        1<<18
+#define CRCLOCK_2        2<<18
+#define CRCLOCK_4        4<<18
+#define CRCLOCK_8        8<<18
+#define CRCLOCK_16      16<<18
+#define CRCLOCK_32      32<<18
+#define CRCLOCK_63      63<<18
+#define CRCLOCK_127    127<<18
+
+#define PLLEN            1<<8
+#define PLLMUX           1<<7
+#define SDR_STOP         1<<6
+#define SYSCLKEN         1<<5
+
+#define BCLK_DIV_4       2<<3
+#define BCLK_DIV_2       1<<3
+#define BCLK_DIV_1       0<<3
+
+#define SDRB_SEL         1<<2
+#define SDRF_SEL         1<<1
+#define FASTBUS          1<<0
+
+
+/* CFG_SDRAM */
+
+#define SDRREFFQ         1<<0  /* Only if SDRSTOPRQ is not set. */
+#define SDRREFACK        1<<1  /* Read-only */
+#define SDRSTOPRQ        1<<2  /* Only if SDRREFFQ is not set. */
+#define SDRSTOPACK       1<<3  /* Read-only */
+#define PICEN            1<<4  /* Enable Co-procesor */
+#define PICTEST          1<<5
+
+#define GET_SDRREFFQ    ((PMU->SDRAM >> 0) & 0x01)
+#define GET_SDRREFACK   ((PMU->SDRAM >> 1) & 0x01) /* Read-only */
+#define GET_SDRSTOPRQ   ((PMU->SDRAM >> 2) & 0x01)
+#define GET_SDRSTOPACK  ((PMU->SDRAM >> 3) & 0x01) /* Read-only */
+#define GET_PICEN       ((PMU->SDRAM >> 4) & 0x01)
+#define GET_PICTEST     ((PMU->SDRAM >> 5) & 0x01)
diff --git a/include/asm-arm/arch-l7200/serial.h b/include/asm-arm/arch-l7200/serial.h
new file mode 100644
index 000000000000..defb8b7fca73
--- /dev/null
+++ b/include/asm-arm/arch-l7200/serial.h
@@ -0,0 +1,37 @@
+/*
+ * linux/include/asm-arm/arch-l7200/serial.h
+ *
+ * Copyright (c) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  03-20-2000  SJH     Created
+ *  03-26-2000  SJH     Added flags for serial ports
+ *  03-27-2000  SJH     Corrected BASE_BAUD value
+ *  04-14-2000  RS      Made register addr dependent on IO_BASE
+ *  05-03-2000  SJH     Complete rewrite
+ *  05-09-2000  SJH     Stripped out architecture specific serial stuff
+ *                      and placed it in a separate file
+ *  07-28-2000  SJH     Moved base baud rate variable
+ */
+#ifndef __ASM_ARCH_SERIAL_H
+#define __ASM_ARCH_SERIAL_H
+
+/*
+ * This assumes you have a 3.6864 MHz clock for your UART.
+ */
+#define BASE_BAUD       3686400
+
+/*
+ * Standard COM flags
+ */
+#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
+
+#define STD_SERIAL_PORT_DEFNS           \
+        /* MAGIC UART CLK   PORT       IRQ     FLAGS */                 \
+        { 0, BASE_BAUD, UART1_BASE, IRQ_UART_1, STD_COM_FLAGS },  /* ttyLU0 */ \
+        { 0, BASE_BAUD, UART2_BASE, IRQ_UART_2, STD_COM_FLAGS },  /* ttyLU1 */ \
+
+#define EXTRA_SERIAL_PORT_DEFNS
+
+#endif
diff --git a/include/asm-arm/arch-l7200/serial_l7200.h b/include/asm-arm/arch-l7200/serial_l7200.h
new file mode 100644
index 000000000000..238c595d97ea
--- /dev/null
+++ b/include/asm-arm/arch-l7200/serial_l7200.h
@@ -0,0 +1,101 @@
+/*
+ * linux/include/asm-arm/arch-l7200/serial_l7200.h
+ *
+ * Copyright (c) 2000 Steven Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  05-09-2000  SJH     Created
+ */
+#ifndef __ASM_ARCH_SERIAL_L7200_H
+#define __ASM_ARCH_SERIAL_L7200_H
+
+#include <asm/arch/memory.h>
+
+/*
+ * This assumes you have a 3.6864 MHz clock for your UART.
+ */
+#define BASE_BAUD 3686400
+
+/*
+ * UART base register addresses
+ */
+#define UART1_BASE      (IO_BASE + 0x00044000)
+#define UART2_BASE      (IO_BASE + 0x00045000)
+
+/*
+ * UART register offsets
+ */
+#define UARTDR                  0x00    /* Tx/Rx data */
+#define RXSTAT                  0x04    /* Rx status */
+#define H_UBRLCR                0x08    /* mode register high */
+#define M_UBRLCR                0x0C    /* mode reg mid (MSB of buad)*/
+#define L_UBRLCR                0x10    /* mode reg low (LSB of baud)*/
+#define UARTCON                 0x14    /* control register */
+#define UARTFLG                 0x18    /* flag register */
+#define UARTINTSTAT             0x1C    /* FIFO IRQ status register */
+#define UARTINTMASK             0x20    /* FIFO IRQ mask register */
+
+/*
+ * UART baud rate register values
+ */
+#define BR_110                  0x827
+#define BR_1200                 0x06e
+#define BR_2400                 0x05f
+#define BR_4800                 0x02f
+#define BR_9600                 0x017
+#define BR_14400                0x00f
+#define BR_19200                0x00b
+#define BR_38400                0x005
+#define BR_57600                0x003
+#define BR_76800                0x002
+#define BR_115200               0x001
+
+/*
+ * Receiver status register (RXSTAT) mask values
+ */
+#define RXSTAT_NO_ERR           0x00    /* No error */
+#define RXSTAT_FRM_ERR          0x01    /* Framing error */
+#define RXSTAT_PAR_ERR          0x02    /* Parity error */
+#define RXSTAT_OVR_ERR          0x04    /* Overrun error */
+
+/*
+ * High byte of UART bit rate and line control register (H_UBRLCR) values
+ */
+#define UBRLCR_BRK              0x01    /* generate break on tx */
+#define UBRLCR_PEN              0x02    /* enable parity */
+#define UBRLCR_PDIS             0x00    /* disable parity */
+#define UBRLCR_EVEN             0x04    /* 1= even parity,0 = odd parity */
+#define UBRLCR_STP2             0x08    /* transmit 2 stop bits */
+#define UBRLCR_FIFO             0x10    /* enable FIFO */
+#define UBRLCR_LEN5             0x60    /* word length5 */
+#define UBRLCR_LEN6             0x40    /* word length6 */
+#define UBRLCR_LEN7             0x20    /* word length7 */
+#define UBRLCR_LEN8             0x00    /* word length8 */
+
+/*
+ * UART control register (UARTCON) values
+ */
+#define UARTCON_UARTEN          0x01    /* Enable UART */
+#define UARTCON_DMAONERR        0x08    /* Mask RxDmaRq when errors occur */
+
+/*
+ * UART flag register (UARTFLG) mask values
+ */
+#define UARTFLG_UTXFF           0x20    /* Transmit FIFO full */
+#define UARTFLG_URXFE           0x10    /* Receiver FIFO empty */
+#define UARTFLG_UBUSY           0x08    /* Transmitter busy */
+#define UARTFLG_DCD             0x04    /* Data carrier detect */
+#define UARTFLG_DSR             0x02    /* Data set ready */
+#define UARTFLG_CTS             0x01    /* Clear to send */
+
+/*
+ * UART interrupt status/clear registers (UARTINTSTAT/CLR) values
+ */
+#define UART_TXINT              0x01    /* TX interrupt */
+#define UART_RXINT              0x02    /* RX interrupt */
+#define UART_RXERRINT           0x04    /* RX error interrupt */
+#define UART_MSINT              0x08    /* Modem Status interrupt */
+#define UART_UDINT              0x10    /* UART Disabled interrupt */
+#define UART_ALLIRQS            0x1f    /* All interrupts */
+
+#endif
diff --git a/include/asm-arm/arch-l7200/sib.h b/include/asm-arm/arch-l7200/sib.h
new file mode 100644
index 000000000000..bf4364ee2535
--- /dev/null
+++ b/include/asm-arm/arch-l7200/sib.h
@@ -0,0 +1,119 @@
+/****************************************************************************/
+/*
+ *  linux/include/asm-arm/arch-l7200/sib.h
+ *
+ *  Registers and helper functions for the Serial Interface Bus.
+ *
+ *  (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define SIB_OFF   0x00040000  /* Offset from IO_START to the SIB reg's. */
+
+/* IO_START and IO_BASE are defined in hardware.h */
+
+#define SIB_START (IO_START + SIB_OFF) /* Physical addr of the SIB reg. */
+#define SIB_BASE  (IO_BASE  + SIB_OFF) /* Virtual addr of the SIB reg.  */
+
+/* Offsets from the start of the SIB for all the registers. */
+
+/* Define the SIB registers for use by device drivers and the kernel. */
+
+typedef struct
+{
+     unsigned int MCCR;    /* SIB Control Register           Offset: 0x00 */
+     unsigned int RES1;    /* Reserved                       Offset: 0x04 */
+     unsigned int MCDR0;   /* SIB Data Register 0            Offset: 0x08 */
+     unsigned int MCDR1;   /* SIB Data Register 1            Offset: 0x0c */
+     unsigned int MCDR2;   /* SIB Data Register 2 (UCB1x00)  Offset: 0x10 */
+     unsigned int RES2;    /* Reserved                       Offset: 0x14 */
+     unsigned int MCSR;    /* SIB Status Register            Offset: 0x18 */
+} SIB_Interface;
+
+#define SIB ((volatile SIB_Interface *) (SIB_BASE))
+
+/* MCCR */
+
+#define INTERNAL_FREQ   9216000  /* Hertz */
+#define AUDIO_FREQ         5000  /* Hertz */
+#define TELECOM_FREQ       5000  /* Hertz */
+
+#define AUDIO_DIVIDE    (INTERNAL_FREQ / (32 * AUDIO_FREQ))
+#define TELECOM_DIVIDE  (INTERNAL_FREQ / (32 * TELECOM_FREQ))
+
+#define MCCR_ASD57      AUDIO_DIVIDE
+#define MCCR_TSD57      (TELECOM_DIVIDE << 8)
+#define MCCR_MCE        (1 << 16)             /* SIB enable */
+#define MCCR_ECS        (1 << 17)             /* External Clock Select */
+#define MCCR_ADM        (1 << 18)             /* A/D Data Sampling */
+#define MCCR_PMC        (1 << 26)             /* PIN Multiplexer Control */
+
+
+#define GET_ASD ((SIB->MCCR >>  0) & 0x3f) /* Audio Sample Rate Div. */
+#define GET_TSD ((SIB->MCCR >>  8) & 0x3f) /* Telcom Sample Rate Div. */
+#define GET_MCE ((SIB->MCCR >> 16) & 0x01) /* SIB Enable */
+#define GET_ECS ((SIB->MCCR >> 17) & 0x01) /* External Clock Select */
+#define GET_ADM ((SIB->MCCR >> 18) & 0x01) /* A/D Data Sampling Mode */
+#define GET_TTM ((SIB->MCCR >> 19) & 0x01) /* Telco Trans. FIFO I mask */ 
+#define GET_TRM ((SIB->MCCR >> 20) & 0x01) /* Telco Recv. FIFO I mask */
+#define GET_ATM ((SIB->MCCR >> 21) & 0x01) /* Audio Trans. FIFO I mask */ 
+#define GET_ARM ((SIB->MCCR >> 22) & 0x01) /* Audio Recv. FIFO I mask */
+#define GET_LBM ((SIB->MCCR >> 23) & 0x01) /* Loop Back Mode */
+#define GET_ECP ((SIB->MCCR >> 24) & 0x03) /* Extern. Clck Prescale sel */
+#define GET_PMC ((SIB->MCCR >> 26) & 0x01) /* PIN Multiplexer Control */
+#define GET_ERI ((SIB->MCCR >> 27) & 0x01) /* External Read Interrupt */
+#define GET_EWI ((SIB->MCCR >> 28) & 0x01) /* External Write Interrupt */
+
+/* MCDR0 */
+
+#define AUDIO_RECV     ((SIB->MCDR0 >> 4) & 0xfff)
+#define AUDIO_WRITE(v) ((SIB->MCDR0 = (v & 0xfff) << 4))
+
+/* MCDR1 */
+
+#define TELECOM_RECV     ((SIB->MCDR1 >> 2) & 032fff)
+#define TELECOM_WRITE(v) ((SIB->MCDR1 = (v & 0x3fff) << 2))
+
+
+/* MCSR */
+
+#define MCSR_ATU (1 << 4)  /* Audio Transmit FIFO Underrun */
+#define MCSR_ARO (1 << 5)  /* Audio Receive  FIFO Underrun */
+#define MCSR_TTU (1 << 6)  /* TELECOM Transmit FIFO Underrun */
+#define MCSR_TRO (1 << 7)  /* TELECOM Receive  FIFO Underrun */
+
+#define MCSR_CLEAR_UNDERUN_BITS (MCSR_ATU | MCSR_ARO | MCSR_TTU | MCSR_TRO)
+
+
+#define GET_ATS ((SIB->MCSR >>  0) & 0x01) /* Audio Transmit FIFO Service Req*/
+#define GET_ARS ((SIB->MCSR >>  1) & 0x01) /* Audio Recv FIFO Service Request*/
+#define GET_TTS ((SIB->MCSR >>  2) & 0x01) /* TELECOM Transmit FIFO  Flag */
+#define GET_TRS ((SIB->MCSR >>  3) & 0x01) /* TELECOM Recv FIFO Service Req. */
+#define GET_ATU ((SIB->MCSR >>  4) & 0x01) /* Audio Transmit FIFO Underrun */
+#define GET_ARO ((SIB->MCSR >>  5) & 0x01) /* Audio Receive  FIFO Underrun */
+#define GET_TTU ((SIB->MCSR >>  6) & 0x01) /* TELECOM Transmit FIFO Underrun */
+#define GET_TRO ((SIB->MCSR >>  7) & 0x01) /* TELECOM Receive  FIFO Underrun */
+#define GET_ANF ((SIB->MCSR >>  8) & 0x01) /* Audio Transmit FIFO not full */
+#define GET_ANE ((SIB->MCSR >>  9) & 0x01) /* Audio Receive FIFO not empty */
+#define GET_TNF ((SIB->MCSR >> 10) & 0x01) /* Telecom Transmit FIFO not full */
+#define GET_TNE ((SIB->MCSR >> 11) & 0x01) /* Telecom Receive FIFO not empty */
+#define GET_CWC ((SIB->MCSR >> 12) & 0x01) /* Codec Write Complete */
+#define GET_CRC ((SIB->MCSR >> 13) & 0x01) /* Codec Read Complete */
+#define GET_ACE ((SIB->MCSR >> 14) & 0x01) /* Audio Codec Enabled */
+#define GET_TCE ((SIB->MCSR >> 15) & 0x01) /* Telecom Codec Enabled */
+
+/* MCDR2 */
+
+#define MCDR2_rW               (1 << 16)
+
+#define WRITE_MCDR2(reg, data) (SIB->MCDR2 =((reg<<17)|MCDR2_rW|(data&0xffff)))
+#define MCDR2_WRITE_COMPLETE   GET_CWC
+
+#define INITIATE_MCDR2_READ(reg) (SIB->MCDR2 = (reg << 17))
+#define MCDR2_READ_COMPLETE      GET_CRC
+#define MCDR2_READ               (SIB->MCDR2 & 0xffff)
diff --git a/include/asm-arm/arch-l7200/sys-clock.h b/include/asm-arm/arch-l7200/sys-clock.h
new file mode 100644
index 000000000000..771c774f4815
--- /dev/null
+++ b/include/asm-arm/arch-l7200/sys-clock.h
@@ -0,0 +1,67 @@
+/****************************************************************************/
+/*
+ *  linux/include/asm-arm/arch-l7200/sys-clock.h
+ *
+ *   Registers and  helper functions for the L7200 Link-Up Systems
+ *   System clocks.
+ *
+ *   (C) Copyright 2000, S A McConnell  (samcconn@cotw.com)
+ *
+ *  This file is subject to the terms and conditions of the GNU General Public
+ *  License. See the file COPYING in the main directory of this archive for
+ *  more details.
+ */
+
+/****************************************************************************/
+
+#define SYS_CLOCK_OFF   0x00050030  /* Offset from IO_START. */
+
+/* IO_START and IO_BASE are defined in hardware.h */
+
+#define SYS_CLOCK_START (IO_START + SYS_CLCOK_OFF)  /* Physical address */
+#define SYS_CLOCK_BASE  (IO_BASE  + SYS_CLOCK_OFF)  /* Virtual address  */
+
+/* Define the interface to the SYS_CLOCK */
+
+typedef struct
+{
+     unsigned int ENABLE;
+     unsigned int ESYNC;
+     unsigned int SELECT;
+} sys_clock_interface;
+
+#define SYS_CLOCK   ((volatile sys_clock_interface *)(SYS_CLOCK_BASE))
+
+//#define CLOCK_EN    (*(volatile unsigned long *)(PMU_BASE+CLOCK_EN_OFF))
+//#define CLOCK_ESYNC (*(volatile unsigned long *)(PMU_BASE+CLOCK_ESYNC_OFF))
+//#define CLOCK_SEL   (*(volatile unsigned long *)(PMU_BASE+CLOCK_SEL_OFF))
+
+/* SYS_CLOCK -> ENABLE */
+
+#define SYN_EN          1<<0
+#define B18M_EN         1<<1
+#define CLK3M6_EN       1<<2
+#define BUART_EN        1<<3
+#define CLK18MU_EN      1<<4
+#define FIR_EN          1<<5
+#define MIRN_EN         1<<6
+#define UARTM_EN        1<<7
+#define SIBADC_EN       1<<8
+#define ALTD_EN         1<<9
+#define CLCLK_EN        1<<10
+
+/* SYS_CLOCK -> SELECT */
+
+#define CLK18M_DIV      1<<0
+#define MIR_SEL         1<<1
+#define SSP_SEL         1<<4
+#define MM_DIV          1<<5
+#define MM_SEL          1<<6
+#define ADC_SEL_2       0<<7
+#define ADC_SEL_4       1<<7
+#define ADC_SEL_8       3<<7
+#define ADC_SEL_16      7<<7
+#define ADC_SEL_32      0x0f<<7
+#define ADC_SEL_64      0x1f<<7
+#define ADC_SEL_128     0x3f<<7
+#define ALTD_SEL        1<<13
diff --git a/include/asm-arm/arch-l7200/system.h b/include/asm-arm/arch-l7200/system.h
new file mode 100644
index 000000000000..cb4ff29059b8
--- /dev/null
+++ b/include/asm-arm/arch-l7200/system.h
@@ -0,0 +1,27 @@
+/*
+ * linux/include/asm-arm/arch-l7200/system.h
+ *
+ * Copyright (c) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog
+ *  03-21-2000  SJH     Created
+ *  04-26-2000  SJH     Fixed functions
+ *  05-03-2000  SJH     Removed usage of obsolete 'iomd.h'
+ *  05-31-2000  SJH     Properly implemented 'arch_idle'
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+        *(unsigned long *)(IO_BASE + 0x50004) = 1;      /* idle mode */
+}
+
+static inline void arch_reset(char mode)
+{
+        if (mode == 's') {
+                cpu_reset(0);
+        }
+}
+
+#endif
diff --git a/include/asm-arm/arch-l7200/time.h b/include/asm-arm/arch-l7200/time.h
new file mode 100644
index 000000000000..7b98b533e63a
--- /dev/null
+++ b/include/asm-arm/arch-l7200/time.h
@@ -0,0 +1,72 @@
+/*
+ * linux/include/asm-arm/arch-l7200/time.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *   01-02-2000 RS      Created l7200 version, derived from rpc code
+ *   05-03-2000 SJH     Complete rewrite
+ */
+#ifndef _ASM_ARCH_TIME_H
+#define _ASM_ARCH_TIME_H
+
+#include <asm/arch/irqs.h>
+
+/*
+ * RTC base register address
+ */
+#define RTC_BASE        (IO_BASE_2 + 0x2000)
+
+/*
+ * RTC registers
+ */
+#define RTC_RTCDR       (*(volatile unsigned char *) (RTC_BASE + 0x000))
+#define RTC_RTCMR       (*(volatile unsigned char *) (RTC_BASE + 0x004))
+#define RTC_RTCS        (*(volatile unsigned char *) (RTC_BASE + 0x008))
+#define RTC_RTCC        (*(volatile unsigned char *) (RTC_BASE + 0x008))
+#define RTC_RTCDV       (*(volatile unsigned char *) (RTC_BASE + 0x00c))
+#define RTC_RTCCR       (*(volatile unsigned char *) (RTC_BASE + 0x010))
+
+/*
+ * RTCCR register values
+ */
+#define RTC_RATE_32     0x00      /* 32 Hz tick */
+#define RTC_RATE_64     0x10      /* 64 Hz tick */
+#define RTC_RATE_128    0x20      /* 128 Hz tick */
+#define RTC_RATE_256    0x30      /* 256 Hz tick */
+#define RTC_EN_ALARM    0x01      /* Enable alarm */
+#define RTC_EN_TIC      0x04      /* Enable counter */
+#define RTC_EN_STWDOG   0x08      /* Enable watchdog */
+
+/*
+ * Handler for RTC timer interrupt
+ */
+static irqreturn_t
+timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+        do_timer(regs);
+#ifndef CONFIG_SMP
+        update_process_times(user_mode(regs));
+#endif
+        do_profile(regs);
+        RTC_RTCC = 0;                           /* Clear interrupt */
+
+        return IRQ_HANDLED;
+}
+
+/*
+ * Set up RTC timer interrupt, and return the current time in seconds.
+ */
+void __init time_init(void)
+{
+        RTC_RTCC = 0;                           /* Clear interrupt */
+
+        timer_irq.handler = timer_interrupt;
+
+        setup_irq(IRQ_RTC_TICK, &timer_irq);
+
+        RTC_RTCCR = RTC_RATE_128 | RTC_EN_TIC;  /* Set rate and enable timer */
+}
+
+#endif
diff --git a/include/asm-arm/arch-l7200/timex.h b/include/asm-arm/arch-l7200/timex.h
new file mode 100644
index 000000000000..3c3202620f00
--- /dev/null
+++ b/include/asm-arm/arch-l7200/timex.h
@@ -0,0 +1,20 @@
+/*
+ * linux/include/asm-arm/arch-l7200/timex.h
+ *
+ * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
+ *                    Steve Hill (sjhill@cotw.com)
+ *
+ * 04-21-2000  RS Created file
+ * 05-03-2000 SJH Tick rate was wrong
+ *
+ */
+
+/*
+ * On the ARM720T, clock ticks are set to 128 Hz.
+ *
+ * NOTE: The actual RTC value is set in 'time.h' which
+ *       must be changed when choosing a different tick
+ *       rate. The value of HZ in 'param.h' must also
+ *       be changed to match below.
+ */
+#define CLOCK_TICK_RATE         128
diff --git a/include/asm-arm/arch-l7200/uncompress.h b/include/asm-arm/arch-l7200/uncompress.h
new file mode 100644
index 000000000000..1caa2b560f53
--- /dev/null
+++ b/include/asm-arm/arch-l7200/uncompress.h
@@ -0,0 +1,44 @@
+/*
+ * linux/include/asm-arm/arch-l7200/uncompress.h
+ *
+ * Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
+ *
+ * Changelog:
+ *  05-01-2000  SJH     Created
+ *  05-13-2000  SJH     Filled in function bodies
+ *  07-26-2000  SJH     Removed hard coded buad rate
+ */
+
+#include <asm/hardware.h>
+
+#define IO_UART  IO_START + 0x00044000
+
+#define __raw_writeb(v,p)       (*(volatile unsigned char *)(p) = (v))
+#define __raw_readb(p)          (*(volatile unsigned char *)(p))
+
+static __inline__ void putc(char c)
+{
+        while(__raw_readb(IO_UART + 0x18) & 0x20 ||
+                __raw_readb(IO_UART + 0x18) & 0x08);
+        __raw_writeb(c, IO_UART + 0x00);
+}
+
+static void putstr(const char *s)
+{
+        while (*s) {
+                if (*s == 10) {                 /* If a LF, add CR */
+                        putc(10);
+                        putc(13);
+                }
+                putc(*(s++));
+        }
+}
+
+static __inline__ void arch_decomp_setup(void)
+{
+        __raw_writeb(0x00, IO_UART + 0x08);     /* Set HSB */
+        __raw_writeb(0x00, IO_UART + 0x20);     /* Disable IRQs */
+        __raw_writeb(0x01, IO_UART + 0x14);     /* Enable UART */
+}
+
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-l7200/vmalloc.h b/include/asm-arm/arch-l7200/vmalloc.h
new file mode 100644
index 000000000000..edeaebe1f14a
--- /dev/null
+++ b/include/asm-arm/arch-l7200/vmalloc.h
@@ -0,0 +1,15 @@
+/*
+ * linux/include/asm-arm/arch-l7200/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h
new file mode 100644
index 000000000000..52c1cb9c39c6
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/constants.h
@@ -0,0 +1,88 @@
+/* include/asm-arm/arch-lh7a40x/constants.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *  Copyright (C) 2004 Logic Product Development
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_CONSTANTS_H
+#define __ASM_ARCH_CONSTANTS_H
+
+#include <linux/config.h>
+
+/* Addressing constants */
+
+        /* SoC CPU IO addressing */
+#define IO_PHYS                 (0x80000000)
+#define IO_VIRT                 (0xf8000000)
+#define IO_SIZE                 (0x0000B000)
+
+#ifdef CONFIG_MACH_KEV7A400
+# define CPLD_PHYS              (0x20000000)
+# define CPLD_VIRT              (0xf2000000)
+# define CPLD_SIZE              PAGE_SIZE
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+
+# define IOBARRIER_PHYS         0xc0000000 /* Start of SDRAM */
+/*# define IOBARRIER_PHYS               0x00000000 */ /* Start of flash */
+# define IOBARRIER_VIRT         0xf0000000
+# define IOBARRIER_SIZE         PAGE_SIZE
+
+# define CF_PHYS                0x60200000
+# define CF_VIRT                0xf6020000
+# define CF_SIZE                (8*1024)
+
+        /* The IO mappings for the LPD CPLD are, unfortunately, sparse.  */
+# define CPLDX_PHYS(x)          (0x70000000 | ((x) << 20))
+# define CPLDX_VIRT(x)          (0xf7000000 | ((x) << 16))
+# define CPLD00_PHYS            CPLDX_PHYS (0x00) /* Wired LAN */
+# define CPLD00_VIRT            CPLDX_VIRT (0x00)
+# define CPLD00_SIZE            PAGE_SIZE
+# define CPLD02_PHYS            CPLDX_PHYS (0x02)
+# define CPLD02_VIRT            CPLDX_VIRT (0x02)
+# define CPLD02_SIZE            PAGE_SIZE
+# define CPLD06_PHYS            CPLDX_PHYS (0x06)
+# define CPLD06_VIRT            CPLDX_VIRT (0x06)
+# define CPLD06_SIZE            PAGE_SIZE
+# define CPLD08_PHYS            CPLDX_PHYS (0x08)
+# define CPLD08_VIRT            CPLDX_VIRT (0x08)
+# define CPLD08_SIZE            PAGE_SIZE
+# define CPLD0C_PHYS            CPLDX_PHYS (0x0c)
+# define CPLD0C_VIRT            CPLDX_VIRT (0x0c)
+# define CPLD0C_SIZE            PAGE_SIZE
+# define CPLD0E_PHYS            CPLDX_PHYS (0x0e)
+# define CPLD0E_VIRT            CPLDX_VIRT (0x0e)
+# define CPLD0E_SIZE            PAGE_SIZE
+# define CPLD10_PHYS            CPLDX_PHYS (0x10)
+# define CPLD10_VIRT            CPLDX_VIRT (0x10)
+# define CPLD10_SIZE            PAGE_SIZE
+# define CPLD12_PHYS            CPLDX_PHYS (0x12)
+# define CPLD12_VIRT            CPLDX_VIRT (0x12)
+# define CPLD12_SIZE            PAGE_SIZE
+# define CPLD14_PHYS            CPLDX_PHYS (0x14)
+# define CPLD14_VIRT            CPLDX_VIRT (0x14)
+# define CPLD14_SIZE            PAGE_SIZE
+# define CPLD16_PHYS            CPLDX_PHYS (0x16)
+# define CPLD16_VIRT            CPLDX_VIRT (0x16)
+# define CPLD16_SIZE            PAGE_SIZE
+# define CPLD18_PHYS            CPLDX_PHYS (0x18)
+# define CPLD18_VIRT            CPLDX_VIRT (0x18)
+# define CPLD18_SIZE            PAGE_SIZE
+# define CPLD1A_PHYS            CPLDX_PHYS (0x1a)
+# define CPLD1A_VIRT            CPLDX_VIRT (0x1a)
+# define CPLD1A_SIZE            PAGE_SIZE
+#endif
+
+        /* Timing constants */
+
+#define XTAL_IN                 14745600        /* 14.7456 MHz crystal */
+#define PLL_CLOCK               (XTAL_IN * 21)  /* 309 MHz PLL clock */
+#define MAX_HCLK_KHZ            100000          /* HCLK max limit ~100MHz */
+
+#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/include/asm-arm/arch-lh7a40x/debug-macro.S b/include/asm-arm/arch-lh7a40x/debug-macro.S
new file mode 100644
index 000000000000..421dcd6a8506
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/debug-macro.S
@@ -0,0 +1,39 @@
+/* linux/include/asm-arm/arch-lh7a40x/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+        @ It is not known if this will be appropriate for every 40x
+        @ board.
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                mov     \rx, #0x00000700        @ offset from base
+                orreq   \rx, \rx, #0x80000000   @ physical base
+                orrne   \rx, \rx, #0xf8000000   @ virtual base
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]              @ DATA
+                .endm
+
+                .macro  busyuart,rd,rx          @ spin while busy
+1001:           ldr     \rd, [\rx, #0x10]       @ STATUS
+                tst     \rd, #1 << 3            @ BUSY (TX FIFO not empty)
+                bne     1001b                   @ yes, spin
+                .endm
+
+                .macro  waituart,rd,rx          @ wait for Tx FIFO room
+1001:           ldrb    \rd, [\rx, #0x10]       @ STATUS
+                tst     \rd, #1 << 5            @ TXFF (TX FIFO full)
+                bne     1001b                   @ yes, spin
+                .endm
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
new file mode 100644
index 000000000000..5797f01e1844
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/dma.h
@@ -0,0 +1,17 @@
+/* include/asm-arm/arch-lh7a40x/dma.h
+ *
+ *  Copyright (C) 2003 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        0 /* All DMA is internal to CPU */
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
new file mode 100644
index 000000000000..865f396aa63c
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/entry-macro.S
@@ -0,0 +1,67 @@
+/*
+ * include/asm-arm/arch-lh7a40x/entry-macro.S
+ *
+ * Low-level IRQ helper macros for LH7A40x platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
+#  error "LH7A400 and LH7A404 are mutually exclusive"
+# endif
+
+# if defined (CONFIG_ARCH_LH7A400)
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \irqnr, #0
+                mov     \base, #io_p2v(0x80000000)      @ APB registers
+                ldr     \irqstat, [\base, #0x500]       @ PIC INTSR
+
+1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
+                bcs     1008f                           @ Bit set; irq found
+                add     \irqnr, \irqnr, #1
+                bne     1001b                           @ Until no bits
+                b       1009f                           @ Nothing?  Hmm.
+1008:           movs    \irqstat, #1                    @ Force !Z
+1009:
+               .endm
+
+#elif defined(CONFIG_ARCH_LH7A404)
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     \irqnr, #0                      @ VIC1 irq base
+                mov     \base, #io_p2v(0x80000000)      @ APB registers
+                add     \base, \base, #0x8000
+                ldr     \tmp, [\base, #0x0030]          @ VIC1_VECTADDR
+                tst     \tmp, #VA_VECTORED              @ Direct vectored
+                bne     1002f
+                tst     \tmp, #VA_VIC1DEFAULT           @ Default vectored VIC1
+                ldrne   \irqstat, [\base, #0]           @ VIC1_IRQSTATUS
+                bne     1001f
+                add     \base, \base, #(0xa000 - 0x8000)
+                ldr     \tmp, [\base, #0x0030]          @ VIC2_VECTADDR
+                tst     \tmp, #VA_VECTORED              @ Direct vectored
+                bne     1002f
+                ldr     \irqstat, [\base, #0]           @ VIC2_IRQSTATUS
+                mov     \irqnr, #32                     @ VIC2 irq base
+
+1001:           movs    \irqstat, \irqstat, lsr #1      @ Shift into carry
+                bcs     1008f                           @ Bit set; irq found
+                add     \irqnr, \irqnr, #1
+                bne     1001b                           @ Until no bits
+                b       1009f                           @ Nothing?  Hmm.
+1002:           and     \irqnr, \tmp, #0x3f             @ Mask for valid bits
+1008:           movs    \irqstat, #1                    @ Force !Z
+                str     \tmp, [\base, #0x0030]          @ Clear vector
+1009:
+               .endm
+#endif
+
+
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h
new file mode 100644
index 000000000000..aeb07c162e25
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/hardware.h
@@ -0,0 +1,58 @@
+/* include/asm-arm/arch-lh7a40x/hardware.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  [ Substantially cribbed from include/asm-arm/arch-pxa/hardware.h ]
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
+#define io_v2p(x) (             (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
+
+#ifdef __ASSEMBLY__
+
+# define __REG(x)       io_p2v(x)
+# define __PREG(x)      io_v2p(x)
+
+#else
+
+# if 0
+#  define __REG(x)      (*((volatile u32 *)io_p2v(x)))
+# else
+/*
+ * This __REG() version gives the same results as the one above,  except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers.  It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+#include <asm/types.h>
+typedef struct { volatile u32 offset[4096]; } __regbase;
+# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x)       __REGP(io_p2v(x))
+typedef struct { volatile u16 offset[4096]; } __regbase16;
+# define __REGP16(x)    ((__regbase16 *)((x)&~4095))->offset[((x)&4095)>>1]
+# define __REG16(x)     __REGP16(io_p2v(x))
+typedef struct { volatile u8 offset[4096]; } __regbase8;
+# define __REGP8(x)     ((__regbase8 *)((x)&~4095))->offset[(x)&4095]
+# define __REG8(x)      __REGP8(io_p2v(x))
+#endif
+
+/* Let's kick gcc's ass again... */
+# define __REG2(x,y)    \
+        ( __builtin_constant_p(y) ? (__REG((x) + (y))) \
+                                  : (*(volatile u32 *)((u32)&__REG(x) + (y))) )
+
+# define __PREG(x)      (io_v2p((u32)&(x)))
+
+#endif
+
+#include "registers.h"
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lh7a40x/io.h b/include/asm-arm/arch-lh7a40x/io.h
new file mode 100644
index 000000000000..c13bdd9add92
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/io.h
@@ -0,0 +1,21 @@
+/* include/asm-arm/arch-lh7a40x/io.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* No ISA or PCI bus on this machine. */
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+#endif /* __ASM_ARCH_IO_H */
diff --git a/include/asm-arm/arch-lh7a40x/irq.h b/include/asm-arm/arch-lh7a40x/irq.h
new file mode 100644
index 000000000000..0f5f0b10f6ca
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/irq.h
@@ -0,0 +1,11 @@
+/* include/asm-arm/arch-lh7a40x/irq.h
+ *
+ *  Copyright (C) 2004 Logic Product Development
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+void __init lh7a40x_init_board_irq (void);
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h
new file mode 100644
index 000000000000..f91f3e59f3ab
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/irqs.h
@@ -0,0 +1,196 @@
+/* include/asm-arm/arch-lh7a40x/irqs.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *  Copyright (C) 2004 Logic Product Development
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+/* It is to be seen whether or not we can build a kernel for more than
+ * one board.  For the time being, these macros assume that we cannot.
+ * Thus, it is OK to ifdef machine/board specific IRQ assignments.
+ */
+
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include <linux/config.h>
+
+#define FIQ_START       80
+
+#if defined (CONFIG_ARCH_LH7A400)
+
+  /* FIQs */
+
+# define IRQ_GPIO0FIQ   0       /* GPIO External FIQ Interrupt on F0 */
+# define IRQ_BLINT      1       /* Battery Low */
+# define IRQ_WEINT      2       /* Watchdog Timer, WDT overflow */
+# define IRQ_MCINT      3       /* Media Change, MEDCHG pin rising */
+
+  /* IRQs */
+
+# define IRQ_CSINT      4       /* Audio Codec (ACI) */
+# define IRQ_GPIO1INTR  5       /* GPIO External IRQ Interrupt on F1 */
+# define IRQ_GPIO2INTR  6       /* GPIO External IRQ Interrupt on F2 */
+# define IRQ_GPIO3INTR  7       /* GPIO External IRQ Interrupt on F3 */
+# define IRQ_T1UI       8       /* Timer 1 underflow */
+# define IRQ_T2UI       9       /* Timer 2 underflow */
+# define IRQ_RTCMI      10
+# define IRQ_TINTR      11      /* Clock State Controller 64 Hz tick (CSC) */
+# define IRQ_UART1INTR  12
+# define IRQ_UART2INTR  13
+# define IRQ_LCDINTR    14
+# define IRQ_SSIEOT     15      /* Synchronous Serial Interface (SSI) */
+# define IRQ_UART3INTR  16
+# define IRQ_SCIINTR    17      /* Smart Card Interface (SCI) */
+# define IRQ_AACINTR    18      /* Advanced Audio Codec (AAC) */
+# define IRQ_MMCINTR    19      /* Multimedia Card (MMC) */
+# define IRQ_USBINTR    20
+# define IRQ_DMAINTR    21
+# define IRQ_T3UI       22      /* Timer 3 underflow */
+# define IRQ_GPIO4INTR  23      /* GPIO External IRQ Interrupt on F4 */
+# define IRQ_GPIO5INTR  24      /* GPIO External IRQ Interrupt on F5 */
+# define IRQ_GPIO6INTR  25      /* GPIO External IRQ Interrupt on F6 */
+# define IRQ_GPIO7INTR  26      /* GPIO External IRQ Interrupt on F7 */
+# define IRQ_BMIINTR    27      /* Battery Monitor Interface (BMI) */
+
+# define NR_IRQ_CPU     28      /* IRQs directly recognized by CPU */
+
+        /* Given IRQ, return GPIO interrupt number 0-7 */
+# define IRQ_TO_GPIO(i)  ((i) \
+        - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
+        - (((i) > IRQ_GPIO0INTR) ? IRQ_GPIO1INTR - IRQ_GPIO0INTR - 1 : 0))
+
+#endif
+
+#if defined (CONFIG_ARCH_LH7A404)
+
+# define IRQ_BROWN      0       /* Brownout */
+# define IRQ_WDTINTR    1       /* Watchdog Timer */
+# define IRQ_COMMRX     2       /* ARM Comm Rx for Debug */
+# define IRQ_COMMTX     3       /* ARM Comm Tx for Debug */
+# define IRQ_T1UI       4       /* Timer 1 underflow */
+# define IRQ_T2UI       5       /* Timer 2 underflow */
+# define IRQ_CSINT      6       /* Codec Interrupt (shared by AAC on 404) */
+# define IRQ_DMAM2P0    7       /* -- DMA Memory to Peripheral */
+# define IRQ_DMAM2P1    8
+# define IRQ_DMAM2P2    9
+# define IRQ_DMAM2P3    10
+# define IRQ_DMAM2P4    11
+# define IRQ_DMAM2P5    12
+# define IRQ_DMAM2P6    13
+# define IRQ_DMAM2P7    14
+# define IRQ_DMAM2P8    15
+# define IRQ_DMAM2P9    16
+# define IRQ_DMAM2M0    17      /* -- DMA Memory to Memory */
+# define IRQ_DMAM2M1    18
+# define IRQ_GPIO0INTR  19      /* -- GPIOF Interrupt */
+# define IRQ_GPIO1INTR  20
+# define IRQ_GPIO2INTR  21
+# define IRQ_GPIO3INTR  22
+# define IRQ_SOFT_V1_23 23      /* -- Unassigned */
+# define IRQ_SOFT_V1_24 24
+# define IRQ_SOFT_V1_25 25
+# define IRQ_SOFT_V1_26 26
+# define IRQ_SOFT_V1_27 27
+# define IRQ_SOFT_V1_28 28
+# define IRQ_SOFT_V1_29 29
+# define IRQ_SOFT_V1_30 30
+# define IRQ_SOFT_V1_31 31
+
+# define IRQ_BLINT      32      /* Battery Low */
+# define IRQ_BMIINTR    33      /* Battery Monitor */
+# define IRQ_MCINTR     34      /* Media Change */
+# define IRQ_TINTR      35      /* 64Hz Tick */
+# define IRQ_WEINT      36      /* Watchdog Expired */
+# define IRQ_RTCMI      37      /* Real-time Clock Match */
+# define IRQ_UART1INTR  38      /* UART1 Interrupt (including error) */
+# define IRQ_UART1ERR   39      /* UART1 Error */
+# define IRQ_UART2INTR  40      /* UART2 Interrupt (including error) */
+# define IRQ_UART2ERR   41      /* UART2 Error */
+# define IRQ_UART3INTR  42      /* UART3 Interrupt (including error) */
+# define IRQ_UART3ERR   43      /* UART3 Error */
+# define IRQ_SCIINTR    44      /* Smart Card */
+# define IRQ_TSCINTR    45      /* Touchscreen */
+# define IRQ_KMIINTR    46      /* Keyboard/Mouse (PS/2) */
+# define IRQ_GPIO4INTR  47      /* -- GPIOF Interrupt */
+# define IRQ_GPIO5INTR  48
+# define IRQ_GPIO6INTR  49
+# define IRQ_GPIO7INTR  50
+# define IRQ_T3UI       51      /* Timer 3 underflow */
+# define IRQ_LCDINTR    52      /* LCD Controller */
+# define IRQ_SSPINTR    53      /* Synchronous Serial Port */
+# define IRQ_SDINTR     54      /* Secure Digital Port (MMC) */
+# define IRQ_USBINTR    55      /* USB Device Port */
+# define IRQ_USHINTR    56      /* USB Host Port */
+# define IRQ_SOFT_V2_25 57      /* -- Unassigned */
+# define IRQ_SOFT_V2_26 58
+# define IRQ_SOFT_V2_27 59
+# define IRQ_SOFT_V2_28 60
+# define IRQ_SOFT_V2_29 61
+# define IRQ_SOFT_V2_30 62
+# define IRQ_SOFT_V2_31 63
+
+# define NR_IRQ_CPU     64      /* IRQs directly recognized by CPU */
+
+        /* Given IRQ, return GPIO interrupt number 0-7 */
+# define IRQ_TO_GPIO(i)  ((i) \
+        - (((i) > IRQ_GPIO3INTR) ? IRQ_GPIO4INTR - IRQ_GPIO3INTR - 1 : 0)\
+        - IRQ_GPIO0INTR)
+
+                        /* Vector Address constants */
+# define VA_VECTORED    0x100   /* Set for vectored interrupt */
+# define VA_VIC1DEFAULT 0x200   /* Set as default VECTADDR for VIC1 */
+# define VA_VIC2DEFAULT 0x400   /* Set as default VECTADDR for VIC2 */
+
+#endif
+
+  /* IRQ aliases */
+
+#if !defined (IRQ_GPIO0INTR)
+# define IRQ_GPIO0INTR  IRQ_GPIO0FIQ
+#endif
+#define IRQ_TICK        IRQ_TINTR
+#define IRQ_PCC1_RDY    IRQ_GPIO6INTR   /* PCCard 1 ready */
+#define IRQ_PCC2_RDY    IRQ_GPIO7INTR   /* PCCard 2 ready */
+
+#ifdef CONFIG_MACH_KEV7A400
+# define IRQ_TS         IRQ_GPIOFIQ     /* Touchscreen */
+# define IRQ_CPLD       IRQ_GPIO1INTR   /* CPLD cascade */
+# define IRQ_PCC1_CD    IRQ_GPIO_F2     /* PCCard 1 card detect */
+# define IRQ_PCC2_CD    IRQ_GPIO_F3     /* PCCard 2 card detect */
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define IRQ_CPLD_V28   IRQ_GPIO7INTR   /* CPLD cascade through GPIO_PF7 */
+# define IRQ_CPLD_V34   IRQ_GPIO3INTR   /* CPLD cascade through GPIO_PF3 */
+#endif
+
+  /* System specific IRQs */
+
+#define IRQ_BOARD_START NR_IRQ_CPU
+
+#ifdef CONFIG_MACH_KEV7A400
+# define IRQ_KEV7A400_CPLD      IRQ_BOARD_START
+# define NR_IRQ_BOARD           5
+# define IRQ_KEV7A400_MMC_CD    IRQ_KEV7A400_CPLD + 0   /* MMC Card Detect */
+# define IRQ_KEV7A400_RI2       IRQ_KEV7A400_CPLD + 1   /* Ring Indicator 2 */
+# define IRQ_KEV7A400_IDE_CF    IRQ_KEV7A400_CPLD + 2   /* Compact Flash (?) */
+# define IRQ_KEV7A400_ETH_INT   IRQ_KEV7A400_CPLD + 3   /* Ethernet chip */
+# define IRQ_KEV7A400_INT       IRQ_KEV7A400_CPLD + 4
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define IRQ_LPD7A40X_CPLD      IRQ_BOARD_START
+# define NR_IRQ_BOARD           2
+# define IRQ_LPD7A40X_ETH_INT   IRQ_LPD7A40X_CPLD + 0   /* Ethernet chip */
+# define IRQ_LPD7A400_TS        IRQ_LPD7A40X_CPLD + 1   /* Touch screen */
+#endif
+
+#define NR_IRQS         (NR_IRQ_CPU + NR_IRQ_BOARD)
+
+#endif
diff --git a/include/asm-arm/arch-lh7a40x/memory.h b/include/asm-arm/arch-lh7a40x/memory.h
new file mode 100644
index 000000000000..7e2fea372663
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/memory.h
@@ -0,0 +1,94 @@
+/* include/asm-arm/arch-lh7a40x/memory.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ *
+ *  Refer to <file:Documentation/arm/Sharp-LH/SDRAM> for more information.
+ *
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0xc0000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+#ifdef CONFIG_DISCONTIGMEM
+
+#define NODES_SHIFT     4       /* Up to 16 nodes */
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+#  define KVADDR_TO_NID(addr) \
+  (  ((((unsigned long) (addr) - PAGE_OFFSET) >> 24) &  1)\
+   | ((((unsigned long) (addr) - PAGE_OFFSET) >> 25) & ~1))
+# else  /* 2 banks per node */
+#  define KVADDR_TO_NID(addr) \
+      (((unsigned long) (addr) - PAGE_OFFSET) >> 26)
+# endif
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+#  define PFN_TO_NID(pfn) \
+  (((((pfn) - PHYS_PFN_OFFSET) >> (24 - PAGE_SHIFT)) &  1)\
+ | ((((pfn) - PHYS_PFN_OFFSET) >> (25 - PAGE_SHIFT)) & ~1))
+# else  /* 2 banks per node */
+#  define PFN_TO_NID(pfn) \
+    (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
+#endif
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and return the mem_map of that node.
+ */
+# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and return the mem_map of that node.
+ */
+# define PFN_TO_MAPBASE(pfn)    NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+
+# ifdef CONFIG_LH7A40X_ONE_BANK_PER_NODE
+#  define LOCAL_MAP_NR(addr) \
+       (((unsigned long)(addr) & 0x003fffff) >> PAGE_SHIFT)
+# else  /* 2 banks per node */
+#  define LOCAL_MAP_NR(addr) \
+       (((unsigned long)(addr) & 0x01ffffff) >> PAGE_SHIFT)
+# endif
+
+#else
+
+# define PFN_TO_NID(addr)       (0)
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-lh7a40x/param.h b/include/asm-arm/arch-lh7a40x/param.h
new file mode 100644
index 000000000000..acad0bc5deba
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/param.h
@@ -0,0 +1,9 @@
+/* include/asm-arm/arch-lh7a40x/param.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h
new file mode 100644
index 000000000000..2edb22e35450
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/registers.h
@@ -0,0 +1,193 @@
+/* include/asm-arm/arch-lh7a40x/registers.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *  Copyright (C) 2004 Logic Product Development
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/config.h>
+#include <asm/arch/constants.h>
+
+#ifndef __ASM_ARCH_REGISTERS_H
+#define __ASM_ARCH_REGISTERS_H
+
+
+        /* Physical register base addresses */
+
+#define AC97_PHYS       (0x80000000)    /* AC97 Controller */
+#define MMC_PHYS        (0x80000100)    /* Multimedia Card Controller */
+#define USB_PHYS        (0x80000200)    /* USB Client */
+#define SCI_PHYS        (0x80000300)    /* Secure Card Interface */
+#define CSC_PHYS        (0x80000400)    /* Clock/State Controller  */
+#define INTC_PHYS       (0x80000500)    /* Interrupt Controller */
+#define UART1_PHYS      (0x80000600)    /* UART1 Controller */
+#define SIR_PHYS        (0x80000600)    /* IR Controller, same are UART1 */
+#define UART2_PHYS      (0x80000700)    /* UART2 Controller */
+#define UART3_PHYS      (0x80000800)    /* UART3 Controller */
+#define DCDC_PHYS       (0x80000900)    /* DC to DC Controller */
+#define ACI_PHYS        (0x80000a00)    /* Audio Codec Interface */
+#define SSP_PHYS        (0x80000b00)    /* Synchronous ... */
+#define TIMER_PHYS      (0x80000c00)    /* Timer Controller */
+#define RTC_PHYS        (0x80000d00)    /* Real-time Clock */
+#define GPIO_PHYS       (0x80000e00)    /* General Purpose IO */
+#define BMI_PHYS        (0x80000f00)    /* Battery Monitor Interface */
+#define WDT_PHYS        (0x80001400)    /* Watchdog Timer */
+#define SMC_PHYS        (0x80002000)    /* Static Memory Controller */
+#define SDRC_PHYS       (0x80002400)    /* SDRAM Controller */
+#define DMAC_PHYS       (0x80002800)    /* DMA Controller */
+#define CLCDC_PHYS      (0x80003000)    /* Color LCD Controller */
+
+        /* Physical registers of the LH7A404 */
+
+#define VIC1_PHYS       (0x80008000)    /* Vectored Interrupt Controller 1 */
+#define USBH_PHYS       (0x80009000)    /* USB OHCI host controller */
+#define VIC2_PHYS       (0x8000a000)    /* Vectored Interrupt Controller 2 */
+
+/*#define KBD_PHYS      (0x80000e00) */
+/*#define LCDICP_PHYS   (0x80001000) */
+
+
+        /* Clock/State Controller register */
+
+#define CSC_PWRCNT      __REG(CSC_PHYS + 0x04) /* Power control */
+
+#define CSC_PWRCNT_USBH_EN      (1<<28) /* USB Host power enable */
+
+
+        /* Interrupt Controller registers */
+
+#define INTC_INTSR      __REG(INTC_PHYS + 0x00) /* Status */
+#define INTC_INTRSR     __REG(INTC_PHYS + 0x04) /* Raw Status */
+#define INTC_INTENS     __REG(INTC_PHYS + 0x08) /* Enable Set */
+#define INTC_INTENC     __REG(INTC_PHYS + 0x0c) /* Enable Clear */
+
+
+        /* Vectored Interrupted Controller registers */
+
+#define VIC1_IRQSTATUS  __REG(VIC1_PHYS + 0x00)
+#define VIC1_FIQSTATUS  __REG(VIC1_PHYS + 0x04)
+#define VIC1_RAWINTR    __REG(VIC1_PHYS + 0x08)
+#define VIC1_INTSEL     __REG(VIC1_PHYS + 0x0c)
+#define VIC1_INTEN      __REG(VIC1_PHYS + 0x10)
+#define VIC1_INTENCLR   __REG(VIC1_PHYS + 0x14)
+#define VIC1_SOFTINT    __REG(VIC1_PHYS + 0x18)
+#define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
+#define VIC1_PROTECT    __REG(VIC1_PHYS + 0x20)
+#define VIC1_VECTADDR   __REG(VIC1_PHYS + 0x30)
+#define VIC1_NVADDR     __REG(VIC1_PHYS + 0x34)
+#define VIC1_VAD0       __REG(VIC1_PHYS + 0x100)
+#define VIC1_VECTCNTL0  __REG(VIC1_PHYS + 0x200)
+#define VIC2_IRQSTATUS  __REG(VIC2_PHYS + 0x00)
+#define VIC2_FIQSTATUS  __REG(VIC2_PHYS + 0x04)
+#define VIC2_RAWINTR    __REG(VIC2_PHYS + 0x08)
+#define VIC2_INTSEL     __REG(VIC2_PHYS + 0x0c)
+#define VIC2_INTEN      __REG(VIC2_PHYS + 0x10)
+#define VIC2_INTENCLR   __REG(VIC2_PHYS + 0x14)
+#define VIC2_SOFTINT    __REG(VIC2_PHYS + 0x18)
+#define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
+#define VIC2_PROTECT    __REG(VIC2_PHYS + 0x20)
+#define VIC2_VECTADDR   __REG(VIC2_PHYS + 0x30)
+#define VIC2_NVADDR     __REG(VIC2_PHYS + 0x34)
+#define VIC2_VAD0       __REG(VIC2_PHYS + 0x100)
+#define VIC2_VECTCNTL0  __REG(VIC2_PHYS + 0x200)
+
+#define VIC_CNTL_ENABLE (0x20)
+
+        /* USB Host registers (Open HCI compatible) */
+
+#define USBH_CMDSTATUS  __REG(USBH_PHYS + 0x08)
+
+
+        /* GPIO registers */
+
+#define GPIO_INTTYPE1   __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
+#define GPIO_INTTYPE2   __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
+#define GPIO_GPIOFEOI   __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
+#define GPIO_GPIOINTEN  __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
+#define GPIO_INTSTATUS  __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
+
+
+        /* Static Memory Controller registers */
+
+#define SMC_BCR0        __REG(SMC_PHYS + 0x00)  /* Bank 0 Configuration */
+#define SMC_BCR1        __REG(SMC_PHYS + 0x04)  /* Bank 1 Configuration */
+#define SMC_BCR2        __REG(SMC_PHYS + 0x08)  /* Bank 2 Configuration */
+#define SMC_BCR3        __REG(SMC_PHYS + 0x0C)  /* Bank 3 Configuration */
+#define SMC_BCR6        __REG(SMC_PHYS + 0x18)  /* Bank 6 Configuration */
+#define SMC_BCR7        __REG(SMC_PHYS + 0x1c)  /* Bank 7 Configuration */
+
+
+#ifdef CONFIG_MACH_KEV7A400
+# define CPLD_RD_OPT_DIP_SW     __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
+# define CPLD_WR_IO_BRD_CTL     __REG16(CPLD_PHYS + 0x00) /* Write Control */
+# define CPLD_RD_PB_KEYS        __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
+# define CPLD_LATCHED_INTS      __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
+# define CPLD_CL_INT            __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
+# define CPLD_BOOT_MMC_STATUS   __REG16(CPLD_PHYS + 0x06) /* R/O */
+# define CPLD_RD_KPD_ROW_SENSE  __REG16(CPLD_PHYS + 0x08)
+# define CPLD_WR_PB_INT_MASK    __REG16(CPLD_PHYS + 0x08)
+# define CPLD_RD_BRD_DISP_SW    __REG16(CPLD_PHYS + 0x0a)
+# define CPLD_WR_EXT_INT_MASK   __REG16(CPLD_PHYS + 0x0a)
+# define CPLD_LCD_PWR_CNTL      __REG16(CPLD_PHYS + 0x0c)
+# define CPLD_SEVEN_SEG         __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
+
+#endif
+
+#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
+# define CPLD_CONTROL           __REG8(CPLD02_PHYS)
+# define CPLD_SPI_DATA          __REG8(CPLD06_PHYS)
+# define CPLD_SPI_CONTROL       __REG8(CPLD08_PHYS)
+# define CPLD_SPI_EEPROM        __REG8(CPLD0A_PHYS)
+# define CPLD_INTERRUPTS        __REG8(CPLD0C_PHYS) /* IRQ mask/status */
+# define CPLD_BOOT_MODE         __REG8(CPLD0E_PHYS)
+# define CPLD_FLASH             __REG8(CPLD10_PHYS)
+# define CPLD_POWER_MGMT        __REG8(CPLD12_PHYS)
+# define CPLD_REVISION          __REG8(CPLD14_PHYS)
+# define CPLD_GPIO_EXT          __REG8(CPLD16_PHYS)
+# define CPLD_GPIO_DATA         __REG8(CPLD18_PHYS)
+# define CPLD_GPIO_DIR          __REG8(CPLD1A_PHYS)
+#endif
+
+
+        /* Timer registers */
+
+#define TIMER_LOAD1     __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
+#define TIMER_VALUE1    __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
+#define TIMER_CONTROL1  __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
+#define TIMER_EOI1      __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
+
+#define TIMER_LOAD2     __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
+#define TIMER_VALUE2    __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
+#define TIMER_CONTROL2  __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
+#define TIMER_EOI2      __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
+
+#define TIMER_BUZZCON   __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
+
+#define TIMER_LOAD3     __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
+#define TIMER_VALUE3    __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
+#define TIMER_CONTROL3  __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
+#define TIMER_EOI3      __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
+
+#define TIMER_C_ENABLE          (1<<7)
+#define TIMER_C_PERIODIC        (1<<6)
+#define TIMER_C_FREERUNNING     (0)
+#define TIMER_C_2KHZ            (0x00)          /* 1.986 kHz */
+#define TIMER_C_508KHZ          (0x08)
+
+        /* GPIO registers */
+
+#define GPIO_PFDD               __REG(GPIO_PHYS + 0x34) /* PF direction */
+#define GPIO_INTTYPE1           __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl  */
+#define GPIO_INTTYPE2           __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
+#define GPIO_GPIOFEOI           __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
+#define GPIO_GPIOFINTEN         __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
+#define GPIO_INTSTATUS          __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
+#define GPIO_RAWINTSTATUS       __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
+
+
+#endif  /* _ASM_ARCH_REGISTERS_H */
+
diff --git a/include/asm-arm/arch-lh7a40x/system.h b/include/asm-arm/arch-lh7a40x/system.h
new file mode 100644
index 000000000000..e1df8aa460f2
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/system.h
@@ -0,0 +1,19 @@
+/* include/asm-arm/arch-lh7a40x/system.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle ();
+}
+
+static inline void arch_reset(char mode)
+{
+        cpu_reset (0);
+}
diff --git a/include/asm-arm/arch-lh7a40x/timex.h b/include/asm-arm/arch-lh7a40x/timex.h
new file mode 100644
index 000000000000..fa726b670829
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/timex.h
@@ -0,0 +1,17 @@
+/* include/asm-arm/arch-lh7a40x/timex.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/arch/constants.h>
+
+#define CLOCK_TICK_RATE         (PLL_CLOCK/6/16)
+
+/*
+#define CLOCK_TICK_RATE         3686400
+*/
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
new file mode 100644
index 000000000000..ec8ab67122f3
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -0,0 +1,43 @@
+/* include/asm-arm/arch-lh7a40x/uncompress.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+#include <asm/arch/registers.h>
+
+#ifndef UART_R_DATA
+# define UART_R_DATA    (0x00)
+#endif
+#ifndef UART_R_STATUS
+# define UART_R_STATUS  (0x10)
+#endif
+#define nTxRdy          (0x20)  /* Not TxReady (literally Tx FIFO full) */
+
+        /* Access UART with physical addresses before MMU is setup */
+#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
+#define UART_DATA   (*(volatile unsigned long*) (UART2_PHYS + UART_R_DATA))
+
+static __inline__ void putc (char ch)
+{
+        while (UART_STATUS & nTxRdy)
+                ;
+        UART_DATA = ch;
+}
+
+static void putstr (const char* sz)
+{
+        for (; *sz; ++sz) {
+                putc (*sz);
+                if (*sz == '\n')
+                        putc ('\r');
+        }
+}
+
+        /* NULL functions; we don't presently need them */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-lh7a40x/vmalloc.h b/include/asm-arm/arch-lh7a40x/vmalloc.h
new file mode 100644
index 000000000000..5ac607925bea
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/vmalloc.h
@@ -0,0 +1,21 @@
+/* include/asm-arm/arch-lh7a40x/vmalloc.h
+ *
+ *  Copyright (C) 2004 Coastal Environmental Systems
+ *
+ *  This program is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU General Public License
+ *  version 2 as published by the Free Software Foundation.
+ *
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after
+ * the physical memory until the kernel virtual memory starts.  That
+ * means that any out-of-bounds memory accesses will hopefully be
+ * caught.  The vmalloc() routines leaves a hole of 4kB (one page)
+ * between each vmalloced area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-omap/aic23.h b/include/asm-arm/arch-omap/aic23.h
new file mode 100644
index 000000000000..590bac25b7c4
--- /dev/null
+++ b/include/asm-arm/arch-omap/aic23.h
@@ -0,0 +1,112 @@
+/*
+ * linux/include/asm-arm/arch-omap/aic23.h
+ *
+ * Hardware definitions for TI TLV320AIC23 audio codec
+ *
+ * Copyright (C) 2002 RidgeRun, Inc.
+ * Author: Steve Johnson
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_AIC23_H
+#define __ASM_ARCH_AIC23_H
+
+// Codec TLV320AIC23
+#define LEFT_LINE_VOLUME_ADDR           0x00
+#define RIGHT_LINE_VOLUME_ADDR          0x01
+#define LEFT_CHANNEL_VOLUME_ADDR        0x02
+#define RIGHT_CHANNEL_VOLUME_ADDR       0x03
+#define ANALOG_AUDIO_CONTROL_ADDR       0x04
+#define DIGITAL_AUDIO_CONTROL_ADDR      0x05
+#define POWER_DOWN_CONTROL_ADDR         0x06
+#define DIGITAL_AUDIO_FORMAT_ADDR       0x07
+#define SAMPLE_RATE_CONTROL_ADDR        0x08
+#define DIGITAL_INTERFACE_ACT_ADDR      0x09
+#define RESET_CONTROL_ADDR              0x0F
+
+// Left (right) line input volume control register
+#define LRS_ENABLED                     0x0100
+#define LIM_MUTED                       0x0080
+#define LIV_DEFAULT                     0x0017
+#define LIV_MAX                         0x001f
+#define LIV_MIN                         0x0000
+
+// Left (right) channel headphone volume control register
+#define LZC_ON                          0x0080
+#define LHV_DEFAULT                     0x0079
+#define LHV_MAX                         0x007f
+#define LHV_MIN                         0x0000
+
+// Analog audio path control register
+#define STE_ENABLED                     0x0020
+#define DAC_SELECTED                    0x0010
+#define BYPASS_ON                       0x0008
+#define INSEL_MIC                       0x0004
+#define MICM_MUTED                      0x0002
+#define MICB_20DB                       0x0001
+
+// Digital audio path control register
+#define DACM_MUTE                       0x0008
+#define DEEMP_32K                       0x0002
+#define DEEMP_44K                       0x0004
+#define DEEMP_48K                       0x0006
+#define ADCHP_ON                        0x0001
+
+// Power control down register
+#define DEVICE_POWER_OFF                0x0080
+#define CLK_OFF                         0x0040
+#define OSC_OFF                         0x0020
+#define OUT_OFF                         0x0010
+#define DAC_OFF                         0x0008
+#define ADC_OFF                         0x0004
+#define MIC_OFF                         0x0002
+#define LINE_OFF                        0x0001
+
+// Digital audio interface register
+#define MS_MASTER                       0x0040
+#define LRSWAP_ON                       0x0020
+#define LRP_ON                          0x0010
+#define IWL_16                          0x0000
+#define IWL_20                          0x0004
+#define IWL_24                          0x0008
+#define IWL_32                          0x000C
+#define FOR_I2S                         0x0002
+#define FOR_DSP                         0x0003
+
+// Sample rate control register
+#define CLKOUT_HALF                     0x0080
+#define CLKIN_HALF                      0x0040
+#define BOSR_384fs                      0x0002 // BOSR_272fs when in USB mode
+#define USB_CLK_ON                      0x0001
+#define SR_MASK                         0xf
+#define CLKOUT_SHIFT                    7
+#define CLKIN_SHIFT                     6
+#define SR_SHIFT                        2
+#define BOSR_SHIFT                      1
+
+// Digital interface register
+#define ACT_ON                          0x0001
+
+#define TLV320AIC23ID1                  (0x1a)  // cs low
+#define TLV320AIC23ID2                  (0x1b)  // cs high
+
+#endif /* __ASM_ARCH_AIC23_H */
diff --git a/include/asm-arm/arch-omap/board-h2.h b/include/asm-arm/arch-omap/board-h2.h
new file mode 100644
index 000000000000..60f002b72983
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-h2.h
@@ -0,0 +1,47 @@
+/*
+ * linux/include/asm-arm/arch-omap/board-h2.h
+ *
+ * Hardware definitions for TI OMAP1610 H2 board.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_H2_H
+#define __ASM_ARCH_OMAP_H2_H
+
+/* Placeholder for H2 specific defines */
+
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define OMAP1610_ETHR_START             0x04000300
+
+/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
+#define OMAP_NOR_FLASH_SIZE             SZ_32M
+#define OMAP_NOR_FLASH_START1           0x0C000000 /* CS3 */
+#define OMAP_NOR_FLASH_START2           0x0A000000 /* CS2B */
+
+/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
+#define OMAP_NAND_FLASH_START1           0x0A000000 /* CS2B */
+#define OMAP_NAND_FLASH_START2           0x0C000000 /* CS3 */
+
+#endif /*  __ASM_ARCH_OMAP_H2_H */
+
diff --git a/include/asm-arm/arch-omap/board-h3.h b/include/asm-arm/arch-omap/board-h3.h
new file mode 100644
index 000000000000..e4d1cd231731
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-h3.h
@@ -0,0 +1,49 @@
+/*
+ * linux/include/asm-arm/arch-omap/board-h3.h
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Copyright (C) 2004 Texas Instruments, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_H3_H
+#define __ASM_ARCH_OMAP_H3_H
+
+/* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
+#define OMAP1710_ETHR_START             0x04000300
+
+/* Intel STRATA NOR flash at CS3 or CS2B(NAND Boot) */
+#define OMAP_NOR_FLASH_SIZE             SZ_32M
+#define OMAP_NOR_FLASH_START1           0x0C000000 /* CS3 */
+#define OMAP_NOR_FLASH_START2           0x0A000000 /* CS2B */
+
+/* Samsung NAND flash at CS2B or CS3(NAND Boot) */
+#define OMAP_NAND_FLASH_START1           0x0A000000 /* CS2B */
+#define OMAP_NAND_FLASH_START2           0x0C000000 /* CS3 */
+
+#define MAXIRQNUM                       (IH_BOARD_BASE)
+#define MAXFIQNUM                       MAXIRQNUM
+#define MAXSWINUM                       MAXIRQNUM
+
+#define NR_IRQS                         (MAXIRQNUM + 1)
+
+
+#endif /*  __ASM_ARCH_OMAP_H3_H */
diff --git a/include/asm-arm/arch-omap/board-h4.h b/include/asm-arm/arch-omap/board-h4.h
new file mode 100644
index 000000000000..79138dcfb4ac
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-h4.h
@@ -0,0 +1,35 @@
+/*
+ * linux/include/asm-arm/arch-omap/board-h4.h
+ *
+ * Hardware definitions for TI OMAP1610 H4 board.
+ *
+ * Initial creation by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_H4_H
+#define __ASM_ARCH_OMAP_H4_H
+
+/* Placeholder for H4 specific defines */
+
+#endif /*  __ASM_ARCH_OMAP_H4_H */
+
diff --git a/include/asm-arm/arch-omap/board-innovator.h b/include/asm-arm/arch-omap/board-innovator.h
new file mode 100644
index 000000000000..0f1abaefe4de
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-innovator.h
@@ -0,0 +1,80 @@
+/*
+ * linux/include/asm-arm/arch-omap/board-innovator.h
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_INNOVATOR_H
+#define __ASM_ARCH_OMAP_INNOVATOR_H
+
+#if defined (CONFIG_ARCH_OMAP1510)
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE                       D256M_1X16_4B
+#endif
+
+#define OMAP1510P1_IMIF_PRI_VALUE               0x00
+#define OMAP1510P1_EMIFS_PRI_VALUE              0x00
+#define OMAP1510P1_EMIFF_PRI_VALUE              0x00
+
+/*
+ * These definitions define an area of FLASH set aside
+ * for the use of MTD/JFFS2. This is the area of flash
+ * that a JFFS2 filesystem will reside which is mounted
+ * at boot with the "root=/dev/mtdblock/0 rw"
+ * command line option. The flash address used here must
+ * fall within the legal range defined by rrload for storing
+ * the filesystem component. This address will be sufficiently
+ * deep into the overall flash range to avoid the other
+ * components also stored in flash such as the bootloader,
+ * the bootloader params, and the kernel.
+ * The SW2 settings for the map below are:
+ * 1 off, 2 off, 3 on, 4 off.
+ */
+
+/* Intel flash_0, partitioned as expected by rrload */
+#define OMAP_FLASH_0_BASE       0xD8000000
+#define OMAP_FLASH_0_START      0x00000000
+#define OMAP_FLASH_0_SIZE       SZ_16M
+
+/* Intel flash_1, used for cramfs or other flash file systems */
+#define OMAP_FLASH_1_BASE       0xD9000000
+#define OMAP_FLASH_1_START      0x01000000
+#define OMAP_FLASH_1_SIZE       SZ_16M
+
+#define NR_FPGA_IRQS            24
+#define NR_IRQS                 IH_BOARD_BASE + NR_FPGA_IRQS
+
+#ifndef __ASSEMBLY__
+void fpga_write(unsigned char val, int reg);
+unsigned char fpga_read(int reg);
+#endif
+
+#endif /* CONFIG_ARCH_OMAP1510 */
+
+#if defined (CONFIG_ARCH_OMAP16XX)
+
+/* At OMAP1610 Innovator the Ethernet is directly connected to CS1 */
+#define INNOVATOR1610_ETHR_START        0x04000300
+
+#endif /* CONFIG_ARCH_OMAP1610 */
+#endif /* __ASM_ARCH_OMAP_INNOVATOR_H */
diff --git a/include/asm-arm/arch-omap/board-netstar.h b/include/asm-arm/arch-omap/board-netstar.h
new file mode 100644
index 000000000000..77cc0fb54d54
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-netstar.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
+ *
+ * Hardware definitions for OMAP5910 based NetStar board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_NETSTAR_H
+#define __ASM_ARCH_NETSTAR_H
+
+#include <asm/arch/tc.h>
+
+#define OMAP_NAND_FLASH_START1          OMAP_CS1_PHYS + (1 << 23)
+#define OMAP_NAND_FLASH_START2          OMAP_CS1_PHYS + (2 << 23)
+
+#endif /*  __ASM_ARCH_NETSTAR_H */
diff --git a/include/asm-arm/arch-omap/board-osk.h b/include/asm-arm/arch-omap/board-osk.h
new file mode 100644
index 000000000000..aaa49a0fbd21
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-osk.h
@@ -0,0 +1,41 @@
+/*
+ * linux/include/asm-arm/arch-omap/board-osk.h
+ *
+ * Hardware definitions for TI OMAP5912 OSK board.
+ *
+ * Written by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_OSK_H
+#define __ASM_ARCH_OMAP_OSK_H
+
+/* At OMAP5912 OSK the Ethernet is directly connected to CS1 */
+#define OMAP_OSK_ETHR_START             0x04800300
+
+/* Micron NOR flash at CS3 mapped to address 0x0 if BM bit is 1 */
+#define OMAP_OSK_NOR_FLASH_BASE         0xD8000000
+#define OMAP_OSK_NOR_FLASH_SIZE         SZ_32M
+#define OMAP_OSK_NOR_FLASH_START        0x00000000
+
+#endif /*  __ASM_ARCH_OMAP_OSK_H */
+
diff --git a/include/asm-arm/arch-omap/board-perseus2.h b/include/asm-arm/arch-omap/board-perseus2.h
new file mode 100644
index 000000000000..0c224cc74fe4
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-perseus2.h
@@ -0,0 +1,58 @@
+/*
+ *  linux/include/asm-arm/arch-omap/board-perseus2.h
+ *
+ *  Copyright 2003 by Texas Instruments Incorporated
+ *    OMAP730 / Perseus2 support by Jean Pihet
+ *
+ * Copyright (C) 2001 RidgeRun, Inc. (http://www.ridgerun.com)
+ * Author: RidgeRun, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef __ASM_ARCH_OMAP_PERSEUS2_H
+#define __ASM_ARCH_OMAP_PERSEUS2_H
+
+#include <asm/arch/fpga.h>
+
+#ifndef OMAP_SDRAM_DEVICE
+#define OMAP_SDRAM_DEVICE               D256M_1X16_4B
+#endif
+
+/*
+ * These definitions define an area of FLASH set aside
+ * for the use of MTD/JFFS2. This is the area of flash
+ * that a JFFS2 filesystem will reside which is mounted
+ * at boot with the "root=/dev/mtdblock/0 rw"
+ * command line option.
+ */
+
+/* Intel flash_0, partitioned as expected by rrload */
+#define OMAP_FLASH_0_BASE       0xD8000000      /* VA */
+#define OMAP_FLASH_0_START      0x00000000      /* PA */
+#define OMAP_FLASH_0_SIZE       SZ_32M
+
+#define MAXIRQNUM               IH_BOARD_BASE
+#define MAXFIQNUM               MAXIRQNUM
+#define MAXSWINUM               MAXIRQNUM
+
+#define NR_IRQS                 (MAXIRQNUM + 1)
+
+#endif
diff --git a/include/asm-arm/arch-omap/board-voiceblue.h b/include/asm-arm/arch-omap/board-voiceblue.h
new file mode 100644
index 000000000000..33977b8956fb
--- /dev/null
+++ b/include/asm-arm/arch-omap/board-voiceblue.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2004 2N Telekomunikace, Ladislav Michl <michl@2n.cz>
+ *
+ * Hardware definitions for OMAP5910 based VoiceBlue board.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_VOICEBLUE_H
+#define __ASM_ARCH_VOICEBLUE_H
+
+#if (EXTERNAL_MAX_NR_PORTS < 4)
+#undef EXTERNAL_MAX_NR_PORTS
+#define EXTERNAL_MAX_NR_PORTS   4
+#endif
+
+extern void voiceblue_wdt_enable(void);
+extern void voiceblue_wdt_disable(void);
+extern void voiceblue_wdt_ping(void);
+extern void voiceblue_reset(void);
+
+#endif /*  __ASM_ARCH_VOICEBLUE_H */
+
diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h
new file mode 100644
index 000000000000..1cefd60b6f2a
--- /dev/null
+++ b/include/asm-arm/arch-omap/board.h
@@ -0,0 +1,126 @@
+/*
+ *  linux/include/asm-arm/arch-omap/board.h
+ *
+ *  Information structures for board-specific data
+ *
+ *  Copyright (C) 2004  Nokia Corporation
+ *  Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ */
+
+#ifndef _OMAP_BOARD_H
+#define _OMAP_BOARD_H
+
+#include <linux/config.h>
+#include <linux/types.h>
+
+/* Different peripheral ids */
+#define OMAP_TAG_CLOCK          0x4f01
+#define OMAP_TAG_MMC            0x4f02
+#define OMAP_TAG_UART           0x4f03
+#define OMAP_TAG_USB            0x4f04
+#define OMAP_TAG_LCD            0x4f05
+#define OMAP_TAG_GPIO_SWITCH    0x4f06
+
+#define OMAP_TAG_BOOT_REASON    0x4f80
+#define OMAP_TAG_FLASH_PART     0x4f81
+
+struct omap_clock_config {
+        /* 0 for 12 MHz, 1 for 13 MHz and 2 for 19.2 MHz */
+        u8 system_clock_type;
+};
+
+struct omap_mmc_config {
+        u8 mmc_blocks;
+        s16 mmc1_power_pin, mmc2_power_pin;
+        s16 mmc1_switch_pin, mmc2_switch_pin;
+};
+
+struct omap_uart_config {
+        u8 console_uart;
+        u32 console_speed;
+};
+
+struct omap_usb_config {
+        /* Configure drivers according to the connectors on your board:
+         *  - "A" connector (rectagular)
+         *      ... for host/OHCI use, set "register_host".
+         *  - "B" connector (squarish) or "Mini-B"
+         *      ... for device/gadget use, set "register_dev".
+         *  - "Mini-AB" connector (very similar to Mini-B)
+         *      ... for OTG use as device OR host, initialize "otg"
+         */
+        unsigned        register_host:1;
+        unsigned        register_dev:1;
+        u8              otg;    /* port number, 1-based:  usb1 == 2 */
+
+        u8              hmc_mode;
+
+        /* implicitly true if otg:  host supports remote wakeup? */
+        u8              rwc;
+
+        /* signaling pins used to talk to transceiver on usbN:
+         *  0 == usbN unused
+         *  2 == usb0-only, using internal transceiver
+         *  3 == 3 wire bidirectional
+         *  4 == 4 wire bidirectional
+         *  6 == 6 wire unidirectional (or TLL)
+         */
+        u8              pins[3];
+};
+
+struct omap_lcd_config {
+        char panel_name[16];
+        char ctrl_name[16];
+};
+
+/* Cover:
+ *      high -> closed
+ *      low  -> open
+ * Connection:
+ *      high -> connected
+ *      low  -> disconnected
+ */
+#define OMAP_GPIO_SWITCH_TYPE_COVER             0x0000
+#define OMAP_GPIO_SWITCH_TYPE_CONNECTION        0x0001
+#define OMAP_GPIO_SWITCH_FLAG_INVERTED          0x0001
+struct omap_gpio_switch_config {
+        char name[12];
+        u16 gpio;
+        int flags:4;
+        int type:4;
+        int key_code:24; /* Linux key code */
+};
+
+struct omap_flash_part_config {
+        char part_table[0];
+};
+
+struct omap_boot_reason_config {
+        char reason_str[12];
+};
+
+
+struct omap_board_config_entry {
+        u16 tag;
+        u16 len;
+        u8  data[0];
+};
+
+struct omap_board_config_kernel {
+        u16 tag;
+        const void *data;
+};
+
+extern const void *__omap_get_config(u16 tag, size_t len, int nr);
+
+#define omap_get_config(tag, type) \
+        ((const type *) __omap_get_config((tag), sizeof(type), 0))
+#define omap_get_nr_config(tag, type, nr) \
+        ((const type *) __omap_get_config((tag), sizeof(type), (nr)))
+
+extern const void *omap_get_var_config(u16 tag, size_t *len);
+
+extern struct omap_board_config_kernel *omap_board_config;
+extern int omap_board_config_size;
+
+#endif
diff --git a/include/asm-arm/arch-omap/cpu.h b/include/asm-arm/arch-omap/cpu.h
new file mode 100644
index 000000000000..e8786713ee5c
--- /dev/null
+++ b/include/asm-arm/arch-omap/cpu.h
@@ -0,0 +1,183 @@
+/*
+ * linux/include/asm-arm/arch-omap/cpu.h
+ *
+ * OMAP cpu type detection
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP_CPU_H
+#define __ASM_ARCH_OMAP_CPU_H
+
+extern unsigned int system_rev;
+
+#define OMAP_DIE_ID_0           0xfffe1800
+#define OMAP_DIE_ID_1           0xfffe1804
+#define OMAP_PRODUCTION_ID_0    0xfffe2000
+#define OMAP_PRODUCTION_ID_1    0xfffe2004
+#define OMAP32_ID_0             0xfffed400
+#define OMAP32_ID_1             0xfffed404
+
+/*
+ * Test if multicore OMAP support is needed
+ */
+#undef MULTI_OMAP
+#undef OMAP_NAME
+
+#ifdef CONFIG_ARCH_OMAP730
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP
+#  define MULTI_OMAP
+# else
+#  define OMAP_NAME omap730
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP1510
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP
+#  define MULTI_OMAP
+# else
+#  define OMAP_NAME omap1510
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP
+#  define MULTI_OMAP
+# else
+#  define OMAP_NAME omap1610
+# endif
+#endif
+#ifdef CONFIG_ARCH_OMAP16XX
+# ifdef OMAP_NAME
+#  undef  MULTI_OMAP
+#  define MULTI_OMAP
+# else
+#  define OMAP_NAME omap1710
+# endif
+#endif
+
+/*
+ * Generate various OMAP cpu specific macros, and cpu class
+ * specific macros
+ */
+#define GET_OMAP_TYPE   ((system_rev >> 24) & 0xff)
+#define GET_OMAP_CLASS  (system_rev & 0xff)
+
+#define IS_OMAP_TYPE(type, id)                          \
+static inline int is_omap ##type (void)                 \
+{                                                       \
+        return (GET_OMAP_TYPE == (id)) ? 1 : 0;         \
+}
+
+#define IS_OMAP_CLASS(class, id)                        \
+static inline int is_omap ##class (void)                \
+{                                                       \
+        return (GET_OMAP_CLASS == (id)) ? 1 : 0;        \
+}
+
+IS_OMAP_TYPE(730, 0x07)
+IS_OMAP_TYPE(1510, 0x15)
+IS_OMAP_TYPE(1610, 0x16)
+IS_OMAP_TYPE(5912, 0x16)
+IS_OMAP_TYPE(1710, 0x17)
+IS_OMAP_TYPE(2420, 0x24)
+
+IS_OMAP_CLASS(7xx, 0x07)
+IS_OMAP_CLASS(15xx, 0x15)
+IS_OMAP_CLASS(16xx, 0x16)
+IS_OMAP_CLASS(24xx, 0x24)
+
+/*
+ * Macros to group OMAP types into cpu classes.
+ * These can be used in most places.
+ * cpu_is_omap15xx():   True for 1510 and 5910
+ * cpu_is_omap16xx():   True for 1610, 5912 and 1710
+ */
+#if defined(MULTI_OMAP)
+# define cpu_is_omap7xx()               is_omap7xx()
+# define cpu_is_omap15xx()              is_omap15xx()
+# if !(defined(CONFIG_ARCH_OMAP1510) || defined(CONFIG_ARCH_OMAP730))
+#  define cpu_is_omap16xx()             1
+# else
+#  define cpu_is_omap16xx()             is_omap16xx()
+# endif
+#else
+# if defined(CONFIG_ARCH_OMAP730)
+#  define cpu_is_omap7xx()              1
+# else
+#  define cpu_is_omap7xx()              0
+# endif
+# if defined(CONFIG_ARCH_OMAP1510)
+#  define cpu_is_omap15xx()             1
+# else
+#  define cpu_is_omap15xx()             0
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  define cpu_is_omap16xx()             1
+# else
+#  define cpu_is_omap16xx()             0
+# endif
+#endif
+
+#if defined(MULTI_OMAP)
+# define cpu_is_omap730()               is_omap730()
+# define cpu_is_omap1510()              is_omap1510()
+# define cpu_is_omap1610()              is_omap1610()
+# define cpu_is_omap5912()              is_omap5912()
+# define cpu_is_omap1710()              is_omap1710()
+#else
+# if defined(CONFIG_ARCH_OMAP730)
+#  define cpu_is_omap730()              1
+# else
+#  define cpu_is_omap730()              0
+# endif
+# if defined(CONFIG_ARCH_OMAP1510)
+#  define cpu_is_omap1510()             1
+# else
+#  define cpu_is_omap1510()             0
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  define cpu_is_omap1610()             1
+# else
+#  define cpu_is_omap1610()             0
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+#  define cpu_is_omap5912()             1
+# else
+#  define cpu_is_omap5912()             0
+# endif
+# if defined(CONFIG_ARCH_OMAP16XX)
+# define cpu_is_omap1610()              is_omap1610()
+# define cpu_is_omap5912()              is_omap5912()
+# define cpu_is_omap1710()              is_omap1710()
+# else
+# define cpu_is_omap1610()              0
+# define cpu_is_omap5912()              0
+# define cpu_is_omap1710()              0
+# endif
+# if defined(CONFIG_ARCH_OMAP2420)
+#  define cpu_is_omap2420()             1
+# else
+#  define cpu_is_omap2420()             0
+# endif
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-omap/debug-macro.S b/include/asm-arm/arch-omap/debug-macro.S
new file mode 100644
index 000000000000..83bb458afd0b
--- /dev/null
+++ b/include/asm-arm/arch-omap/debug-macro.S
@@ -0,0 +1,45 @@
+/* linux/include/asm-arm/arch-omap/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0xff000000        @ physical base address
+                movne   \rx, #0xfe000000        @ virtual base
+                orr     \rx, \rx, #0x00fb0000
+#ifdef CONFIG_OMAP_LL_DEBUG_UART3
+                orr     \rx, \rx, #0x00009000   @ UART 3
+#endif
+#if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
+                orr     \rx, \rx, #0x00000800   @ UART 2 & 3
+#endif
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldrb    \rd, [\rx, #(0x5 << 2)] @ OMAP-1510 and friends
+                and     \rd, \rd, #0x60
+                teq     \rd, #0x60
+                beq     1002f
+                ldrb    \rd, [\rx, #(0x5 << 0)] @ OMAP-730 only
+                and     \rd, \rd, #0x60
+                teq     \rd, #0x60
+                bne     1001b
+1002:
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
new file mode 100644
index 000000000000..d785248377db
--- /dev/null
+++ b/include/asm-arm/arch-omap/dma.h
@@ -0,0 +1,264 @@
+/*
+ *  linux/include/asm-arm/arch-omap/dma.h
+ *
+ *  Copyright (C) 2003 Nokia Corporation
+ *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS                 0xffffffff
+
+#define OMAP_LOGICAL_DMA_CH_COUNT       17
+
+#define OMAP_DMA_NO_DEVICE              0
+#define OMAP_DMA_MCSI1_TX               1
+#define OMAP_DMA_MCSI1_RX               2
+#define OMAP_DMA_I2C_RX                 3
+#define OMAP_DMA_I2C_TX                 4
+#define OMAP_DMA_EXT_NDMA_REQ           5
+#define OMAP_DMA_EXT_NDMA_REQ2          6
+#define OMAP_DMA_UWIRE_TX               7
+#define OMAP_DMA_MCBSP1_TX              8
+#define OMAP_DMA_MCBSP1_RX              9
+#define OMAP_DMA_MCBSP3_TX              10
+#define OMAP_DMA_MCBSP3_RX              11
+#define OMAP_DMA_UART1_TX               12
+#define OMAP_DMA_UART1_RX               13
+#define OMAP_DMA_UART2_TX               14
+#define OMAP_DMA_UART2_RX               15
+#define OMAP_DMA_MCBSP2_TX              16
+#define OMAP_DMA_MCBSP2_RX              17
+#define OMAP_DMA_UART3_TX               18
+#define OMAP_DMA_UART3_RX               19
+#define OMAP_DMA_CAMERA_IF_RX           20
+#define OMAP_DMA_MMC_TX                 21
+#define OMAP_DMA_MMC_RX                 22
+#define OMAP_DMA_NAND                   23
+#define OMAP_DMA_IRQ_LCD_LINE           24
+#define OMAP_DMA_MEMORY_STICK           25
+#define OMAP_DMA_USB_W2FC_RX0           26
+#define OMAP_DMA_USB_W2FC_RX1           27
+#define OMAP_DMA_USB_W2FC_RX2           28
+#define OMAP_DMA_USB_W2FC_TX0           29
+#define OMAP_DMA_USB_W2FC_TX1           30
+#define OMAP_DMA_USB_W2FC_TX2           31
+
+/* These are only for 1610 */
+#define OMAP_DMA_CRYPTO_DES_IN          32
+#define OMAP_DMA_SPI_TX                 33
+#define OMAP_DMA_SPI_RX                 34
+#define OMAP_DMA_CRYPTO_HASH            35
+#define OMAP_DMA_CCP_ATTN               36
+#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
+#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
+#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
+#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
+#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
+#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
+#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
+#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
+#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
+#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
+#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
+#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
+#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
+#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
+#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
+#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
+#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
+#define OMAP_DMA_MMC2_TX                54
+#define OMAP_DMA_MMC2_RX                55
+#define OMAP_DMA_CRYPTO_DES_OUT         56
+
+
+#define OMAP_DMA_BASE                   (0xfffed800)
+#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
+#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
+#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
+#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
+#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
+#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
+#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
+#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
+#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
+#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
+#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
+#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
+#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
+#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
+#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
+#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
+#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
+#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
+#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
+#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
+
+#define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
+#define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
+#define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
+#define OMAP1510_DMA_LCD_TOP_F1_U       (OMAP1510_DMA_LCD_BASE + 0x04)
+#define OMAP1510_DMA_LCD_BOT_F1_L       (OMAP1510_DMA_LCD_BASE + 0x06)
+#define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
+
+#define OMAP1610_DMA_LCD_BASE           (0xfffee300)
+#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
+#define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
+#define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
+#define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
+#define OMAP1610_DMA_LCD_TOP_B1_U       (OMAP1610_DMA_LCD_BASE + 0xca)
+#define OMAP1610_DMA_LCD_BOT_B1_L       (OMAP1610_DMA_LCD_BASE + 0xcc)
+#define OMAP1610_DMA_LCD_BOT_B1_U       (OMAP1610_DMA_LCD_BASE + 0xce)
+#define OMAP1610_DMA_LCD_TOP_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd0)
+#define OMAP1610_DMA_LCD_TOP_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd2)
+#define OMAP1610_DMA_LCD_BOT_B2_L       (OMAP1610_DMA_LCD_BASE + 0xd4)
+#define OMAP1610_DMA_LCD_BOT_B2_U       (OMAP1610_DMA_LCD_BASE + 0xd6)
+#define OMAP1610_DMA_LCD_SRC_EI_B1      (OMAP1610_DMA_LCD_BASE + 0xd8)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_L    (OMAP1610_DMA_LCD_BASE + 0xda)
+#define OMAP1610_DMA_LCD_SRC_EN_B1      (OMAP1610_DMA_LCD_BASE + 0xe0)
+#define OMAP1610_DMA_LCD_SRC_FN_B1      (OMAP1610_DMA_LCD_BASE + 0xe4)
+#define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
+#define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
+
+
+/* Every LCh has its own set of the registers below */
+#define OMAP_DMA_CSDP(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
+#define OMAP_DMA_CCR(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
+#define OMAP_DMA_CICR(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
+#define OMAP_DMA_CSR(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
+#define OMAP_DMA_CSSA_L(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
+#define OMAP_DMA_CSSA_U(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
+#define OMAP_DMA_CDSA_L(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
+#define OMAP_DMA_CDSA_U(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
+#define OMAP_DMA_CEN(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
+#define OMAP_DMA_CFN(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
+#define OMAP_DMA_CSFI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
+#define OMAP_DMA_CSEI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
+#define OMAP_DMA_CSAC(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
+#define OMAP_DMA_CDAC(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
+#define OMAP_DMA_CDEI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
+#define OMAP_DMA_CDFI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
+#define OMAP_DMA_COLOR_L(n)             (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
+#define OMAP_DMA_COLOR_U(n)             (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
+#define OMAP_DMA_CCR2(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
+#define OMAP_DMA_CLNK_CTRL(n)           (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
+#define OMAP_DMA_LCH_CTRL(n)            (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+
+#define OMAP_DMA_TOUT_IRQ               (1 << 0)
+#define OMAP_DMA_DROP_IRQ               (1 << 1)
+#define OMAP_DMA_HALF_IRQ               (1 << 2)
+#define OMAP_DMA_FRAME_IRQ              (1 << 3)
+#define OMAP_DMA_LAST_IRQ               (1 << 4)
+#define OMAP_DMA_BLOCK_IRQ              (1 << 5)
+#define OMAP_DMA_SYNC_IRQ               (1 << 6)
+
+#define OMAP_DMA_DATA_TYPE_S8           0x00
+#define OMAP_DMA_DATA_TYPE_S16          0x01
+#define OMAP_DMA_DATA_TYPE_S32          0x02
+
+#define OMAP_DMA_SYNC_ELEMENT           0x00
+#define OMAP_DMA_SYNC_FRAME             0x01
+#define OMAP_DMA_SYNC_BLOCK             0x02
+
+#define OMAP_DMA_PORT_EMIFF             0x00
+#define OMAP_DMA_PORT_EMIFS             0x01
+#define OMAP_DMA_PORT_OCP_T1            0x02
+#define OMAP_DMA_PORT_TIPB              0x03
+#define OMAP_DMA_PORT_OCP_T2            0x04
+#define OMAP_DMA_PORT_MPUI              0x05
+
+#define OMAP_DMA_AMODE_CONSTANT         0x00
+#define OMAP_DMA_AMODE_POST_INC         0x01
+#define OMAP_DMA_AMODE_SINGLE_IDX       0x02
+#define OMAP_DMA_AMODE_DOUBLE_IDX       0x03
+
+/* LCD DMA block numbers */
+enum {
+        OMAP_LCD_DMA_B1_TOP,
+        OMAP_LCD_DMA_B1_BOTTOM,
+        OMAP_LCD_DMA_B2_TOP,
+        OMAP_LCD_DMA_B2_BOTTOM
+};
+
+enum omap_dma_burst_mode {
+        OMAP_DMA_DATA_BURST_DIS = 0,
+        OMAP_DMA_DATA_BURST_4,
+        OMAP_DMA_DATA_BURST_8
+};
+
+enum omap_dma_color_mode {
+        OMAP_DMA_COLOR_DIS = 0,
+        OMAP_DMA_CONSTANT_FILL,
+        OMAP_DMA_TRANSPARENT_COPY
+};
+
+extern void omap_set_dma_priority(int dst_port, int priority);
+extern int omap_request_dma(int dev_id, const char *dev_name,
+                            void (* callback)(int lch, u16 ch_status, void *data),
+                            void *data, int *dma_ch);
+extern void omap_enable_dma_irq(int ch, u16 irq_bits);
+extern void omap_disable_dma_irq(int ch, u16 irq_bits);
+extern void omap_free_dma(int ch);
+extern void omap_start_dma(int lch);
+extern void omap_stop_dma(int lch);
+extern void omap_set_dma_transfer_params(int lch, int data_type,
+                                         int elem_count, int frame_count,
+                                         int sync_mode);
+extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
+                                    u32 color);
+
+extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
+                                    unsigned long src_start);
+extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
+extern void omap_set_dma_src_data_pack(int lch, int enable);
+extern void omap_set_dma_src_burst_mode(int lch,
+                                        enum omap_dma_burst_mode burst_mode);
+
+extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
+                                     unsigned long dest_start);
+extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
+extern void omap_set_dma_dest_data_pack(int lch, int enable);
+extern void omap_set_dma_dest_burst_mode(int lch,
+                                         enum omap_dma_burst_mode burst_mode);
+
+extern void omap_dma_link_lch (int lch_head, int lch_queue);
+extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
+
+extern dma_addr_t omap_get_dma_src_pos(int lch);
+extern dma_addr_t omap_get_dma_dst_pos(int lch);
+extern void omap_clear_dma(int lch);
+
+/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
+extern int omap_dma_in_1510_mode(void);
+
+/* LCD DMA functions */
+extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+                                void *data);
+extern void omap_free_lcd_dma(void);
+extern void omap_setup_lcd_dma(void);
+extern void omap_enable_lcd_dma(void);
+extern void omap_stop_lcd_dma(void);
+extern void omap_set_lcd_dma_ext_controller(int external);
+extern void omap_set_lcd_dma_single_transfer(int single);
+extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
+                                int data_type);
+extern void omap_set_lcd_dma_b1_rotation(int rotate);
+extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
+extern void omap_set_lcd_dma_b1_mirror(int mirror);
+extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
+
+#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-omap/entry-macro.S b/include/asm-arm/arch-omap/entry-macro.S
new file mode 100644
index 000000000000..57b126889b98
--- /dev/null
+++ b/include/asm-arm/arch-omap/entry-macro.S
@@ -0,0 +1,32 @@
+/*
+ * include/asm-arm/arch-omap/entry-macro.S
+ *
+ * Low-level IRQ helper macros for OMAP-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IO_ADDRESS(OMAP_IH1_BASE)
+                ldr     \irqnr, [\base, #IRQ_ITR_REG_OFFSET]
+                ldr     \tmp, [\base, #IRQ_MIR_REG_OFFSET]
+                mov     \irqstat, #0xffffffff
+                bic     \tmp, \irqstat, \tmp
+                tst     \irqnr, \tmp
+                beq     1510f
+
+                ldr     \irqnr, [\base, #IRQ_SIR_FIQ_REG_OFFSET]
+                cmp     \irqnr, #0
+                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
+                cmpeq   \irqnr, #INT_IH2_IRQ
+                ldreq   \base, =IO_ADDRESS(OMAP_IH2_BASE)
+                ldreq   \irqnr, [\base, #IRQ_SIR_IRQ_REG_OFFSET]
+                addeqs  \irqnr, \irqnr, #32
+1510:
+                .endm
+
diff --git a/include/asm-arm/arch-omap/fpga.h b/include/asm-arm/arch-omap/fpga.h
new file mode 100644
index 000000000000..676807dc50e1
--- /dev/null
+++ b/include/asm-arm/arch-omap/fpga.h
@@ -0,0 +1,196 @@
+/*
+ * linux/include/asm-arm/arch-omap/fpga.h
+ *
+ * Interrupt handler for OMAP-1510 FPGA
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Copyright (C) 2002 MontaVista Software, Inc.
+ *
+ * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
+ * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_OMAP_FPGA_H
+#define __ASM_ARCH_OMAP_FPGA_H
+
+#if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP1510)
+extern void omap1510_fpga_init_irq(void);
+#else
+#define omap1510_fpga_init_irq()        (0)
+#endif
+
+#define fpga_read(reg)                  __raw_readb(reg)
+#define fpga_write(val, reg)            __raw_writeb(val, reg)
+
+/*
+ * ---------------------------------------------------------------------------
+ *  H2/P2 Debug board FPGA
+ * ---------------------------------------------------------------------------
+ */
+/* maps in the FPGA registers and the ETHR registers */
+#define H2P2_DBG_FPGA_BASE              0xE8000000      /* VA */
+#define H2P2_DBG_FPGA_SIZE              SZ_4K           /* SIZE */
+#define H2P2_DBG_FPGA_START             0x04000000      /* PA */
+
+#define H2P2_DBG_FPGA_ETHR_START        (H2P2_DBG_FPGA_START + 0x300)
+#define H2P2_DBG_FPGA_FPGA_REV          (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
+#define H2P2_DBG_FPGA_BOARD_REV         (H2P2_DBG_FPGA_BASE + 0x12)     /* Board Revision */
+#define H2P2_DBG_FPGA_GPIO              (H2P2_DBG_FPGA_BASE + 0x14)     /* GPIO outputs */
+#define H2P2_DBG_FPGA_LEDS              (H2P2_DBG_FPGA_BASE + 0x16)     /* LEDs outputs */
+#define H2P2_DBG_FPGA_MISC_INPUTS       (H2P2_DBG_FPGA_BASE + 0x18)     /* Misc inputs */
+#define H2P2_DBG_FPGA_LAN_STATUS        (H2P2_DBG_FPGA_BASE + 0x1A)     /* LAN Status line */
+#define H2P2_DBG_FPGA_LAN_RESET         (H2P2_DBG_FPGA_BASE + 0x1C)     /* LAN Reset line */
+
+/* NOTE:  most boards don't have a static mapping for the FPGA ... */
+struct h2p2_dbg_fpga {
+        /* offset 0x00 */
+        u16             smc91x[8];
+        /* offset 0x10 */
+        u16             fpga_rev;
+        u16             board_rev;
+        u16             gpio_outputs;
+        u16             leds;
+        /* offset 0x18 */
+        u16             misc_inputs;
+        u16             lan_status;
+        u16             lan_reset;
+        u16             reserved0;
+        /* offset 0x20 */
+        u16             ps2_data;
+        u16             ps2_ctrl;
+        /* plus also 4 rs232 ports ... */
+};
+
+/* LEDs definition on debug board (16 LEDs, all physically green) */
+#define H2P2_DBG_FPGA_LED_GREEN         (1 << 15)
+#define H2P2_DBG_FPGA_LED_AMBER         (1 << 14)
+#define H2P2_DBG_FPGA_LED_RED           (1 << 13)
+#define H2P2_DBG_FPGA_LED_BLUE          (1 << 12)
+/*  cpu0 load-meter LEDs */
+#define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
+#define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
+#define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
+
+
+/*
+ * ---------------------------------------------------------------------------
+ *  OMAP-1510 FPGA
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP1510_FPGA_BASE                      0xE8000000      /* Virtual */
+#define OMAP1510_FPGA_SIZE                      SZ_4K
+#define OMAP1510_FPGA_START                     0x08000000      /* Physical */
+
+/* Revision */
+#define OMAP1510_FPGA_REV_LOW                   (OMAP1510_FPGA_BASE + 0x0)
+#define OMAP1510_FPGA_REV_HIGH                  (OMAP1510_FPGA_BASE + 0x1)
+
+#define OMAP1510_FPGA_LCD_PANEL_CONTROL         (OMAP1510_FPGA_BASE + 0x2)
+#define OMAP1510_FPGA_LED_DIGIT                 (OMAP1510_FPGA_BASE + 0x3)
+#define INNOVATOR_FPGA_HID_SPI                  (OMAP1510_FPGA_BASE + 0x4)
+#define OMAP1510_FPGA_POWER                     (OMAP1510_FPGA_BASE + 0x5)
+
+/* Interrupt status */
+#define OMAP1510_FPGA_ISR_LO                    (OMAP1510_FPGA_BASE + 0x6)
+#define OMAP1510_FPGA_ISR_HI                    (OMAP1510_FPGA_BASE + 0x7)
+
+/* Interrupt mask */
+#define OMAP1510_FPGA_IMR_LO                    (OMAP1510_FPGA_BASE + 0x8)
+#define OMAP1510_FPGA_IMR_HI                    (OMAP1510_FPGA_BASE + 0x9)
+
+/* Reset registers */
+#define OMAP1510_FPGA_HOST_RESET                (OMAP1510_FPGA_BASE + 0xa)
+#define OMAP1510_FPGA_RST                       (OMAP1510_FPGA_BASE + 0xb)
+
+#define OMAP1510_FPGA_AUDIO                     (OMAP1510_FPGA_BASE + 0xc)
+#define OMAP1510_FPGA_DIP                       (OMAP1510_FPGA_BASE + 0xe)
+#define OMAP1510_FPGA_FPGA_IO                   (OMAP1510_FPGA_BASE + 0xf)
+#define OMAP1510_FPGA_UART1                     (OMAP1510_FPGA_BASE + 0x14)
+#define OMAP1510_FPGA_UART2                     (OMAP1510_FPGA_BASE + 0x15)
+#define OMAP1510_FPGA_OMAP1510_STATUS           (OMAP1510_FPGA_BASE + 0x16)
+#define OMAP1510_FPGA_BOARD_REV                 (OMAP1510_FPGA_BASE + 0x18)
+#define OMAP1510P1_PPT_DATA                     (OMAP1510_FPGA_BASE + 0x100)
+#define OMAP1510P1_PPT_STATUS                   (OMAP1510_FPGA_BASE + 0x101)
+#define OMAP1510P1_PPT_CONTROL                  (OMAP1510_FPGA_BASE + 0x102)
+
+#define OMAP1510_FPGA_TOUCHSCREEN               (OMAP1510_FPGA_BASE + 0x204)
+
+#define INNOVATOR_FPGA_INFO                     (OMAP1510_FPGA_BASE + 0x205)
+#define INNOVATOR_FPGA_LCD_BRIGHT_LO            (OMAP1510_FPGA_BASE + 0x206)
+#define INNOVATOR_FPGA_LCD_BRIGHT_HI            (OMAP1510_FPGA_BASE + 0x207)
+#define INNOVATOR_FPGA_LED_GRN_LO               (OMAP1510_FPGA_BASE + 0x208)
+#define INNOVATOR_FPGA_LED_GRN_HI               (OMAP1510_FPGA_BASE + 0x209)
+#define INNOVATOR_FPGA_LED_RED_LO               (OMAP1510_FPGA_BASE + 0x20a)
+#define INNOVATOR_FPGA_LED_RED_HI               (OMAP1510_FPGA_BASE + 0x20b)
+#define INNOVATOR_FPGA_CAM_USB_CONTROL          (OMAP1510_FPGA_BASE + 0x20c)
+#define INNOVATOR_FPGA_EXP_CONTROL              (OMAP1510_FPGA_BASE + 0x20d)
+#define INNOVATOR_FPGA_ISR2                     (OMAP1510_FPGA_BASE + 0x20e)
+#define INNOVATOR_FPGA_IMR2                     (OMAP1510_FPGA_BASE + 0x210)
+
+#define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
+
+/*
+ * Power up Giga UART driver, turn on HID clock.
+ * Turn off BT power, since we're not using it and it
+ * draws power.
+ */
+#define OMAP1510_FPGA_RESET_VALUE               0x42
+
+#define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
+#define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
+#define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
+#define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
+#define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
+#define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
+#define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
+#define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
+
+/*
+ * Innovator/OMAP1510 FPGA HID register bit definitions
+ */
+#define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
+#define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
+#define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
+#define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
+#define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
+#define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
+#define OMAP1510_FPGA_HID_rsrvd (1<<6)
+#define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
+
+/* The FPGA IRQ is cascaded through GPIO_13 */
+#define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
+
+/* IRQ Numbers for interrupts muxed through the FPGA */
+#define OMAP1510_IH_FPGA_BASE           IH_BOARD_BASE
+#define OMAP1510_INT_FPGA_ATN           (OMAP1510_IH_FPGA_BASE + 0)
+#define OMAP1510_INT_FPGA_ACK           (OMAP1510_IH_FPGA_BASE + 1)
+#define OMAP1510_INT_FPGA2              (OMAP1510_IH_FPGA_BASE + 2)
+#define OMAP1510_INT_FPGA3              (OMAP1510_IH_FPGA_BASE + 3)
+#define OMAP1510_INT_FPGA4              (OMAP1510_IH_FPGA_BASE + 4)
+#define OMAP1510_INT_FPGA5              (OMAP1510_IH_FPGA_BASE + 5)
+#define OMAP1510_INT_FPGA6              (OMAP1510_IH_FPGA_BASE + 6)
+#define OMAP1510_INT_FPGA7              (OMAP1510_IH_FPGA_BASE + 7)
+#define OMAP1510_INT_FPGA8              (OMAP1510_IH_FPGA_BASE + 8)
+#define OMAP1510_INT_FPGA9              (OMAP1510_IH_FPGA_BASE + 9)
+#define OMAP1510_INT_FPGA10             (OMAP1510_IH_FPGA_BASE + 10)
+#define OMAP1510_INT_FPGA11             (OMAP1510_IH_FPGA_BASE + 11)
+#define OMAP1510_INT_FPGA12             (OMAP1510_IH_FPGA_BASE + 12)
+#define OMAP1510_INT_ETHER              (OMAP1510_IH_FPGA_BASE + 13)
+#define OMAP1510_INT_FPGAUART1          (OMAP1510_IH_FPGA_BASE + 14)
+#define OMAP1510_INT_FPGAUART2          (OMAP1510_IH_FPGA_BASE + 15)
+#define OMAP1510_INT_FPGA_TS            (OMAP1510_IH_FPGA_BASE + 16)
+#define OMAP1510_INT_FPGA17             (OMAP1510_IH_FPGA_BASE + 17)
+#define OMAP1510_INT_FPGA_CAM           (OMAP1510_IH_FPGA_BASE + 18)
+#define OMAP1510_INT_FPGA_RTC_A         (OMAP1510_IH_FPGA_BASE + 19)
+#define OMAP1510_INT_FPGA_RTC_B         (OMAP1510_IH_FPGA_BASE + 20)
+#define OMAP1510_INT_FPGA_CD            (OMAP1510_IH_FPGA_BASE + 21)
+#define OMAP1510_INT_FPGA22             (OMAP1510_IH_FPGA_BASE + 22)
+#define OMAP1510_INT_FPGA23             (OMAP1510_IH_FPGA_BASE + 23)
+
+#endif
diff --git a/include/asm-arm/arch-omap/gpio.h b/include/asm-arm/arch-omap/gpio.h
new file mode 100644
index 000000000000..fad2fc93ee70
--- /dev/null
+++ b/include/asm-arm/arch-omap/gpio.h
@@ -0,0 +1,69 @@
+/*
+ * linux/include/asm-arm/arch-omap/gpio.h
+ *
+ * OMAP GPIO handling defines and functions
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ *
+ * Written by Juha Yrjölä <juha.yrjola@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_OMAP_GPIO_H
+#define __ASM_ARCH_OMAP_GPIO_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+
+#define OMAP_MPUIO_BASE                 0xfffb5000
+#define OMAP_MPUIO_INPUT_LATCH          0x00
+#define OMAP_MPUIO_OUTPUT               0x04
+#define OMAP_MPUIO_IO_CNTL              0x08
+#define OMAP_MPUIO_KBR_LATCH            0x10
+#define OMAP_MPUIO_KBC                  0x14
+#define OMAP_MPUIO_GPIO_EVENT_MODE      0x18
+#define OMAP_MPUIO_GPIO_INT_EDGE        0x1c
+#define OMAP_MPUIO_KBD_INT              0x20
+#define OMAP_MPUIO_GPIO_INT             0x24
+#define OMAP_MPUIO_KBD_MASKIT           0x28
+#define OMAP_MPUIO_GPIO_MASKIT          0x2c
+#define OMAP_MPUIO_GPIO_DEBOUNCING      0x30
+#define OMAP_MPUIO_LATCH                0x34
+
+#define OMAP_MPUIO(nr)          (OMAP_MAX_GPIO_LINES + (nr))
+#define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
+
+#define OMAP_GPIO_IRQ(nr)       (OMAP_GPIO_IS_MPUIO(nr) ? \
+                                 IH_MPUIO_BASE + ((nr) & 0x0f) : \
+                                 IH_GPIO_BASE + ((nr) & 0x3f))
+
+/* For EDGECTRL */
+#define OMAP_GPIO_NO_EDGE         0x00
+#define OMAP_GPIO_FALLING_EDGE    0x01
+#define OMAP_GPIO_RISING_EDGE     0x02
+#define OMAP_GPIO_BOTH_EDGES      0x03
+
+extern int omap_gpio_init(void);        /* Call from board init only */
+extern int omap_request_gpio(int gpio);
+extern void omap_free_gpio(int gpio);
+extern void omap_set_gpio_direction(int gpio, int is_input);
+extern void omap_set_gpio_dataout(int gpio, int enable);
+extern int omap_get_gpio_datain(int gpio);
+extern void omap_set_gpio_edge_ctrl(int gpio, int edge);
+
+#endif
diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h
new file mode 100644
index 000000000000..37e06c782bdf
--- /dev/null
+++ b/include/asm-arm/arch-omap/hardware.h
@@ -0,0 +1,324 @@
+/*
+ * linux/include/asm-arm/arch-omap/hardware.h
+ *
+ * Hardware definitions for TI OMAP processors and boards
+ *
+ * NOTE: Please put device driver specific defines into a separate header
+ *       file for each driver.
+ *
+ * Copyright (C) 2001 RidgeRun, Inc.
+ * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
+ *                          and Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_HARDWARE_H
+#define __ASM_ARCH_OMAP_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <linux/config.h>
+#ifndef __ASSEMBLER__
+#include <asm/types.h>
+#include <asm/arch/cpu.h>
+#endif
+#include <asm/arch/io.h>
+
+/*
+ * ---------------------------------------------------------------------------
+ * Common definitions for all OMAP processors
+ * NOTE: Put all processor or board specific parts to the special header
+ *       files.
+ * ---------------------------------------------------------------------------
+ */
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_BASE         (0xfffece00)
+#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
+#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
+#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
+#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
+#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
+#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
+#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
+#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
+
+#define CK_RATEF                1
+#define CK_IDLEF                2
+#define CK_ENABLEF              4
+#define CK_SELECTF              8
+#define SETARM_IDLE_SHIFT
+
+/* DPLL control registers */
+#define DPLL_CTL                (0xfffecf00)
+
+/* DSP clock control */
+#define DSP_CONFIG_REG_BASE     (0xe1008000)
+#define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
+#define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
+
+/*
+ * ---------------------------------------------------------------------------
+ * UPLD
+ * ---------------------------------------------------------------------------
+ */
+#define ULPD_REG_BASE           (0xfffe0800)
+#define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
+#define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
+#       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
+#       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
+#define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
+#       define SOFT_UDC_REQ             (1 << 4)
+#       define SOFT_USB_CLK_REQ         (1 << 3)
+#       define SOFT_DPLL_REQ            (1 << 0)
+#define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
+#define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
+#define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
+#define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
+#define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
+#       define DIS_MMC2_DPLL_REQ        (1 << 11)
+#       define DIS_MMC1_DPLL_REQ        (1 << 10)
+#       define DIS_UART3_DPLL_REQ       (1 << 9)
+#       define DIS_UART2_DPLL_REQ       (1 << 8)
+#       define DIS_UART1_DPLL_REQ       (1 << 7)
+#       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
+#define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
+#define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Watchdog timer
+ * ---------------------------------------------------------------------------
+ */
+
+/* Watchdog timer within the OMAP3.2 gigacell */
+#define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
+#define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
+#define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
+#define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Interrupts
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_IH1_BASE           0xfffecb00
+#define OMAP_IH2_BASE           0xfffe0000
+
+#define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
+#define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
+#define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
+#define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
+#define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
+#define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
+#define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
+
+#define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
+#define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
+#define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
+#define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
+#define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
+#define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
+#define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
+
+#define IRQ_ITR_REG_OFFSET      0x00
+#define IRQ_MIR_REG_OFFSET      0x04
+#define IRQ_SIR_IRQ_REG_OFFSET  0x10
+#define IRQ_SIR_FIQ_REG_OFFSET  0x14
+#define IRQ_CONTROL_REG_OFFSET  0x18
+#define IRQ_ISR_REG_OFFSET      0x9c
+#define IRQ_ILR0_REG_OFFSET     0x1c
+#define IRQ_GMR_REG_OFFSET      0xa0
+
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+#define MOD_CONF_CTRL_0         0xfffe1080
+#define MOD_CONF_CTRL_1         0xfffe1110
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pin multiplexing registers
+ * ----------------------------------------------------------------------------
+ */
+#define FUNC_MUX_CTRL_0         0xfffe1000
+#define FUNC_MUX_CTRL_1         0xfffe1004
+#define FUNC_MUX_CTRL_2         0xfffe1008
+#define COMP_MODE_CTRL_0        0xfffe100c
+#define FUNC_MUX_CTRL_3         0xfffe1010
+#define FUNC_MUX_CTRL_4         0xfffe1014
+#define FUNC_MUX_CTRL_5         0xfffe1018
+#define FUNC_MUX_CTRL_6         0xfffe101C
+#define FUNC_MUX_CTRL_7         0xfffe1020
+#define FUNC_MUX_CTRL_8         0xfffe1024
+#define FUNC_MUX_CTRL_9         0xfffe1028
+#define FUNC_MUX_CTRL_A         0xfffe102C
+#define FUNC_MUX_CTRL_B         0xfffe1030
+#define FUNC_MUX_CTRL_C         0xfffe1034
+#define FUNC_MUX_CTRL_D         0xfffe1038
+#define PULL_DWN_CTRL_0         0xfffe1040
+#define PULL_DWN_CTRL_1         0xfffe1044
+#define PULL_DWN_CTRL_2         0xfffe1048
+#define PULL_DWN_CTRL_3         0xfffe104c
+#define PULL_DWN_CTRL_4         0xfffe10ac
+
+/* OMAP-1610 specific multiplexing registers */
+#define FUNC_MUX_CTRL_E         0xfffe1090
+#define FUNC_MUX_CTRL_F         0xfffe1094
+#define FUNC_MUX_CTRL_10        0xfffe1098
+#define FUNC_MUX_CTRL_11        0xfffe109c
+#define FUNC_MUX_CTRL_12        0xfffe10a0
+#define PU_PD_SEL_0             0xfffe10b4
+#define PU_PD_SEL_1             0xfffe10b8
+#define PU_PD_SEL_2             0xfffe10bc
+#define PU_PD_SEL_3             0xfffe10c0
+#define PU_PD_SEL_4             0xfffe10c4
+
+/* Timer32K for 1610 and 1710*/
+#define OMAP_TIMER32K_BASE      0xFFFBC400
+
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+#define TIPB_PUBLIC_CNTL_BASE           0xfffed300
+#define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
+#define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
+#define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
+
+/*
+ * ----------------------------------------------------------------------------
+ * MPUI interface
+ * ----------------------------------------------------------------------------
+ */
+#define MPUI_BASE                       (0xfffec900)
+#define MPUI_CTRL                       (MPUI_BASE + 0x0)
+#define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
+#define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
+#define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
+#define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
+#define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
+#define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
+#define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
+
+/*
+ * ----------------------------------------------------------------------------
+ * LED Pulse Generator
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP_LPG1_BASE                  0xfffbd000
+#define OMAP_LPG2_BASE                  0xfffbd800
+#define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
+#define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
+#define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
+#define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
+
+#ifndef __ASSEMBLER__
+
+/*
+ * ---------------------------------------------------------------------------
+ * Serial ports
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_UART1_BASE         (unsigned char *)0xfffb0000
+#define OMAP_UART2_BASE         (unsigned char *)0xfffb0800
+#define OMAP_UART3_BASE         (unsigned char *)0xfffb9800
+#define OMAP_MAX_NR_PORTS       3
+#define OMAP1510_BASE_BAUD      (12000000/16)
+#define OMAP16XX_BASE_BAUD      (48000000/16)
+
+#define is_omap_port(p) ({int __ret = 0;                        \
+                        if (p == IO_ADDRESS(OMAP_UART1_BASE) || \
+                            p == IO_ADDRESS(OMAP_UART2_BASE) || \
+                            p == IO_ADDRESS(OMAP_UART3_BASE))   \
+                                __ret = 1;                      \
+                        __ret;                                  \
+                        })
+
+/*
+ * ---------------------------------------------------------------------------
+ * Processor specific defines
+ * ---------------------------------------------------------------------------
+ */
+#ifdef CONFIG_ARCH_OMAP730
+#include "omap730.h"
+#endif
+
+#ifdef CONFIG_ARCH_OMAP1510
+#include "omap1510.h"
+#endif
+
+#ifdef CONFIG_ARCH_OMAP16XX
+#include "omap16xx.h"
+#endif
+
+/*
+ * ---------------------------------------------------------------------------
+ * Board specific defines
+ * ---------------------------------------------------------------------------
+ */
+
+#ifdef CONFIG_MACH_OMAP_INNOVATOR
+#include "board-innovator.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H2
+#include "board-h2.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_PERSEUS2
+#include "board-perseus2.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H3
+#include "board-h3.h"
+#endif
+
+#ifdef CONFIG_MACH_OMAP_H4
+#include "board-h4.h"
+#error "Support for H4 board not yet implemented."
+#endif
+
+#ifdef CONFIG_MACH_OMAP_OSK
+#include "board-osk.h"
+#endif
+
+#ifdef CONFIG_MACH_VOICEBLUE
+#include "board-voiceblue.h"
+#endif
+
+#ifdef CONFIG_MACH_NETSTAR
+#include "board-netstar.h"
+#endif
+
+#endif /* !__ASSEMBLER__ */
+
+#endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h
new file mode 100644
index 000000000000..1c8c9fcc766e
--- /dev/null
+++ b/include/asm-arm/arch-omap/io.h
@@ -0,0 +1,107 @@
+/*
+ * linux/include/asm-arm/arch-omap/io.h
+ *
+ * IO definitions for TI OMAP processors and boards
+ *
+ * Copied from linux/include/asm-arm/arch-sa1100/io.h
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+/*
+ * ----------------------------------------------------------------------------
+ * I/O mapping
+ * ----------------------------------------------------------------------------
+ */
+#define IO_PHYS                 0xFFFB0000
+#define IO_OFFSET               0x01000000      /* Virtual IO = 0xfefb0000 */
+#define IO_VIRT                 (IO_PHYS - IO_OFFSET)
+#define IO_SIZE                 0x40000
+#define IO_ADDRESS(x)           ((x) - IO_OFFSET)
+
+#define PCIO_BASE               0
+
+#define io_p2v(x)               ((x) - IO_OFFSET)
+#define io_v2p(x)               ((x) + IO_OFFSET)
+
+#ifndef __ASSEMBLER__
+
+/*
+ * Functions to access the OMAP IO region
+ *
+ * NOTE: - Use omap_read/write[bwl] for physical register addresses
+ *       - Use __raw_read/write[bwl]() for virtual register addresses
+ *       - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
+ *       - DO NOT use hardcoded virtual addresses to allow changing the
+ *         IO address space again if needed
+ */
+#define omap_readb(a)           (*(volatile unsigned char  *)IO_ADDRESS(a))
+#define omap_readw(a)           (*(volatile unsigned short *)IO_ADDRESS(a))
+#define omap_readl(a)           (*(volatile unsigned int   *)IO_ADDRESS(a))
+
+#define omap_writeb(v,a)        (*(volatile unsigned char  *)IO_ADDRESS(a) = (v))
+#define omap_writew(v,a)        (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
+#define omap_writel(v,a)        (*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
+
+/* 16 bit uses LDRH/STRH, base +/- offset_8 */
+typedef struct { volatile u16 offset[256]; } __regbase16;
+#define __REGV16(vaddr)         ((__regbase16 *)((vaddr)&~0xff)) \
+                                        ->offset[((vaddr)&0xff)>>1]
+#define __REG16(paddr)          __REGV16(io_p2v(paddr))
+
+/* 8/32 bit uses LDR/STR, base +/- offset_12 */
+typedef struct { volatile u8 offset[4096]; } __regbase8;
+#define __REGV8(vaddr)          ((__regbase8  *)((vaddr)&~4095)) \
+                                        ->offset[((vaddr)&4095)>>0]
+#define __REG8(paddr)           __REGV8(io_p2v(paddr))
+
+typedef struct { volatile u32 offset[4096]; } __regbase32;
+#define __REGV32(vaddr)         ((__regbase32 *)((vaddr)&~4095)) \
+                                        ->offset[((vaddr)&4095)>>2]
+#define __REG32(paddr)          __REGV32(io_p2v(paddr))
+
+#else
+
+#define __REG8(paddr)           io_p2v(paddr)
+#define __REG16(paddr)          io_p2v(paddr)
+#define __REG32(paddr)          io_p2v(paddr)
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-omap/irqs.h b/include/asm-arm/arch-omap/irqs.h
new file mode 100644
index 000000000000..6701fd9e5f9b
--- /dev/null
+++ b/include/asm-arm/arch-omap/irqs.h
@@ -0,0 +1,255 @@
+/*
+ *  linux/include/asm-arm/arch-omap/irqs.h
+ *
+ *  Copyright (C) Greg Lonnon 2001
+ *  Updated for OMAP-1610 by Tony Lindgren <tony@atomide.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: The interrupt vectors for the OMAP-1509, OMAP-1510, and OMAP-1610
+ *       are different.
+ */
+
+#ifndef __ASM_ARCH_OMAP1510_IRQS_H
+#define __ASM_ARCH_OMAP1510_IRQS_H
+
+/*
+ * IRQ numbers for interrupt handler 1
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ *
+ */
+#define INT_IH2_IRQ             0
+#define INT_CAMERA              1
+#define INT_FIQ                 3
+#define INT_RTDX                6
+#define INT_DSP_MMU_ABORT       7
+#define INT_HOST                8
+#define INT_ABORT               9
+#define INT_DSP_MAILBOX1        10
+#define INT_DSP_MAILBOX2        11
+#define INT_BRIDGE_PRIV         13
+#define INT_GPIO_BANK1          14
+#define INT_UART3               15
+#define INT_TIMER3              16
+#define INT_DMA_CH0_6           19
+#define INT_DMA_CH1_7           20
+#define INT_DMA_CH2_8           21
+#define INT_DMA_CH3             22
+#define INT_DMA_CH4             23
+#define INT_DMA_CH5             24
+#define INT_DMA_LCD             25
+#define INT_TIMER1              26
+#define INT_WD_TIMER            27
+#define INT_BRIDGE_PUB          28
+#define INT_TIMER2              30
+#define INT_LCD_CTRL            31
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1510_RES2           2
+#define INT_1510_SPI_TX         4
+#define INT_1510_SPI_RX         5
+#define INT_1510_RES12          12
+#define INT_1510_LB_MMU         17
+#define INT_1510_RES18          18
+#define INT_1510_LOCAL_BUS      29
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_1610_IH2_FIQ        2
+#define INT_1610_McBSP2_TX      4
+#define INT_1610_McBSP2_RX      5
+#define INT_1610_LCD_LINE       12
+#define INT_1610_GPTIMER1       17
+#define INT_1610_GPTIMER2       18
+#define INT_1610_SSR_FIFO_0     29
+
+/*
+ * OMAP-730 specific IRQ numbers for interrupt handler 1
+ */
+#define INT_730_IH2_FIQ         0
+#define INT_730_IH2_IRQ         1
+#define INT_730_USB_NON_ISO     2
+#define INT_730_USB_ISO         3
+#define INT_730_ICR             4
+#define INT_730_EAC             5
+#define INT_730_GPIO_BANK1      6
+#define INT_730_GPIO_BANK2      7
+#define INT_730_GPIO_BANK3      8
+#define INT_730_McBSP2TX        10
+#define INT_730_McBSP2RX        11
+#define INT_730_McBSP2RX_OVF    12
+#define INT_730_LCD_LINE        14
+#define INT_730_GSM_PROTECT     15
+#define INT_730_TIMER3          16
+#define INT_730_GPIO_BANK5      17
+#define INT_730_GPIO_BANK6      18
+#define INT_730_SPGIO_WR        29
+
+/*
+ * IRQ numbers for interrupt handler 2
+ *
+ * NOTE: See also the OMAP-1510 and 1610 specific IRQ numbers below
+ */
+#define IH2_BASE                32
+
+#define INT_KEYBOARD            (1 + IH2_BASE)
+#define INT_uWireTX             (2 + IH2_BASE)
+#define INT_uWireRX             (3 + IH2_BASE)
+#define INT_I2C                 (4 + IH2_BASE)
+#define INT_MPUIO               (5 + IH2_BASE)
+#define INT_USB_HHC_1           (6 + IH2_BASE)
+#define INT_McBSP3TX            (10 + IH2_BASE)
+#define INT_McBSP3RX            (11 + IH2_BASE)
+#define INT_McBSP1TX            (12 + IH2_BASE)
+#define INT_McBSP1RX            (13 + IH2_BASE)
+#define INT_UART1               (14 + IH2_BASE)
+#define INT_UART2               (15 + IH2_BASE)
+#define INT_BT_MCSI1TX          (16 + IH2_BASE)
+#define INT_BT_MCSI1RX          (17 + IH2_BASE)
+#define INT_USB_W2FC            (20 + IH2_BASE)
+#define INT_1WIRE               (21 + IH2_BASE)
+#define INT_OS_TIMER            (22 + IH2_BASE)
+#define INT_MMC                 (23 + IH2_BASE)
+#define INT_GAUGE_32K           (24 + IH2_BASE)
+#define INT_RTC_TIMER           (25 + IH2_BASE)
+#define INT_RTC_ALARM           (26 + IH2_BASE)
+#define INT_MEM_STICK           (27 + IH2_BASE)
+#define INT_DSP_MMU             (28 + IH2_BASE)
+
+/*
+ * OMAP-1510 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1510_OS_32kHz_TIMER (22 + IH2_BASE)
+#define INT_1510_COM_SPI_RO     (31 + IH2_BASE)
+
+/*
+ * OMAP-1610 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_1610_FAC            (0 + IH2_BASE)
+#define INT_1610_USB_HHC_2      (7 + IH2_BASE)
+#define INT_1610_USB_OTG        (8 + IH2_BASE)
+#define INT_1610_SoSSI          (9 + IH2_BASE)
+#define INT_1610_SoSSI_MATCH    (19 + IH2_BASE)
+#define INT_1610_McBSP2RX_OF    (31 + IH2_BASE)
+#define INT_1610_STI            (32 + IH2_BASE)
+#define INT_1610_STI_WAKEUP     (33 + IH2_BASE)
+#define INT_1610_GPTIMER3       (34 + IH2_BASE)
+#define INT_1610_GPTIMER4       (35 + IH2_BASE)
+#define INT_1610_GPTIMER5       (36 + IH2_BASE)
+#define INT_1610_GPTIMER6       (37 + IH2_BASE)
+#define INT_1610_GPTIMER7       (38 + IH2_BASE)
+#define INT_1610_GPTIMER8       (39 + IH2_BASE)
+#define INT_1610_GPIO_BANK2     (40 + IH2_BASE)
+#define INT_1610_GPIO_BANK3     (41 + IH2_BASE)
+#define INT_1610_MMC2           (42 + IH2_BASE)
+#define INT_1610_CF             (43 + IH2_BASE)
+#define INT_1610_GPIO_BANK4     (48 + IH2_BASE)
+#define INT_1610_SPI            (49 + IH2_BASE)
+#define INT_1610_DMA_CH6        (53 + IH2_BASE)
+#define INT_1610_DMA_CH7        (54 + IH2_BASE)
+#define INT_1610_DMA_CH8        (55 + IH2_BASE)
+#define INT_1610_DMA_CH9        (56 + IH2_BASE)
+#define INT_1610_DMA_CH10       (57 + IH2_BASE)
+#define INT_1610_DMA_CH11       (58 + IH2_BASE)
+#define INT_1610_DMA_CH12       (59 + IH2_BASE)
+#define INT_1610_DMA_CH13       (60 + IH2_BASE)
+#define INT_1610_DMA_CH14       (61 + IH2_BASE)
+#define INT_1610_DMA_CH15       (62 + IH2_BASE)
+#define INT_1610_NAND           (63 + IH2_BASE)
+
+/*
+ * OMAP-730 specific IRQ numbers for interrupt handler 2
+ */
+#define INT_730_HW_ERRORS       (0 + IH2_BASE)
+#define INT_730_NFIQ_PWR_FAIL   (1 + IH2_BASE)
+#define INT_730_CFCD            (2 + IH2_BASE)
+#define INT_730_CFIREQ          (3 + IH2_BASE)
+#define INT_730_I2C             (4 + IH2_BASE)
+#define INT_730_PCC             (5 + IH2_BASE)
+#define INT_730_MPU_EXT_NIRQ    (6 + IH2_BASE)
+#define INT_730_SPI_100K_1      (7 + IH2_BASE)
+#define INT_730_SYREN_SPI       (8 + IH2_BASE)
+#define INT_730_VLYNQ           (9 + IH2_BASE)
+#define INT_730_GPIO_BANK4      (10 + IH2_BASE)
+#define INT_730_McBSP1TX        (11 + IH2_BASE)
+#define INT_730_McBSP1RX        (12 + IH2_BASE)
+#define INT_730_McBSP1RX_OF     (13 + IH2_BASE)
+#define INT_730_UART_MODEM_IRDA_2 (14 + IH2_BASE)
+#define INT_730_UART_MODEM_1    (15 + IH2_BASE)
+#define INT_730_MCSI            (16 + IH2_BASE)
+#define INT_730_uWireTX         (17 + IH2_BASE)
+#define INT_730_uWireRX         (18 + IH2_BASE)
+#define INT_730_SMC_CD          (19 + IH2_BASE)
+#define INT_730_SMC_IREQ        (20 + IH2_BASE)
+#define INT_730_HDQ_1WIRE       (21 + IH2_BASE)
+#define INT_730_TIMER32K        (22 + IH2_BASE)
+#define INT_730_MMC_SDIO        (23 + IH2_BASE)
+#define INT_730_UPLD            (24 + IH2_BASE)
+#define INT_730_USB_HHC_1       (27 + IH2_BASE)
+#define INT_730_USB_HHC_2       (28 + IH2_BASE)
+#define INT_730_USB_GENI        (29 + IH2_BASE)
+#define INT_730_USB_OTG         (30 + IH2_BASE)
+#define INT_730_CAMERA_IF       (31 + IH2_BASE)
+#define INT_730_RNG             (32 + IH2_BASE)
+#define INT_730_DUAL_MODE_TIMER (33 + IH2_BASE)
+#define INT_730_DBB_RF_EN       (34 + IH2_BASE)
+#define INT_730_MPUIO_KEYPAD    (35 + IH2_BASE)
+#define INT_730_SHA1_MD5        (36 + IH2_BASE)
+#define INT_730_SPI_100K_2      (37 + IH2_BASE)
+#define INT_730_RNG_IDLE        (38 + IH2_BASE)
+#define INT_730_MPUIO           (39 + IH2_BASE)
+#define INT_730_LLPC_LCD_CTRL_CAN_BE_OFF        (40 + IH2_BASE)
+#define INT_730_LLPC_OE_FALLING (41 + IH2_BASE)
+#define INT_730_LLPC_OE_RISING  (42 + IH2_BASE)
+#define INT_730_LLPC_VSYNC      (43 + IH2_BASE)
+#define INT_730_WAKE_UP_REQ     (46 + IH2_BASE)
+#define INT_730_DMA_CH6         (53 + IH2_BASE)
+#define INT_730_DMA_CH7         (54 + IH2_BASE)
+#define INT_730_DMA_CH8         (55 + IH2_BASE)
+#define INT_730_DMA_CH9         (56 + IH2_BASE)
+#define INT_730_DMA_CH10        (57 + IH2_BASE)
+#define INT_730_DMA_CH11        (58 + IH2_BASE)
+#define INT_730_DMA_CH12        (59 + IH2_BASE)
+#define INT_730_DMA_CH13        (60 + IH2_BASE)
+#define INT_730_DMA_CH14        (61 + IH2_BASE)
+#define INT_730_DMA_CH15        (62 + IH2_BASE)
+#define INT_730_NAND            (63 + IH2_BASE)
+
+/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
+ * 16 MPUIO lines */
+#define OMAP_MAX_GPIO_LINES     192
+#define IH_GPIO_BASE            (128 + IH2_BASE)
+#define IH_MPUIO_BASE           (OMAP_MAX_GPIO_LINES + IH_GPIO_BASE)
+#define IH_BOARD_BASE           (16 + IH_MPUIO_BASE)
+
+#ifndef __ASSEMBLY__
+extern void omap_init_irq(void);
+#endif
+
+/*
+ * The definition of NR_IRQS is in board-specific header file, which is
+ * included via hardware.h
+ */
+#include <asm/arch/hardware.h>
+
+#ifndef NR_IRQS
+#define NR_IRQS                 IH_BOARD_BASE
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-omap/mcbsp.h b/include/asm-arm/arch-omap/mcbsp.h
new file mode 100644
index 000000000000..305bdeb16ab8
--- /dev/null
+++ b/include/asm-arm/arch-omap/mcbsp.h
@@ -0,0 +1,257 @@
+/*
+ * linux/include/asm-arm/arch-omap/gpio.h
+ *
+ * Defines for Multi-Channel Buffered Serial Port
+ *
+ * Copyright (C) 2002 RidgeRun, Inc.
+ * Author: Steve Johnson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+#ifndef __ASM_ARCH_OMAP_MCBSP_H
+#define __ASM_ARCH_OMAP_MCBSP_H
+
+#include <asm/arch/hardware.h>
+
+#define OMAP730_MCBSP1_BASE     0xfffb1000
+#define OMAP730_MCBSP2_BASE     0xfffb1800
+
+#define OMAP1510_MCBSP1_BASE    0xe1011800
+#define OMAP1510_MCBSP2_BASE    0xfffb1000
+#define OMAP1510_MCBSP3_BASE    0xe1017000
+
+#define OMAP1610_MCBSP1_BASE    0xe1011800
+#define OMAP1610_MCBSP2_BASE    0xfffb1000
+#define OMAP1610_MCBSP3_BASE    0xe1017000
+
+#define OMAP_MCBSP_REG_DRR2     0x00
+#define OMAP_MCBSP_REG_DRR1     0x02
+#define OMAP_MCBSP_REG_DXR2     0x04
+#define OMAP_MCBSP_REG_DXR1     0x06
+#define OMAP_MCBSP_REG_SPCR2    0x08
+#define OMAP_MCBSP_REG_SPCR1    0x0a
+#define OMAP_MCBSP_REG_RCR2     0x0c
+#define OMAP_MCBSP_REG_RCR1     0x0e
+#define OMAP_MCBSP_REG_XCR2     0x10
+#define OMAP_MCBSP_REG_XCR1     0x12
+#define OMAP_MCBSP_REG_SRGR2    0x14
+#define OMAP_MCBSP_REG_SRGR1    0x16
+#define OMAP_MCBSP_REG_MCR2     0x18
+#define OMAP_MCBSP_REG_MCR1     0x1a
+#define OMAP_MCBSP_REG_RCERA    0x1c
+#define OMAP_MCBSP_REG_RCERB    0x1e
+#define OMAP_MCBSP_REG_XCERA    0x20
+#define OMAP_MCBSP_REG_XCERB    0x22
+#define OMAP_MCBSP_REG_PCR0     0x24
+#define OMAP_MCBSP_REG_RCERC    0x26
+#define OMAP_MCBSP_REG_RCERD    0x28
+#define OMAP_MCBSP_REG_XCERC    0x2A
+#define OMAP_MCBSP_REG_XCERD    0x2C
+#define OMAP_MCBSP_REG_RCERE    0x2E
+#define OMAP_MCBSP_REG_RCERF    0x30
+#define OMAP_MCBSP_REG_XCERE    0x32
+#define OMAP_MCBSP_REG_XCERF    0x34
+#define OMAP_MCBSP_REG_RCERG    0x36
+#define OMAP_MCBSP_REG_RCERH    0x38
+#define OMAP_MCBSP_REG_XCERG    0x3A
+#define OMAP_MCBSP_REG_XCERH    0x3C
+
+#define OMAP_MAX_MCBSP_COUNT 3
+
+#define OMAP_MCBSP_READ(base, reg)              __raw_readw((base) + OMAP_MCBSP_REG_##reg)
+#define OMAP_MCBSP_WRITE(base, reg, val)        __raw_writew((val), (base) + OMAP_MCBSP_REG_##reg)
+
+/************************** McBSP SPCR1 bit definitions ***********************/
+#define RRST                    0x0001
+#define RRDY                    0x0002
+#define RFULL                   0x0004
+#define RSYNC_ERR               0x0008
+#define RINTM(value)            ((value)<<4)    /* bits 4:5 */
+#define ABIS                    0x0040
+#define DXENA                   0x0080
+#define CLKSTP(value)           ((value)<<11)   /* bits 11:12 */
+#define RJUST(value)            ((value)<<13)   /* bits 13:14 */
+#define DLB                     0x8000
+
+/************************** McBSP SPCR2 bit definitions ***********************/
+#define XRST            0x0001
+#define XRDY            0x0002
+#define XEMPTY          0x0004
+#define XSYNC_ERR       0x0008
+#define XINTM(value)    ((value)<<4)            /* bits 4:5 */
+#define GRST            0x0040
+#define FRST            0x0080
+#define SOFT            0x0100
+#define FREE            0x0200
+
+/************************** McBSP PCR bit definitions *************************/
+#define CLKRP           0x0001
+#define CLKXP           0x0002
+#define FSRP            0x0004
+#define FSXP            0x0008
+#define DR_STAT         0x0010
+#define DX_STAT         0x0020
+#define CLKS_STAT       0x0040
+#define SCLKME          0x0080
+#define CLKRM           0x0100
+#define CLKXM           0x0200
+#define FSRM            0x0400
+#define FSXM            0x0800
+#define RIOEN           0x1000
+#define XIOEN           0x2000
+#define IDLE_EN         0x4000
+
+/************************** McBSP RCR1 bit definitions ************************/
+#define RWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
+#define RFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
+
+/************************** McBSP XCR1 bit definitions ************************/
+#define XWDLEN1(value)          ((value)<<5)    /* Bits 5:7 */
+#define XFRLEN1(value)          ((value)<<8)    /* Bits 8:14 */
+
+/*************************** McBSP RCR2 bit definitions ***********************/
+#define RDATDLY(value)          (value)         /* Bits 0:1 */
+#define RFIG                    0x0004
+#define RCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
+#define RWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
+#define RFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
+#define RPHASE                  0x8000
+
+/*************************** McBSP XCR2 bit definitions ***********************/
+#define XDATDLY(value)          (value)         /* Bits 0:1 */
+#define XFIG                    0x0004
+#define XCOMPAND(value)         ((value)<<3)    /* Bits 3:4 */
+#define XWDLEN2(value)          ((value)<<5)    /* Bits 5:7 */
+#define XFRLEN2(value)          ((value)<<8)    /* Bits 8:14 */
+#define XPHASE                  0x8000
+
+/************************* McBSP SRGR1 bit definitions ************************/
+#define CLKGDV(value)           (value)         /* Bits 0:7 */
+#define FWID(value)             ((value)<<8)    /* Bits 8:15 */
+
+/************************* McBSP SRGR2 bit definitions ************************/
+#define FPER(value)             (value)         /* Bits 0:11 */
+#define FSGM                    0x1000
+#define CLKSM                   0x2000
+#define CLKSP                   0x4000
+#define GSYNC                   0x8000
+
+/************************* McBSP MCR1 bit definitions *************************/
+#define RMCM                    0x0001
+#define RCBLK(value)            ((value)<<2)    /* Bits 2:4 */
+#define RPABLK(value)           ((value)<<5)    /* Bits 5:6 */
+#define RPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
+
+/************************* McBSP MCR2 bit definitions *************************/
+#define XMCM(value)             (value)         /* Bits 0:1 */
+#define XCBLK(value)            ((value)<<2)    /* Bits 2:4 */
+#define XPABLK(value)           ((value)<<5)    /* Bits 5:6 */
+#define XPBBLK(value)           ((value)<<7)    /* Bits 7:8 */
+
+
+/* we don't do multichannel for now */
+struct omap_mcbsp_reg_cfg {
+        u16 spcr2;
+        u16 spcr1;
+        u16 rcr2;
+        u16 rcr1;
+        u16 xcr2;
+        u16 xcr1;
+        u16 srgr2;
+        u16 srgr1;
+        u16 mcr2;
+        u16 mcr1;
+        u16 pcr0;
+        u16 rcerc;
+        u16 rcerd;
+        u16 xcerc;
+        u16 xcerd;
+        u16 rcere;
+        u16 rcerf;
+        u16 xcere;
+        u16 xcerf;
+        u16 rcerg;
+        u16 rcerh;
+        u16 xcerg;
+        u16 xcerh;
+};
+
+typedef enum {
+        OMAP_MCBSP1 = 0,
+        OMAP_MCBSP2,
+        OMAP_MCBSP3,
+} omap_mcbsp_id;
+
+typedef enum {
+        OMAP_MCBSP_WORD_8 = 0,
+        OMAP_MCBSP_WORD_12,
+        OMAP_MCBSP_WORD_16,
+        OMAP_MCBSP_WORD_20,
+        OMAP_MCBSP_WORD_24,
+        OMAP_MCBSP_WORD_32,
+} omap_mcbsp_word_length;
+
+typedef enum {
+        OMAP_MCBSP_CLK_RISING = 0,
+        OMAP_MCBSP_CLK_FALLING,
+} omap_mcbsp_clk_polarity;
+
+typedef enum {
+        OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
+        OMAP_MCBSP_FS_ACTIVE_LOW,
+} omap_mcbsp_fs_polarity;
+
+typedef enum {
+        OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
+        OMAP_MCBSP_CLK_STP_MODE_DELAY,
+} omap_mcbsp_clk_stp_mode;
+
+
+/******* SPI specific mode **********/
+typedef enum {
+        OMAP_MCBSP_SPI_MASTER = 0,
+        OMAP_MCBSP_SPI_SLAVE,
+} omap_mcbsp_spi_mode;
+
+struct omap_mcbsp_spi_cfg {
+        omap_mcbsp_spi_mode             spi_mode;
+        omap_mcbsp_clk_polarity         rx_clock_polarity;
+        omap_mcbsp_clk_polarity         tx_clock_polarity;
+        omap_mcbsp_fs_polarity          fsx_polarity;
+        u8                              clk_div;
+        omap_mcbsp_clk_stp_mode         clk_stp_mode;
+        omap_mcbsp_word_length          word_length;
+};
+
+void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
+int omap_mcbsp_request(unsigned int id);
+void omap_mcbsp_free(unsigned int id);
+void omap_mcbsp_start(unsigned int id);
+void omap_mcbsp_stop(unsigned int id);
+void omap_mcbsp_xmit_word(unsigned int id, u32 word);
+u32 omap_mcbsp_recv_word(unsigned int id);
+
+int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
+
+/* SPI specific API */
+void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
+
+/* Polled read/write functions */
+int omap_mcbsp_pollread(unsigned int id, u16 * buf);
+int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
+
+#endif
diff --git a/include/asm-arm/arch-omap/memory.h b/include/asm-arm/arch-omap/memory.h
new file mode 100644
index 000000000000..f6b57dd846a3
--- /dev/null
+++ b/include/asm-arm/arch-omap/memory.h
@@ -0,0 +1,87 @@
+/*
+ * linux/include/asm-arm/arch-omap/memory.h
+ *
+ * Memory map for OMAP-1510 and 1610
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This file was derived from linux/include/asm-arm/arch-intergrator/memory.h
+ * Copyright (C) 1999 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET             (0x10000000UL)
+
+/*
+ * OMAP-1510 Local Bus address offset
+ */
+#define OMAP1510_LB_OFFSET      (0x30000000UL)
+
+/*
+ * Conversion between SDRAM and fake PCI bus, used by USB
+ * NOTE: Physical address must be converted to Local Bus address
+ *       on OMAP-1510 only
+ */
+
+/*
+ * Bus address is physical address, except for OMAP-1510 Local Bus.
+ */
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+/*
+ * OMAP-1510 bus address is translated into a Local Bus address if the
+ * OMAP bus type is lbus. We do the address translation based on the
+ * device overriding the defaults used in the dma-mapping API.
+ * Note that the is_lbus_device() test is not very efficient on 1510
+ * because of the strncmp().
+ */
+#ifdef CONFIG_ARCH_OMAP1510
+
+#define virt_to_lbus(x)         ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
+#define lbus_to_virt(x)         ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
+#define is_lbus_device(dev)     (cpu_is_omap1510() && dev && (strncmp(dev->bus_id, "ohci", 4) == 0))
+
+#define __arch_page_to_dma(dev, page)   ({is_lbus_device(dev) ? \
+                                        (dma_addr_t)virt_to_lbus(page_address(page)) : \
+                                        (dma_addr_t)__virt_to_bus(page_address(page));})
+
+#define __arch_dma_to_virt(dev, addr)   ({is_lbus_device(dev) ? \
+                                        lbus_to_virt(addr) : \
+                                        __bus_to_virt(addr);})
+
+#define __arch_virt_to_dma(dev, addr)   ({is_lbus_device(dev) ? \
+                                        virt_to_lbus(addr) : \
+                                        __virt_to_bus(addr);})
+
+#endif  /* CONFIG_ARCH_OMAP1510 */
+
+#define PHYS_TO_NID(addr) (0)
+#endif
+
diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h
new file mode 100644
index 000000000000..39f99decbb7b
--- /dev/null
+++ b/include/asm-arm/arch-omap/mux.h
@@ -0,0 +1,561 @@
+/*
+ * linux/include/asm-arm/arch-omap/mux.h
+ *
+ * Table of the Omap register configurations for the FUNC_MUX and
+ * PULL_DWN combinations.
+ *
+ * Copyright (C) 2003 Nokia Corporation
+ *
+ * Written by Tony Lindgren <tony.lindgren@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * NOTE: Please use the following naming style for new pin entries.
+ *       For example, W8_1610_MMC2_DAT0, where:
+ *       - W8        = ball
+ *       - 1610      = 1510 or 1610, none if common for both 1510 and 1610
+ *       - MMC2_DAT0 = function
+ *
+ * Change log:
+ *   Added entry for the I2C interface. (02Feb 2004)
+ *   Copyright (C) 2004 Texas Instruments
+ *
+ *   Added entry for the keypad and uwire CS1. (09Mar 2004)
+ *   Copyright (C) 2004 Texas Instruments
+ *
+ */
+
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+
+#define PU_PD_SEL_NA            0       /* No pu_pd reg available */
+#define PULL_DWN_CTRL_NA        0       /* No pull-down control needed */
+
+#ifdef  CONFIG_OMAP_MUX_DEBUG
+#define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
+                                        .mux_reg = FUNC_MUX_CTRL_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+
+#define PULL_REG(reg, bit, status)      .pull_name = "PULL_DWN_CTRL_"#reg, \
+                                        .pull_reg = PULL_DWN_CTRL_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
+
+#define PU_PD_REG(reg, status)          .pu_pd_name = "PU_PD_SEL_"#reg, \
+                                        .pu_pd_reg = PU_PD_SEL_##reg, \
+                                        .pu_pd_val = status,
+
+#else
+
+#define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
+                                        .mask_offset = mode_offset, \
+                                        .mask = mode,
+
+#define PULL_REG(reg, bit, status)      .pull_reg = PULL_DWN_CTRL_##reg, \
+                                        .pull_bit = bit, \
+                                        .pull_val = status,
+
+#define PU_PD_REG(reg, status)          .pu_pd_reg = PU_PD_SEL_##reg, \
+                                        .pu_pd_val = status,
+
+#endif /* CONFIG_OMAP_MUX_DEBUG */
+
+#define MUX_CFG(desc, mux_reg, mode_offset, mode,       \
+                pull_reg, pull_bit, pull_status,        \
+                pu_pd_reg, pu_pd_status, debug_status)  \
+{                                                       \
+        .name =  desc,                                  \
+        .debug = debug_status,                          \
+        MUX_REG(mux_reg, mode_offset, mode)             \
+        PULL_REG(pull_reg, pull_bit, pull_status)       \
+        PU_PD_REG(pu_pd_reg, pu_pd_status)              \
+},
+
+#define PULL_DISABLED   0
+#define PULL_ENABLED    1
+
+#define PULL_DOWN       0
+#define PULL_UP         1
+
+typedef struct {
+        char *name;
+        unsigned char busy;
+        unsigned char debug;
+
+        const char *mux_reg_name;
+        const unsigned int mux_reg;
+        const unsigned char mask_offset;
+        const unsigned char mask;
+
+        const char *pull_name;
+        const unsigned int pull_reg;
+        const unsigned char pull_val;
+        const unsigned char pull_bit;
+
+        const char *pu_pd_name;
+        const unsigned int pu_pd_reg;
+        const unsigned char pu_pd_val;
+} reg_cfg_set;
+
+/*
+ * Lookup table for FUNC_MUX and PULL_DWN register combinations for each
+ * device. See also reg_cfg_table below for the register values.
+ */
+typedef enum {
+        /* UART1 (BT_UART_GATING)*/
+        UART1_TX = 0,
+        UART1_RTS,
+
+        /* UART2 (COM_UART_GATING)*/
+        UART2_TX,
+        UART2_RX,
+        UART2_CTS,
+        UART2_RTS,
+
+        /* UART3 (GIGA_UART_GATING) */
+        UART3_TX,
+        UART3_RX,
+        UART3_CTS,
+        UART3_RTS,
+        UART3_CLKREQ,
+        UART3_BCLK,     /* 12MHz clock out */
+        Y15_1610_UART3_RTS,
+
+        /* PWT & PWL */
+        PWT,
+        PWL,
+
+        /* USB master generic */
+        R18_USB_VBUS,
+        R18_1510_USB_GPIO0,
+        W4_USB_PUEN,
+        W4_USB_CLKO,
+        W4_USB_HIGHZ,
+        W4_GPIO58,
+
+        /* USB1 master */
+        USB1_SUSP,
+        USB1_SEO,
+        W13_1610_USB1_SE0,
+        USB1_TXEN,
+        USB1_TXD,
+        USB1_VP,
+        USB1_VM,
+        USB1_RCV,
+        USB1_SPEED,
+        R13_1610_USB1_SPEED,
+        R13_1710_USB1_SE0,
+
+        /* USB2 master */
+        USB2_SUSP,
+        USB2_VP,
+        USB2_TXEN,
+        USB2_VM,
+        USB2_RCV,
+        USB2_SEO,
+        USB2_TXD,
+
+        /* OMAP-1510 GPIO */
+        R18_1510_GPIO0,
+        R19_1510_GPIO1,
+        M14_1510_GPIO2,
+
+        /* OMAP1610 GPIO */
+        P18_1610_GPIO3,
+        Y15_1610_GPIO17,
+
+        /* OMAP-1710 GPIO */
+        R18_1710_GPIO0,
+        V2_1710_GPIO10,
+        N21_1710_GPIO14,
+        W15_1710_GPIO40,
+
+        /* MPUIO */
+        MPUIO2,
+        MPUIO4,
+        MPUIO5,
+        T20_1610_MPUIO5,
+        W11_1610_MPUIO6,
+        V10_1610_MPUIO7,
+        W11_1610_MPUIO9,
+        V10_1610_MPUIO10,
+        W10_1610_MPUIO11,
+        E20_1610_MPUIO13,
+        U20_1610_MPUIO14,
+        E19_1610_MPUIO15,
+
+        /* MCBSP2 */
+        MCBSP2_CLKR,
+        MCBSP2_CLKX,
+        MCBSP2_DR,
+        MCBSP2_DX,
+        MCBSP2_FSR,
+        MCBSP2_FSX,
+
+        /* MCBSP3 */
+        MCBSP3_CLKX,
+
+        /* Misc ballouts */
+        BALLOUT_V8_ARMIO3,
+
+        /* OMAP-1610 MMC2 */
+        W8_1610_MMC2_DAT0,
+        V8_1610_MMC2_DAT1,
+        W15_1610_MMC2_DAT2,
+        R10_1610_MMC2_DAT3,
+        Y10_1610_MMC2_CLK,
+        Y8_1610_MMC2_CMD,
+        V9_1610_MMC2_CMDDIR,
+        V5_1610_MMC2_DATDIR0,
+        W19_1610_MMC2_DATDIR1,
+        R18_1610_MMC2_CLKIN,
+
+        /* OMAP-1610 External Trace Interface */
+        M19_1610_ETM_PSTAT0,
+        L15_1610_ETM_PSTAT1,
+        L18_1610_ETM_PSTAT2,
+        L19_1610_ETM_D0,
+        J19_1610_ETM_D6,
+        J18_1610_ETM_D7,
+
+        /* OMAP-1610 GPIO */
+        P20_1610_GPIO4,
+        V9_1610_GPIO7,
+        W8_1610_GPIO9,
+        N19_1610_GPIO13,
+        P10_1610_GPIO22,
+        V5_1610_GPIO24,
+        AA20_1610_GPIO_41,
+        W19_1610_GPIO48,
+        M7_1610_GPIO62,
+
+        /* OMAP-1610 uWire */
+        V19_1610_UWIRE_SCLK,
+        U18_1610_UWIRE_SDI,
+        W21_1610_UWIRE_SDO,
+        N14_1610_UWIRE_CS0,
+        P15_1610_UWIRE_CS0,
+        N15_1610_UWIRE_CS1,
+
+        /* OMAP-1610 Flash */
+        L3_1610_FLASH_CS2B_OE,
+        M8_1610_FLASH_CS2B_WE,
+
+        /* First MMC */
+        MMC_CMD,
+        MMC_DAT1,
+        MMC_DAT2,
+        MMC_DAT0,
+        MMC_CLK,
+        MMC_DAT3,
+
+        /* OMAP-1710 MMC CMDDIR and DATDIR0 */
+        M15_1710_MMC_CLKI,
+        P19_1710_MMC_CMDDIR,
+        P20_1710_MMC_DATDIR0,
+
+        /* OMAP-1610 USB0 alternate pin configuration */
+        W9_USB0_TXEN,
+        AA9_USB0_VP,
+        Y5_USB0_RCV,
+        R9_USB0_VM,
+        V6_USB0_TXD,
+        W5_USB0_SE0,
+        V9_USB0_SPEED,
+        V9_USB0_SUSP,
+
+        /* USB2 */
+        W9_USB2_TXEN,
+        AA9_USB2_VP,
+        Y5_USB2_RCV,
+        R9_USB2_VM,
+        V6_USB2_TXD,
+        W5_USB2_SE0,
+
+        /* UART1 1610 */
+
+        R13_1610_UART1_TX,
+        V14_1610_UART1_RX,
+        R14_1610_UART1_CTS,
+        AA15_1610_UART1_RTS,
+
+        /* I2C OMAP-1610 */
+        I2C_SCL,
+        I2C_SDA,
+
+        /* Keypad */
+        F18_1610_KBC0,
+        D20_1610_KBC1,
+        D19_1610_KBC2,
+        E18_1610_KBC3,
+        C21_1610_KBC4,
+        G18_1610_KBR0,
+        F19_1610_KBR1,
+        H14_1610_KBR2,
+        E20_1610_KBR3,
+        E19_1610_KBR4,
+        N19_1610_KBR5,
+
+        /* Power management */
+        T20_1610_LOW_PWR,
+
+        /* MCLK Settings */
+        V5_1710_MCLK_ON,
+        V5_1710_MCLK_OFF,
+        R10_1610_MCLK_ON,
+        R10_1610_MCLK_OFF,
+
+        /* CompactFlash controller */
+        P11_1610_CF_CD2,
+        R11_1610_CF_IOIS16,
+        V10_1610_CF_IREQ,
+        W10_1610_CF_RESET,
+        W11_1610_CF_CD1,
+} reg_cfg_t;
+
+#if defined(__MUX_C__) && defined(CONFIG_OMAP_MUX)
+
+/*
+ * Table of various FUNC_MUX and PULL_DWN combinations for each device.
+ * See also reg_cfg_t above for the lookup table.
+ */
+static reg_cfg_set __initdata_or_module
+reg_cfg_table[] = {
+/*
+ *       description            mux  mode   mux  pull pull  pull  pu_pd  pu  dbg
+ *                              reg  offset mode reg  bit   ena   reg
+ */
+MUX_CFG("UART1_TX",              9,   21,    1,   2,   3,   0,   NA,     0,  0)
+MUX_CFG("UART1_RTS",             9,   12,    1,   2,   0,   0,   NA,     0,  0)
+
+/* UART2 (COM_UART_GATING), conflicts with USB2 */
+MUX_CFG("UART2_TX",              C,   27,    1,   3,   3,   0,   NA,     0,  0)
+MUX_CFG("UART2_RX",              C,   18,    0,   3,   1,   1,   NA,     0,  0)
+MUX_CFG("UART2_CTS",             C,   21,    0,   3,   1,   1,   NA,     0,  0)
+MUX_CFG("UART2_RTS",             C,   24,    1,   3,   2,   0,   NA,     0,  0)
+
+/* UART3 (GIGA_UART_GATING) */
+MUX_CFG("UART3_TX",              6,    0,    1,   0,  30,   0,   NA,     0,  0)
+MUX_CFG("UART3_RX",              6,    3,    0,   0,  31,   1,   NA,     0,  0)
+MUX_CFG("UART3_CTS",             5,   12,    2,   0,  24,   0,   NA,     0,  0)
+MUX_CFG("UART3_RTS",             5,   15,    2,   0,  25,   0,   NA,     0,  0)
+MUX_CFG("UART3_CLKREQ",          9,   27,    0,   2,   5,   0,   NA,     0,  0)
+MUX_CFG("UART3_BCLK",            A,    0,    0,   2,   6,   0,   NA,     0,  0)
+MUX_CFG("Y15_1610_UART3_RTS",    A,    0,    1,   2,   6,   0,   NA,     0,  0)
+
+/* PWT & PWL, conflicts with UART3 */
+MUX_CFG("PWT",                   6,    0,    2,   0,  30,   0,   NA,     0,  0)
+MUX_CFG("PWL",                   6,    3,    1,   0,  31,   1,   NA,     0,  0)
+
+/* USB internal master generic */
+MUX_CFG("R18_USB_VBUS",          7,    9,    2,   1,  11,   0,   NA,     0,  1)
+MUX_CFG("R18_1510_USB_GPIO0",    7,    9,    0,   1,  11,   1,   NA,     0,  1)
+/* works around erratum:  W4_USB_PUEN and W4_USB_PUDIS are switched! */
+MUX_CFG("W4_USB_PUEN",           D,    3,    3,   3,   5,   1,   NA,     0,  1)
+MUX_CFG("W4_USB_CLKO",           D,    3,    1,   3,   5,   0,   NA,     0,  1)
+MUX_CFG("W4_USB_HIGHZ",          D,    3,    4,   3,   5,   0,    3,     0,  1)
+MUX_CFG("W4_GPIO58",             D,    3,    7,   3,   5,   0,    3,     0,  1)
+
+/* USB1 master */
+MUX_CFG("USB1_SUSP",             8,   27,    2,   1,  27,   0,   NA,     0,  1)
+MUX_CFG("USB1_SE0",              9,    0,    2,   1,  28,   0,   NA,     0,  1)
+MUX_CFG("W13_1610_USB1_SE0",     9,    0,    4,   1,  28,   0,   NA,     0,  1)
+MUX_CFG("USB1_TXEN",             9,    3,    2,   1,  29,   0,   NA,     0,  1)
+MUX_CFG("USB1_TXD",              9,   24,    1,   2,   4,   0,   NA,     0,  1)
+MUX_CFG("USB1_VP",               A,    3,    1,   2,   7,   0,   NA,     0,  1)
+MUX_CFG("USB1_VM",               A,    6,    1,   2,   8,   0,   NA,     0,  1)
+MUX_CFG("USB1_RCV",              A,    9,    1,   2,   9,   0,   NA,     0,  1)
+MUX_CFG("USB1_SPEED",            A,   12,    2,   2,  10,   0,   NA,     0,  1)
+MUX_CFG("R13_1610_USB1_SPEED",   A,   12,    5,   2,  10,   0,   NA,     0,  1)
+MUX_CFG("R13_1710_USB1_SEO",     A,   12,    5,   2,  10,   0,   NA,     0,  1)
+
+/* USB2 master */
+MUX_CFG("USB2_SUSP",             B,    3,    1,   2,  17,   0,   NA,     0,  1)
+MUX_CFG("USB2_VP",               B,    6,    1,   2,  18,   0,   NA,     0,  1)
+MUX_CFG("USB2_TXEN",             B,    9,    1,   2,  19,   0,   NA,     0,  1)
+MUX_CFG("USB2_VM",               C,   18,    1,   3,   0,   0,   NA,     0,  1)
+MUX_CFG("USB2_RCV",              C,   21,    1,   3,   1,   0,   NA,     0,  1)
+MUX_CFG("USB2_SE0",              C,   24,    2,   3,   2,   0,   NA,     0,  1)
+MUX_CFG("USB2_TXD",              C,   27,    2,   3,   3,   0,   NA,     0,  1)
+
+/* OMAP-1510 GPIO */
+MUX_CFG("R18_1510_GPIO0",        7,    9,    0,   1,  11,   1,    0,     0,  1)
+MUX_CFG("R19_1510_GPIO1",        7,    6,    0,   1,  10,   1,    0,     0,  1)
+MUX_CFG("M14_1510_GPIO2",        7,    3,    0,   1,   9,   1,    0,     0,  1)
+
+/* OMAP1610 GPIO */
+MUX_CFG("P18_1610_GPIO3",        7,    0,    0,   1,   8,   0,   NA,     0,  1)
+MUX_CFG("Y15_1610_GPIO17",       A,    0,    7,   2,   6,   0,   NA,     0,  1)
+
+/* OMAP-1710 GPIO */
+MUX_CFG("R18_1710_GPIO0",        7,    9,    0,   1,  11,   1,    1,     1,  1)
+MUX_CFG("V2_1710_GPIO10",        F,   27,    1,   4,   3,   1,    4,     1,  1)
+MUX_CFG("N21_1710_GPIO14",       6,    9,    0,   1,   1,   1,    1,     1,  1)
+MUX_CFG("W15_1710_GPIO40",       9,   27,    7,   2,   5,   1,    2,     1,  1)
+
+/* MPUIO */
+MUX_CFG("MPUIO2",                7,   18,    0,   1,   1,   1,   NA,     0,  1)
+MUX_CFG("MPUIO4",                7,   15,    0,   1,  13,   1,   NA,     0,  1)
+MUX_CFG("MPUIO5",                7,   12,    0,   1,  12,   1,   NA,     0,  1)
+
+MUX_CFG("T20_1610_MPUIO5",       7,   12,    0,   1,  12,   0,    3,     0,  1)
+MUX_CFG("W11_1610_MPUIO6",      10,   15,    2,   3,   8,   0,    3,     0,  1)
+MUX_CFG("V10_1610_MPUIO7",       A,   24,    2,   2,  14,   0,    2,     0,  1)
+MUX_CFG("W11_1610_MPUIO9",      10,   15,    1,   3,   8,   0,    3,     0,  1)
+MUX_CFG("V10_1610_MPUIO10",      A,   24,    1,   2,  14,   0,    2,     0,  1)
+MUX_CFG("W10_1610_MPUIO11",      A,   18,    2,   2,  11,   0,    2,     0,  1)
+MUX_CFG("E20_1610_MPUIO13",      3,   21,    1,   0,   7,   0,    0,     0,  1)
+MUX_CFG("U20_1610_MPUIO14",      9,    6,    6,   0,  30,   0,    0,     0,  1)
+MUX_CFG("E19_1610_MPUIO15",      3,   18,    1,   0,   6,   0,    0,     0,  1)
+
+/* MCBSP2 */
+MUX_CFG("MCBSP2_CLKR",           C,    6,    0,   2,  27,   1,   NA,     0,  1)
+MUX_CFG("MCBSP2_CLKX",           C,    9,    0,   2,  29,   1,   NA,     0,  1)
+MUX_CFG("MCBSP2_DR",             C,    0,    0,   2,  26,   1,   NA,     0,  1)
+MUX_CFG("MCBSP2_DX",             C,   15,    0,   2,  31,   1,   NA,     0,  1)
+MUX_CFG("MCBSP2_FSR",            C,   12,    0,   2,  30,   1,   NA,     0,  1)
+MUX_CFG("MCBSP2_FSX",            C,    3,    0,   2,  27,   1,   NA,     0,  1)
+
+/* MCBSP3 NOTE: Mode must 1 for clock */
+MUX_CFG("MCBSP3_CLKX",           9,    3,    1,   1,  29,   0,   NA,     0,  1)
+
+/* Misc ballouts */
+MUX_CFG("BALLOUT_V8_ARMIO3",     B,   18,    0,   2,  25,   1,   NA,     0,  1)
+
+/* OMAP-1610 MMC2 */
+MUX_CFG("W8_1610_MMC2_DAT0",     B,   21,    6,   2,  23,   1,    2,     1,  1)
+MUX_CFG("V8_1610_MMC2_DAT1",     B,   27,    6,   2,  25,   1,    2,     1,  1)
+MUX_CFG("W15_1610_MMC2_DAT2",    9,   12,    6,   2,   5,   1,    2,     1,  1)
+MUX_CFG("R10_1610_MMC2_DAT3",    B,   18,    6,   2,  22,   1,    2,     1,  1)
+MUX_CFG("Y10_1610_MMC2_CLK",     B,    3,    6,   2,  17,   0,    2,     0,  1)
+MUX_CFG("Y8_1610_MMC2_CMD",      B,   24,    6,   2,  24,   1,    2,     1,  1)
+MUX_CFG("V9_1610_MMC2_CMDDIR",   B,   12,    6,   2,  20,   0,    2,     1,  1)
+MUX_CFG("V5_1610_MMC2_DATDIR0",  B,   15,    6,   2,  21,   0,    2,     1,  1)
+MUX_CFG("W19_1610_MMC2_DATDIR1", 8,   15,    6,   1,  23,   0,    1,     1,  1)
+MUX_CFG("R18_1610_MMC2_CLKIN",   7,    9,    6,   1,  11,   0,    1,    11,  1)
+
+/* OMAP-1610 External Trace Interface */
+MUX_CFG("M19_1610_ETM_PSTAT0",   5,   27,    1,   0,  29,   0,    0,     0,  1)
+MUX_CFG("L15_1610_ETM_PSTAT1",   5,   24,    1,   0,  28,   0,    0,     0,  1)
+MUX_CFG("L18_1610_ETM_PSTAT2",   5,   21,    1,   0,  27,   0,    0,     0,  1)
+MUX_CFG("L19_1610_ETM_D0",       5,   18,    1,   0,  26,   0,    0,     0,  1)
+MUX_CFG("J19_1610_ETM_D6",       5,    0,    1,   0,  20,   0,    0,     0,  1)
+MUX_CFG("J18_1610_ETM_D7",       5,   27,    1,   0,  19,   0,    0,     0,  1)
+
+/* OMAP-1610 GPIO */
+MUX_CFG("P20_1610_GPIO4",        6,   27,    0,   1,   7,   0,    1,     1,  1)
+MUX_CFG("V9_1610_GPIO7",         B,   12,    1,   2,  20,   0,    2,     1,  1)
+MUX_CFG("W8_1610_GPIO9",         B,   21,    0,   2,  23,   0,    2,     1,  1)
+MUX_CFG("N19_1610_GPIO13",       6,   12,    0,   1,   2,   0,    1,     1,  1)
+MUX_CFG("P10_1610_GPIO22",       C,    0,    7,   2,  26,   0,    2,     1,  1)
+MUX_CFG("V5_1610_GPIO24",        B,   15,    7,   2,  21,   0,    2,     1,  1)
+MUX_CFG("AA20_1610_GPIO_41",     9,    9,    7,   1,  31,   0,    1,     1,  1)
+MUX_CFG("W19_1610_GPIO48",       8,   15,    7,   1,  23,   1,    1,     0,  1)
+MUX_CFG("M7_1610_GPIO62",       10,    0,    0,   4,  24,   0,    4,     0,  1)
+
+/* OMAP-1610 uWire */
+MUX_CFG("V19_1610_UWIRE_SCLK",   8,    6,    0,   1,  20,   0,    1,     1,  1)
+MUX_CFG("U18_1610_UWIRE_SDI",    8,    0,    0,   1,  18,   0,    1,     1,  1)
+MUX_CFG("W21_1610_UWIRE_SDO",    8,    3,    0,   1,  19,   0,    1,     1,  1)
+MUX_CFG("N14_1610_UWIRE_CS0",    8,    9,    1,   1,  21,   0,    1,     1,  1)
+MUX_CFG("P15_1610_UWIRE_CS3",    8,   12,    1,   1,  22,   0,    1,     1,  1)
+MUX_CFG("N15_1610_UWIRE_CS1",    7,   18,    2,   1,  14,   0,   NA,     0,  1)
+
+/* OMAP-1610 Flash */
+MUX_CFG("L3_1610_FLASH_CS2B_OE",10,    6,    1,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("M8_1610_FLASH_CS2B_WE",10,    3,    1,  NA,   0,   0,   NA,     0,  1)
+
+/* First MMC interface, same on 1510, 1610 and 1710 */
+MUX_CFG("MMC_CMD",               A,   27,    0,   2,  15,   1,    2,     1,  1)
+MUX_CFG("MMC_DAT1",              A,   24,    0,   2,  14,   1,    2,     1,  1)
+MUX_CFG("MMC_DAT2",              A,   18,    0,   2,  12,   1,    2,     1,  1)
+MUX_CFG("MMC_DAT0",              B,    0,    0,   2,  16,   1,    2,     1,  1)
+MUX_CFG("MMC_CLK",               A,   21,    0,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("MMC_DAT3",             10,   15,    0,   3,   8,   1,    3,     1,  1)
+MUX_CFG("M15_1710_MMC_CLKI",     6,   21,    2,   0,   0,   0,   NA,     0,  1)
+MUX_CFG("P19_1710_MMC_CMDDIR",   6,   24,    6,   0,   0,   0,   NA,     0,  1)
+MUX_CFG("P20_1710_MMC_DATDIR0",  6,   27,    5,   0,   0,   0,   NA,     0,  1)
+
+/* OMAP-1610 USB0 alternate configuration */
+MUX_CFG("W9_USB0_TXEN",          B,   9,     5,   2,  19,   0,    2,     0,  1)
+MUX_CFG("AA9_USB0_VP",           B,   6,     5,   2,  18,   0,    2,     0,  1)
+MUX_CFG("Y5_USB0_RCV",           C,  21,     5,   3,   1,   0,    1,     0,  1)
+MUX_CFG("R9_USB0_VM",            C,  18,     5,   3,   0,   0,    3,     0,  1)
+MUX_CFG("V6_USB0_TXD",           C,  27,     5,   3,   3,   0,    3,     0,  1)
+MUX_CFG("W5_USB0_SE0",           C,  24,     5,   3,   2,   0,    3,     0,  1)
+MUX_CFG("V9_USB0_SPEED",         B,  12,     5,   2,  20,   0,    2,     0,  1)
+MUX_CFG("Y10_USB0_SUSP",         B,   3,     5,   2,  17,   0,    2,     0,  1)
+
+/* USB2 interface */
+MUX_CFG("W9_USB2_TXEN",          B,   9,     1,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("AA9_USB2_VP",           B,   6,     1,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("Y5_USB2_RCV",           C,  21,     1,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("R8_USB2_VM",            C,  18,     1,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("V6_USB2_TXD",           C,  27,     2,  NA,   0,   0,   NA,     0,  1)
+MUX_CFG("W5_USB2_SE0",           C,  24,     2,  NA,   0,   0,   NA,     0,  1)
+
+
+/* UART1 */
+MUX_CFG("R13_1610_UART1_TX",     A,  12,     6,   2,  10,   0,    2,    10,  1)
+MUX_CFG("V14_1610_UART1_RX",     9,  18,     0,   2,   2,   0,    2,     2,  1)
+MUX_CFG("R14_1610_UART1_CTS",    9,  15,     0,   2,   1,   0,    2,     1,  1)
+MUX_CFG("AA15_1610_UART1_RTS",   9,  12,     1,   2,   0,   0,    2,     0,  1)
+
+/* I2C interface */
+MUX_CFG("I2C_SCL",               7,  24,     0,  NA,   0,   0,   NA,     0,  0)
+MUX_CFG("I2C_SDA",               7,  27,     0,  NA,   0,   0,   NA,     0,  0)
+
+/* Keypad */
+MUX_CFG("F18_1610_KBC0",         3,  15,     0,   0,   5,   1,    0,     0,  0)
+MUX_CFG("D20_1610_KBC1",         3,  12,     0,   0,   4,   1,    0,     0,  0)
+MUX_CFG("D19_1610_KBC2",         3,   9,     0,   0,   3,   1,    0,     0,  0)
+MUX_CFG("E18_1610_KBC3",         3,   6,     0,   0,   2,   1,    0,     0,  0)
+MUX_CFG("C21_1610_KBC4",         3,   3,     0,   0,   1,   1,    0,     0,  0)
+MUX_CFG("G18_1610_KBR0",         4,   0,     0,   0,   10,  1,    0,     1,  0)
+MUX_CFG("F19_1610_KBR1",         3,   27,    0,   0,   9,   1,    0,     1,  0)
+MUX_CFG("H14_1610_KBR2",         3,   24,    0,   0,   8,   1,    0,     1,  0)
+MUX_CFG("E20_1610_KBR3",         3,   21,    0,   0,   7,   1,    0,     1,  0)
+MUX_CFG("E19_1610_KBR4",         3,   18,    0,   0,   6,   1,    0,     1,  0)
+MUX_CFG("N19_1610_KBR5",         6,  12,     1,   1,   2,   1,    1,     1,  0)
+
+/* Power management */
+MUX_CFG("T20_1610_LOW_PWR",      7,   12,    1,   NA,   0,   0,   NA,    0,  0)
+
+/* MCLK Settings */
+MUX_CFG("V5_1710_MCLK_ON",       B,   15,    0,   NA,   0,   0,   NA,    0,  0)
+MUX_CFG("V5_1710_MCLK_OFF",      B,   15,    6,   NA,   0,   0,   NA,    0,  0)
+MUX_CFG("R10_1610_MCLK_ON",      B,   18,    0,   NA,  22,   0,   NA,    1,  0)
+MUX_CFG("R10_1610_MCLK_OFF",     B,   18,    6,   2,   22,   1,   2,     1,  1)
+
+/* CompactFlash controller, conflicts with MMC1 */
+MUX_CFG("P11_1610_CF_CD2",       A,   27,    3,   2,   15,   1,   2,     1,  1)
+MUX_CFG("R11_1610_CF_IOIS16",    B,    0,    3,   2,   16,   1,   2,     1,  1)
+MUX_CFG("V10_1610_CF_IREQ",      A,   24,    3,   2,   14,   0,   2,     0,  1)
+MUX_CFG("W10_1610_CF_RESET",     A,   18,    3,   2,   12,   1,   2,     1,  1)
+MUX_CFG("W11_1610_CF_CD1",      10,   15,    3,   3,    8,   1,   3,     1,  1)
+};
+
+#endif  /* __MUX_C__ */
+
+#ifdef  CONFIG_OMAP_MUX
+/* setup pin muxing in Linux */
+extern int omap_cfg_reg(reg_cfg_t reg_cfg);
+#else
+/* boot loader does it all (no warnings from CONFIG_OMAP_MUX_WARNINGS) */
+static inline int omap_cfg_reg(reg_cfg_t reg_cfg) { return 0; }
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-omap/omap1510.h b/include/asm-arm/arch-omap/omap1510.h
new file mode 100644
index 000000000000..f491a48ef2e1
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap1510.h
@@ -0,0 +1,61 @@
+/* linux/include/asm-arm/arch-omap/omap1510.h
+ *
+ * Hardware definitions for TI OMAP1510 processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP1510_H
+#define __ASM_ARCH_OMAP1510_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP1510_SRAM_BASE      0xD0000000
+#define OMAP1510_SRAM_SIZE      (SZ_128K + SZ_64K)
+#define OMAP1510_SRAM_START     0x20000000
+
+#define OMAP1510_DSP_BASE       0xE0000000
+#define OMAP1510_DSP_SIZE       0x28000
+#define OMAP1510_DSP_START      0xE0000000
+
+#define OMAP1510_DSPREG_BASE    0xE1000000
+#define OMAP1510_DSPREG_SIZE    SZ_128K
+#define OMAP1510_DSPREG_START   0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * Memory used by power management
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1510_SRAM_IDLE_SUSPEND      (OMAP1510_SRAM_BASE + OMAP1510_SRAM_SIZE - 0x200)
+#define OMAP1510_SRAM_API_SUSPEND       (OMAP1510_SRAM_IDLE_SUSPEND + 0x100)
+
+#endif /*  __ASM_ARCH_OMAP1510_H */
+
diff --git a/include/asm-arm/arch-omap/omap16xx.h b/include/asm-arm/arch-omap/omap16xx.h
new file mode 100644
index 000000000000..88b1fe43ae9e
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap16xx.h
@@ -0,0 +1,187 @@
+/* linux/include/asm-arm/arch-omap/omap16xx.h
+ *
+ * Hardware definitions for TI OMAP1610/5912/1710 processors.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP16XX_H
+#define __ASM_ARCH_OMAP16XX_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP16XX_SRAM_BASE      0xD0000000
+#define OMAP1610_SRAM_SIZE      (SZ_16K)
+#define OMAP5912_SRAM_SIZE      0x3E800
+#define OMAP16XX_SRAM_START     0x20000000
+
+#define OMAP16XX_DSP_BASE       0xE0000000
+#define OMAP16XX_DSP_SIZE       0x28000
+#define OMAP16XX_DSP_START      0xE0000000
+
+#define OMAP16XX_DSPREG_BASE    0xE1000000
+#define OMAP16XX_DSPREG_SIZE    SZ_128K
+#define OMAP16XX_DSPREG_START   0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * Memory used by power management
+ * ----------------------------------------------------------------------------
+ */
+
+#define OMAP1610_SRAM_IDLE_SUSPEND      (OMAP16XX_SRAM_BASE + OMAP1610_SRAM_SIZE - 0x200)
+#define OMAP1610_SRAM_API_SUSPEND       (OMAP1610_SRAM_IDLE_SUSPEND + 0x100)
+#define OMAP5912_SRAM_IDLE_SUSPEND      (OMAP16XX_SRAM_BASE + OMAP5912_SRAM_SIZE - 0x200)
+#define OMAP5912_SRAM_API_SUSPEND       (OMAP5912_SRAM_IDLE_SUSPEND + 0x100)
+
+/*
+ * ---------------------------------------------------------------------------
+ * Interrupts
+ * ---------------------------------------------------------------------------
+ */
+#define OMAP_IH2_0_BASE         (0xfffe0000)
+#define OMAP_IH2_1_BASE         (0xfffe0100)
+#define OMAP_IH2_2_BASE         (0xfffe0200)
+#define OMAP_IH2_3_BASE         (0xfffe0300)
+
+#define OMAP_IH2_0_ITR          (OMAP_IH2_0_BASE + 0x00)
+#define OMAP_IH2_0_MIR          (OMAP_IH2_0_BASE + 0x04)
+#define OMAP_IH2_0_SIR_IRQ      (OMAP_IH2_0_BASE + 0x10)
+#define OMAP_IH2_0_SIR_FIQ      (OMAP_IH2_0_BASE + 0x14)
+#define OMAP_IH2_0_CONTROL      (OMAP_IH2_0_BASE + 0x18)
+#define OMAP_IH2_0_ILR0         (OMAP_IH2_0_BASE + 0x1c)
+#define OMAP_IH2_0_ISR          (OMAP_IH2_0_BASE + 0x9c)
+
+#define OMAP_IH2_1_ITR          (OMAP_IH2_1_BASE + 0x00)
+#define OMAP_IH2_1_MIR          (OMAP_IH2_1_BASE + 0x04)
+#define OMAP_IH2_1_SIR_IRQ      (OMAP_IH2_1_BASE + 0x10)
+#define OMAP_IH2_1_SIR_FIQ      (OMAP_IH2_1_BASE + 0x14)
+#define OMAP_IH2_1_CONTROL      (OMAP_IH2_1_BASE + 0x18)
+#define OMAP_IH2_1_ILR1         (OMAP_IH2_1_BASE + 0x1c)
+#define OMAP_IH2_1_ISR          (OMAP_IH2_1_BASE + 0x9c)
+
+#define OMAP_IH2_2_ITR          (OMAP_IH2_2_BASE + 0x00)
+#define OMAP_IH2_2_MIR          (OMAP_IH2_2_BASE + 0x04)
+#define OMAP_IH2_2_SIR_IRQ      (OMAP_IH2_2_BASE + 0x10)
+#define OMAP_IH2_2_SIR_FIQ      (OMAP_IH2_2_BASE + 0x14)
+#define OMAP_IH2_2_CONTROL      (OMAP_IH2_2_BASE + 0x18)
+#define OMAP_IH2_2_ILR2         (OMAP_IH2_2_BASE + 0x1c)
+#define OMAP_IH2_2_ISR          (OMAP_IH2_2_BASE + 0x9c)
+
+#define OMAP_IH2_3_ITR          (OMAP_IH2_3_BASE + 0x00)
+#define OMAP_IH2_3_MIR          (OMAP_IH2_3_BASE + 0x04)
+#define OMAP_IH2_3_SIR_IRQ      (OMAP_IH2_3_BASE + 0x10)
+#define OMAP_IH2_3_SIR_FIQ      (OMAP_IH2_3_BASE + 0x14)
+#define OMAP_IH2_3_CONTROL      (OMAP_IH2_3_BASE + 0x18)
+#define OMAP_IH2_3_ILR3         (OMAP_IH2_3_BASE + 0x1c)
+#define OMAP_IH2_3_ISR          (OMAP_IH2_3_BASE + 0x9c)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Clocks
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP16XX_ARM_IDLECT3    (CLKGEN_REG_BASE + 0x24)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pin configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP16XX_CONF_VOLTAGE_VDDSHV6   (1 << 8)
+#define OMAP16XX_CONF_VOLTAGE_VDDSHV7   (1 << 9)
+#define OMAP16XX_CONF_VOLTAGE_VDDSHV8   (1 << 10)
+#define OMAP16XX_CONF_VOLTAGE_VDDSHV9   (1 << 11)
+#define OMAP16XX_SUBLVDS_CONF_VALID     (1 << 13)
+
+/*
+ * ----------------------------------------------------------------------------
+ * System control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP1610_RESET_CONTROL  0xfffe1140
+
+/*
+ * ---------------------------------------------------------------------------
+ * TIPB bus interface
+ * ---------------------------------------------------------------------------
+ */
+#define TIPB_SWITCH_BASE                 (0xfffbc800)
+#define OMAP16XX_MMCSD2_SSW_MPU_CONF    (TIPB_SWITCH_BASE + 0x160)
+
+/* UART3 Registers Maping through MPU bus */
+#define UART3_RHR               (OMAP_UART3_BASE + 0)
+#define UART3_THR               (OMAP_UART3_BASE + 0)
+#define UART3_DLL               (OMAP_UART3_BASE + 0)
+#define UART3_IER               (OMAP_UART3_BASE + 4)
+#define UART3_DLH               (OMAP_UART3_BASE + 4)
+#define UART3_IIR               (OMAP_UART3_BASE + 8)
+#define UART3_FCR               (OMAP_UART3_BASE + 8)
+#define UART3_EFR               (OMAP_UART3_BASE + 8)
+#define UART3_LCR               (OMAP_UART3_BASE + 0x0C)
+#define UART3_MCR               (OMAP_UART3_BASE + 0x10)
+#define UART3_XON1_ADDR1        (OMAP_UART3_BASE + 0x10)
+#define UART3_XON2_ADDR2        (OMAP_UART3_BASE + 0x14)
+#define UART3_LSR               (OMAP_UART3_BASE + 0x14)
+#define UART3_TCR               (OMAP_UART3_BASE + 0x18)
+#define UART3_MSR               (OMAP_UART3_BASE + 0x18)
+#define UART3_XOFF1             (OMAP_UART3_BASE + 0x18)
+#define UART3_XOFF2             (OMAP_UART3_BASE + 0x1C)
+#define UART3_SPR               (OMAP_UART3_BASE + 0x1C)
+#define UART3_TLR               (OMAP_UART3_BASE + 0x1C)
+#define UART3_MDR1              (OMAP_UART3_BASE + 0x20)
+#define UART3_MDR2              (OMAP_UART3_BASE + 0x24)
+#define UART3_SFLSR             (OMAP_UART3_BASE + 0x28)
+#define UART3_TXFLL             (OMAP_UART3_BASE + 0x28)
+#define UART3_RESUME            (OMAP_UART3_BASE + 0x2C)
+#define UART3_TXFLH             (OMAP_UART3_BASE + 0x2C)
+#define UART3_SFREGL            (OMAP_UART3_BASE + 0x30)
+#define UART3_RXFLL             (OMAP_UART3_BASE + 0x30)
+#define UART3_SFREGH            (OMAP_UART3_BASE + 0x34)
+#define UART3_RXFLH             (OMAP_UART3_BASE + 0x34)
+#define UART3_BLR               (OMAP_UART3_BASE + 0x38)
+#define UART3_ACREG             (OMAP_UART3_BASE + 0x3C)
+#define UART3_DIV16             (OMAP_UART3_BASE + 0x3C)
+#define UART3_SCR               (OMAP_UART3_BASE + 0x40)
+#define UART3_SSR               (OMAP_UART3_BASE + 0x44)
+#define UART3_EBLR              (OMAP_UART3_BASE + 0x48)
+#define UART3_OSC_12M_SEL       (OMAP_UART3_BASE + 0x4C)
+#define UART3_MVR               (OMAP_UART3_BASE + 0x50)
+
+/*
+ * ----------------------------------------------------------------------------
+ * Pulse-Width Light
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP16XX_PWL_BASE       (0xfffb5800)
+#define OMAP16XX_PWL_ENABLE     (OMAP16XX_PWL_BASE + 0x00)
+#define OMAP16XX_PWL_CLK_ENABLE (OMAP16XX_PWL_BASE + 0x04)
+
+#endif /*  __ASM_ARCH_OMAP16XX_H */
+
diff --git a/include/asm-arm/arch-omap/omap730.h b/include/asm-arm/arch-omap/omap730.h
new file mode 100644
index 000000000000..599ab00f5488
--- /dev/null
+++ b/include/asm-arm/arch-omap/omap730.h
@@ -0,0 +1,106 @@
+/* linux/include/asm-arm/arch-omap/omap730.h
+ *
+ * Hardware definitions for TI OMAP730 processor.
+ *
+ * Cleanup for Linux-2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP730_H
+#define __ASM_ARCH_OMAP730_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Base addresses
+ * ----------------------------------------------------------------------------
+ */
+
+/* Syntax: XX_BASE = Virtual base address, XX_START = Physical base address */
+
+#define OMAP730_SRAM_BASE       0xD0000000
+#define OMAP730_SRAM_SIZE       (SZ_128K + SZ_64K + SZ_8K)
+#define OMAP730_SRAM_START      0x20000000
+
+#define OMAP730_DSP_BASE        0xE0000000
+#define OMAP730_DSP_SIZE        0x50000
+#define OMAP730_DSP_START       0xE0000000
+
+#define OMAP730_DSPREG_BASE     0xE1000000
+#define OMAP730_DSPREG_SIZE     SZ_128K
+#define OMAP730_DSPREG_START    0xE1000000
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 specific configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_CONFIG_BASE     0xfffe1000
+#define OMAP730_IO_CONF_0       0xfffe1070
+#define OMAP730_IO_CONF_1       0xfffe1074
+#define OMAP730_IO_CONF_2       0xfffe1078
+#define OMAP730_IO_CONF_3       0xfffe107c
+#define OMAP730_IO_CONF_4       0xfffe1080
+#define OMAP730_IO_CONF_5       0xfffe1084
+#define OMAP730_IO_CONF_6       0xfffe1088
+#define OMAP730_IO_CONF_7       0xfffe108c
+#define OMAP730_IO_CONF_8       0xfffe1090
+#define OMAP730_IO_CONF_9       0xfffe1094
+#define OMAP730_IO_CONF_10      0xfffe1098
+#define OMAP730_IO_CONF_11      0xfffe109c
+#define OMAP730_IO_CONF_12      0xfffe10a0
+#define OMAP730_IO_CONF_13      0xfffe10a4
+
+#define OMAP730_MODE_1          0xfffe1010
+#define OMAP730_MODE_2          0xfffe1014
+
+/* CSMI specials: in terms of base + offset */
+#define OMAP730_MODE2_OFFSET    0x14
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 traffic controller configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_FLASH_CFG_0     0xfffecc10
+#define OMAP730_FLASH_ACFG_0    0xfffecc50
+#define OMAP730_FLASH_CFG_1     0xfffecc14
+#define OMAP730_FLASH_ACFG_1    0xfffecc54
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 DSP control registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_ICR_BASE        0xfffbb800
+#define OMAP730_DSP_M_CTL       0xfffbb804
+#define OMAP730_DSP_MMU_BASE    0xfffed200
+
+/*
+ * ----------------------------------------------------------------------------
+ * OMAP730 PCC_UPLD configuration registers
+ * ----------------------------------------------------------------------------
+ */
+#define OMAP730_PCC_UPLD_CTRL_BASE      (0xfffe0900)
+#define OMAP730_PCC_UPLD_CTRL           (OMAP730_PCC_UPLD_CTRL_BASE + 0x00)
+
+#endif /*  __ASM_ARCH_OMAP730_H */
+
diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h
new file mode 100644
index 000000000000..face9ad41e97
--- /dev/null
+++ b/include/asm-arm/arch-omap/param.h
@@ -0,0 +1,8 @@
+/*
+ *  linux/include/asm-arm/arch-omap/param.h
+ *
+ */
+
+#ifdef CONFIG_OMAP_32K_TIMER_HZ
+#define HZ      CONFIG_OMAP_32K_TIMER_HZ
+#endif
diff --git a/include/asm-arm/arch-omap/pm.h b/include/asm-arm/arch-omap/pm.h
new file mode 100644
index 000000000000..f209fc0953fb
--- /dev/null
+++ b/include/asm-arm/arch-omap/pm.h
@@ -0,0 +1,229 @@
+/*
+ * linux/include/asm/arch-omap/pm.h
+ *
+ * Header file for OMAP Power Management Routines
+ *
+ * Author: MontaVista Software, Inc.
+ *         support@mvista.com
+ *
+ * Copyright 2002 MontaVista Software Inc.
+ *
+ * Cleanup 2004 for Linux 2.6 by Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_OMAP_PM_H
+#define __ASM_ARCH_OMAP_PM_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Register and offset definitions to be used in PM assembler code
+ * ----------------------------------------------------------------------------
+ */
+#define CLKGEN_REG_ASM_BASE             io_p2v(0xfffece00)
+#define ARM_IDLECT1_ASM_OFFSET          0x04
+#define ARM_IDLECT2_ASM_OFFSET          0x08
+
+#define TCMIF_ASM_BASE                  io_p2v(0xfffecc00)
+#define EMIFS_CONFIG_ASM_OFFSET         0x0c
+#define EMIFF_SDRAM_CONFIG_ASM_OFFSET   0x20
+
+/*
+ * ----------------------------------------------------------------------------
+ * Powermanagement bitmasks
+ * ----------------------------------------------------------------------------
+ */
+#define IDLE_WAIT_CYCLES                0x00000fff
+#define PERIPHERAL_ENABLE               0x2
+
+#define SELF_REFRESH_MODE               0x0c000001
+#define IDLE_EMIFS_REQUEST              0xc
+#define MODEM_32K_EN                    0x1
+#define PER_EN                          0x1
+
+#define CPU_SUSPEND_SIZE                200
+#define ULPD_LOW_POWER_EN               0x0001
+
+#define DSP_IDLE_DELAY                  10
+#define DSP_IDLE                        0x0040
+#define DSP_RST                         0x0004
+#define DSP_ENABLE                      0x0002
+#define SUFFICIENT_DSP_RESET_TIME       1000
+#define DEFAULT_MPUI_CONFIG             0x05cf
+#define ENABLE_XORCLK                   0x2
+#define DSP_CLOCK_ENABLE                0x2000
+#define DSP_IDLE_MODE                   0x2
+#define TC_IDLE_REQUEST                 (0x0000000c)
+
+#define IRQ_LEVEL2                      (1<<0)
+#define IRQ_KEYBOARD                    (1<<1)
+#define IRQ_UART2                       (1<<15)
+
+#define PDE_BIT                         0x08
+#define PWD_EN_BIT                      0x04
+#define EN_PERCK_BIT                    0x04
+
+#define OMAP1510_DEEP_SLEEP_REQUEST     0x0ec7
+#define OMAP1510_BIG_SLEEP_REQUEST      0x0cc5
+#define OMAP1510_IDLE_LOOP_REQUEST      0x0c00
+#define OMAP1510_IDLE_CLOCK_DOMAINS     0x2
+#define OMAP1510_ULPD_LOW_POWER_REQ     0x0001
+
+#define OMAP1610_DEEP_SLEEP_REQUEST     0x17c7
+#define OMAP1610_BIG_SLEEP_REQUEST      TBD
+#define OMAP1610_IDLE_LOOP_REQUEST      0x0400
+#define OMAP1610_IDLE_CLOCK_DOMAINS     0x09c7
+#define OMAP1610_ULPD_LOW_POWER_REQ     0x3
+
+#ifndef OMAP1510_SRAM_IDLE_SUSPEND
+#define OMAP1510_SRAM_IDLE_SUSPEND 0
+#endif
+#ifndef OMAP1610_SRAM_IDLE_SUSPEND
+#define OMAP1610_SRAM_IDLE_SUSPEND 0
+#endif
+#ifndef OMAP5912_SRAM_IDLE_SUSPEND
+#define OMAP5912_SRAM_IDLE_SUSPEND 0
+#endif
+
+#ifndef OMAP1510_SRAM_API_SUSPEND
+#define OMAP1510_SRAM_API_SUSPEND 0
+#endif
+#ifndef OMAP1610_SRAM_API_SUSPEND
+#define OMAP1610_SRAM_API_SUSPEND 0
+#endif
+#ifndef OMAP5912_SRAM_API_SUSPEND
+#define OMAP5912_SRAM_API_SUSPEND 0
+#endif
+
+#if     !defined(CONFIG_ARCH_OMAP1510) && \
+        !defined(CONFIG_ARCH_OMAP16XX)
+#error "Power management for this processor not implemented yet"
+#endif
+
+#ifndef __ASSEMBLER__
+extern void omap_pm_idle(void);
+extern void omap_pm_suspend(void);
+extern int omap1510_cpu_suspend(unsigned short, unsigned short);
+extern int omap1610_cpu_suspend(unsigned short, unsigned short);
+extern int omap1510_idle_loop_suspend(void);
+extern int omap1610_idle_loop_suspend(void);
+extern unsigned int omap1510_cpu_suspend_sz;
+extern unsigned int omap1510_idle_loop_suspend_sz;
+extern unsigned int omap1610_cpu_suspend_sz;
+extern unsigned int omap1610_idle_loop_suspend_sz;
+
+#define ARM_SAVE(x) arm_sleep_save[ARM_SLEEP_SAVE_##x] = omap_readl(x)
+#define ARM_RESTORE(x) omap_writel((arm_sleep_save[ARM_SLEEP_SAVE_##x]), (x))
+#define ARM_SHOW(x) arm_sleep_save[ARM_SLEEP_SAVE_##x]
+
+#define ULPD_SAVE(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x] = omap_readw(x)
+#define ULPD_RESTORE(x) omap_writew((ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]), (x))
+#define ULPD_SHOW(x) ulpd_sleep_save[ULPD_SLEEP_SAVE_##x]
+
+#define MPUI1510_SAVE(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x] = omap_readl(x)
+#define MPUI1510_RESTORE(x) omap_writel((mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]), (x))
+#define MPUI1510_SHOW(x) mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_##x]
+
+#define MPUI1610_SAVE(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x] = omap_readl(x)
+#define MPUI1610_RESTORE(x) omap_writel((mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]), (x))
+#define MPUI1610_SHOW(x) mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_##x]
+
+/*
+ * List of global OMAP registers to preserve.
+ * More ones like CP and general purpose register values are preserved
+ * with the stack pointer in sleep.S.
+ */
+
+enum arm_save_state {
+        ARM_SLEEP_SAVE_START = 0,
+        /*
+         * MPU control registers 32 bits
+         */
+        ARM_SLEEP_SAVE_ARM_CKCTL,
+        ARM_SLEEP_SAVE_ARM_IDLECT1,
+        ARM_SLEEP_SAVE_ARM_IDLECT2,
+        ARM_SLEEP_SAVE_ARM_EWUPCT,
+        ARM_SLEEP_SAVE_ARM_RSTCT1,
+        ARM_SLEEP_SAVE_ARM_RSTCT2,
+        ARM_SLEEP_SAVE_ARM_SYSST,
+        ARM_SLEEP_SAVE_SIZE
+};
+
+enum ulpd_save_state {
+        ULPD_SLEEP_SAVE_START = 0,
+        /*
+         * ULPD registers 16 bits
+         */
+        ULPD_SLEEP_SAVE_ULPD_IT_STATUS,
+        ULPD_SLEEP_SAVE_ULPD_CLOCK_CTRL,
+        ULPD_SLEEP_SAVE_ULPD_SOFT_REQ,
+        ULPD_SLEEP_SAVE_ULPD_STATUS_REQ,
+        ULPD_SLEEP_SAVE_ULPD_DPLL_CTRL,
+        ULPD_SLEEP_SAVE_ULPD_POWER_CTRL,
+        ULPD_SLEEP_SAVE_SIZE
+};
+
+enum mpui1510_save_state {
+        MPUI1510_SLEEP_SAVE_START = 0,
+        /*
+         * MPUI registers 32 bits
+         */
+        MPUI1510_SLEEP_SAVE_MPUI_CTRL,
+        MPUI1510_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
+        MPUI1510_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
+        MPUI1510_SLEEP_SAVE_MPUI_DSP_STATUS,
+        MPUI1510_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
+        MPUI1510_SLEEP_SAVE_EMIFS_CONFIG,
+        MPUI1510_SLEEP_SAVE_OMAP_IH1_MIR,
+        MPUI1510_SLEEP_SAVE_OMAP_IH2_MIR,
+#if defined(CONFIG_ARCH_OMAP1510)
+        MPUI1510_SLEEP_SAVE_SIZE
+#else
+        MPUI1510_SLEEP_SAVE_SIZE = 0
+#endif
+};
+
+enum mpui1610_save_state {
+        MPUI1610_SLEEP_SAVE_START = 0,
+        /*
+         * MPUI registers 32 bits
+         */
+        MPUI1610_SLEEP_SAVE_MPUI_CTRL,
+        MPUI1610_SLEEP_SAVE_MPUI_DSP_BOOT_CONFIG,
+        MPUI1610_SLEEP_SAVE_MPUI_DSP_API_CONFIG,
+        MPUI1610_SLEEP_SAVE_MPUI_DSP_STATUS,
+        MPUI1610_SLEEP_SAVE_EMIFF_SDRAM_CONFIG,
+        MPUI1610_SLEEP_SAVE_EMIFS_CONFIG,
+        MPUI1610_SLEEP_SAVE_OMAP_IH1_MIR,
+        MPUI1610_SLEEP_SAVE_OMAP_IH2_0_MIR,
+        MPUI1610_SLEEP_SAVE_OMAP_IH2_1_MIR,
+        MPUI1610_SLEEP_SAVE_OMAP_IH2_2_MIR,
+        MPUI1610_SLEEP_SAVE_OMAP_IH2_3_MIR,
+#if defined(CONFIG_ARCH_OMAP16XX)
+        MPUI1610_SLEEP_SAVE_SIZE
+#else
+        MPUI1610_SLEEP_SAVE_SIZE = 0
+#endif
+};
+
+#endif /* ASSEMBLER */
+#endif /* __ASM_ARCH_OMAP_PM_H */
diff --git a/include/asm-arm/arch-omap/system.h b/include/asm-arm/arch-omap/system.h
new file mode 100644
index 000000000000..17a2c4825f07
--- /dev/null
+++ b/include/asm-arm/arch-omap/system.h
@@ -0,0 +1,20 @@
+/*
+ * Copied from linux/include/asm-arm/arch-sa1100/system.h
+ * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+#include <linux/config.h>
+#include <asm/arch/hardware.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        omap_writew(1, ARM_RSTCT1);
+}
+
+#endif
diff --git a/include/asm-arm/arch-omap/tc.h b/include/asm-arm/arch-omap/tc.h
new file mode 100644
index 000000000000..8ded218cbea5
--- /dev/null
+++ b/include/asm-arm/arch-omap/tc.h
@@ -0,0 +1,108 @@
+/*
+ * linux/include/asm-arm/arch-omap/tc.h
+ *
+ * OMAP Traffic Controller
+ *
+ * Copyright (C) 2004 Nokia Corporation
+ * Author: Imre Deak <imre.deak@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifndef __ASM_ARCH_TC_H
+#define __ASM_ARCH_TC_H
+
+#define TCMIF_BASE              0xfffecc00
+#define OMAP_TC_OCPT1_PRIOR     (TCMIF_BASE + 0x00)
+#define OMAP_TC_EMIFS_PRIOR     (TCMIF_BASE + 0x04)
+#define OMAP_TC_EMIFF_PRIOR     (TCMIF_BASE + 0x08)
+#define EMIFS_CONFIG            (TCMIF_BASE + 0x0c)
+#define EMIFS_CS0_CONFIG        (TCMIF_BASE + 0x10)
+#define EMIFS_CS1_CONFIG        (TCMIF_BASE + 0x14)
+#define EMIFS_CS2_CONFIG        (TCMIF_BASE + 0x18)
+#define EMIFS_CS3_CONFIG        (TCMIF_BASE + 0x1c)
+#define EMIFF_SDRAM_CONFIG      (TCMIF_BASE + 0x20)
+#define EMIFF_MRS               (TCMIF_BASE + 0x24)
+#define TC_TIMEOUT1             (TCMIF_BASE + 0x28)
+#define TC_TIMEOUT2             (TCMIF_BASE + 0x2c)
+#define TC_TIMEOUT3             (TCMIF_BASE + 0x30)
+#define TC_ENDIANISM            (TCMIF_BASE + 0x34)
+#define EMIFF_SDRAM_CONFIG_2    (TCMIF_BASE + 0x3c)
+#define EMIF_CFG_DYNAMIC_WS     (TCMIF_BASE + 0x40)
+#define EMIFS_ACS0              (TCMIF_BASE + 0x50)
+#define EMIFS_ACS1              (TCMIF_BASE + 0x54)
+#define EMIFS_ACS2              (TCMIF_BASE + 0x58)
+#define EMIFS_ACS3              (TCMIF_BASE + 0x5c)
+#define OMAP_TC_OCPT2_PRIOR     (TCMIF_BASE + 0xd0)
+
+/* external EMIFS chipselect regions */
+#define OMAP_CS0_PHYS           0x00000000
+#define OMAP_CS0_SIZE           SZ_64M
+
+#define OMAP_CS1_PHYS           0x04000000
+#define OMAP_CS1_SIZE           SZ_64M
+
+#define OMAP_CS1A_PHYS          OMAP_CS1_PHYS
+#define OMAP_CS1A_SIZE          SZ_32M
+
+#define OMAP_CS1B_PHYS          (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
+#define OMAP_CS1B_SIZE          SZ_32M
+
+#define OMAP_CS2_PHYS           0x08000000
+#define OMAP_CS2_SIZE           SZ_64M
+
+#define OMAP_CS2A_PHYS          OMAP_CS2_PHYS
+#define OMAP_CS2A_SIZE          SZ_32M
+
+#define OMAP_CS2B_PHYS          (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
+#define OMAP_CS2B_SIZE          SZ_32M
+
+#define OMAP_CS3_PHYS           0x0c000000
+#define OMAP_CS3_SIZE           SZ_64M
+
+#ifndef __ASSEMBLER__
+
+/* EMIF Slow Interface Configuration Register */
+#define OMAP_EMIFS_CONFIG_REG   __REG32(EMIFS_CONFIG)
+
+#define OMAP_EMIFS_CONFIG_FR            (1 << 4)
+#define OMAP_EMIFS_CONFIG_PDE           (1 << 3)
+#define OMAP_EMIFS_CONFIG_PWD_EN        (1 << 2)
+#define OMAP_EMIFS_CONFIG_BM            (1 << 1)
+#define OMAP_EMIFS_CONFIG_WP            (1 << 0)
+
+#define EMIFS_CCS(n)            __REG32(EMIFS_CS0_CONFIG + (4 * (n)))
+#define EMIFS_ACS(n)            __REG32(EMIFS_ACS0 + (4 * (n)))
+
+/* Almost all documentation for chip and board memory maps assumes
+ * BM is clear.  Most devel boards have a switch to control booting
+ * from NOR flash (using external chipselect 3) rather than mask ROM,
+ * which uses BM to interchange the physical CS0 and CS3 addresses.
+ */
+static inline u32 omap_cs0_phys(void)
+{
+        return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
+                        ?  OMAP_CS3_PHYS : 0;
+}
+
+static inline u32 omap_cs3_phys(void)
+{
+        return (OMAP_EMIFS_CONFIG_REG & OMAP_EMIFS_CONFIG_BM)
+                        ? 0 : OMAP_CS3_PHYS;
+}
+
+#endif  /* __ASSEMBLER__ */
+
+#endif  /* __ASM_ARCH_TC_H */
diff --git a/include/asm-arm/arch-omap/timex.h b/include/asm-arm/arch-omap/timex.h
new file mode 100644
index 000000000000..b61ddb491e83
--- /dev/null
+++ b/include/asm-arm/arch-omap/timex.h
@@ -0,0 +1,33 @@
+/*
+ * linux/include/asm-arm/arch-omap/timex.h
+ *
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author:  Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
+#define __ASM_ARCH_OMAP_TIMEX_H
+
+#define CLOCK_TICK_RATE         (HZ * 100000UL)
+
+#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/include/asm-arm/arch-omap/tps65010.h b/include/asm-arm/arch-omap/tps65010.h
new file mode 100644
index 000000000000..0f97bb2e8fce
--- /dev/null
+++ b/include/asm-arm/arch-omap/tps65010.h
@@ -0,0 +1,80 @@
+/* linux/include/asm-arm/arch-omap/tps65010.h
+ *
+ * Functions to access TPS65010 power management device.
+ *
+ * Copyright (C) 2004 Dirk Behme <dirk.behme@de.bosch.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the  GNU General Public License along
+ * with this program; if not, write  to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __ASM_ARCH_TPS65010_H
+#define __ASM_ARCH_TPS65010_H
+
+/*
+ * ----------------------------------------------------------------------------
+ * Macros used by exported functions
+ * ----------------------------------------------------------------------------
+ */
+
+#define LED1  1
+#define LED2  2
+#define OFF   0
+#define ON    1
+#define BLINK 2
+#define GPIO1 1
+#define GPIO2 2
+#define GPIO3 3
+#define GPIO4 4
+#define LOW   0
+#define HIGH  1
+
+/*
+ * ----------------------------------------------------------------------------
+ * Exported functions
+ * ----------------------------------------------------------------------------
+ */
+
+/* Draw from VBUS:
+ *   0 mA -- DON'T DRAW (might supply power instead)
+ * 100 mA -- usb unit load (slowest charge rate)
+ * 500 mA -- usb high power (fast battery charge)
+ */
+extern int tps65010_set_vbus_draw(unsigned mA);
+
+/* tps65010_set_gpio_out_value parameter:
+ * gpio:  GPIO1, GPIO2, GPIO3 or GPIO4
+ * value: LOW or HIGH
+ */
+extern int tps65010_set_gpio_out_value(unsigned gpio, unsigned value);
+
+/* tps65010_set_led parameter:
+ * led:  LED1 or LED2
+ * mode: ON, OFF or BLINK
+ */
+extern int tps65010_set_led(unsigned led, unsigned mode);
+
+/* tps65010_set_low_pwr parameter:
+ * mode: ON or OFF
+ */
+extern int tps65010_set_low_pwr(unsigned mode);
+
+#endif /*  __ASM_ARCH_TPS65010_H */
+
diff --git a/include/asm-arm/arch-omap/uncompress.h b/include/asm-arm/arch-omap/uncompress.h
new file mode 100644
index 000000000000..3e640aba8c20
--- /dev/null
+++ b/include/asm-arm/arch-omap/uncompress.h
@@ -0,0 +1,82 @@
+/*
+ * linux/include/asm-arm/arch-omap/uncompress.h
+ *
+ * Serial port stubs for kernel decompress status messages
+ *
+ * Initially based on:
+ * linux-2.4.15-rmk1-dsplinux1.6/include/asm-arm/arch-omap1510/uncompress.h
+ * Copyright (C) 2000 RidgeRun, Inc.
+ * Author: Greg Lonnon <glonnon@ridgerun.com>
+ *
+ * Rewritten by:
+ * Author: <source@mvista.com>
+ * 2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/serial_reg.h>
+#include <asm/arch/hardware.h>
+
+unsigned int system_rev;
+
+#define UART_OMAP_MDR1          0x08    /* mode definition register */
+#define OMAP_ID_730             0x355F
+#define ID_MASK                 0x7fff
+#define check_port(base, shift) ((base[UART_OMAP_MDR1 << shift] & 7) == 0)
+#define omap_get_id() ((*(volatile unsigned int *)(0xfffed404)) >> 12) & ID_MASK
+
+static void
+putstr(const char *s)
+{
+        volatile u8 * uart = 0;
+        int shift;
+
+#ifdef  CONFIG_OMAP_LL_DEBUG_UART3
+        uart = (volatile u8 *)(OMAP_UART3_BASE);
+#elif   CONFIG_OMAP_LL_DEBUG_UART2
+        uart = (volatile u8 *)(OMAP_UART2_BASE);
+#else
+        uart = (volatile u8 *)(OMAP_UART1_BASE);
+#endif
+
+        /* Determine which serial port to use */
+        do {
+                /* MMU is not on, so cpu_is_omapXXXX() won't work here */
+                unsigned int omap_id = omap_get_id();
+
+                if (omap_id == OMAP_ID_730)
+                        shift = 0;
+                else
+                        shift = 2;
+
+                if (check_port(uart, shift))
+                        break;
+                /* Silent boot if no serial ports are enabled. */
+                return;
+        } while (0);
+
+        /*
+         * Now, xmit each character
+         */
+        while (*s) {
+                while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+                        barrier();
+                uart[UART_TX << shift] = *s;
+                if (*s++ == '\n') {
+                        while (!(uart[UART_LSR << shift] & UART_LSR_THRE))
+                                barrier();
+                        uart[UART_TX << shift] = '\r';
+                }
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-omap/usb.h b/include/asm-arm/arch-omap/usb.h
new file mode 100644
index 000000000000..1438c6cef0ca
--- /dev/null
+++ b/include/asm-arm/arch-omap/usb.h
@@ -0,0 +1,108 @@
+// include/asm-arm/mach-omap/usb.h
+
+#ifndef __ASM_ARCH_OMAP_USB_H
+#define __ASM_ARCH_OMAP_USB_H
+
+#include <asm/arch/board.h>
+
+/*-------------------------------------------------------------------------*/
+
+#define OTG_BASE                        0xfffb0400
+#define UDC_BASE                        0xfffb4000
+#define OMAP_OHCI_BASE                  0xfffba000
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * OTG and transceiver registers, for OMAPs starting with ARM926
+ */
+#define OTG_REG32(offset)               __REG32(OTG_BASE + (offset))
+#define OTG_REG16(offset)               __REG16(OTG_BASE + (offset))
+
+#define OTG_REV_REG                     OTG_REG32(0x00)
+#define OTG_SYSCON_1_REG                OTG_REG32(0x04)
+#       define   USB2_TRX_MODE(w)       (((w)>>24)&0x07)
+#       define   USB1_TRX_MODE(w)       (((w)>>20)&0x07)
+#       define   USB0_TRX_MODE(w)       (((w)>>16)&0x07)
+#       define   OTG_IDLE_EN            (1 << 15)
+#       define   HST_IDLE_EN            (1 << 14)
+#       define   DEV_IDLE_EN            (1 << 13)
+#       define   OTG_RESET_DONE         (1 << 2)
+#define OTG_SYSCON_2_REG                OTG_REG32(0x08)
+#       define   OTG_EN                 (1 << 31)
+#       define   USBX_SYNCHRO           (1 << 30)
+#       define   OTG_MST16              (1 << 29)
+#       define   SRP_GPDATA             (1 << 28)
+#       define   SRP_GPDVBUS            (1 << 27)
+#       define   SRP_GPUVBUS(w)         (((w)>>24)&0x07)
+#       define   A_WAIT_VRISE(w)        (((w)>>20)&0x07)
+#       define   B_ASE_BRST(w)          (((w)>>16)&0x07)
+#       define   SRP_DPW                (1 << 14)
+#       define   SRP_DATA               (1 << 13)
+#       define   SRP_VBUS               (1 << 12)
+#       define   OTG_PADEN              (1 << 10)
+#       define   HMC_PADEN              (1 << 9)
+#       define   UHOST_EN               (1 << 8)
+#       define   HMC_TLLSPEED           (1 << 7)
+#       define   HMC_TLLATTACH          (1 << 6)
+#       define   OTG_HMC(w)             (((w)>>0)&0x3f)
+#define OTG_CTRL_REG                    OTG_REG32(0x0c)
+#       define   OTG_ASESSVLD           (1 << 20)
+#       define   OTG_BSESSEND           (1 << 19)
+#       define   OTG_BSESSVLD           (1 << 18)
+#       define   OTG_VBUSVLD            (1 << 17)
+#       define   OTG_ID                 (1 << 16)
+#       define   OTG_DRIVER_SEL         (1 << 15)
+#       define   OTG_A_SETB_HNPEN       (1 << 12)
+#       define   OTG_A_BUSREQ           (1 << 11)
+#       define   OTG_B_HNPEN            (1 << 9)
+#       define   OTG_B_BUSREQ           (1 << 8)
+#       define   OTG_BUSDROP            (1 << 7)
+#       define   OTG_PULLDOWN           (1 << 5)
+#       define   OTG_PULLUP             (1 << 4)
+#       define   OTG_DRV_VBUS           (1 << 3)
+#       define   OTG_PD_VBUS            (1 << 2)
+#       define   OTG_PU_VBUS            (1 << 1)
+#       define   OTG_PU_ID              (1 << 0)
+#define OTG_IRQ_EN_REG                  OTG_REG16(0x10)
+#       define   DRIVER_SWITCH          (1 << 15)
+#       define   A_VBUS_ERR             (1 << 13)
+#       define   A_REQ_TMROUT           (1 << 12)
+#       define   A_SRP_DETECT           (1 << 11)
+#       define   B_HNP_FAIL             (1 << 10)
+#       define   B_SRP_TMROUT           (1 << 9)
+#       define   B_SRP_DONE             (1 << 8)
+#       define   B_SRP_STARTED          (1 << 7)
+#       define   OPRT_CHG               (1 << 0)
+#define OTG_IRQ_SRC_REG                 OTG_REG16(0x14)
+        // same bits as in IRQ_EN
+#define OTG_OUTCTRL_REG                 OTG_REG16(0x18)
+#       define   OTGVPD                 (1 << 14)
+#       define   OTGVPU                 (1 << 13)
+#       define   OTGPUID                (1 << 12)
+#       define   USB2VDR                (1 << 10)
+#       define   USB2PDEN               (1 << 9)
+#       define   USB2PUEN               (1 << 8)
+#       define   USB1VDR                (1 << 6)
+#       define   USB1PDEN               (1 << 5)
+#       define   USB1PUEN               (1 << 4)
+#       define   USB0VDR                (1 << 2)
+#       define   USB0PDEN               (1 << 1)
+#       define   USB0PUEN               (1 << 0)
+#define OTG_TEST_REG                    OTG_REG16(0x20)
+#define OTG_VENDOR_CODE_REG             OTG_REG32(0xfc)
+
+/*-------------------------------------------------------------------------*/
+
+#define USB_TRANSCEIVER_CTRL_REG        __REG32(0xfffe1000 + 0x0064)
+#       define  CONF_USB2_UNI_R         (1 << 8)
+#       define  CONF_USB1_UNI_R         (1 << 7)
+#       define  CONF_USB_PORT0_R(x)     (((x)>>4)&0x7)
+#       define  CONF_USB0_ISOLATE_R     (1 << 3)
+#       define  CONF_USB_PWRDN_DM_R     (1 << 2)
+#       define  CONF_USB_PWRDN_DP_R     (1 << 1)
+
+
+
+
+#endif  /* __ASM_ARCH_OMAP_USB_H */
diff --git a/include/asm-arm/arch-omap/vmalloc.h b/include/asm-arm/arch-omap/vmalloc.h
new file mode 100644
index 000000000000..c6a83581a2fc
--- /dev/null
+++ b/include/asm-arm/arch-omap/vmalloc.h
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/arch-omap/vmalloc.h
+ *
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
+
diff --git a/include/asm-arm/arch-pxa/audio.h b/include/asm-arm/arch-pxa/audio.h
new file mode 100644
index 000000000000..60976f830e3f
--- /dev/null
+++ b/include/asm-arm/arch-pxa/audio.h
@@ -0,0 +1,16 @@
+#ifndef __ASM_ARCH_AUDIO_H__
+#define __ASM_ARCH_AUDIO_H__
+
+#include <sound/driver.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+
+typedef struct {
+        int (*startup)(snd_pcm_substream_t *, void *);
+        void (*shutdown)(snd_pcm_substream_t *, void *);
+        void (*suspend)(void *);
+        void (*resume)(void *);
+        void *priv;
+} pxa2xx_audio_ops_t;
+
+#endif
diff --git a/include/asm-arm/arch-pxa/bitfield.h b/include/asm-arm/arch-pxa/bitfield.h
new file mode 100644
index 000000000000..f1f0e3387d9c
--- /dev/null
+++ b/include/asm-arm/arch-pxa/bitfield.h
@@ -0,0 +1,113 @@
+/*
+ *      FILE            bitfield.h
+ *
+ *      Version         1.1
+ *      Author          Copyright (c) Marc A. Viredaz, 1998
+ *                      DEC Western Research Laboratory, Palo Alto, CA
+ *      Date            April 1998 (April 1997)
+ *      System          Advanced RISC Machine (ARM)
+ *      Language        C or ARM Assembly
+ *      Purpose         Definition of macros to operate on bit fields.
+ */
+
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)     ((unsigned long) (Data))
+#else
+#define UData(Data)     (Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size              Size of the bit field, in number of bits.
+ *    Shft              Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld               Encoded bit field.
+ */
+
+#define Fld(Size, Shft) (((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field             Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize             Size of the bit field, in number of bits.
+ *    FShft             Shift value of the bit field with respect to bit 0.
+ *    FMsk              Mask for the bit field.
+ *    FAlnMsk           Mask for the bit field, aligned on bit 0.
+ *    F1stBit           First bit of the bit field.
+ */
+
+#define FSize(Field)    ((Field) >> 16)
+#define FShft(Field)    ((Field) & 0x0000FFFF)
+#define FMsk(Field)     (((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)  ((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)  (UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value             Bit-field value.
+ *    Field             Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt            Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+                        (UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data              Data containing the bit-field to be extracted.
+ *    Field             Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr             Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+                        ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
diff --git a/include/asm-arm/arch-pxa/corgi.h b/include/asm-arm/arch-pxa/corgi.h
new file mode 100644
index 000000000000..324db06b5dd4
--- /dev/null
+++ b/include/asm-arm/arch-pxa/corgi.h
@@ -0,0 +1,120 @@
+/*
+ * Hardware specific definitions for SL-C7xx series of PDAs
+ *
+ * Copyright (c) 2004-2005 Richard Purdie
+ *
+ * Based on Sharp's 2.4 kernel patches
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __ASM_ARCH_CORGI_H
+#define __ASM_ARCH_CORGI_H  1
+
+
+/*
+ * Corgi (Non Standard) GPIO Definitions
+ */
+#define CORGI_GPIO_KEY_INT                      (0)     /* Keyboard Interrupt */
+#define CORGI_GPIO_AC_IN                        (1) /* Charger Detection */
+#define CORGI_GPIO_WAKEUP                       (3) /* System wakeup notification? */
+#define CORGI_GPIO_AK_INT                       (4)     /* Headphone Jack Control Interrupt */
+#define CORGI_GPIO_TP_INT                       (5)     /* Touch Panel Interrupt */
+#define CORGI_GPIO_nSD_WP                       (7) /* SD Write Protect? */
+#define CORGI_GPIO_nSD_DETECT           (9) /* MMC/SD Card Detect */
+#define CORGI_GPIO_nSD_INT                      (10) /* SD Interrupt for SDIO? */
+#define CORGI_GPIO_MAIN_BAT_LOW         (11) /* Main Battery Low Notification */
+#define CORGI_GPIO_BAT_COVER            (11) /* Battery Cover Detect */
+#define CORGI_GPIO_LED_ORANGE           (13) /* Orange LED Control */
+#define CORGI_GPIO_CF_CD                        (14) /* Compact Flash Card Detect */
+#define CORGI_GPIO_CHRG_FULL            (16) /* Charging Complete Notification */
+#define CORGI_GPIO_CF_IRQ                       (17) /* Compact Flash Interrupt */
+#define CORGI_GPIO_LCDCON_CS            (19) /* LCD Control Chip Select */
+#define CORGI_GPIO_MAX1111_CS           (20) /* MAX1111 Chip Select */
+#define CORGI_GPIO_ADC_TEMP_ON          (21) /* Select battery voltage or temperature */
+#define CORGI_GPIO_IR_ON                        (22) /* Enable IR Transciever */
+#define CORGI_GPIO_ADS7846_CS           (24) /* ADS7846 Chip Select */
+#define CORGI_GPIO_SD_PWR                       (33) /* MMC/SD Power */
+#define CORGI_GPIO_CHRG_ON                      (38) /* Enable battery Charging */
+#define CORGI_GPIO_DISCHARGE_ON         (42) /* Enable battery Discharge */
+#define CORGI_GPIO_CHRG_UKN                     (43) /* Unknown Charging (Bypass Control?) */
+#define CORGI_GPIO_HSYNC                        (44) /* LCD HSync Pulse */
+#define CORGI_GPIO_USB_PULLUP           (45) /* USB show presence to host */
+
+
+/*
+ * Corgi Keyboard Definitions
+ */
+#define CORGI_KEY_STROBE_NUM            (12)
+#define CORGI_KEY_SENSE_NUM                     (8)
+#define CORGI_GPIO_ALL_STROBE_BIT       (0x00003ffc)
+#define CORGI_GPIO_HIGH_SENSE_BIT       (0xfc000000)
+#define CORGI_GPIO_HIGH_SENSE_RSHIFT    (26)
+#define CORGI_GPIO_LOW_SENSE_BIT        (0x00000003)
+#define CORGI_GPIO_LOW_SENSE_LSHIFT     (6)
+#define CORGI_GPIO_STROBE_BIT(a)        GPIO_bit(66+(a))
+#define CORGI_GPIO_SENSE_BIT(a)         GPIO_bit(58+(a))
+#define CORGI_GAFR_ALL_STROBE_BIT       (0x0ffffff0)
+#define CORGI_GAFR_HIGH_SENSE_BIT       (0xfff00000)
+#define CORGI_GAFR_LOW_SENSE_BIT        (0x0000000f)
+#define CORGI_GPIO_KEY_SENSE(a)         (58+(a))
+#define CORGI_GPIO_KEY_STROBE(a)        (66+(a))
+
+
+/*
+ * Corgi Interrupts
+ */
+#define CORGI_IRQ_GPIO_KEY_INT          IRQ_GPIO(0)
+#define CORGI_IRQ_GPIO_AC_IN            IRQ_GPIO(1)
+#define CORGI_IRQ_GPIO_WAKEUP           IRQ_GPIO(3)
+#define CORGI_IRQ_GPIO_AK_INT           IRQ_GPIO(4)
+#define CORGI_IRQ_GPIO_TP_INT           IRQ_GPIO(5)
+#define CORGI_IRQ_GPIO_nSD_DETECT       IRQ_GPIO(9)
+#define CORGI_IRQ_GPIO_nSD_INT          IRQ_GPIO(10)
+#define CORGI_IRQ_GPIO_MAIN_BAT_LOW     IRQ_GPIO(11)
+#define CORGI_IRQ_GPIO_CF_CD            IRQ_GPIO(14)
+#define CORGI_IRQ_GPIO_CHRG_FULL        IRQ_GPIO(16)    /* Battery fully charged */
+#define CORGI_IRQ_GPIO_CF_IRQ           IRQ_GPIO(17)
+#define CORGI_IRQ_GPIO_KEY_SENSE(a)     IRQ_GPIO(58+(a))        /* Keyboard Sense lines */
+
+
+/*
+ * Corgi SCOOP GPIOs and Config
+ */
+#define CORGI_SCP_LED_GREEN             SCOOP_GPCR_PA11
+#define CORGI_SCP_SWA                   SCOOP_GPCR_PA12  /* Hinge Switch A */
+#define CORGI_SCP_SWB                   SCOOP_GPCR_PA13  /* Hinge Switch B */
+#define CORGI_SCP_MUTE_L                SCOOP_GPCR_PA14
+#define CORGI_SCP_MUTE_R                SCOOP_GPCR_PA15
+#define CORGI_SCP_AKIN_PULLUP   SCOOP_GPCR_PA16
+#define CORGI_SCP_APM_ON                SCOOP_GPCR_PA17
+#define CORGI_SCP_BACKLIGHT_CONT        SCOOP_GPCR_PA18
+#define CORGI_SCP_MIC_BIAS              SCOOP_GPCR_PA19
+
+#define CORGI_SCOOP_IO_DIR      ( CORGI_SCP_LED_GREEN | CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R | \
+                        CORGI_SCP_AKIN_PULLUP | CORGI_SCP_APM_ON | CORGI_SCP_BACKLIGHT_CONT | \
+                        CORGI_SCP_MIC_BIAS )
+#define CORGI_SCOOP_IO_OUT      ( CORGI_SCP_MUTE_L | CORGI_SCP_MUTE_R )
+
+
+/*
+ * Shared data structures
+ */
+extern struct platform_device corgiscoop_device;
+
+/*
+ * External Functions
+ */
+extern unsigned long corgi_ssp_ads7846_putget(unsigned long);
+extern unsigned long corgi_ssp_ads7846_get(void);
+extern void corgi_ssp_ads7846_put(ulong data);
+extern void corgi_ssp_ads7846_lock(void);
+extern void corgi_ssp_ads7846_unlock(void);
+extern void corgi_ssp_lcdtg_send (u8 adrs, u8 data);
+extern void corgi_ssp_blduty_set(int duty);
+extern int corgi_ssp_max1111_get(ulong data);
+
+#endif /* __ASM_ARCH_CORGI_H  */
+
diff --git a/include/asm-arm/arch-pxa/debug-macro.S b/include/asm-arm/arch-pxa/debug-macro.S
new file mode 100644
index 000000000000..f288e74b67c2
--- /dev/null
+++ b/include/asm-arm/arch-pxa/debug-macro.S
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-pxa/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x40000000                @ physical
+                movne   \rx, #io_p2v(0x40000000)        @ virtual
+                orr     \rx, \rx, #0x00100000
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #0]
+                .endm
+
+                .macro  busyuart,rd,rx
+1002:           ldr     \rd, [\rx, #0x14]
+                tst     \rd, #(1 << 6)
+                beq     1002b
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x14]
+                tst     \rd, #(1 << 5)
+                beq     1001b
+                .endm
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
new file mode 100644
index 000000000000..56db3d49bfc8
--- /dev/null
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -0,0 +1,67 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/dma.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+
+/* No DMA as the rest of the world see it */
+#define MAX_DMA_CHANNELS        0
+
+/*
+ * Descriptor structure for PXA's DMA engine
+ * Note: this structure must always be aligned to a 16-byte boundary.
+ */
+
+typedef struct pxa_dma_desc {
+        volatile u32 ddadr;     /* Points to the next descriptor + flags */
+        volatile u32 dsadr;     /* DSADR value for the current transfer */
+        volatile u32 dtadr;     /* DTADR value for the current transfer */
+        volatile u32 dcmd;      /* DCMD value for the current transfer */
+} pxa_dma_desc;
+
+#if defined(CONFIG_PXA27x)
+
+#define PXA_DMA_CHANNELS        32
+#define PXA_DMA_NBCH(prio)      ((prio == DMA_PRIO_LOW) ? 16 : 8)
+
+typedef enum {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 8,
+        DMA_PRIO_LOW = 16
+} pxa_dma_prio;
+
+#elif defined(CONFIG_PXA25x)
+
+#define PXA_DMA_CHANNELS        16
+#define PXA_DMA_NBCH(prio)      ((prio == DMA_PRIO_LOW) ? 8 : 4)
+
+typedef enum {
+        DMA_PRIO_HIGH = 0,
+        DMA_PRIO_MEDIUM = 4,
+        DMA_PRIO_LOW = 8
+} pxa_dma_prio;
+
+#endif
+
+/*
+ * DMA registration
+ */
+
+int pxa_request_dma (char *name,
+                         pxa_dma_prio prio,
+                         void (*irq_handler)(int, void *, struct pt_regs *),
+                         void *data);
+
+void pxa_free_dma (int dma_ch);
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S
new file mode 100644
index 000000000000..2abfc8bb3ee5
--- /dev/null
+++ b/include/asm-arm/arch-pxa/entry-macro.S
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-pxa/entry-macro.S
+ *
+ * Low-level IRQ helper macros for PXA-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+#ifdef CONFIG_PXA27x
+                mrc     p6, 0, \irqstat, c0, c0, 0              @ ICIP
+                mrc     p6, 0, \irqnr, c1, c0, 0                @ ICMR
+#else
+                mov     \base, #io_p2v(0x40000000)      @ IIR Ctl = 0x40d00000
+                add     \base, \base, #0x00d00000
+                ldr     \irqstat, [\base, #0]           @ ICIP
+                ldr     \irqnr, [\base, #4]             @ ICMR
+#endif
+                ands    \irqnr, \irqstat, \irqnr
+                beq     1001f
+                rsb     \irqstat, \irqnr, #0
+                and     \irqstat, \irqstat, \irqnr
+                clz     \irqnr, \irqstat
+                rsb     \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP)
+1001:
+                .endm
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
new file mode 100644
index 000000000000..72b04d846a23
--- /dev/null
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -0,0 +1,95 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/hardware.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/*
+ * We requires absolute addresses.
+ */
+#define PCIO_BASE               0
+
+/*
+ * Workarounds for at least 2 errata so far require this.
+ * The mapping is set in mach-pxa/generic.c.
+ */
+#define UNCACHED_PHYS_0         0xff000000
+#define UNCACHED_ADDR           UNCACHED_PHYS_0
+
+/*
+ * Intel PXA2xx internal register mapping:
+ *
+ * 0x40000000 - 0x41ffffff <--> 0xf2000000 - 0xf3ffffff
+ * 0x44000000 - 0x45ffffff <--> 0xf4000000 - 0xf5ffffff
+ * 0x48000000 - 0x49ffffff <--> 0xf6000000 - 0xf7ffffff
+ * 0x4c000000 - 0x4dffffff <--> 0xf8000000 - 0xf9ffffff
+ * 0x50000000 - 0x51ffffff <--> 0xfa000000 - 0xfbffffff
+ * 0x54000000 - 0x55ffffff <--> 0xfc000000 - 0xfdffffff
+ * 0x58000000 - 0x59ffffff <--> 0xfe000000 - 0xffffffff
+ *
+ * Note that not all PXA2xx chips implement all those addresses, and the
+ * kernel only maps the minimum needed range of this mapping.
+ */
+#define io_p2v(x) (0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
+#define io_v2p(x) (0x3c000000 + ((x) & 0x01ffffff) + (((x) & 0x0e000000) << 1))
+
+#ifndef __ASSEMBLY__
+
+#if 0
+# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
+#else
+/*
+ * This __REG() version gives the same results as the one above,  except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers.  It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+#include <asm/types.h>
+typedef struct { volatile u32 offset[4096]; } __regbase;
+# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x)       __REGP(io_p2v(x))
+#endif
+
+/* With indexed regs we don't want to feed the index through io_p2v()
+   especially if it is a variable, otherwise horrible code will result. */
+# define __REG2(x,y)     (*(volatile u32 *)((u32)&__REG(x) + (y)))
+
+# define __PREG(x)      (io_v2p((u32)&(x)))
+
+#else
+
+# define __REG(x)       io_p2v(x)
+# define __PREG(x)      io_v2p(x)
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Handy routine to set GPIO alternate functions
+ */
+extern void pxa_gpio_mode( int gpio_mode );
+
+/*
+ * Routine to enable or disable CKEN
+ */
+extern void pxa_set_cken(int clock, int enable);
+
+/*
+ * return current memory and LCD clock frequency in units of 10kHz
+ */
+extern unsigned int get_memclk_frequency_10khz(void);
+extern unsigned int get_lcdclk_frequency_10khz(void);
+
+#endif
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-pxa/idp.h b/include/asm-arm/arch-pxa/idp.h
new file mode 100644
index 000000000000..e7ef497417bb
--- /dev/null
+++ b/include/asm-arm/arch-pxa/idp.h
@@ -0,0 +1,200 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/idp.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright (c) 2001 Cliff Brake, Accelent Systems Inc.
+ *
+ * 2001-09-13: Cliff Brake <cbrake@accelent.com>
+ *             Initial code
+ *
+ * 2005-02-15: Cliff Brake <cliff.brake@gmail.com>
+ *             <http://www.vibren.com> <http://bec-systems.com>
+ *             Changes for 2.6 kernel.
+ */
+
+#include <linux/config.h>
+
+/*
+ * Note: this file must be safe to include in assembly files
+ *
+ * Support for the Vibren PXA255 IDP requires rev04 or later
+ * IDP hardware.
+ */
+
+
+#define IDP_FLASH_PHYS          (PXA_CS0_PHYS)
+#define IDP_ALT_FLASH_PHYS      (PXA_CS1_PHYS)
+#define IDP_MEDIAQ_PHYS         (PXA_CS3_PHYS)
+#define IDP_IDE_PHYS            (PXA_CS5_PHYS + 0x03000000)
+#define IDP_ETH_PHYS            (PXA_CS5_PHYS + 0x03400000)
+#define IDP_COREVOLT_PHYS       (PXA_CS5_PHYS + 0x03800000)
+#define IDP_CPLD_PHYS           (PXA_CS5_PHYS + 0x03C00000)
+
+
+/*
+ * virtual memory map
+ */
+
+#define IDP_COREVOLT_VIRT       (0xf0000000)
+#define IDP_COREVOLT_SIZE       (1*1024*1024)
+
+#define IDP_CPLD_VIRT           (IDP_COREVOLT_VIRT + IDP_COREVOLT_SIZE)
+#define IDP_CPLD_SIZE           (1*1024*1024)
+
+#if (IDP_CPLD_VIRT + IDP_CPLD_SIZE) > 0xfc000000
+#error Your custom IO space is getting a bit large !!
+#endif
+
+#define CPLD_P2V(x)             ((x) - IDP_CPLD_PHYS + IDP_CPLD_VIRT)
+#define CPLD_V2P(x)             ((x) - IDP_CPLD_VIRT + IDP_CPLD_PHYS)
+
+#ifndef __ASSEMBLY__
+#  define __CPLD_REG(x)         (*((volatile unsigned long *)CPLD_P2V(x)))
+#else
+#  define __CPLD_REG(x)         CPLD_P2V(x)
+#endif
+
+/* board level registers in the CPLD: (offsets from CPLD_VIRT) */
+
+#define _IDP_CPLD_REV                   (IDP_CPLD_PHYS + 0x00)
+#define _IDP_CPLD_PERIPH_PWR            (IDP_CPLD_PHYS + 0x04)
+#define _IDP_CPLD_LED_CONTROL           (IDP_CPLD_PHYS + 0x08)
+#define _IDP_CPLD_KB_COL_HIGH           (IDP_CPLD_PHYS + 0x0C)
+#define _IDP_CPLD_KB_COL_LOW            (IDP_CPLD_PHYS + 0x10)
+#define _IDP_CPLD_PCCARD_EN             (IDP_CPLD_PHYS + 0x14)
+#define _IDP_CPLD_GPIOH_DIR             (IDP_CPLD_PHYS + 0x18)
+#define _IDP_CPLD_GPIOH_VALUE           (IDP_CPLD_PHYS + 0x1C)
+#define _IDP_CPLD_GPIOL_DIR             (IDP_CPLD_PHYS + 0x20)
+#define _IDP_CPLD_GPIOL_VALUE           (IDP_CPLD_PHYS + 0x24)
+#define _IDP_CPLD_PCCARD_PWR            (IDP_CPLD_PHYS + 0x28)
+#define _IDP_CPLD_MISC_CTRL             (IDP_CPLD_PHYS + 0x2C)
+#define _IDP_CPLD_LCD                   (IDP_CPLD_PHYS + 0x30)
+#define _IDP_CPLD_FLASH_WE              (IDP_CPLD_PHYS + 0x34)
+
+#define _IDP_CPLD_KB_ROW                (IDP_CPLD_PHYS + 0x50)
+#define _IDP_CPLD_PCCARD0_STATUS        (IDP_CPLD_PHYS + 0x54)
+#define _IDP_CPLD_PCCARD1_STATUS        (IDP_CPLD_PHYS + 0x58)
+#define _IDP_CPLD_MISC_STATUS           (IDP_CPLD_PHYS + 0x5C)
+
+/* FPGA register virtual addresses */
+
+#define IDP_CPLD_REV                    __CPLD_REG(_IDP_CPLD_REV)
+#define IDP_CPLD_PERIPH_PWR             __CPLD_REG(_IDP_CPLD_PERIPH_PWR)
+#define IDP_CPLD_LED_CONTROL            __CPLD_REG(_IDP_CPLD_LED_CONTROL)
+#define IDP_CPLD_KB_COL_HIGH            __CPLD_REG(_IDP_CPLD_KB_COL_HIGH)
+#define IDP_CPLD_KB_COL_LOW             __CPLD_REG(_IDP_CPLD_KB_COL_LOW)
+#define IDP_CPLD_PCCARD_EN              __CPLD_REG(_IDP_CPLD_PCCARD_EN)
+#define IDP_CPLD_GPIOH_DIR              __CPLD_REG(_IDP_CPLD_GPIOH_DIR)
+#define IDP_CPLD_GPIOH_VALUE            __CPLD_REG(_IDP_CPLD_GPIOH_VALUE)
+#define IDP_CPLD_GPIOL_DIR              __CPLD_REG(_IDP_CPLD_GPIOL_DIR)
+#define IDP_CPLD_GPIOL_VALUE            __CPLD_REG(_IDP_CPLD_GPIOL_VALUE)
+#define IDP_CPLD_PCCARD_PWR             __CPLD_REG(_IDP_CPLD_PCCARD_PWR)
+#define IDP_CPLD_MISC_CTRL              __CPLD_REG(_IDP_CPLD_MISC_CTRL)
+#define IDP_CPLD_LCD                    __CPLD_REG(_IDP_CPLD_LCD)
+#define IDP_CPLD_FLASH_WE               __CPLD_REG(_IDP_CPLD_FLASH_WE)
+
+#define IDP_CPLD_KB_ROW                 __CPLD_REG(_IDP_CPLD_KB_ROW)
+#define IDP_CPLD_PCCARD0_STATUS         __CPLD_REG(_IDP_CPLD_PCCARD0_STATUS)
+#define IDP_CPLD_PCCARD1_STATUS         __CPLD_REG(_IDP_CPLD_PCCARD1_STATUS)
+#define IDP_CPLD_MISC_STATUS            __CPLD_REG(_IDP_CPLD_MISC_STATUS)
+
+
+/*
+ * Bit masks for various registers
+ */
+
+// IDP_CPLD_PCCARD_PWR
+#define PCC0_PWR0       (1 << 0)
+#define PCC0_PWR1       (1 << 1)
+#define PCC0_PWR2       (1 << 2)
+#define PCC0_PWR3       (1 << 3)
+#define PCC1_PWR0       (1 << 4)
+#define PCC1_PWR1       (1 << 5)
+#define PCC1_PWR2       (1 << 6)
+#define PCC1_PWR3       (1 << 7)
+
+// IDP_CPLD_PCCARD_EN
+#define PCC0_RESET      (1 << 6)
+#define PCC1_RESET      (1 << 7)
+#define PCC0_ENABLE     (1 << 0)
+#define PCC1_ENABLE     (1 << 1)
+
+// IDP_CPLD_PCCARDx_STATUS
+#define _PCC_WRPROT     (1 << 7) // 7-4 read as low true
+#define _PCC_RESET      (1 << 6)
+#define _PCC_IRQ        (1 << 5)
+#define _PCC_INPACK     (1 << 4)
+#define PCC_BVD2        (1 << 3)
+#define PCC_BVD1        (1 << 2)
+#define PCC_VS2         (1 << 1)
+#define PCC_VS1         (1 << 0)
+
+#define PCC_DETECT(x)   (GPLR(7 + (x)) & GPIO_bit(7 + (x)))
+
+/* A listing of interrupts used by external hardware devices */
+
+#define TOUCH_PANEL_IRQ                 IRQ_GPIO(5)
+#define IDE_IRQ                         IRQ_GPIO(21)
+
+#define TOUCH_PANEL_IRQ_EDGE            IRQT_FALLING
+
+#define ETHERNET_IRQ                    IRQ_GPIO(4)
+#define ETHERNET_IRQ_EDGE               IRQT_RISING
+
+#define IDE_IRQ_EDGE                    IRQT_RISING
+
+#define PCMCIA_S0_CD_VALID              IRQ_GPIO(7)
+#define PCMCIA_S0_CD_VALID_EDGE         IRQT_BOTHEDGE
+
+#define PCMCIA_S1_CD_VALID              IRQ_GPIO(8)
+#define PCMCIA_S1_CD_VALID_EDGE         IRQT_BOTHEDGE
+
+#define PCMCIA_S0_RDYINT                IRQ_GPIO(19)
+#define PCMCIA_S1_RDYINT                IRQ_GPIO(22)
+
+
+/*
+ * Macros for LED Driver
+ */
+
+/* leds 0 = ON */
+#define IDP_HB_LED      (1<<5)
+#define IDP_BUSY_LED    (1<<6)
+
+#define IDP_LEDS_MASK   (IDP_HB_LED | IDP_BUSY_LED)
+
+/*
+ * macros for MTD driver
+ */
+
+#define FLASH_WRITE_PROTECT_DISABLE()   ((IDP_CPLD_FLASH_WE) &= ~(0x1))
+#define FLASH_WRITE_PROTECT_ENABLE()    ((IDP_CPLD_FLASH_WE) |= (0x1))
+
+/*
+ * macros for matrix keyboard driver
+ */
+
+#define KEYBD_MATRIX_NUMBER_INPUTS      7
+#define KEYBD_MATRIX_NUMBER_OUTPUTS     14
+
+#define KEYBD_MATRIX_INVERT_OUTPUT_LOGIC        FALSE
+#define KEYBD_MATRIX_INVERT_INPUT_LOGIC         FALSE
+
+#define KEYBD_MATRIX_SETTLING_TIME_US                   100
+#define KEYBD_MATRIX_KEYSTATE_DEBOUNCE_CONSTANT         2
+
+#define KEYBD_MATRIX_SET_OUTPUTS(outputs) \
+{\
+        IDP_CPLD_KB_COL_LOW = outputs;\
+        IDP_CPLD_KB_COL_HIGH = outputs >> 7;\
+}
+
+#define KEYBD_MATRIX_GET_INPUTS(inputs) \
+{\
+        inputs = (IDP_CPLD_KB_ROW & 0x7f);\
+}
+
+
diff --git a/include/asm-arm/arch-pxa/io.h b/include/asm-arm/arch-pxa/io.h
new file mode 100644
index 000000000000..c3bdbe44e21f
--- /dev/null
+++ b/include/asm-arm/arch-pxa/io.h
@@ -0,0 +1,19 @@
+/*
+ * linux/include/asm-arm/arch-pxa/io.h
+ *
+ * Copied from asm/arch/sa1100/io.h
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+#endif
diff --git a/include/asm-arm/arch-pxa/irq.h b/include/asm-arm/arch-pxa/irq.h
new file mode 100644
index 000000000000..d770e4b37ae1
--- /dev/null
+++ b/include/asm-arm/arch-pxa/irq.h
@@ -0,0 +1,19 @@
+/*
+ * linux/include/asm-arm/arch-pxa/irq.h
+ *
+ * Author:      Nicolas Pitre
+ * Created:     Jun 15, 2001
+ * Copyright:   MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define fixup_irq(x)    (x)
+
+/*
+ * This prototype is required for cascading of multiplexed interrupts.
+ * Since it doesn't exist elsewhere, we'll put it here for now.
+ */
+extern void do_IRQ(int irq, struct pt_regs *regs);
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
new file mode 100644
index 000000000000..05c4b7027592
--- /dev/null
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -0,0 +1,219 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/irqs.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+
+#ifdef CONFIG_PXA27x
+#define PXA_IRQ_SKIP    0
+#else
+#define PXA_IRQ_SKIP    7
+#endif
+
+#define PXA_IRQ(x)      ((x) - PXA_IRQ_SKIP)
+
+#define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
+#define IRQ_MSL         PXA_IRQ(1)      /* MSL Interface interrupt */
+#define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI) */
+#define IRQ_USBH1       PXA_IRQ(3)      /* USB Host interrupt 2 (non-OHCI) */
+#define IRQ_KEYPAD      PXA_IRQ(4)      /* Key pad controller */
+#define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt */
+#define IRQ_PWRI2C      PXA_IRQ(6)      /* Power I2C interrupt */
+#define IRQ_HWUART      PXA_IRQ(7)      /* HWUART Transmit/Receive/Error (PXA26x) */
+#define IRQ_OST_4_11    PXA_IRQ(7)      /* OS timer 4-11 matches (PXA27x) */
+#define IRQ_GPIO0       PXA_IRQ(8)      /* GPIO0 Edge Detect */
+#define IRQ_GPIO1       PXA_IRQ(9)      /* GPIO1 Edge Detect */
+#define IRQ_GPIO_2_x    PXA_IRQ(10)     /* GPIO[2-x] Edge Detect */
+#define IRQ_USB         PXA_IRQ(11)     /* USB Service */
+#define IRQ_PMU         PXA_IRQ(12)     /* Performance Monitoring Unit */
+#define IRQ_I2S         PXA_IRQ(13)     /* I2S Interrupt */
+#define IRQ_AC97        PXA_IRQ(14)     /* AC97 Interrupt */
+#define IRQ_ASSP        PXA_IRQ(15)     /* Audio SSP Service Request (PXA25x) */
+#define IRQ_USIM        PXA_IRQ(15)     /* Smart Card interface interrupt (PXA27x) */
+#define IRQ_NSSP        PXA_IRQ(16)     /* Network SSP Service Request (PXA25x) */
+#define IRQ_SSP2        PXA_IRQ(16)     /* SSP2 interrupt (PXA27x) */
+#define IRQ_LCD         PXA_IRQ(17)     /* LCD Controller Service Request */
+#define IRQ_I2C         PXA_IRQ(18)     /* I2C Service Request */
+#define IRQ_ICP         PXA_IRQ(19)     /* ICP Transmit/Receive/Error */
+#define IRQ_STUART      PXA_IRQ(20)     /* STUART Transmit/Receive/Error */
+#define IRQ_BTUART      PXA_IRQ(21)     /* BTUART Transmit/Receive/Error */
+#define IRQ_FFUART      PXA_IRQ(22)     /* FFUART Transmit/Receive/Error*/
+#define IRQ_MMC         PXA_IRQ(23)     /* MMC Status/Error Detection */
+#define IRQ_SSP         PXA_IRQ(24)     /* SSP Service Request */
+#define IRQ_DMA         PXA_IRQ(25)     /* DMA Channel Service Request */
+#define IRQ_OST0        PXA_IRQ(26)     /* OS Timer match 0 */
+#define IRQ_OST1        PXA_IRQ(27)     /* OS Timer match 1 */
+#define IRQ_OST2        PXA_IRQ(28)     /* OS Timer match 2 */
+#define IRQ_OST3        PXA_IRQ(29)     /* OS Timer match 3 */
+#define IRQ_RTC1Hz      PXA_IRQ(30)     /* RTC HZ Clock Tick */
+#define IRQ_RTCAlrm     PXA_IRQ(31)     /* RTC Alarm */
+
+#ifdef CONFIG_PXA27x
+#define IRQ_TPM         PXA_IRQ(32)     /* TPM interrupt */
+#define IRQ_CAMERA      PXA_IRQ(33)     /* Camera Interface */
+
+#define PXA_INTERNAL_IRQS 34
+#else
+#define PXA_INTERNAL_IRQS 32
+#endif
+
+#define GPIO_2_x_TO_IRQ(x)      \
+                        PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS)
+#define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
+
+#define IRQ_TO_GPIO_2_x(i)      \
+                        ((i) - IRQ_GPIO(2) + 2)
+#define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
+
+#if defined(CONFIG_PXA25x)
+#define PXA_LAST_GPIO   80
+#elif defined(CONFIG_PXA27x)
+#define PXA_LAST_GPIO   127
+#endif
+
+/*
+ * The next 16 interrupts are for board specific purposes.  Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these.  If you need more, increase IRQ_BOARD_END, but keep it
+ * within sensible limits.
+ */
+#define IRQ_BOARD_START         (IRQ_GPIO(PXA_LAST_GPIO) + 1)
+#define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
+
+#define IRQ_SA1111_START        (IRQ_BOARD_END)
+#define IRQ_GPAIN0              (IRQ_BOARD_END + 0)
+#define IRQ_GPAIN1              (IRQ_BOARD_END + 1)
+#define IRQ_GPAIN2              (IRQ_BOARD_END + 2)
+#define IRQ_GPAIN3              (IRQ_BOARD_END + 3)
+#define IRQ_GPBIN0              (IRQ_BOARD_END + 4)
+#define IRQ_GPBIN1              (IRQ_BOARD_END + 5)
+#define IRQ_GPBIN2              (IRQ_BOARD_END + 6)
+#define IRQ_GPBIN3              (IRQ_BOARD_END + 7)
+#define IRQ_GPBIN4              (IRQ_BOARD_END + 8)
+#define IRQ_GPBIN5              (IRQ_BOARD_END + 9)
+#define IRQ_GPCIN0              (IRQ_BOARD_END + 10)
+#define IRQ_GPCIN1              (IRQ_BOARD_END + 11)
+#define IRQ_GPCIN2              (IRQ_BOARD_END + 12)
+#define IRQ_GPCIN3              (IRQ_BOARD_END + 13)
+#define IRQ_GPCIN4              (IRQ_BOARD_END + 14)
+#define IRQ_GPCIN5              (IRQ_BOARD_END + 15)
+#define IRQ_GPCIN6              (IRQ_BOARD_END + 16)
+#define IRQ_GPCIN7              (IRQ_BOARD_END + 17)
+#define IRQ_MSTXINT             (IRQ_BOARD_END + 18)
+#define IRQ_MSRXINT             (IRQ_BOARD_END + 19)
+#define IRQ_MSSTOPERRINT        (IRQ_BOARD_END + 20)
+#define IRQ_TPTXINT             (IRQ_BOARD_END + 21)
+#define IRQ_TPRXINT             (IRQ_BOARD_END + 22)
+#define IRQ_TPSTOPERRINT        (IRQ_BOARD_END + 23)
+#define SSPXMTINT               (IRQ_BOARD_END + 24)
+#define SSPRCVINT               (IRQ_BOARD_END + 25)
+#define SSPROR                  (IRQ_BOARD_END + 26)
+#define AUDXMTDMADONEA          (IRQ_BOARD_END + 32)
+#define AUDRCVDMADONEA          (IRQ_BOARD_END + 33)
+#define AUDXMTDMADONEB          (IRQ_BOARD_END + 34)
+#define AUDRCVDMADONEB          (IRQ_BOARD_END + 35)
+#define AUDTFSR                 (IRQ_BOARD_END + 36)
+#define AUDRFSR                 (IRQ_BOARD_END + 37)
+#define AUDTUR                  (IRQ_BOARD_END + 38)
+#define AUDROR                  (IRQ_BOARD_END + 39)
+#define AUDDTS                  (IRQ_BOARD_END + 40)
+#define AUDRDD                  (IRQ_BOARD_END + 41)
+#define AUDSTO                  (IRQ_BOARD_END + 42)
+#define IRQ_USBPWR              (IRQ_BOARD_END + 43)
+#define IRQ_HCIM                (IRQ_BOARD_END + 44)
+#define IRQ_HCIBUFFACC          (IRQ_BOARD_END + 45)
+#define IRQ_HCIRMTWKP           (IRQ_BOARD_END + 46)
+#define IRQ_NHCIMFCIR           (IRQ_BOARD_END + 47)
+#define IRQ_USB_PORT_RESUME     (IRQ_BOARD_END + 48)
+#define IRQ_S0_READY_NINT       (IRQ_BOARD_END + 49)
+#define IRQ_S1_READY_NINT       (IRQ_BOARD_END + 50)
+#define IRQ_S0_CD_VALID         (IRQ_BOARD_END + 51)
+#define IRQ_S1_CD_VALID         (IRQ_BOARD_END + 52)
+#define IRQ_S0_BVD1_STSCHG      (IRQ_BOARD_END + 53)
+#define IRQ_S1_BVD1_STSCHG      (IRQ_BOARD_END + 54)
+
+#define IRQ_LOCOMO_START        (IRQ_BOARD_END)
+#define IRQ_LOCOMO_KEY          (IRQ_BOARD_END + 0)
+#define IRQ_LOCOMO_GPIO0        (IRQ_BOARD_END + 1)
+#define IRQ_LOCOMO_GPIO1        (IRQ_BOARD_END + 2)
+#define IRQ_LOCOMO_GPIO2        (IRQ_BOARD_END + 3)
+#define IRQ_LOCOMO_GPIO3        (IRQ_BOARD_END + 4)
+#define IRQ_LOCOMO_GPIO4        (IRQ_BOARD_END + 5)
+#define IRQ_LOCOMO_GPIO5        (IRQ_BOARD_END + 6)
+#define IRQ_LOCOMO_GPIO6        (IRQ_BOARD_END + 7)
+#define IRQ_LOCOMO_GPIO7        (IRQ_BOARD_END + 8)
+#define IRQ_LOCOMO_GPIO8        (IRQ_BOARD_END + 9)
+#define IRQ_LOCOMO_GPIO9        (IRQ_BOARD_END + 10)
+#define IRQ_LOCOMO_GPIO10       (IRQ_BOARD_END + 11)
+#define IRQ_LOCOMO_GPIO11       (IRQ_BOARD_END + 12)
+#define IRQ_LOCOMO_GPIO12       (IRQ_BOARD_END + 13)
+#define IRQ_LOCOMO_GPIO13       (IRQ_BOARD_END + 14)
+#define IRQ_LOCOMO_GPIO14       (IRQ_BOARD_END + 15)
+#define IRQ_LOCOMO_GPIO15       (IRQ_BOARD_END + 16)
+#define IRQ_LOCOMO_LT           (IRQ_BOARD_END + 17)
+#define IRQ_LOCOMO_SPI_RFR      (IRQ_BOARD_END + 18)
+#define IRQ_LOCOMO_SPI_RFW      (IRQ_BOARD_END + 19)
+#define IRQ_LOCOMO_SPI_OVRN     (IRQ_BOARD_END + 20)
+#define IRQ_LOCOMO_SPI_TEND     (IRQ_BOARD_END + 21)
+
+/*
+ * Figure out the MAX IRQ number.
+ *
+ * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
+ * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
+ * Otherwise, we have the standard IRQs only.
+ */
+#ifdef CONFIG_SA1111
+#define NR_IRQS                 (IRQ_S1_BVD1_STSCHG + 1)
+#elif defined(CONFIG_SHARP_LOCOMO)
+#define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
+#elif defined(CONFIG_ARCH_LUBBOCK) || \
+      defined(CONFIG_MACH_MAINSTONE)
+#define NR_IRQS                 (IRQ_BOARD_END)
+#else
+#define NR_IRQS                 (IRQ_BOARD_START)
+#endif
+
+/*
+ * Board specific IRQs.  Define them here.
+ * Do not surround them with ifdefs.
+ */
+#define LUBBOCK_IRQ(x)          (IRQ_BOARD_START + (x))
+#define LUBBOCK_SD_IRQ          LUBBOCK_IRQ(0)
+#define LUBBOCK_SA1111_IRQ      LUBBOCK_IRQ(1)
+#define LUBBOCK_USB_IRQ         LUBBOCK_IRQ(2)  /* usb connect */
+#define LUBBOCK_ETH_IRQ         LUBBOCK_IRQ(3)
+#define LUBBOCK_UCB1400_IRQ     LUBBOCK_IRQ(4)
+#define LUBBOCK_BB_IRQ          LUBBOCK_IRQ(5)
+#define LUBBOCK_USB_DISC_IRQ    LUBBOCK_IRQ(6)  /* usb disconnect */
+#define LUBBOCK_LAST_IRQ        LUBBOCK_IRQ(6)
+
+#define MAINSTONE_IRQ(x)        (IRQ_BOARD_START + (x))
+#define MAINSTONE_MMC_IRQ       MAINSTONE_IRQ(0)
+#define MAINSTONE_USIM_IRQ      MAINSTONE_IRQ(1)
+#define MAINSTONE_USBC_IRQ      MAINSTONE_IRQ(2)
+#define MAINSTONE_ETHERNET_IRQ  MAINSTONE_IRQ(3)
+#define MAINSTONE_AC97_IRQ      MAINSTONE_IRQ(4)
+#define MAINSTONE_PEN_IRQ       MAINSTONE_IRQ(5)
+#define MAINSTONE_MSINS_IRQ     MAINSTONE_IRQ(6)
+#define MAINSTONE_EXBRD_IRQ     MAINSTONE_IRQ(7)
+#define MAINSTONE_S0_CD_IRQ     MAINSTONE_IRQ(9)
+#define MAINSTONE_S0_STSCHG_IRQ MAINSTONE_IRQ(10)
+#define MAINSTONE_S0_IRQ        MAINSTONE_IRQ(11)
+#define MAINSTONE_S1_CD_IRQ     MAINSTONE_IRQ(13)
+#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
+#define MAINSTONE_S1_IRQ        MAINSTONE_IRQ(15)
+
+/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
+#define IRQ_LOCOMO_KEY_BASE     (IRQ_BOARD_START + 0)
+#define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
+#define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
+#define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
diff --git a/include/asm-arm/arch-pxa/lubbock.h b/include/asm-arm/arch-pxa/lubbock.h
new file mode 100644
index 000000000000..11ee73593fc3
--- /dev/null
+++ b/include/asm-arm/arch-pxa/lubbock.h
@@ -0,0 +1,40 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/lubbock.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define LUBBOCK_ETH_PHYS        PXA_CS3_PHYS
+
+#define LUBBOCK_FPGA_PHYS       PXA_CS2_PHYS
+#define LUBBOCK_FPGA_VIRT       (0xf0000000)
+#define LUB_P2V(x)              ((x) - LUBBOCK_FPGA_PHYS + LUBBOCK_FPGA_VIRT)
+#define LUB_V2P(x)              ((x) - LUBBOCK_FPGA_VIRT + LUBBOCK_FPGA_PHYS)
+
+#ifndef __ASSEMBLY__
+#  define __LUB_REG(x)          (*((volatile unsigned long *)LUB_P2V(x)))
+#else
+#  define __LUB_REG(x)          LUB_P2V(x)
+#endif
+
+/* FPGA register virtual addresses */
+#define LUB_WHOAMI              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x000)
+#define LUB_HEXLED              __LUB_REG(LUBBOCK_FPGA_PHYS + 0x010)
+#define LUB_DISC_BLNK_LED       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x040)
+#define LUB_CONF_SWITCHES       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x050)
+#define LUB_USER_SWITCHES       __LUB_REG(LUBBOCK_FPGA_PHYS + 0x060)
+#define LUB_MISC_WR             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x080)
+#define LUB_MISC_RD             __LUB_REG(LUBBOCK_FPGA_PHYS + 0x090)
+#define LUB_IRQ_MASK_EN         __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0c0)
+#define LUB_IRQ_SET_CLR         __LUB_REG(LUBBOCK_FPGA_PHYS + 0x0d0)
+#define LUB_GP                  __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
+
+#ifndef __ASSEMBLY__
+extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
+#endif
diff --git a/include/asm-arm/arch-pxa/mainstone.h b/include/asm-arm/arch-pxa/mainstone.h
new file mode 100644
index 000000000000..14c862adcaa1
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mainstone.h
@@ -0,0 +1,120 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/mainstone.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Nov 14, 2002
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef ASM_ARCH_MAINSTONE_H
+#define ASM_ARCH_MAINSTONE_H
+
+#define MST_ETH_PHYS            PXA_CS4_PHYS
+
+#define MST_FPGA_PHYS           PXA_CS2_PHYS
+#define MST_FPGA_VIRT           (0xf0000000)
+#define MST_P2V(x)              ((x) - MST_FPGA_PHYS + MST_FPGA_VIRT)
+#define MST_V2P(x)              ((x) - MST_FPGA_VIRT + MST_FPGA_PHYS)
+
+#ifndef __ASSEMBLY__
+# define __MST_REG(x)           (*((volatile unsigned long *)MST_P2V(x)))
+#else
+# define __MST_REG(x)           MST_P2V(x)
+#endif
+
+/* board level registers in the FPGA */
+
+#define MST_LEDDAT1             __MST_REG(0x08000010)
+#define MST_LEDDAT2             __MST_REG(0x08000014)
+#define MST_LEDCTRL             __MST_REG(0x08000040)
+#define MST_GPSWR               __MST_REG(0x08000060)
+#define MST_MSCWR1              __MST_REG(0x08000080)
+#define MST_MSCWR2              __MST_REG(0x08000084)
+#define MST_MSCWR3              __MST_REG(0x08000088)
+#define MST_MSCRD               __MST_REG(0x08000090)
+#define MST_INTMSKENA           __MST_REG(0x080000c0)
+#define MST_INTSETCLR           __MST_REG(0x080000d0)
+#define MST_PCMCIA0             __MST_REG(0x080000e0)
+#define MST_PCMCIA1             __MST_REG(0x080000e4)
+
+#define MST_MSCWR1_CAMERA_ON    (1 << 15)  /* Camera interface power control */
+#define MST_MSCWR1_CAMERA_SEL   (1 << 14)  /* Camera interface mux control */
+#define MST_MSCWR1_LCD_CTL      (1 << 13)  /* General-purpose LCD control */
+#define MST_MSCWR1_MS_ON        (1 << 12)  /* Memory Stick power control */
+#define MST_MSCWR1_MMC_ON       (1 << 11)  /* MultiMediaCard* power control */
+#define MST_MSCWR1_MS_SEL       (1 << 10)  /* SD/MS multiplexer control */
+#define MST_MSCWR1_BB_SEL       (1 << 9)   /* PCMCIA/Baseband multiplexer */
+#define MST_MSCWR1_BT_ON        (1 << 8)   /* Bluetooth UART transceiver */
+#define MST_MSCWR1_BTDTR        (1 << 7)   /* Bluetooth UART DTR */
+
+#define MST_MSCWR1_IRDA_MASK    (3 << 5)   /* IrDA transceiver mode */
+#define MST_MSCWR1_IRDA_FULL    (0 << 5)   /* full distance power */
+#define MST_MSCWR1_IRDA_OFF     (1 << 5)   /* shutdown */
+#define MST_MSCWR1_IRDA_MED     (2 << 5)   /* 2/3 distance power */
+#define MST_MSCWR1_IRDA_LOW     (3 << 5)   /* 1/3 distance power */
+
+#define MST_MSCWR1_IRDA_FIR     (1 << 4)   /* IrDA transceiver SIR/FIR */
+#define MST_MSCWR1_GREENLED     (1 << 3)   /* LED D1 control */
+#define MST_MSCWR1_PDC_CTL      (1 << 2)   /* reserved */
+#define MST_MSCWR1_MTR_ON       (1 << 1)   /* Silent alert motor */
+#define MST_MSCWR1_SYSRESET     (1 << 0)   /* System reset */
+
+#define MST_MSCWR2_USB_OTG_RST  (1 << 6)   /* USB On The Go reset */
+#define MST_MSCWR2_USB_OTG_SEL  (1 << 5)   /* USB On The Go control */
+#define MST_MSCWR2_nUSBC_SC     (1 << 4)   /* USB client soft connect control */
+#define MST_MSCWR2_I2S_SPKROFF  (1 << 3)   /* I2S CODEC amplifier control */
+#define MST_MSCWR2_AC97_SPKROFF (1 << 2)   /* AC97 CODEC amplifier control */
+#define MST_MSCWR2_RADIO_PWR    (1 << 1)   /* Radio module power control */
+#define MST_MSCWR2_RADIO_WAKE   (1 << 0)   /* Radio module wake-up signal */
+
+#define MST_MSCWR3_GPIO_RESET_EN        (1 << 2) /* Enable GPIO Reset */
+#define MST_MSCWR3_GPIO_RESET           (1 << 1) /* Initiate a GPIO Reset */
+#define MST_MSCWR3_COMMS_SW_RESET       (1 << 0) /* Communications Processor Reset Control */
+
+#define MST_MSCRD_nPENIRQ       (1 << 9)   /* ADI7873* nPENIRQ signal */
+#define MST_MSCRD_nMEMSTK_CD    (1 << 8)   /* Memory Stick detection signal */
+#define MST_MSCRD_nMMC_CD       (1 << 7)   /* SD/MMC card detection signal */
+#define MST_MSCRD_nUSIM_CD      (1 << 6)   /* USIM card detection signal */
+#define MST_MSCRD_USB_CBL       (1 << 5)   /* USB client cable status */
+#define MST_MSCRD_TS_BUSY       (1 << 4)   /* ADI7873 busy */
+#define MST_MSCRD_BTDSR         (1 << 3)   /* Bluetooth UART DSR */
+#define MST_MSCRD_BTRI          (1 << 2)   /* Bluetooth UART Ring Indicator */
+#define MST_MSCRD_BTDCD         (1 << 1)   /* Bluetooth UART DCD */
+#define MST_MSCRD_nMMC_WP       (1 << 0)   /* SD/MMC write-protect status */
+
+#define MST_INT_S1_IRQ          (1 << 15)  /* PCMCIA socket 1 IRQ */
+#define MST_INT_S1_STSCHG       (1 << 14)  /* PCMCIA socket 1 status changed */
+#define MST_INT_S1_CD           (1 << 13)  /* PCMCIA socket 1 card detection */
+#define MST_INT_S0_IRQ          (1 << 11)  /* PCMCIA socket 0 IRQ */
+#define MST_INT_S0_STSCHG       (1 << 10)  /* PCMCIA socket 0 status changed */
+#define MST_INT_S0_CD           (1 << 9)   /* PCMCIA socket 0 card detection */
+#define MST_INT_nEXBRD_INT      (1 << 7)   /* Expansion board IRQ */
+#define MST_INT_MSINS           (1 << 6)   /* Memory Stick* detection */
+#define MST_INT_PENIRQ          (1 << 5)   /* ADI7873* touch-screen IRQ */
+#define MST_INT_AC97            (1 << 4)   /* AC'97 CODEC IRQ */
+#define MST_INT_ETHERNET        (1 << 3)   /* Ethernet controller IRQ */
+#define MST_INT_USBC            (1 << 2)   /* USB client cable detection IRQ */
+#define MST_INT_USIM            (1 << 1)   /* USIM card detection IRQ */
+#define MST_INT_MMC             (1 << 0)   /* MMC/SD card detection IRQ */
+
+#define MST_PCMCIA_nIRQ         (1 << 10)  /* IRQ / ready signal */
+#define MST_PCMCIA_nSPKR_BVD2   (1 << 9)   /* VDD sense / digital speaker */
+#define MST_PCMCIA_nSTSCHG_BVD1 (1 << 8)   /* VDD sense / card status changed */
+#define MST_PCMCIA_nVS2         (1 << 7)   /* VSS voltage sense */
+#define MST_PCMCIA_nVS1         (1 << 6)   /* VSS voltage sense */
+#define MST_PCMCIA_nCD          (1 << 5)   /* Card detection signal */
+#define MST_PCMCIA_RESET        (1 << 4)   /* Card reset signal */
+#define MST_PCMCIA_PWR_MASK     (0x000f)   /* MAX1602 power-supply controls */
+
+#define MST_PCMCIA_PWR_VPP_0    0x0        /* voltage VPP = 0V */
+#define MST_PCMCIA_PWR_VPP_120  0x2        /* voltage VPP = 12V*/
+#define MST_PCMCIA_PWR_VPP_VCC  0x1        /* voltage VPP = VCC */
+#define MST_PCMCIA_PWR_VCC_0    0x0        /* voltage VCC = 0V */
+#define MST_PCMCIA_PWR_VCC_33   0x8        /* voltage VCC = 3.3V */
+#define MST_PCMCIA_PWR_VCC_50   0x4        /* voltage VCC = 5.0V */
+
+#endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
new file mode 100644
index 000000000000..217a80b820ff
--- /dev/null
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -0,0 +1,76 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/memory.h
+ *
+ * Author:      Nicolas Pitre
+ * Copyright:   (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0xa0000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * The nodes are matched with the physical SDRAM banks as follows:
+ *
+ *      node 0:  0xa0000000-0xa3ffffff  -->  0xc0000000-0xc3ffffff
+ *      node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
+ *      node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
+ *      node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
+ */
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and returns the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+        (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
+
+#else
+
+#define PFN_TO_NID(addr)        (0)
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h
new file mode 100644
index 000000000000..7492ea7ea614
--- /dev/null
+++ b/include/asm-arm/arch-pxa/mmc.h
@@ -0,0 +1,19 @@
+#ifndef ASMARM_ARCH_MMC_H
+#define ASMARM_ARCH_MMC_H
+
+#include <linux/mmc/protocol.h>
+#include <linux/interrupt.h>
+
+struct device;
+struct mmc_host;
+
+struct pxamci_platform_data {
+        unsigned int ocr_mask;                  /* available voltages */
+        int (*init)(struct device *, irqreturn_t (*)(int, void *, struct pt_regs *), void *);
+        void (*setpower)(struct device *, unsigned int);
+        void (*exit)(struct device *, void *);
+};
+
+extern void pxa_set_mci_info(struct pxamci_platform_data *info);
+
+#endif
diff --git a/include/asm-arm/arch-pxa/param.h b/include/asm-arm/arch-pxa/param.h
new file mode 100644
index 000000000000..3197d82d7573
--- /dev/null
+++ b/include/asm-arm/arch-pxa/param.h
@@ -0,0 +1,3 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/param.h
+ */
diff --git a/include/asm-arm/arch-pxa/poodle.h b/include/asm-arm/arch-pxa/poodle.h
new file mode 100644
index 000000000000..58bda9d571a5
--- /dev/null
+++ b/include/asm-arm/arch-pxa/poodle.h
@@ -0,0 +1,70 @@
+/*
+ * linux/include/asm-arm/arch-pxa/poodle.h
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on:
+ *   linux/include/asm-arm/arch-sa1100/collie.h
+ *
+ * ChangeLog:
+ *   04-06-2001 Lineo Japan, Inc.
+ *   04-16-2001 SHARP Corporation
+ *   Update to 2.6 John Lenz
+ */
+#ifndef __ASM_ARCH_POODLE_H
+#define __ASM_ARCH_POODLE_H  1
+
+/*
+ * GPIOs
+ */
+/* PXA GPIOs */
+#define POODLE_GPIO_ON_KEY              (0)
+#define POODLE_GPIO_AC_IN               (1)
+#define POODLE_GPIO_CO                  16
+#define POODLE_GPIO_TP_INT              (5)
+#define POODLE_GPIO_WAKEUP              (11)    /* change battery */
+#define POODLE_GPIO_GA_INT              (10)
+#define POODLE_GPIO_IR_ON               (22)
+#define POODLE_GPIO_HP_IN               (4)
+#define POODLE_GPIO_CF_IRQ              (17)
+#define POODLE_GPIO_CF_CD               (14)
+#define POODLE_GPIO_CF_STSCHG           (14)
+#define POODLE_GPIO_SD_PWR              (33)
+#define POODLE_GPIO_nSD_CLK             (6)
+#define POODLE_GPIO_nSD_WP              (7)
+#define POODLE_GPIO_nSD_INT             (8)
+#define POODLE_GPIO_nSD_DETECT          (9)
+#define POODLE_GPIO_MAIN_BAT_LOW        (13)
+#define POODLE_GPIO_BAT_COVER           (13)
+#define POODLE_GPIO_ADC_TEMP_ON         (21)
+#define POODLE_GPIO_BYPASS_ON           (36)
+#define POODLE_GPIO_CHRG_ON             (38)
+#define POODLE_GPIO_CHRG_FULL           (16)
+
+/* PXA GPIOs */
+#define POODLE_IRQ_GPIO_ON_KEY          IRQ_GPIO0
+#define POODLE_IRQ_GPIO_AC_IN           IRQ_GPIO1
+#define POODLE_IRQ_GPIO_HP_IN           IRQ_GPIO4
+#define POODLE_IRQ_GPIO_CO              IRQ_GPIO16
+#define POODLE_IRQ_GPIO_TP_INT          IRQ_GPIO5
+#define POODLE_IRQ_GPIO_WAKEUP          IRQ_GPIO11
+#define POODLE_IRQ_GPIO_GA_INT          IRQ_GPIO10
+#define POODLE_IRQ_GPIO_CF_IRQ          IRQ_GPIO17
+#define POODLE_IRQ_GPIO_CF_CD           IRQ_GPIO14
+#define POODLE_IRQ_GPIO_nSD_INT         IRQ_GPIO8
+#define POODLE_IRQ_GPIO_nSD_DETECT      IRQ_GPIO9
+#define POODLE_IRQ_GPIO_MAIN_BAT_LOW    IRQ_GPIO13
+
+/* SCOOP GPIOs */
+#define POODLE_SCOOP_CHARGE_ON  SCOOP_GPCR_PA11
+#define POODLE_SCOOP_CP401      SCOOP_GPCR_PA13
+#define POODLE_SCOOP_VPEN       SCOOP_GPCR_PA18
+#define POODLE_SCOOP_L_PCLK     SCOOP_GPCR_PA20
+#define POODLE_SCOOP_L_LCLK     SCOOP_GPCR_PA21
+#define POODLE_SCOOP_HS_OUT     SCOOP_GPCR_PA22
+
+#define POODLE_SCOOP_IO_DIR     ( POODLE_SCOOP_VPEN | POODLE_SCOOP_HS_OUT )
+#define POODLE_SCOOP_IO_OUT     ( 0 )
+
+#endif /* __ASM_ARCH_POODLE_H  */
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
new file mode 100644
index 000000000000..39741d3c9a34
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -0,0 +1,2251 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/pxa-regs.h
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    Jun 15, 2001
+ *  Copyright:  MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __PXA_REGS_H
+#define __PXA_REGS_H
+
+#include <linux/config.h>
+
+/*
+ * PXA Chip selects
+ */
+
+#define PXA_CS0_PHYS    0x00000000
+#define PXA_CS1_PHYS    0x04000000
+#define PXA_CS2_PHYS    0x08000000
+#define PXA_CS3_PHYS    0x0C000000
+#define PXA_CS4_PHYS    0x10000000
+#define PXA_CS5_PHYS    0x14000000
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+
+#define PCMCIAPrtSp     0x04000000      /* PCMCIA Partition Space [byte]   */
+#define PCMCIASp        (4*PCMCIAPrtSp) /* PCMCIA Space [byte]             */
+#define PCMCIAIOSp      PCMCIAPrtSp     /* PCMCIA I/O Space [byte]         */
+#define PCMCIAAttrSp    PCMCIAPrtSp     /* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp     PCMCIAPrtSp     /* PCMCIA Memory Space [byte]      */
+
+#define PCMCIA0Sp       PCMCIASp        /* PCMCIA 0 Space [byte]           */
+#define PCMCIA0IOSp     PCMCIAIOSp      /* PCMCIA 0 I/O Space [byte]       */
+#define PCMCIA0AttrSp   PCMCIAAttrSp    /* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp    PCMCIAMemSp     /* PCMCIA 0 Memory Space [byte]    */
+
+#define PCMCIA1Sp       PCMCIASp        /* PCMCIA 1 Space [byte]           */
+#define PCMCIA1IOSp     PCMCIAIOSp      /* PCMCIA 1 I/O Space [byte]       */
+#define PCMCIA1AttrSp   PCMCIAAttrSp    /* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp    PCMCIAMemSp     /* PCMCIA 1 Memory Space [byte]    */
+
+#define _PCMCIA(Nb)                     /* PCMCIA [0..1]                   */ \
+                        (0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)   _PCMCIA (Nb)    /* PCMCIA I/O [0..1]               */
+#define _PCMCIAAttr(Nb)                 /* PCMCIA Attribute [0..1]         */ \
+                        (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)                  /* PCMCIA Memory [0..1]            */ \
+                        (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0        _PCMCIA (0)     /* PCMCIA 0                        */
+#define _PCMCIA0IO      _PCMCIAIO (0)   /* PCMCIA 0 I/O                    */
+#define _PCMCIA0Attr    _PCMCIAAttr (0) /* PCMCIA 0 Attribute              */
+#define _PCMCIA0Mem     _PCMCIAMem (0)  /* PCMCIA 0 Memory                 */
+
+#define _PCMCIA1        _PCMCIA (1)     /* PCMCIA 1                        */
+#define _PCMCIA1IO      _PCMCIAIO (1)   /* PCMCIA 1 I/O                    */
+#define _PCMCIA1Attr    _PCMCIAAttr (1) /* PCMCIA 1 Attribute              */
+#define _PCMCIA1Mem     _PCMCIAMem (1)  /* PCMCIA 1 Memory                 */
+
+
+
+/*
+ * DMA Controller
+ */
+
+#define DCSR0           __REG(0x40000000)  /* DMA Control / Status Register for Channel 0 */
+#define DCSR1           __REG(0x40000004)  /* DMA Control / Status Register for Channel 1 */
+#define DCSR2           __REG(0x40000008)  /* DMA Control / Status Register for Channel 2 */
+#define DCSR3           __REG(0x4000000c)  /* DMA Control / Status Register for Channel 3 */
+#define DCSR4           __REG(0x40000010)  /* DMA Control / Status Register for Channel 4 */
+#define DCSR5           __REG(0x40000014)  /* DMA Control / Status Register for Channel 5 */
+#define DCSR6           __REG(0x40000018)  /* DMA Control / Status Register for Channel 6 */
+#define DCSR7           __REG(0x4000001c)  /* DMA Control / Status Register for Channel 7 */
+#define DCSR8           __REG(0x40000020)  /* DMA Control / Status Register for Channel 8 */
+#define DCSR9           __REG(0x40000024)  /* DMA Control / Status Register for Channel 9 */
+#define DCSR10          __REG(0x40000028)  /* DMA Control / Status Register for Channel 10 */
+#define DCSR11          __REG(0x4000002c)  /* DMA Control / Status Register for Channel 11 */
+#define DCSR12          __REG(0x40000030)  /* DMA Control / Status Register for Channel 12 */
+#define DCSR13          __REG(0x40000034)  /* DMA Control / Status Register for Channel 13 */
+#define DCSR14          __REG(0x40000038)  /* DMA Control / Status Register for Channel 14 */
+#define DCSR15          __REG(0x4000003c)  /* DMA Control / Status Register for Channel 15 */
+
+#define DCSR(x)         __REG2(0x40000000, (x) << 2)
+
+#define DCSR_RUN        (1 << 31)       /* Run Bit (read / write) */
+#define DCSR_NODESC     (1 << 30)       /* No-Descriptor Fetch (read / write) */
+#define DCSR_STOPIRQEN  (1 << 29)       /* Stop Interrupt Enable (read / write) */
+#ifdef CONFIG_PXA27x
+#define DCSR_EORIRQEN   (1 << 28)       /* End of Receive Interrupt Enable (R/W) */
+#define DCSR_EORJMPEN   (1 << 27)       /* Jump to next descriptor on EOR */
+#define DCSR_EORSTOPEN  (1 << 26)       /* STOP on an EOR */
+#define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
+#define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
+#define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
+#define DCSR_ENRINTR    (1 << 9)        /* The end of Receive */
+#endif
+#define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
+#define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
+#define DCSR_ENDINTR    (1 << 2)        /* End Interrupt (read / write) */
+#define DCSR_STARTINTR  (1 << 1)        /* Start Interrupt (read / write) */
+#define DCSR_BUSERR     (1 << 0)        /* Bus Error Interrupt (read / write) */
+
+#define DINT            __REG(0x400000f0)  /* DMA Interrupt Register */
+
+#define DRCMR(n)        __REG2(0x40000100, (n)<<2)
+#define DRCMR0          __REG(0x40000100)  /* Request to Channel Map Register for DREQ 0 */
+#define DRCMR1          __REG(0x40000104)  /* Request to Channel Map Register for DREQ 1 */
+#define DRCMR2          __REG(0x40000108)  /* Request to Channel Map Register for I2S receive Request */
+#define DRCMR3          __REG(0x4000010c)  /* Request to Channel Map Register for I2S transmit Request */
+#define DRCMR4          __REG(0x40000110)  /* Request to Channel Map Register for BTUART receive Request */
+#define DRCMR5          __REG(0x40000114)  /* Request to Channel Map Register for BTUART transmit Request. */
+#define DRCMR6          __REG(0x40000118)  /* Request to Channel Map Register for FFUART receive Request */
+#define DRCMR7          __REG(0x4000011c)  /* Request to Channel Map Register for FFUART transmit Request */
+#define DRCMR8          __REG(0x40000120)  /* Request to Channel Map Register for AC97 microphone Request */
+#define DRCMR9          __REG(0x40000124)  /* Request to Channel Map Register for AC97 modem receive Request */
+#define DRCMR10         __REG(0x40000128)  /* Request to Channel Map Register for AC97 modem transmit Request */
+#define DRCMR11         __REG(0x4000012c)  /* Request to Channel Map Register for AC97 audio receive Request */
+#define DRCMR12         __REG(0x40000130)  /* Request to Channel Map Register for AC97 audio transmit Request */
+#define DRCMR13         __REG(0x40000134)  /* Request to Channel Map Register for SSP receive Request */
+#define DRCMR14         __REG(0x40000138)  /* Request to Channel Map Register for SSP transmit Request */
+#define DRCMR15         __REG(0x4000013c)  /* Reserved */
+#define DRCMR16         __REG(0x40000140)  /* Reserved */
+#define DRCMR17         __REG(0x40000144)  /* Request to Channel Map Register for ICP receive Request */
+#define DRCMR18         __REG(0x40000148)  /* Request to Channel Map Register for ICP transmit Request */
+#define DRCMR19         __REG(0x4000014c)  /* Request to Channel Map Register for STUART receive Request */
+#define DRCMR20         __REG(0x40000150)  /* Request to Channel Map Register for STUART transmit Request */
+#define DRCMR21         __REG(0x40000154)  /* Request to Channel Map Register for MMC receive Request */
+#define DRCMR22         __REG(0x40000158)  /* Request to Channel Map Register for MMC transmit Request */
+#define DRCMR23         __REG(0x4000015c)  /* Reserved */
+#define DRCMR24         __REG(0x40000160)  /* Reserved */
+#define DRCMR25         __REG(0x40000164)  /* Request to Channel Map Register for USB endpoint 1 Request */
+#define DRCMR26         __REG(0x40000168)  /* Request to Channel Map Register for USB endpoint 2 Request */
+#define DRCMR27         __REG(0x4000016C)  /* Request to Channel Map Register for USB endpoint 3 Request */
+#define DRCMR28         __REG(0x40000170)  /* Request to Channel Map Register for USB endpoint 4 Request */
+#define DRCMR29         __REG(0x40000174)  /* Reserved */
+#define DRCMR30         __REG(0x40000178)  /* Request to Channel Map Register for USB endpoint 6 Request */
+#define DRCMR31         __REG(0x4000017C)  /* Request to Channel Map Register for USB endpoint 7 Request */
+#define DRCMR32         __REG(0x40000180)  /* Request to Channel Map Register for USB endpoint 8 Request */
+#define DRCMR33         __REG(0x40000184)  /* Request to Channel Map Register for USB endpoint 9 Request */
+#define DRCMR34         __REG(0x40000188)  /* Reserved */
+#define DRCMR35         __REG(0x4000018C)  /* Request to Channel Map Register for USB endpoint 11 Request */
+#define DRCMR36         __REG(0x40000190)  /* Request to Channel Map Register for USB endpoint 12 Request */
+#define DRCMR37         __REG(0x40000194)  /* Request to Channel Map Register for USB endpoint 13 Request */
+#define DRCMR38         __REG(0x40000198)  /* Request to Channel Map Register for USB endpoint 14 Request */
+#define DRCMR39         __REG(0x4000019C)  /* Reserved */
+
+#define DRCMR68         __REG(0x40001110)  /* Request to Channel Map Register for Camera FIFO 0 Request */
+#define DRCMR69         __REG(0x40001114)  /* Request to Channel Map Register for Camera FIFO 1 Request */
+#define DRCMR70         __REG(0x40001118)  /* Request to Channel Map Register for Camera FIFO 2 Request */
+
+#define DRCMRRXSADR     DRCMR2
+#define DRCMRTXSADR     DRCMR3
+#define DRCMRRXBTRBR    DRCMR4
+#define DRCMRTXBTTHR    DRCMR5
+#define DRCMRRXFFRBR    DRCMR6
+#define DRCMRTXFFTHR    DRCMR7
+#define DRCMRRXMCDR     DRCMR8
+#define DRCMRRXMODR     DRCMR9
+#define DRCMRTXMODR     DRCMR10
+#define DRCMRRXPCDR     DRCMR11
+#define DRCMRTXPCDR     DRCMR12
+#define DRCMRRXSSDR     DRCMR13
+#define DRCMRTXSSDR     DRCMR14
+#define DRCMRRXSS2DR   DRCMR15
+#define DRCMRTXSS2DR   DRCMR16
+#define DRCMRRXICDR     DRCMR17
+#define DRCMRTXICDR     DRCMR18
+#define DRCMRRXSTRBR    DRCMR19
+#define DRCMRTXSTTHR    DRCMR20
+#define DRCMRRXMMC      DRCMR21
+#define DRCMRTXMMC      DRCMR22
+#define DRCMRRXSS3DR   DRCMR66
+#define DRCMRTXSS3DR   DRCMR67
+#define DRCMRUDC(x)     DRCMR((x) + 24)
+
+#define DRCMR_MAPVLD    (1 << 7)        /* Map Valid (read / write) */
+#define DRCMR_CHLNUM    0x1f            /* mask for Channel Number (read / write) */
+
+#define DDADR0          __REG(0x40000200)  /* DMA Descriptor Address Register Channel 0 */
+#define DSADR0          __REG(0x40000204)  /* DMA Source Address Register Channel 0 */
+#define DTADR0          __REG(0x40000208)  /* DMA Target Address Register Channel 0 */
+#define DCMD0           __REG(0x4000020c)  /* DMA Command Address Register Channel 0 */
+#define DDADR1          __REG(0x40000210)  /* DMA Descriptor Address Register Channel 1 */
+#define DSADR1          __REG(0x40000214)  /* DMA Source Address Register Channel 1 */
+#define DTADR1          __REG(0x40000218)  /* DMA Target Address Register Channel 1 */
+#define DCMD1           __REG(0x4000021c)  /* DMA Command Address Register Channel 1 */
+#define DDADR2          __REG(0x40000220)  /* DMA Descriptor Address Register Channel 2 */
+#define DSADR2          __REG(0x40000224)  /* DMA Source Address Register Channel 2 */
+#define DTADR2          __REG(0x40000228)  /* DMA Target Address Register Channel 2 */
+#define DCMD2           __REG(0x4000022c)  /* DMA Command Address Register Channel 2 */
+#define DDADR3          __REG(0x40000230)  /* DMA Descriptor Address Register Channel 3 */
+#define DSADR3          __REG(0x40000234)  /* DMA Source Address Register Channel 3 */
+#define DTADR3          __REG(0x40000238)  /* DMA Target Address Register Channel 3 */
+#define DCMD3           __REG(0x4000023c)  /* DMA Command Address Register Channel 3 */
+#define DDADR4          __REG(0x40000240)  /* DMA Descriptor Address Register Channel 4 */
+#define DSADR4          __REG(0x40000244)  /* DMA Source Address Register Channel 4 */
+#define DTADR4          __REG(0x40000248)  /* DMA Target Address Register Channel 4 */
+#define DCMD4           __REG(0x4000024c)  /* DMA Command Address Register Channel 4 */
+#define DDADR5          __REG(0x40000250)  /* DMA Descriptor Address Register Channel 5 */
+#define DSADR5          __REG(0x40000254)  /* DMA Source Address Register Channel 5 */
+#define DTADR5          __REG(0x40000258)  /* DMA Target Address Register Channel 5 */
+#define DCMD5           __REG(0x4000025c)  /* DMA Command Address Register Channel 5 */
+#define DDADR6          __REG(0x40000260)  /* DMA Descriptor Address Register Channel 6 */
+#define DSADR6          __REG(0x40000264)  /* DMA Source Address Register Channel 6 */
+#define DTADR6          __REG(0x40000268)  /* DMA Target Address Register Channel 6 */
+#define DCMD6           __REG(0x4000026c)  /* DMA Command Address Register Channel 6 */
+#define DDADR7          __REG(0x40000270)  /* DMA Descriptor Address Register Channel 7 */
+#define DSADR7          __REG(0x40000274)  /* DMA Source Address Register Channel 7 */
+#define DTADR7          __REG(0x40000278)  /* DMA Target Address Register Channel 7 */
+#define DCMD7           __REG(0x4000027c)  /* DMA Command Address Register Channel 7 */
+#define DDADR8          __REG(0x40000280)  /* DMA Descriptor Address Register Channel 8 */
+#define DSADR8          __REG(0x40000284)  /* DMA Source Address Register Channel 8 */
+#define DTADR8          __REG(0x40000288)  /* DMA Target Address Register Channel 8 */
+#define DCMD8           __REG(0x4000028c)  /* DMA Command Address Register Channel 8 */
+#define DDADR9          __REG(0x40000290)  /* DMA Descriptor Address Register Channel 9 */
+#define DSADR9          __REG(0x40000294)  /* DMA Source Address Register Channel 9 */
+#define DTADR9          __REG(0x40000298)  /* DMA Target Address Register Channel 9 */
+#define DCMD9           __REG(0x4000029c)  /* DMA Command Address Register Channel 9 */
+#define DDADR10         __REG(0x400002a0)  /* DMA Descriptor Address Register Channel 10 */
+#define DSADR10         __REG(0x400002a4)  /* DMA Source Address Register Channel 10 */
+#define DTADR10         __REG(0x400002a8)  /* DMA Target Address Register Channel 10 */
+#define DCMD10          __REG(0x400002ac)  /* DMA Command Address Register Channel 10 */
+#define DDADR11         __REG(0x400002b0)  /* DMA Descriptor Address Register Channel 11 */
+#define DSADR11         __REG(0x400002b4)  /* DMA Source Address Register Channel 11 */
+#define DTADR11         __REG(0x400002b8)  /* DMA Target Address Register Channel 11 */
+#define DCMD11          __REG(0x400002bc)  /* DMA Command Address Register Channel 11 */
+#define DDADR12         __REG(0x400002c0)  /* DMA Descriptor Address Register Channel 12 */
+#define DSADR12         __REG(0x400002c4)  /* DMA Source Address Register Channel 12 */
+#define DTADR12         __REG(0x400002c8)  /* DMA Target Address Register Channel 12 */
+#define DCMD12          __REG(0x400002cc)  /* DMA Command Address Register Channel 12 */
+#define DDADR13         __REG(0x400002d0)  /* DMA Descriptor Address Register Channel 13 */
+#define DSADR13         __REG(0x400002d4)  /* DMA Source Address Register Channel 13 */
+#define DTADR13         __REG(0x400002d8)  /* DMA Target Address Register Channel 13 */
+#define DCMD13          __REG(0x400002dc)  /* DMA Command Address Register Channel 13 */
+#define DDADR14         __REG(0x400002e0)  /* DMA Descriptor Address Register Channel 14 */
+#define DSADR14         __REG(0x400002e4)  /* DMA Source Address Register Channel 14 */
+#define DTADR14         __REG(0x400002e8)  /* DMA Target Address Register Channel 14 */
+#define DCMD14          __REG(0x400002ec)  /* DMA Command Address Register Channel 14 */
+#define DDADR15         __REG(0x400002f0)  /* DMA Descriptor Address Register Channel 15 */
+#define DSADR15         __REG(0x400002f4)  /* DMA Source Address Register Channel 15 */
+#define DTADR15         __REG(0x400002f8)  /* DMA Target Address Register Channel 15 */
+#define DCMD15          __REG(0x400002fc)  /* DMA Command Address Register Channel 15 */
+
+#define DDADR(x)        __REG2(0x40000200, (x) << 4)
+#define DSADR(x)        __REG2(0x40000204, (x) << 4)
+#define DTADR(x)        __REG2(0x40000208, (x) << 4)
+#define DCMD(x)         __REG2(0x4000020c, (x) << 4)
+
+#define DDADR_DESCADDR  0xfffffff0      /* Address of next descriptor (mask) */
+#define DDADR_STOP      (1 << 0)        /* Stop (read / write) */
+
+#define DCMD_INCSRCADDR (1 << 31)       /* Source Address Increment Setting. */
+#define DCMD_INCTRGADDR (1 << 30)       /* Target Address Increment Setting. */
+#define DCMD_FLOWSRC    (1 << 29)       /* Flow Control by the source. */
+#define DCMD_FLOWTRG    (1 << 28)       /* Flow Control by the target. */
+#define DCMD_STARTIRQEN (1 << 22)       /* Start Interrupt Enable */
+#define DCMD_ENDIRQEN   (1 << 21)       /* End Interrupt Enable */
+#define DCMD_ENDIAN     (1 << 18)       /* Device Endian-ness. */
+#define DCMD_BURST8     (1 << 16)       /* 8 byte burst */
+#define DCMD_BURST16    (2 << 16)       /* 16 byte burst */
+#define DCMD_BURST32    (3 << 16)       /* 32 byte burst */
+#define DCMD_WIDTH1     (1 << 14)       /* 1 byte width */
+#define DCMD_WIDTH2     (2 << 14)       /* 2 byte width (HalfWord) */
+#define DCMD_WIDTH4     (3 << 14)       /* 4 byte width (Word) */
+#define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
+
+
+/*
+ * UARTs
+ */
+
+/* Full Function UART (FFUART) */
+#define FFUART          FFRBR
+#define FFRBR           __REG(0x40100000)  /* Receive Buffer Register (read only) */
+#define FFTHR           __REG(0x40100000)  /* Transmit Holding Register (write only) */
+#define FFIER           __REG(0x40100004)  /* Interrupt Enable Register (read/write) */
+#define FFIIR           __REG(0x40100008)  /* Interrupt ID Register (read only) */
+#define FFFCR           __REG(0x40100008)  /* FIFO Control Register (write only) */
+#define FFLCR           __REG(0x4010000C)  /* Line Control Register (read/write) */
+#define FFMCR           __REG(0x40100010)  /* Modem Control Register (read/write) */
+#define FFLSR           __REG(0x40100014)  /* Line Status Register (read only) */
+#define FFMSR           __REG(0x40100018)  /* Modem Status Register (read only) */
+#define FFSPR           __REG(0x4010001C)  /* Scratch Pad Register (read/write) */
+#define FFISR           __REG(0x40100020)  /* Infrared Selection Register (read/write) */
+#define FFDLL           __REG(0x40100000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define FFDLH           __REG(0x40100004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Bluetooth UART (BTUART) */
+#define BTUART          BTRBR
+#define BTRBR           __REG(0x40200000)  /* Receive Buffer Register (read only) */
+#define BTTHR           __REG(0x40200000)  /* Transmit Holding Register (write only) */
+#define BTIER           __REG(0x40200004)  /* Interrupt Enable Register (read/write) */
+#define BTIIR           __REG(0x40200008)  /* Interrupt ID Register (read only) */
+#define BTFCR           __REG(0x40200008)  /* FIFO Control Register (write only) */
+#define BTLCR           __REG(0x4020000C)  /* Line Control Register (read/write) */
+#define BTMCR           __REG(0x40200010)  /* Modem Control Register (read/write) */
+#define BTLSR           __REG(0x40200014)  /* Line Status Register (read only) */
+#define BTMSR           __REG(0x40200018)  /* Modem Status Register (read only) */
+#define BTSPR           __REG(0x4020001C)  /* Scratch Pad Register (read/write) */
+#define BTISR           __REG(0x40200020)  /* Infrared Selection Register (read/write) */
+#define BTDLL           __REG(0x40200000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define BTDLH           __REG(0x40200004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+/* Standard UART (STUART) */
+#define STUART          STRBR
+#define STRBR           __REG(0x40700000)  /* Receive Buffer Register (read only) */
+#define STTHR           __REG(0x40700000)  /* Transmit Holding Register (write only) */
+#define STIER           __REG(0x40700004)  /* Interrupt Enable Register (read/write) */
+#define STIIR           __REG(0x40700008)  /* Interrupt ID Register (read only) */
+#define STFCR           __REG(0x40700008)  /* FIFO Control Register (write only) */
+#define STLCR           __REG(0x4070000C)  /* Line Control Register (read/write) */
+#define STMCR           __REG(0x40700010)  /* Modem Control Register (read/write) */
+#define STLSR           __REG(0x40700014)  /* Line Status Register (read only) */
+#define STMSR           __REG(0x40700018)  /* Reserved */
+#define STSPR           __REG(0x4070001C)  /* Scratch Pad Register (read/write) */
+#define STISR           __REG(0x40700020)  /* Infrared Selection Register (read/write) */
+#define STDLL           __REG(0x40700000)  /* Divisor Latch Low Register (DLAB = 1) (read/write) */
+#define STDLH           __REG(0x40700004)  /* Divisor Latch High Register (DLAB = 1) (read/write) */
+
+#define IER_DMAE        (1 << 7)        /* DMA Requests Enable */
+#define IER_UUE         (1 << 6)        /* UART Unit Enable */
+#define IER_NRZE        (1 << 5)        /* NRZ coding Enable */
+#define IER_RTIOE       (1 << 4)        /* Receiver Time Out Interrupt Enable */
+#define IER_MIE         (1 << 3)        /* Modem Interrupt Enable */
+#define IER_RLSE        (1 << 2)        /* Receiver Line Status Interrupt Enable */
+#define IER_TIE         (1 << 1)        /* Transmit Data request Interrupt Enable */
+#define IER_RAVIE       (1 << 0)        /* Receiver Data Available Interrupt Enable */
+
+#define IIR_FIFOES1     (1 << 7)        /* FIFO Mode Enable Status */
+#define IIR_FIFOES0     (1 << 6)        /* FIFO Mode Enable Status */
+#define IIR_TOD         (1 << 3)        /* Time Out Detected */
+#define IIR_IID2        (1 << 2)        /* Interrupt Source Encoded */
+#define IIR_IID1        (1 << 1)        /* Interrupt Source Encoded */
+#define IIR_IP          (1 << 0)        /* Interrupt Pending (active low) */
+
+#define FCR_ITL2        (1 << 7)        /* Interrupt Trigger Level */
+#define FCR_ITL1        (1 << 6)        /* Interrupt Trigger Level */
+#define FCR_RESETTF     (1 << 2)        /* Reset Transmitter FIFO */
+#define FCR_RESETRF     (1 << 1)        /* Reset Receiver FIFO */
+#define FCR_TRFIFOE     (1 << 0)        /* Transmit and Receive FIFO Enable */
+#define FCR_ITL_1       (0)
+#define FCR_ITL_8       (FCR_ITL1)
+#define FCR_ITL_16      (FCR_ITL2)
+#define FCR_ITL_32      (FCR_ITL2|FCR_ITL1)
+
+#define LCR_DLAB        (1 << 7)        /* Divisor Latch Access Bit */
+#define LCR_SB          (1 << 6)        /* Set Break */
+#define LCR_STKYP       (1 << 5)        /* Sticky Parity */
+#define LCR_EPS         (1 << 4)        /* Even Parity Select */
+#define LCR_PEN         (1 << 3)        /* Parity Enable */
+#define LCR_STB         (1 << 2)        /* Stop Bit */
+#define LCR_WLS1        (1 << 1)        /* Word Length Select */
+#define LCR_WLS0        (1 << 0)        /* Word Length Select */
+
+#define LSR_FIFOE       (1 << 7)        /* FIFO Error Status */
+#define LSR_TEMT        (1 << 6)        /* Transmitter Empty */
+#define LSR_TDRQ        (1 << 5)        /* Transmit Data Request */
+#define LSR_BI          (1 << 4)        /* Break Interrupt */
+#define LSR_FE          (1 << 3)        /* Framing Error */
+#define LSR_PE          (1 << 2)        /* Parity Error */
+#define LSR_OE          (1 << 1)        /* Overrun Error */
+#define LSR_DR          (1 << 0)        /* Data Ready */
+
+#define MCR_LOOP        (1 << 4)
+#define MCR_OUT2        (1 << 3)        /* force MSR_DCD in loopback mode */
+#define MCR_OUT1        (1 << 2)        /* force MSR_RI in loopback mode */
+#define MCR_RTS         (1 << 1)        /* Request to Send */
+#define MCR_DTR         (1 << 0)        /* Data Terminal Ready */
+
+#define MSR_DCD         (1 << 7)        /* Data Carrier Detect */
+#define MSR_RI          (1 << 6)        /* Ring Indicator */
+#define MSR_DSR         (1 << 5)        /* Data Set Ready */
+#define MSR_CTS         (1 << 4)        /* Clear To Send */
+#define MSR_DDCD        (1 << 3)        /* Delta Data Carrier Detect */
+#define MSR_TERI        (1 << 2)        /* Trailing Edge Ring Indicator */
+#define MSR_DDSR        (1 << 1)        /* Delta Data Set Ready */
+#define MSR_DCTS        (1 << 0)        /* Delta Clear To Send */
+
+/*
+ * IrSR (Infrared Selection Register)
+ */
+#define STISR_RXPL      (1 << 4)        /* Receive Data Polarity */
+#define STISR_TXPL      (1 << 3)        /* Transmit Data Polarity */
+#define STISR_XMODE     (1 << 2)        /* Transmit Pulse Width Select */
+#define STISR_RCVEIR    (1 << 1)        /* Receiver SIR Enable */
+#define STISR_XMITIR    (1 << 0)        /* Transmitter SIR Enable */
+
+
+/*
+ * I2C registers
+ */
+
+#define IBMR            __REG(0x40301680)  /* I2C Bus Monitor Register - IBMR */
+#define IDBR            __REG(0x40301688)  /* I2C Data Buffer Register - IDBR */
+#define ICR             __REG(0x40301690)  /* I2C Control Register - ICR */
+#define ISR             __REG(0x40301698)  /* I2C Status Register - ISR */
+#define ISAR            __REG(0x403016A0)  /* I2C Slave Address Register - ISAR */
+
+#define PWRIBMR    __REG(0x40f00180)  /* Power I2C Bus Monitor Register-IBMR */
+#define PWRIDBR    __REG(0x40f00188)  /* Power I2C Data Buffer Register-IDBR */
+#define PWRICR __REG(0x40f00190)  /* Power I2C Control Register - ICR */
+#define PWRISR __REG(0x40f00198)  /* Power I2C Status Register - ISR */
+#define PWRISAR    __REG(0x40f001A0)  /*Power I2C Slave Address Register-ISAR */
+
+#define ICR_START       (1 << 0)           /* start bit */
+#define ICR_STOP        (1 << 1)           /* stop bit */
+#define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
+#define ICR_TB          (1 << 3)           /* transfer byte bit */
+#define ICR_MA          (1 << 4)           /* master abort */
+#define ICR_SCLE        (1 << 5)           /* master clock enable */
+#define ICR_IUE         (1 << 6)           /* unit enable */
+#define ICR_GCD         (1 << 7)           /* general call disable */
+#define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
+#define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
+#define ICR_BEIE        (1 << 10)          /* enable bus error ints */
+#define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
+#define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
+#define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
+#define ICR_UR          (1 << 14)          /* unit reset */
+
+#define ISR_RWM         (1 << 0)           /* read/write mode */
+#define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
+#define ISR_UB          (1 << 2)           /* unit busy */
+#define ISR_IBB         (1 << 3)           /* bus busy */
+#define ISR_SSD         (1 << 4)           /* slave stop detected */
+#define ISR_ALD         (1 << 5)           /* arbitration loss detected */
+#define ISR_ITE         (1 << 6)           /* tx buffer empty */
+#define ISR_IRF         (1 << 7)           /* rx buffer full */
+#define ISR_GCAD        (1 << 8)           /* general call address detected */
+#define ISR_SAD         (1 << 9)           /* slave address detected */
+#define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
+
+
+/*
+ * Serial Audio Controller
+ */
+
+/* FIXME: This clash with SA1111 defines */
+#ifndef _ASM_ARCH_SA1111
+
+#define SACR0           __REG(0x40400000)  /* Global Control Register */
+#define SACR1           __REG(0x40400004)  /* Serial Audio I 2 S/MSB-Justified Control Register */
+#define SASR0           __REG(0x4040000C)  /* Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
+#define SAIMR           __REG(0x40400014)  /* Serial Audio Interrupt Mask Register */
+#define SAICR           __REG(0x40400018)  /* Serial Audio Interrupt Clear Register */
+#define SADIV           __REG(0x40400060)  /* Audio Clock Divider Register. */
+#define SADR            __REG(0x40400080)  /* Serial Audio Data Register (TX and RX FIFO access Register). */
+
+#define SACR0_RFTH(x)   (x << 12)       /* Rx FIFO Interrupt or DMA Trigger Threshold */
+#define SACR0_TFTH(x)   (x << 8)        /* Tx FIFO Interrupt or DMA Trigger Threshold */
+#define SACR0_STRF      (1 << 5)        /* FIFO Select for EFWR Special Function */
+#define SACR0_EFWR      (1 << 4)        /* Enable EFWR Function  */
+#define SACR0_RST       (1 << 3)        /* FIFO, i2s Register Reset */
+#define SACR0_BCKD      (1 << 2)        /* Bit Clock Direction */
+#define SACR0_ENB       (1 << 0)        /* Enable I2S Link */
+#define SACR1_ENLBF     (1 << 5)        /* Enable Loopback */
+#define SACR1_DRPL      (1 << 4)        /* Disable Replaying Function */
+#define SACR1_DREC      (1 << 3)        /* Disable Recording Function */
+#define SACR1_AMSL      (1 << 1)        /* Specify Alternate Mode */
+
+#define SASR0_I2SOFF    (1 << 7)        /* Controller Status */
+#define SASR0_ROR       (1 << 6)        /* Rx FIFO Overrun */
+#define SASR0_TUR       (1 << 5)        /* Tx FIFO Underrun */
+#define SASR0_RFS       (1 << 4)        /* Rx FIFO Service Request */
+#define SASR0_TFS       (1 << 3)        /* Tx FIFO Service Request */
+#define SASR0_BSY       (1 << 2)        /* I2S Busy */
+#define SASR0_RNE       (1 << 1)        /* Rx FIFO Not Empty */
+#define SASR0_TNF       (1 << 0)        /* Tx FIFO Not Empty */
+
+#define SAICR_ROR       (1 << 6)        /* Clear Rx FIFO Overrun Interrupt */
+#define SAICR_TUR       (1 << 5)        /* Clear Tx FIFO Underrun Interrupt */
+
+#define SAIMR_ROR       (1 << 6)        /* Enable Rx FIFO Overrun Condition Interrupt */
+#define SAIMR_TUR       (1 << 5)        /* Enable Tx FIFO Underrun Condition Interrupt */
+#define SAIMR_RFS       (1 << 4)        /* Enable Rx FIFO Service Interrupt */
+#define SAIMR_TFS       (1 << 3)        /* Enable Tx FIFO Service Interrupt */
+
+#endif
+
+/*
+ * AC97 Controller registers
+ */
+
+#define POCR            __REG(0x40500000)  /* PCM Out Control Register */
+#define POCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define POCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define PICR            __REG(0x40500004)  /* PCM In Control Register */
+#define PICR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define PICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define MCCR            __REG(0x40500008)  /* Mic In Control Register */
+#define MCCR_FEIE       (1 << 3)        /* FIFO Error Interrupt Enable */
+#define MCCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define GCR             __REG(0x4050000C)  /* Global Control Register */
+#define GCR_nDMAEN      (1 << 24)       /* non DMA Enable */
+#define GCR_CDONE_IE    (1 << 19)       /* Command Done Interrupt Enable */
+#define GCR_SDONE_IE    (1 << 18)       /* Status Done Interrupt Enable */
+#define GCR_SECRDY_IEN  (1 << 9)        /* Secondary Ready Interrupt Enable */
+#define GCR_PRIRDY_IEN  (1 << 8)        /* Primary Ready Interrupt Enable */
+#define GCR_SECRES_IEN  (1 << 5)        /* Secondary Resume Interrupt Enable */
+#define GCR_PRIRES_IEN  (1 << 4)        /* Primary Resume Interrupt Enable */
+#define GCR_ACLINK_OFF  (1 << 3)        /* AC-link Shut Off */
+#define GCR_WARM_RST    (1 << 2)        /* AC97 Warm Reset */
+#define GCR_COLD_RST    (1 << 1)        /* AC'97 Cold Reset (0 = active) */
+#define GCR_GIE         (1 << 0)        /* Codec GPI Interrupt Enable */
+
+#define POSR            __REG(0x40500010)  /* PCM Out Status Register */
+#define POSR_FIFOE      (1 << 4)        /* FIFO error */
+#define POSR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define PISR            __REG(0x40500014)  /* PCM In Status Register */
+#define PISR_FIFOE      (1 << 4)        /* FIFO error */
+#define PISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define PISR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define MCSR            __REG(0x40500018)  /* Mic In Status Register */
+#define MCSR_FIFOE      (1 << 4)        /* FIFO error */
+#define MCSR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define MCSR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define GSR             __REG(0x4050001C)  /* Global Status Register */
+#define GSR_CDONE       (1 << 19)       /* Command Done */
+#define GSR_SDONE       (1 << 18)       /* Status Done */
+#define GSR_RDCS        (1 << 15)       /* Read Completion Status */
+#define GSR_BIT3SLT12   (1 << 14)       /* Bit 3 of slot 12 */
+#define GSR_BIT2SLT12   (1 << 13)       /* Bit 2 of slot 12 */
+#define GSR_BIT1SLT12   (1 << 12)       /* Bit 1 of slot 12 */
+#define GSR_SECRES      (1 << 11)       /* Secondary Resume Interrupt */
+#define GSR_PRIRES      (1 << 10)       /* Primary Resume Interrupt */
+#define GSR_SCR         (1 << 9)        /* Secondary Codec Ready */
+#define GSR_PCR         (1 << 8)        /*  Primary Codec Ready */
+#define GSR_MCINT       (1 << 7)        /* Mic In Interrupt */
+#define GSR_POINT       (1 << 6)        /* PCM Out Interrupt */
+#define GSR_PIINT       (1 << 5)        /* PCM In Interrupt */
+#define GSR_ACOFFD      (1 << 3)        /* AC-link Shut Off Done */
+#define GSR_MOINT       (1 << 2)        /* Modem Out Interrupt */
+#define GSR_MIINT       (1 << 1)        /* Modem In Interrupt */
+#define GSR_GSCI        (1 << 0)        /* Codec GPI Status Change Interrupt */
+
+#define CAR             __REG(0x40500020)  /* CODEC Access Register */
+#define CAR_CAIP        (1 << 0)        /* Codec Access In Progress */
+
+#define PCDR            __REG(0x40500040)  /* PCM FIFO Data Register */
+#define MCDR            __REG(0x40500060)  /* Mic-in FIFO Data Register */
+
+#define MOCR            __REG(0x40500100)  /* Modem Out Control Register */
+#define MOCR_FEIE       (1 << 3)        /* FIFO Error */
+#define MOCR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define MICR            __REG(0x40500108)  /* Modem In Control Register */
+#define MICR_FEIE       (1 << 3)        /* FIFO Error */
+#define MICR_FSRIE      (1 << 1)        /* FIFO Service Request Interrupt Enable */
+
+#define MOSR            __REG(0x40500110)  /* Modem Out Status Register */
+#define MOSR_FIFOE      (1 << 4)        /* FIFO error */
+#define MOSR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define MISR            __REG(0x40500118)  /* Modem In Status Register */
+#define MISR_FIFOE      (1 << 4)        /* FIFO error */
+#define MISR_EOC        (1 << 3)        /* DMA End-of-Chain (exclusive clear) */
+#define MISR_FSR        (1 << 2)        /* FIFO Service Request */
+
+#define MODR            __REG(0x40500140)  /* Modem FIFO Data Register */
+
+#define PAC_REG_BASE    __REG(0x40500200)  /* Primary Audio Codec */
+#define SAC_REG_BASE    __REG(0x40500300)  /* Secondary Audio Codec */
+#define PMC_REG_BASE    __REG(0x40500400)  /* Primary Modem Codec */
+#define SMC_REG_BASE    __REG(0x40500500)  /* Secondary Modem Codec */
+
+
+/*
+ * USB Device Controller
+ * PXA25x and PXA27x USB device controller registers are different.
+ */
+#if defined(CONFIG_PXA25x)
+
+#define UDC_RES1        __REG(0x40600004)  /* UDC Undocumented - Reserved1 */
+#define UDC_RES2        __REG(0x40600008)  /* UDC Undocumented - Reserved2 */
+#define UDC_RES3        __REG(0x4060000C)  /* UDC Undocumented - Reserved3 */
+
+#define UDCCR           __REG(0x40600000)  /* UDC Control Register */
+#define UDCCR_UDE       (1 << 0)        /* UDC enable */
+#define UDCCR_UDA       (1 << 1)        /* UDC active */
+#define UDCCR_RSM       (1 << 2)        /* Device resume */
+#define UDCCR_RESIR     (1 << 3)        /* Resume interrupt request */
+#define UDCCR_SUSIR     (1 << 4)        /* Suspend interrupt request */
+#define UDCCR_SRM       (1 << 5)        /* Suspend/resume interrupt mask */
+#define UDCCR_RSTIR     (1 << 6)        /* Reset interrupt request */
+#define UDCCR_REM       (1 << 7)        /* Reset interrupt mask */
+
+#define UDCCS0          __REG(0x40600010)  /* UDC Endpoint 0 Control/Status Register */
+#define UDCCS0_OPR      (1 << 0)        /* OUT packet ready */
+#define UDCCS0_IPR      (1 << 1)        /* IN packet ready */
+#define UDCCS0_FTF      (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS0_DRWF     (1 << 3)        /* Device remote wakeup feature */
+#define UDCCS0_SST      (1 << 4)        /* Sent stall */
+#define UDCCS0_FST      (1 << 5)        /* Force stall */
+#define UDCCS0_RNE      (1 << 6)        /* Receive FIFO no empty */
+#define UDCCS0_SA       (1 << 7)        /* Setup active */
+
+/* Bulk IN - Endpoint 1,6,11 */
+#define UDCCS1          __REG(0x40600014)  /* UDC Endpoint 1 (IN) Control/Status Register */
+#define UDCCS6          __REG(0x40600028)  /* UDC Endpoint 6 (IN) Control/Status Register */
+#define UDCCS11         __REG(0x4060003C)  /* UDC Endpoint 11 (IN) Control/Status Register */
+
+#define UDCCS_BI_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_BI_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_BI_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_BI_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_BI_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BI_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BI_TSP    (1 << 7)        /* Transmit short packet */
+
+/* Bulk OUT - Endpoint 2,7,12 */
+#define UDCCS2          __REG(0x40600018)  /* UDC Endpoint 2 (OUT) Control/Status Register */
+#define UDCCS7          __REG(0x4060002C)  /* UDC Endpoint 7 (OUT) Control/Status Register */
+#define UDCCS12         __REG(0x40600040)  /* UDC Endpoint 12 (OUT) Control/Status Register */
+
+#define UDCCS_BO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_BO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_BO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_BO_SST    (1 << 4)        /* Sent stall */
+#define UDCCS_BO_FST    (1 << 5)        /* Force stall */
+#define UDCCS_BO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_BO_RSP    (1 << 7)        /* Receive short packet */
+
+/* Isochronous IN - Endpoint 3,8,13 */
+#define UDCCS3          __REG(0x4060001C)  /* UDC Endpoint 3 (IN) Control/Status Register */
+#define UDCCS8          __REG(0x40600030)  /* UDC Endpoint 8 (IN) Control/Status Register */
+#define UDCCS13         __REG(0x40600044)  /* UDC Endpoint 13 (IN) Control/Status Register */
+
+#define UDCCS_II_TFS    (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_II_TPC    (1 << 1)        /* Transmit packet complete */
+#define UDCCS_II_FTF    (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_II_TUR    (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_II_TSP    (1 << 7)        /* Transmit short packet */
+
+/* Isochronous OUT - Endpoint 4,9,14 */
+#define UDCCS4          __REG(0x40600020)  /* UDC Endpoint 4 (OUT) Control/Status Register */
+#define UDCCS9          __REG(0x40600034)  /* UDC Endpoint 9 (OUT) Control/Status Register */
+#define UDCCS14         __REG(0x40600048)  /* UDC Endpoint 14 (OUT) Control/Status Register */
+
+#define UDCCS_IO_RFS    (1 << 0)        /* Receive FIFO service */
+#define UDCCS_IO_RPC    (1 << 1)        /* Receive packet complete */
+#define UDCCS_IO_ROF    (1 << 3)        /* Receive overflow */
+#define UDCCS_IO_DME    (1 << 3)        /* DMA enable */
+#define UDCCS_IO_RNE    (1 << 6)        /* Receive FIFO not empty */
+#define UDCCS_IO_RSP    (1 << 7)        /* Receive short packet */
+
+/* Interrupt IN - Endpoint 5,10,15 */
+#define UDCCS5          __REG(0x40600024)  /* UDC Endpoint 5 (Interrupt) Control/Status Register */
+#define UDCCS10         __REG(0x40600038)  /* UDC Endpoint 10 (Interrupt) Control/Status Register */
+#define UDCCS15         __REG(0x4060004C)  /* UDC Endpoint 15 (Interrupt) Control/Status Register */
+
+#define UDCCS_INT_TFS   (1 << 0)        /* Transmit FIFO service */
+#define UDCCS_INT_TPC   (1 << 1)        /* Transmit packet complete */
+#define UDCCS_INT_FTF   (1 << 2)        /* Flush Tx FIFO */
+#define UDCCS_INT_TUR   (1 << 3)        /* Transmit FIFO underrun */
+#define UDCCS_INT_SST   (1 << 4)        /* Sent stall */
+#define UDCCS_INT_FST   (1 << 5)        /* Force stall */
+#define UDCCS_INT_TSP   (1 << 7)        /* Transmit short packet */
+
+#define UFNRH           __REG(0x40600060)  /* UDC Frame Number Register High */
+#define UFNRL           __REG(0x40600064)  /* UDC Frame Number Register Low */
+#define UBCR2           __REG(0x40600068)  /* UDC Byte Count Reg 2 */
+#define UBCR4           __REG(0x4060006c)  /* UDC Byte Count Reg 4 */
+#define UBCR7           __REG(0x40600070)  /* UDC Byte Count Reg 7 */
+#define UBCR9           __REG(0x40600074)  /* UDC Byte Count Reg 9 */
+#define UBCR12          __REG(0x40600078)  /* UDC Byte Count Reg 12 */
+#define UBCR14          __REG(0x4060007c)  /* UDC Byte Count Reg 14 */
+#define UDDR0           __REG(0x40600080)  /* UDC Endpoint 0 Data Register */
+#define UDDR1           __REG(0x40600100)  /* UDC Endpoint 1 Data Register */
+#define UDDR2           __REG(0x40600180)  /* UDC Endpoint 2 Data Register */
+#define UDDR3           __REG(0x40600200)  /* UDC Endpoint 3 Data Register */
+#define UDDR4           __REG(0x40600400)  /* UDC Endpoint 4 Data Register */
+#define UDDR5           __REG(0x406000A0)  /* UDC Endpoint 5 Data Register */
+#define UDDR6           __REG(0x40600600)  /* UDC Endpoint 6 Data Register */
+#define UDDR7           __REG(0x40600680)  /* UDC Endpoint 7 Data Register */
+#define UDDR8           __REG(0x40600700)  /* UDC Endpoint 8 Data Register */
+#define UDDR9           __REG(0x40600900)  /* UDC Endpoint 9 Data Register */
+#define UDDR10          __REG(0x406000C0)  /* UDC Endpoint 10 Data Register */
+#define UDDR11          __REG(0x40600B00)  /* UDC Endpoint 11 Data Register */
+#define UDDR12          __REG(0x40600B80)  /* UDC Endpoint 12 Data Register */
+#define UDDR13          __REG(0x40600C00)  /* UDC Endpoint 13 Data Register */
+#define UDDR14          __REG(0x40600E00)  /* UDC Endpoint 14 Data Register */
+#define UDDR15          __REG(0x406000E0)  /* UDC Endpoint 15 Data Register */
+
+#define UICR0           __REG(0x40600050)  /* UDC Interrupt Control Register 0 */
+
+#define UICR0_IM0       (1 << 0)        /* Interrupt mask ep 0 */
+#define UICR0_IM1       (1 << 1)        /* Interrupt mask ep 1 */
+#define UICR0_IM2       (1 << 2)        /* Interrupt mask ep 2 */
+#define UICR0_IM3       (1 << 3)        /* Interrupt mask ep 3 */
+#define UICR0_IM4       (1 << 4)        /* Interrupt mask ep 4 */
+#define UICR0_IM5       (1 << 5)        /* Interrupt mask ep 5 */
+#define UICR0_IM6       (1 << 6)        /* Interrupt mask ep 6 */
+#define UICR0_IM7       (1 << 7)        /* Interrupt mask ep 7 */
+
+#define UICR1           __REG(0x40600054)  /* UDC Interrupt Control Register 1 */
+
+#define UICR1_IM8       (1 << 0)        /* Interrupt mask ep 8 */
+#define UICR1_IM9       (1 << 1)        /* Interrupt mask ep 9 */
+#define UICR1_IM10      (1 << 2)        /* Interrupt mask ep 10 */
+#define UICR1_IM11      (1 << 3)        /* Interrupt mask ep 11 */
+#define UICR1_IM12      (1 << 4)        /* Interrupt mask ep 12 */
+#define UICR1_IM13      (1 << 5)        /* Interrupt mask ep 13 */
+#define UICR1_IM14      (1 << 6)        /* Interrupt mask ep 14 */
+#define UICR1_IM15      (1 << 7)        /* Interrupt mask ep 15 */
+
+#define USIR0           __REG(0x40600058)  /* UDC Status Interrupt Register 0 */
+
+#define USIR0_IR0       (1 << 0)        /* Interrup request ep 0 */
+#define USIR0_IR1       (1 << 1)        /* Interrup request ep 1 */
+#define USIR0_IR2       (1 << 2)        /* Interrup request ep 2 */
+#define USIR0_IR3       (1 << 3)        /* Interrup request ep 3 */
+#define USIR0_IR4       (1 << 4)        /* Interrup request ep 4 */
+#define USIR0_IR5       (1 << 5)        /* Interrup request ep 5 */
+#define USIR0_IR6       (1 << 6)        /* Interrup request ep 6 */
+#define USIR0_IR7       (1 << 7)        /* Interrup request ep 7 */
+
+#define USIR1           __REG(0x4060005C)  /* UDC Status Interrupt Register 1 */
+
+#define USIR1_IR8       (1 << 0)        /* Interrup request ep 8 */
+#define USIR1_IR9       (1 << 1)        /* Interrup request ep 9 */
+#define USIR1_IR10      (1 << 2)        /* Interrup request ep 10 */
+#define USIR1_IR11      (1 << 3)        /* Interrup request ep 11 */
+#define USIR1_IR12      (1 << 4)        /* Interrup request ep 12 */
+#define USIR1_IR13      (1 << 5)        /* Interrup request ep 13 */
+#define USIR1_IR14      (1 << 6)        /* Interrup request ep 14 */
+#define USIR1_IR15      (1 << 7)        /* Interrup request ep 15 */
+
+#elif defined(CONFIG_PXA27x)
+
+#define UDCCR           __REG(0x40600000) /* UDC Control Register */
+#define UDCCR_OEN       (1 << 31)       /* On-the-Go Enable */
+#define UDCCR_AALTHNP   (1 << 30)       /* A-device Alternate Host Negotiation
+                                           Protocol Port Support */
+#define UDCCR_AHNP      (1 << 29)       /* A-device Host Negotiation Protocol
+                                           Support */
+#define UDCCR_BHNP      (1 << 28)       /* B-device Host Negotiation Protocol
+                                           Enable */
+#define UDCCR_DWRE      (1 << 16)       /* Device Remote Wake-up Enable */
+#define UDCCR_ACN       (0x03 << 11)    /* Active UDC configuration Number */
+#define UDCCR_ACN_S     11
+#define UDCCR_AIN       (0x07 << 8)     /* Active UDC interface Number */
+#define UDCCR_AIN_S     8
+#define UDCCR_AAISN     (0x07 << 5)     /* Active UDC Alternate Interface
+                                           Setting Number */
+#define UDCCR_AAISN_S   5
+#define UDCCR_SMAC      (1 << 4)        /* Switch Endpoint Memory to Active
+                                           Configuration */
+#define UDCCR_EMCE      (1 << 3)        /* Endpoint Memory Configuration
+                                           Error */
+#define UDCCR_UDR       (1 << 2)        /* UDC Resume */
+#define UDCCR_UDA       (1 << 1)        /* UDC Active */
+#define UDCCR_UDE       (1 << 0)        /* UDC Enable */
+
+#define UDCICR0         __REG(0x40600004) /* UDC Interrupt Control Register0 */
+#define UDCICR1         __REG(0x40600008) /* UDC Interrupt Control Register1 */
+#define UDCICR_FIFOERR  (1 << 1)        /* FIFO Error interrupt for EP */
+#define UDCICR_PKTCOMPL (1 << 0)        /* Packet Complete interrupt for EP */
+
+#define UDC_INT_FIFOERROR  (0x2)
+#define UDC_INT_PACKETCMP  (0x1)
+
+#define UDCICR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCICR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
+#define UDCICR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
+#define UDCICR1_IERU    (1 << 29)       /* IntEn - Resume */
+#define UDCICR1_IESU    (1 << 28)       /* IntEn - Suspend */
+#define UDCICR1_IERS    (1 << 27)       /* IntEn - Reset */
+
+#define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
+#define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
+#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
+#define UDCISR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
+#define UDCISR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
+#define UDCISR1_IERU    (1 << 29)       /* IntEn - Resume */
+#define UDCISR1_IESU    (1 << 28)       /* IntEn - Suspend */
+#define UDCISR1_IERS    (1 << 27)       /* IntEn - Reset */
+
+
+#define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
+#define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
+#define UDCOTGICR_IESF  (1 << 24)       /* OTG SET_FEATURE command recvd */
+#define UDCOTGICR_IEXR  (1 << 17)       /* Extra Transciever Interrupt
+                                           Rising Edge Interrupt Enable */
+#define UDCOTGICR_IEXF  (1 << 16)       /* Extra Transciever Interrupt
+                                           Falling Edge Interrupt Enable */
+#define UDCOTGICR_IEVV40R (1 << 9)      /* OTG Vbus Valid 4.0V Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV40F (1 << 8)      /* OTG Vbus Valid 4.0V Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV44R (1 << 7)      /* OTG Vbus Valid 4.4V Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEVV44F (1 << 6)      /* OTG Vbus Valid 4.4V Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESVR (1 << 5)        /* OTG Session Valid Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESVF (1 << 4)        /* OTG Session Valid Falling Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IESDR (1 << 3)        /* OTG A-Device SRP Detect Rising
+                                           Edge Interrupt Enable */
+#define UDCOTGICR_IESDF (1 << 2)        /* OTG A-Device SRP Detect Falling
+                                           Edge Interrupt Enable */
+#define UDCOTGICR_IEIDR (1 << 1)        /* OTG ID Change Rising Edge
+                                           Interrupt Enable */
+#define UDCOTGICR_IEIDF (1 << 0)        /* OTG ID Change Falling Edge
+                                           Interrupt Enable */
+
+#define UDCCSN(x)       __REG2(0x40600100, (x) << 2)
+#define UDCCSR0         __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
+#define UDCCSR0_SA      (1 << 7)        /* Setup Active */
+#define UDCCSR0_RNE     (1 << 6)        /* Receive FIFO Not Empty */
+#define UDCCSR0_FST     (1 << 5)        /* Force Stall */
+#define UDCCSR0_SST     (1 << 4)        /* Sent Stall */
+#define UDCCSR0_DME     (1 << 3)        /* DMA Enable */
+#define UDCCSR0_FTF     (1 << 2)        /* Flush Transmit FIFO */
+#define UDCCSR0_IPR     (1 << 1)        /* IN Packet Ready */
+#define UDCCSR0_OPC     (1 << 0)        /* OUT Packet Complete */
+
+#define UDCCSRA         __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
+#define UDCCSRB         __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
+#define UDCCSRC         __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
+#define UDCCSRD         __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
+#define UDCCSRE         __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
+#define UDCCSRF         __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
+#define UDCCSRG         __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
+#define UDCCSRH         __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
+#define UDCCSRI         __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
+#define UDCCSRJ         __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
+#define UDCCSRK         __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
+#define UDCCSRL         __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
+#define UDCCSRM         __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
+#define UDCCSRN         __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
+#define UDCCSRP         __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
+#define UDCCSRQ         __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
+#define UDCCSRR         __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
+#define UDCCSRS         __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
+#define UDCCSRT         __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
+#define UDCCSRU         __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
+#define UDCCSRV         __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
+#define UDCCSRW         __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
+#define UDCCSRX         __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
+
+#define UDCCSR_DPE      (1 << 9)        /* Data Packet Error */
+#define UDCCSR_FEF      (1 << 8)        /* Flush Endpoint FIFO */
+#define UDCCSR_SP       (1 << 7)        /* Short Packet Control/Status */
+#define UDCCSR_BNE      (1 << 6)        /* Buffer Not Empty (IN endpoints) */
+#define UDCCSR_BNF      (1 << 6)        /* Buffer Not Full (OUT endpoints) */
+#define UDCCSR_FST      (1 << 5)        /* Force STALL */
+#define UDCCSR_SST      (1 << 4)        /* Sent STALL */
+#define UDCCSR_DME      (1 << 3)        /* DMA Enable */
+#define UDCCSR_TRN      (1 << 2)        /* Tx/Rx NAK */
+#define UDCCSR_PC       (1 << 1)        /* Packet Complete */
+#define UDCCSR_FS       (1 << 0)        /* FIFO needs service */
+
+#define UDCBCN(x)       __REG2(0x40600200, (x)<<2)
+#define UDCBCR0         __REG(0x40600200) /* Byte Count Register - EP0 */
+#define UDCBCRA         __REG(0x40600204) /* Byte Count Register - EPA */
+#define UDCBCRB         __REG(0x40600208) /* Byte Count Register - EPB */
+#define UDCBCRC         __REG(0x4060020C) /* Byte Count Register - EPC */
+#define UDCBCRD         __REG(0x40600210) /* Byte Count Register - EPD */
+#define UDCBCRE         __REG(0x40600214) /* Byte Count Register - EPE */
+#define UDCBCRF         __REG(0x40600218) /* Byte Count Register - EPF */
+#define UDCBCRG         __REG(0x4060021C) /* Byte Count Register - EPG */
+#define UDCBCRH         __REG(0x40600220) /* Byte Count Register - EPH */
+#define UDCBCRI         __REG(0x40600224) /* Byte Count Register - EPI */
+#define UDCBCRJ         __REG(0x40600228) /* Byte Count Register - EPJ */
+#define UDCBCRK         __REG(0x4060022C) /* Byte Count Register - EPK */
+#define UDCBCRL         __REG(0x40600230) /* Byte Count Register - EPL */
+#define UDCBCRM         __REG(0x40600234) /* Byte Count Register - EPM */
+#define UDCBCRN         __REG(0x40600238) /* Byte Count Register - EPN */
+#define UDCBCRP         __REG(0x4060023C) /* Byte Count Register - EPP */
+#define UDCBCRQ         __REG(0x40600240) /* Byte Count Register - EPQ */
+#define UDCBCRR         __REG(0x40600244) /* Byte Count Register - EPR */
+#define UDCBCRS         __REG(0x40600248) /* Byte Count Register - EPS */
+#define UDCBCRT         __REG(0x4060024C) /* Byte Count Register - EPT */
+#define UDCBCRU         __REG(0x40600250) /* Byte Count Register - EPU */
+#define UDCBCRV         __REG(0x40600254) /* Byte Count Register - EPV */
+#define UDCBCRW         __REG(0x40600258) /* Byte Count Register - EPW */
+#define UDCBCRX         __REG(0x4060025C) /* Byte Count Register - EPX */
+
+#define UDCDN(x)        __REG2(0x40600300, (x)<<2)
+#define PHYS_UDCDN(x)   (0x40600300 + ((x)<<2))
+#define PUDCDN(x)       (volatile u32 *)(io_p2v(PHYS_UDCDN((x))))
+#define UDCDR0          __REG(0x40600300) /* Data Register - EP0 */
+#define UDCDRA          __REG(0x40600304) /* Data Register - EPA */
+#define UDCDRB          __REG(0x40600308) /* Data Register - EPB */
+#define UDCDRC          __REG(0x4060030C) /* Data Register - EPC */
+#define UDCDRD          __REG(0x40600310) /* Data Register - EPD */
+#define UDCDRE          __REG(0x40600314) /* Data Register - EPE */
+#define UDCDRF          __REG(0x40600318) /* Data Register - EPF */
+#define UDCDRG          __REG(0x4060031C) /* Data Register - EPG */
+#define UDCDRH          __REG(0x40600320) /* Data Register - EPH */
+#define UDCDRI          __REG(0x40600324) /* Data Register - EPI */
+#define UDCDRJ          __REG(0x40600328) /* Data Register - EPJ */
+#define UDCDRK          __REG(0x4060032C) /* Data Register - EPK */
+#define UDCDRL          __REG(0x40600330) /* Data Register - EPL */
+#define UDCDRM          __REG(0x40600334) /* Data Register - EPM */
+#define UDCDRN          __REG(0x40600338) /* Data Register - EPN */
+#define UDCDRP          __REG(0x4060033C) /* Data Register - EPP */
+#define UDCDRQ          __REG(0x40600340) /* Data Register - EPQ */
+#define UDCDRR          __REG(0x40600344) /* Data Register - EPR */
+#define UDCDRS          __REG(0x40600348) /* Data Register - EPS */
+#define UDCDRT          __REG(0x4060034C) /* Data Register - EPT */
+#define UDCDRU          __REG(0x40600350) /* Data Register - EPU */
+#define UDCDRV          __REG(0x40600354) /* Data Register - EPV */
+#define UDCDRW          __REG(0x40600358) /* Data Register - EPW */
+#define UDCDRX          __REG(0x4060035C) /* Data Register - EPX */
+
+#define UDCCN(x)       __REG2(0x40600400, (x)<<2)
+#define UDCCRA          __REG(0x40600404) /* Configuration register EPA */
+#define UDCCRB          __REG(0x40600408) /* Configuration register EPB */
+#define UDCCRC          __REG(0x4060040C) /* Configuration register EPC */
+#define UDCCRD          __REG(0x40600410) /* Configuration register EPD */
+#define UDCCRE          __REG(0x40600414) /* Configuration register EPE */
+#define UDCCRF          __REG(0x40600418) /* Configuration register EPF */
+#define UDCCRG          __REG(0x4060041C) /* Configuration register EPG */
+#define UDCCRH          __REG(0x40600420) /* Configuration register EPH */
+#define UDCCRI          __REG(0x40600424) /* Configuration register EPI */
+#define UDCCRJ          __REG(0x40600428) /* Configuration register EPJ */
+#define UDCCRK          __REG(0x4060042C) /* Configuration register EPK */
+#define UDCCRL          __REG(0x40600430) /* Configuration register EPL */
+#define UDCCRM          __REG(0x40600434) /* Configuration register EPM */
+#define UDCCRN          __REG(0x40600438) /* Configuration register EPN */
+#define UDCCRP          __REG(0x4060043C) /* Configuration register EPP */
+#define UDCCRQ          __REG(0x40600440) /* Configuration register EPQ */
+#define UDCCRR          __REG(0x40600444) /* Configuration register EPR */
+#define UDCCRS          __REG(0x40600448) /* Configuration register EPS */
+#define UDCCRT          __REG(0x4060044C) /* Configuration register EPT */
+#define UDCCRU          __REG(0x40600450) /* Configuration register EPU */
+#define UDCCRV          __REG(0x40600454) /* Configuration register EPV */
+#define UDCCRW          __REG(0x40600458) /* Configuration register EPW */
+#define UDCCRX          __REG(0x4060045C) /* Configuration register EPX */
+
+#define UDCCONR_CN      (0x03 << 25)    /* Configuration Number */
+#define UDCCONR_CN_S    (25)
+#define UDCCONR_IN      (0x07 << 22)    /* Interface Number */
+#define UDCCONR_IN_S    (22)
+#define UDCCONR_AISN    (0x07 << 19)    /* Alternate Interface Number */
+#define UDCCONR_AISN_S  (19)
+#define UDCCONR_EN      (0x0f << 15)    /* Endpoint Number */
+#define UDCCONR_EN_S    (15)
+#define UDCCONR_ET      (0x03 << 13)    /* Endpoint Type: */
+#define UDCCONR_ET_S    (13)
+#define UDCCONR_ET_INT  (0x03 << 13)    /*   Interrupt */
+#define UDCCONR_ET_BULK (0x02 << 13)    /*   Bulk */
+#define UDCCONR_ET_ISO  (0x01 << 13)    /*   Isochronous */
+#define UDCCONR_ET_NU   (0x00 << 13)    /*   Not used */
+#define UDCCONR_ED      (1 << 12)       /* Endpoint Direction */
+#define UDCCONR_MPS     (0x3ff << 2)    /* Maximum Packet Size */
+#define UDCCONR_MPS_S   (2)
+#define UDCCONR_DE      (1 << 1)        /* Double Buffering Enable */
+#define UDCCONR_EE      (1 << 0)        /* Endpoint Enable */
+
+
+#define UDC_INT_FIFOERROR  (0x2)
+#define UDC_INT_PACKETCMP  (0x1)
+
+#define UDC_FNR_MASK     (0x7ff)
+
+#define UDCCSR_WR_MASK   (UDCCSR_DME|UDCCSR_FST)
+#define UDC_BCR_MASK    (0x3ff)
+#endif
+
+/*
+ * Fast Infrared Communication Port
+ */
+
+#define FICP            __REG(0x40800000)  /* Start of FICP area */
+#define ICCR0           __REG(0x40800000)  /* ICP Control Register 0 */
+#define ICCR1           __REG(0x40800004)  /* ICP Control Register 1 */
+#define ICCR2           __REG(0x40800008)  /* ICP Control Register 2 */
+#define ICDR            __REG(0x4080000c)  /* ICP Data Register */
+#define ICSR0           __REG(0x40800014)  /* ICP Status Register 0 */
+#define ICSR1           __REG(0x40800018)  /* ICP Status Register 1 */
+
+#define ICCR0_AME       (1 << 7)        /* Adress match enable */
+#define ICCR0_TIE       (1 << 6)        /* Transmit FIFO interrupt enable */
+#define ICCR0_RIE       (1 << 5)        /* Recieve FIFO interrupt enable */
+#define ICCR0_RXE       (1 << 4)        /* Receive enable */
+#define ICCR0_TXE       (1 << 3)        /* Transmit enable */
+#define ICCR0_TUS       (1 << 2)        /* Transmit FIFO underrun select */
+#define ICCR0_LBM       (1 << 1)        /* Loopback mode */
+#define ICCR0_ITR       (1 << 0)        /* IrDA transmission */
+
+#ifdef CONFIG_PXA27x
+#define ICCR2_RXP       (1 << 3)        /* Receive Pin Polarity select */
+#define ICCR2_TXP       (1 << 2)        /* Transmit Pin Polarity select */
+#define ICCR2_TRIG      (3 << 0)        /* Receive FIFO Trigger threshold */
+#define ICCR2_TRIG_8    (0 << 0)        /*      >= 8 bytes */
+#define ICCR2_TRIG_16   (1 << 0)        /*      >= 16 bytes */
+#define ICCR2_TRIG_32   (2 << 0)        /*      >= 32 bytes */
+#endif
+
+#ifdef CONFIG_PXA27x
+#define ICSR0_EOC       (1 << 6)        /* DMA End of Descriptor Chain */
+#endif
+#define ICSR0_FRE       (1 << 5)        /* Framing error */
+#define ICSR0_RFS       (1 << 4)        /* Receive FIFO service request */
+#define ICSR0_TFS       (1 << 3)        /* Transnit FIFO service request */
+#define ICSR0_RAB       (1 << 2)        /* Receiver abort */
+#define ICSR0_TUR       (1 << 1)        /* Trunsmit FIFO underun */
+#define ICSR0_EIF       (1 << 0)        /* End/Error in FIFO */
+
+#define ICSR1_ROR       (1 << 6)        /* Receiver FIFO underrun  */
+#define ICSR1_CRE       (1 << 5)        /* CRC error */
+#define ICSR1_EOF       (1 << 4)        /* End of frame */
+#define ICSR1_TNF       (1 << 3)        /* Transmit FIFO not full */
+#define ICSR1_RNE       (1 << 2)        /* Receive FIFO not empty */
+#define ICSR1_TBY       (1 << 1)        /* Tramsmiter busy flag */
+#define ICSR1_RSY       (1 << 0)        /* Recevier synchronized flag */
+
+
+/*
+ * Real Time Clock
+ */
+
+#define RCNR            __REG(0x40900000)  /* RTC Count Register */
+#define RTAR            __REG(0x40900004)  /* RTC Alarm Register */
+#define RTSR            __REG(0x40900008)  /* RTC Status Register */
+#define RTTR            __REG(0x4090000C)  /* RTC Timer Trim Register */
+#define PIAR            __REG(0x40900038)  /* Periodic Interrupt Alarm Register */
+
+#define RTSR_PICE       (1 << 15)       /* Periodic interrupt count enable */
+#define RTSR_PIALE      (1 << 14)       /* Periodic interrupt Alarm enable */
+#define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
+#define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
+#define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
+#define RTSR_AL         (1 << 0)        /* RTC alarm detected */
+
+
+/*
+ * OS Timer & Match Registers
+ */
+
+#define OSMR0           __REG(0x40A00000)  /* */
+#define OSMR1           __REG(0x40A00004)  /* */
+#define OSMR2           __REG(0x40A00008)  /* */
+#define OSMR3           __REG(0x40A0000C)  /* */
+#define OSMR4           __REG(0x40A00080)  /* */
+#define OSCR            __REG(0x40A00010)  /* OS Timer Counter Register */
+#define OSCR4           __REG(0x40A00040)  /* OS Timer Counter Register */
+#define OMCR4           __REG(0x40A000C0)  /* */
+#define OSSR            __REG(0x40A00014)  /* OS Timer Status Register */
+#define OWER            __REG(0x40A00018)  /* OS Timer Watchdog Enable Register */
+#define OIER            __REG(0x40A0001C)  /* OS Timer Interrupt Enable Register */
+
+#define OSSR_M3         (1 << 3)        /* Match status channel 3 */
+#define OSSR_M2         (1 << 2)        /* Match status channel 2 */
+#define OSSR_M1         (1 << 1)        /* Match status channel 1 */
+#define OSSR_M0         (1 << 0)        /* Match status channel 0 */
+
+#define OWER_WME        (1 << 0)        /* Watchdog Match Enable */
+
+#define OIER_E3         (1 << 3)        /* Interrupt enable channel 3 */
+#define OIER_E2         (1 << 2)        /* Interrupt enable channel 2 */
+#define OIER_E1         (1 << 1)        /* Interrupt enable channel 1 */
+#define OIER_E0         (1 << 0)        /* Interrupt enable channel 0 */
+
+
+/*
+ * Pulse Width Modulator
+ */
+
+#define PWM_CTRL0       __REG(0x40B00000)  /* PWM 0 Control Register */
+#define PWM_PWDUTY0     __REG(0x40B00004)  /* PWM 0 Duty Cycle Register */
+#define PWM_PERVAL0     __REG(0x40B00008)  /* PWM 0 Period Control Register */
+
+#define PWM_CTRL1       __REG(0x40C00000)  /* PWM 1Control Register */
+#define PWM_PWDUTY1     __REG(0x40C00004)  /* PWM 1 Duty Cycle Register */
+#define PWM_PERVAL1     __REG(0x40C00008)  /* PWM 1 Period Control Register */
+
+
+/*
+ * Interrupt Controller
+ */
+
+#define ICIP            __REG(0x40D00000)  /* Interrupt Controller IRQ Pending Register */
+#define ICMR            __REG(0x40D00004)  /* Interrupt Controller Mask Register */
+#define ICLR            __REG(0x40D00008)  /* Interrupt Controller Level Register */
+#define ICFP            __REG(0x40D0000C)  /* Interrupt Controller FIQ Pending Register */
+#define ICPR            __REG(0x40D00010)  /* Interrupt Controller Pending Register */
+#define ICCR            __REG(0x40D00014)  /* Interrupt Controller Control Register */
+
+
+/*
+ * General Purpose I/O
+ */
+
+#define GPLR0           __REG(0x40E00000)  /* GPIO Pin-Level Register GPIO<31:0> */
+#define GPLR1           __REG(0x40E00004)  /* GPIO Pin-Level Register GPIO<63:32> */
+#define GPLR2           __REG(0x40E00008)  /* GPIO Pin-Level Register GPIO<80:64> */
+
+#define GPDR0           __REG(0x40E0000C)  /* GPIO Pin Direction Register GPIO<31:0> */
+#define GPDR1           __REG(0x40E00010)  /* GPIO Pin Direction Register GPIO<63:32> */
+#define GPDR2           __REG(0x40E00014)  /* GPIO Pin Direction Register GPIO<80:64> */
+
+#define GPSR0           __REG(0x40E00018)  /* GPIO Pin Output Set Register GPIO<31:0> */
+#define GPSR1           __REG(0x40E0001C)  /* GPIO Pin Output Set Register GPIO<63:32> */
+#define GPSR2           __REG(0x40E00020)  /* GPIO Pin Output Set Register GPIO<80:64> */
+
+#define GPCR0           __REG(0x40E00024)  /* GPIO Pin Output Clear Register GPIO<31:0> */
+#define GPCR1           __REG(0x40E00028)  /* GPIO Pin Output Clear Register GPIO <63:32> */
+#define GPCR2           __REG(0x40E0002C)  /* GPIO Pin Output Clear Register GPIO <80:64> */
+
+#define GRER0           __REG(0x40E00030)  /* GPIO Rising-Edge Detect Register GPIO<31:0> */
+#define GRER1           __REG(0x40E00034)  /* GPIO Rising-Edge Detect Register GPIO<63:32> */
+#define GRER2           __REG(0x40E00038)  /* GPIO Rising-Edge Detect Register GPIO<80:64> */
+
+#define GFER0           __REG(0x40E0003C)  /* GPIO Falling-Edge Detect Register GPIO<31:0> */
+#define GFER1           __REG(0x40E00040)  /* GPIO Falling-Edge Detect Register GPIO<63:32> */
+#define GFER2           __REG(0x40E00044)  /* GPIO Falling-Edge Detect Register GPIO<80:64> */
+
+#define GEDR0           __REG(0x40E00048)  /* GPIO Edge Detect Status Register GPIO<31:0> */
+#define GEDR1           __REG(0x40E0004C)  /* GPIO Edge Detect Status Register GPIO<63:32> */
+#define GEDR2           __REG(0x40E00050)  /* GPIO Edge Detect Status Register GPIO<80:64> */
+
+#define GAFR0_L         __REG(0x40E00054)  /* GPIO Alternate Function Select Register GPIO<15:0> */
+#define GAFR0_U         __REG(0x40E00058)  /* GPIO Alternate Function Select Register GPIO<31:16> */
+#define GAFR1_L         __REG(0x40E0005C)  /* GPIO Alternate Function Select Register GPIO<47:32> */
+#define GAFR1_U         __REG(0x40E00060)  /* GPIO Alternate Function Select Register GPIO<63:48> */
+#define GAFR2_L         __REG(0x40E00064)  /* GPIO Alternate Function Select Register GPIO<79:64> */
+#define GAFR2_U         __REG(0x40E00068)  /* GPIO Alternate Function Select Register GPIO<95-80> */
+#define GAFR3_L         __REG(0x40E0006C)  /* GPIO Alternate Function Select Register GPIO<111:96> */
+#define GAFR3_U         __REG(0x40E00070)  /* GPIO Alternate Function Select Register GPIO<127:112> */
+
+#define GPLR3           __REG(0x40E00100)  /* GPIO Pin-Level Register GPIO<127:96> */
+#define GPDR3           __REG(0x40E0010C)  /* GPIO Pin Direction Register GPIO<127:96> */
+#define GPSR3           __REG(0x40E00118)  /* GPIO Pin Output Set Register GPIO<127:96> */
+#define GPCR3           __REG(0x40E00124)  /* GPIO Pin Output Clear Register GPIO<127:96> */
+#define GRER3           __REG(0x40E00130)  /* GPIO Rising-Edge Detect Register GPIO<127:96> */
+#define GFER3           __REG(0x40E0013C)  /* GPIO Falling-Edge Detect Register GPIO<127:96> */
+#define GEDR3           __REG(0x40E00148)  /* GPIO Edge Detect Status Register GPIO<127:96> */
+
+/* More handy macros.  The argument is a literal GPIO number. */
+
+#define GPIO_bit(x)     (1 << ((x) & 0x1f))
+
+#ifdef CONFIG_PXA27x
+
+/* Interrupt Controller */
+
+#define ICIP2           __REG(0x40D0009C)  /* Interrupt Controller IRQ Pending Register 2 */
+#define ICMR2           __REG(0x40D000A0)  /* Interrupt Controller Mask Register 2 */
+#define ICLR2           __REG(0x40D000A4)  /* Interrupt Controller Level Register 2 */
+#define ICFP2           __REG(0x40D000A8)  /* Interrupt Controller FIQ Pending Register 2 */
+#define ICPR2           __REG(0x40D000AC)  /* Interrupt Controller Pending Register 2 */
+
+#define _GPLR(x)        __REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define _GPDR(x)        __REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define _GPSR(x)        __REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define _GPCR(x)        __REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define _GRER(x)        __REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define _GFER(x)        __REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define _GEDR(x)        __REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define _GAFR(x)        __REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#define GPLR(x)         (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
+#define GPDR(x)         (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
+#define GPSR(x)         (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
+#define GPCR(x)         (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
+#define GRER(x)         (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
+#define GFER(x)         (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
+#define GEDR(x)         (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
+#define GAFR(x)         (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
+                         ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
+#else
+
+#define GPLR(x)         __REG2(0x40E00000, ((x) & 0x60) >> 3)
+#define GPDR(x)         __REG2(0x40E0000C, ((x) & 0x60) >> 3)
+#define GPSR(x)         __REG2(0x40E00018, ((x) & 0x60) >> 3)
+#define GPCR(x)         __REG2(0x40E00024, ((x) & 0x60) >> 3)
+#define GRER(x)         __REG2(0x40E00030, ((x) & 0x60) >> 3)
+#define GFER(x)         __REG2(0x40E0003C, ((x) & 0x60) >> 3)
+#define GEDR(x)         __REG2(0x40E00048, ((x) & 0x60) >> 3)
+#define GAFR(x)         __REG2(0x40E00054, ((x) & 0x70) >> 2)
+
+#endif
+
+
+/* GPIO alternate function assignments */
+
+#define GPIO1_RST               1       /* reset */
+#define GPIO6_MMCCLK            6       /* MMC Clock */
+#define GPIO7_48MHz             7       /* 48 MHz clock output */
+#define GPIO8_MMCCS0            8       /* MMC Chip Select 0 */
+#define GPIO9_MMCCS1            9       /* MMC Chip Select 1 */
+#define GPIO10_RTCCLK           10      /* real time clock (1 Hz) */
+#define GPIO11_3_6MHz           11      /* 3.6 MHz oscillator out */
+#define GPIO12_32KHz            12      /* 32 kHz out */
+#define GPIO13_MBGNT            13      /* memory controller grant */
+#define GPIO14_MBREQ            14      /* alternate bus master request */
+#define GPIO15_nCS_1            15      /* chip select 1 */
+#define GPIO16_PWM0             16      /* PWM0 output */
+#define GPIO17_PWM1             17      /* PWM1 output */
+#define GPIO18_RDY              18      /* Ext. Bus Ready */
+#define GPIO19_DREQ1            19      /* External DMA Request */
+#define GPIO20_DREQ0            20      /* External DMA Request */
+#define GPIO23_SCLK             23      /* SSP clock */
+#define GPIO24_SFRM             24      /* SSP Frame */
+#define GPIO25_STXD             25      /* SSP transmit */
+#define GPIO26_SRXD             26      /* SSP receive */
+#define GPIO27_SEXTCLK          27      /* SSP ext_clk */
+#define GPIO28_BITCLK           28      /* AC97/I2S bit_clk */
+#define GPIO29_SDATA_IN         29      /* AC97 Sdata_in0 / I2S Sdata_in */
+#define GPIO30_SDATA_OUT        30      /* AC97/I2S Sdata_out */
+#define GPIO31_SYNC             31      /* AC97/I2S sync */
+#define GPIO32_SDATA_IN1        32      /* AC97 Sdata_in1 */
+#define GPIO32_SYSCLK           32      /* I2S System Clock */
+#define GPIO32_MMCCLK           32      /* MMC Clock (PXA270) */
+#define GPIO33_nCS_5            33      /* chip select 5 */
+#define GPIO34_FFRXD            34      /* FFUART receive */
+#define GPIO34_MMCCS0           34      /* MMC Chip Select 0 */
+#define GPIO35_FFCTS            35      /* FFUART Clear to send */
+#define GPIO36_FFDCD            36      /* FFUART Data carrier detect */
+#define GPIO37_FFDSR            37      /* FFUART data set ready */
+#define GPIO38_FFRI             38      /* FFUART Ring Indicator */
+#define GPIO39_MMCCS1           39      /* MMC Chip Select 1 */
+#define GPIO39_FFTXD            39      /* FFUART transmit data */
+#define GPIO40_FFDTR            40      /* FFUART data terminal Ready */
+#define GPIO41_FFRTS            41      /* FFUART request to send */
+#define GPIO42_BTRXD            42      /* BTUART receive data */
+#define GPIO43_BTTXD            43      /* BTUART transmit data */
+#define GPIO44_BTCTS            44      /* BTUART clear to send */
+#define GPIO45_BTRTS            45      /* BTUART request to send */
+#define GPIO45_AC97_SYSCLK      45      /* AC97 System Clock */
+#define GPIO46_ICPRXD           46      /* ICP receive data */
+#define GPIO46_STRXD            46      /* STD_UART receive data */
+#define GPIO47_ICPTXD           47      /* ICP transmit data */
+#define GPIO47_STTXD            47      /* STD_UART transmit data */
+#define GPIO48_nPOE             48      /* Output Enable for Card Space */
+#define GPIO49_nPWE             49      /* Write Enable for Card Space */
+#define GPIO50_nPIOR            50      /* I/O Read for Card Space */
+#define GPIO51_nPIOW            51      /* I/O Write for Card Space */
+#define GPIO52_nPCE_1           52      /* Card Enable for Card Space */
+#define GPIO53_nPCE_2           53      /* Card Enable for Card Space */
+#define GPIO53_MMCCLK           53      /* MMC Clock */
+#define GPIO54_MMCCLK           54      /* MMC Clock */
+#define GPIO54_pSKTSEL          54      /* Socket Select for Card Space */
+#define GPIO54_nPCE_2           54      /* Card Enable for Card Space (PXA27x) */
+#define GPIO55_nPREG            55      /* Card Address bit 26 */
+#define GPIO56_nPWAIT           56      /* Wait signal for Card Space */
+#define GPIO57_nIOIS16          57      /* Bus Width select for I/O Card Space */
+#define GPIO58_LDD_0            58      /* LCD data pin 0 */
+#define GPIO59_LDD_1            59      /* LCD data pin 1 */
+#define GPIO60_LDD_2            60      /* LCD data pin 2 */
+#define GPIO61_LDD_3            61      /* LCD data pin 3 */
+#define GPIO62_LDD_4            62      /* LCD data pin 4 */
+#define GPIO63_LDD_5            63      /* LCD data pin 5 */
+#define GPIO64_LDD_6            64      /* LCD data pin 6 */
+#define GPIO65_LDD_7            65      /* LCD data pin 7 */
+#define GPIO66_LDD_8            66      /* LCD data pin 8 */
+#define GPIO66_MBREQ            66      /* alternate bus master req */
+#define GPIO67_LDD_9            67      /* LCD data pin 9 */
+#define GPIO67_MMCCS0           67      /* MMC Chip Select 0 */
+#define GPIO68_LDD_10           68      /* LCD data pin 10 */
+#define GPIO68_MMCCS1           68      /* MMC Chip Select 1 */
+#define GPIO69_LDD_11           69      /* LCD data pin 11 */
+#define GPIO69_MMCCLK           69      /* MMC_CLK */
+#define GPIO70_LDD_12           70      /* LCD data pin 12 */
+#define GPIO70_RTCCLK           70      /* Real Time clock (1 Hz) */
+#define GPIO71_LDD_13           71      /* LCD data pin 13 */
+#define GPIO71_3_6MHz           71      /* 3.6 MHz Oscillator clock */
+#define GPIO72_LDD_14           72      /* LCD data pin 14 */
+#define GPIO72_32kHz            72      /* 32 kHz clock */
+#define GPIO73_LDD_15           73      /* LCD data pin 15 */
+#define GPIO73_MBGNT            73      /* Memory controller grant */
+#define GPIO74_LCD_FCLK         74      /* LCD Frame clock */
+#define GPIO75_LCD_LCLK         75      /* LCD line clock */
+#define GPIO76_LCD_PCLK         76      /* LCD Pixel clock */
+#define GPIO77_LCD_ACBIAS       77      /* LCD AC Bias */
+#define GPIO78_nCS_2            78      /* chip select 2 */
+#define GPIO79_nCS_3            79      /* chip select 3 */
+#define GPIO80_nCS_4            80      /* chip select 4 */
+#define GPIO81_NSCLK            81      /* NSSP clock */
+#define GPIO82_NSFRM            82      /* NSSP Frame */
+#define GPIO83_NSTXD            83      /* NSSP transmit */
+#define GPIO84_NSRXD            84      /* NSSP receive */
+#define GPIO85_nPCE_1           85      /* Card Enable for Card Space (PXA27x) */
+#define GPIO92_MMCDAT0          92      /* MMC DAT0 (PXA27x) */
+#define GPIO109_MMCDAT1         109     /* MMC DAT1 (PXA27x) */
+#define GPIO110_MMCDAT2         110     /* MMC DAT2 (PXA27x) */
+#define GPIO110_MMCCS0          110     /* MMC Chip Select 0 (PXA27x) */
+#define GPIO111_MMCDAT3         111     /* MMC DAT3 (PXA27x) */
+#define GPIO111_MMCCS1          111     /* MMC Chip Select 1 (PXA27x) */
+#define GPIO112_MMCCMD          112     /* MMC CMD (PXA27x) */
+#define GPIO113_AC97_RESET_N    113     /* AC97 NRESET on (PXA27x) */
+
+/* GPIO alternate function mode & direction */
+
+#define GPIO_IN                 0x000
+#define GPIO_OUT                0x080
+#define GPIO_ALT_FN_1_IN        0x100
+#define GPIO_ALT_FN_1_OUT       0x180
+#define GPIO_ALT_FN_2_IN        0x200
+#define GPIO_ALT_FN_2_OUT       0x280
+#define GPIO_ALT_FN_3_IN        0x300
+#define GPIO_ALT_FN_3_OUT       0x380
+#define GPIO_MD_MASK_NR         0x07f
+#define GPIO_MD_MASK_DIR        0x080
+#define GPIO_MD_MASK_FN         0x300
+#define GPIO_DFLT_LOW           0x400
+#define GPIO_DFLT_HIGH          0x800
+
+#define GPIO1_RTS_MD            ( 1 | GPIO_ALT_FN_1_IN)
+#define GPIO6_MMCCLK_MD         ( 6 | GPIO_ALT_FN_1_OUT)
+#define GPIO7_48MHz_MD          ( 7 | GPIO_ALT_FN_1_OUT)
+#define GPIO8_MMCCS0_MD         ( 8 | GPIO_ALT_FN_1_OUT)
+#define GPIO9_MMCCS1_MD         ( 9 | GPIO_ALT_FN_1_OUT)
+#define GPIO10_RTCCLK_MD        (10 | GPIO_ALT_FN_1_OUT)
+#define GPIO11_3_6MHz_MD        (11 | GPIO_ALT_FN_1_OUT)
+#define GPIO12_32KHz_MD         (12 | GPIO_ALT_FN_1_OUT)
+#define GPIO13_MBGNT_MD         (13 | GPIO_ALT_FN_2_OUT)
+#define GPIO14_MBREQ_MD         (14 | GPIO_ALT_FN_1_IN)
+#define GPIO15_nCS_1_MD         (15 | GPIO_ALT_FN_2_OUT)
+#define GPIO16_PWM0_MD          (16 | GPIO_ALT_FN_2_OUT)
+#define GPIO17_PWM1_MD          (17 | GPIO_ALT_FN_2_OUT)
+#define GPIO18_RDY_MD           (18 | GPIO_ALT_FN_1_IN)
+#define GPIO19_DREQ1_MD         (19 | GPIO_ALT_FN_1_IN)
+#define GPIO20_DREQ0_MD         (20 | GPIO_ALT_FN_1_IN)
+#define GPIO23_SCLK_MD          (23 | GPIO_ALT_FN_2_OUT)
+#define GPIO24_SFRM_MD          (24 | GPIO_ALT_FN_2_OUT)
+#define GPIO25_STXD_MD          (25 | GPIO_ALT_FN_2_OUT)
+#define GPIO26_SRXD_MD          (26 | GPIO_ALT_FN_1_IN)
+#define GPIO27_SEXTCLK_MD       (27 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_AC97_MD   (28 | GPIO_ALT_FN_1_IN)
+#define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN)
+#define GPIO28_BITCLK_OUT_I2S_MD        (28 | GPIO_ALT_FN_1_OUT)
+#define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
+#define GPIO29_SDATA_IN_I2S_MD  (29 | GPIO_ALT_FN_2_IN)
+#define GPIO30_SDATA_OUT_AC97_MD        (30 | GPIO_ALT_FN_2_OUT)
+#define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_I2S_MD      (31 | GPIO_ALT_FN_1_OUT)
+#define GPIO31_SYNC_AC97_MD     (31 | GPIO_ALT_FN_2_OUT)
+#define GPIO32_SDATA_IN1_AC97_MD        (32 | GPIO_ALT_FN_1_IN)
+#define GPIO32_SYSCLK_I2S_MD    (32 | GPIO_ALT_FN_1_OUT)
+#define GPIO32_MMCCLK_MD                ( 32 | GPIO_ALT_FN_2_OUT)
+#define GPIO33_nCS_5_MD         (33 | GPIO_ALT_FN_2_OUT)
+#define GPIO34_FFRXD_MD         (34 | GPIO_ALT_FN_1_IN)
+#define GPIO34_MMCCS0_MD        (34 | GPIO_ALT_FN_2_OUT)
+#define GPIO35_FFCTS_MD         (35 | GPIO_ALT_FN_1_IN)
+#define GPIO36_FFDCD_MD         (36 | GPIO_ALT_FN_1_IN)
+#define GPIO37_FFDSR_MD         (37 | GPIO_ALT_FN_1_IN)
+#define GPIO38_FFRI_MD          (38 | GPIO_ALT_FN_1_IN)
+#define GPIO39_MMCCS1_MD        (39 | GPIO_ALT_FN_1_OUT)
+#define GPIO39_FFTXD_MD         (39 | GPIO_ALT_FN_2_OUT)
+#define GPIO40_FFDTR_MD         (40 | GPIO_ALT_FN_2_OUT)
+#define GPIO41_FFRTS_MD         (41 | GPIO_ALT_FN_2_OUT)
+#define GPIO42_BTRXD_MD         (42 | GPIO_ALT_FN_1_IN)
+#define GPIO43_BTTXD_MD         (43 | GPIO_ALT_FN_2_OUT)
+#define GPIO44_BTCTS_MD         (44 | GPIO_ALT_FN_1_IN)
+#define GPIO45_BTRTS_MD         (45 | GPIO_ALT_FN_2_OUT)
+#define GPIO45_SYSCLK_AC97_MD           (45 | GPIO_ALT_FN_1_OUT)
+#define GPIO46_ICPRXD_MD        (46 | GPIO_ALT_FN_1_IN)
+#define GPIO46_STRXD_MD         (46 | GPIO_ALT_FN_2_IN)
+#define GPIO47_ICPTXD_MD        (47 | GPIO_ALT_FN_2_OUT)
+#define GPIO47_STTXD_MD         (47 | GPIO_ALT_FN_1_OUT)
+#define GPIO48_nPOE_MD          (48 | GPIO_ALT_FN_2_OUT)
+#define GPIO49_nPWE_MD          (49 | GPIO_ALT_FN_2_OUT)
+#define GPIO50_nPIOR_MD         (50 | GPIO_ALT_FN_2_OUT)
+#define GPIO51_nPIOW_MD         (51 | GPIO_ALT_FN_2_OUT)
+#define GPIO52_nPCE_1_MD        (52 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_nPCE_2_MD        (53 | GPIO_ALT_FN_2_OUT)
+#define GPIO53_MMCCLK_MD        (53 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_MMCCLK_MD        (54 | GPIO_ALT_FN_1_OUT)
+#define GPIO54_nPCE_2_MD        (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO54_pSKTSEL_MD       (54 | GPIO_ALT_FN_2_OUT)
+#define GPIO55_nPREG_MD         (55 | GPIO_ALT_FN_2_OUT)
+#define GPIO56_nPWAIT_MD        (56 | GPIO_ALT_FN_1_IN)
+#define GPIO57_nIOIS16_MD       (57 | GPIO_ALT_FN_1_IN)
+#define GPIO58_LDD_0_MD         (58 | GPIO_ALT_FN_2_OUT)
+#define GPIO59_LDD_1_MD         (59 | GPIO_ALT_FN_2_OUT)
+#define GPIO60_LDD_2_MD         (60 | GPIO_ALT_FN_2_OUT)
+#define GPIO61_LDD_3_MD         (61 | GPIO_ALT_FN_2_OUT)
+#define GPIO62_LDD_4_MD         (62 | GPIO_ALT_FN_2_OUT)
+#define GPIO63_LDD_5_MD         (63 | GPIO_ALT_FN_2_OUT)
+#define GPIO64_LDD_6_MD         (64 | GPIO_ALT_FN_2_OUT)
+#define GPIO65_LDD_7_MD         (65 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_LDD_8_MD         (66 | GPIO_ALT_FN_2_OUT)
+#define GPIO66_MBREQ_MD         (66 | GPIO_ALT_FN_1_IN)
+#define GPIO67_LDD_9_MD         (67 | GPIO_ALT_FN_2_OUT)
+#define GPIO67_MMCCS0_MD        (67 | GPIO_ALT_FN_1_OUT)
+#define GPIO68_LDD_10_MD        (68 | GPIO_ALT_FN_2_OUT)
+#define GPIO68_MMCCS1_MD        (68 | GPIO_ALT_FN_1_OUT)
+#define GPIO69_LDD_11_MD        (69 | GPIO_ALT_FN_2_OUT)
+#define GPIO69_MMCCLK_MD        (69 | GPIO_ALT_FN_1_OUT)
+#define GPIO70_LDD_12_MD        (70 | GPIO_ALT_FN_2_OUT)
+#define GPIO70_RTCCLK_MD        (70 | GPIO_ALT_FN_1_OUT)
+#define GPIO71_LDD_13_MD        (71 | GPIO_ALT_FN_2_OUT)
+#define GPIO71_3_6MHz_MD        (71 | GPIO_ALT_FN_1_OUT)
+#define GPIO72_LDD_14_MD        (72 | GPIO_ALT_FN_2_OUT)
+#define GPIO72_32kHz_MD         (72 | GPIO_ALT_FN_1_OUT)
+#define GPIO73_LDD_15_MD        (73 | GPIO_ALT_FN_2_OUT)
+#define GPIO73_MBGNT_MD         (73 | GPIO_ALT_FN_1_OUT)
+#define GPIO74_LCD_FCLK_MD      (74 | GPIO_ALT_FN_2_OUT)
+#define GPIO75_LCD_LCLK_MD      (75 | GPIO_ALT_FN_2_OUT)
+#define GPIO76_LCD_PCLK_MD      (76 | GPIO_ALT_FN_2_OUT)
+#define GPIO77_LCD_ACBIAS_MD    (77 | GPIO_ALT_FN_2_OUT)
+#define GPIO78_nCS_2_MD         (78 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_nCS_3_MD         (79 | GPIO_ALT_FN_2_OUT)
+#define GPIO79_pSKTSEL_MD       (79 | GPIO_ALT_FN_1_OUT)
+#define GPIO80_nCS_4_MD         (80 | GPIO_ALT_FN_2_OUT)
+#define GPIO81_NSSP_CLK_OUT     (81 | GPIO_ALT_FN_1_OUT)
+#define GPIO81_NSSP_CLK_IN      (81 | GPIO_ALT_FN_1_IN)
+#define GPIO82_NSSP_FRM_OUT     (82 | GPIO_ALT_FN_1_OUT)
+#define GPIO82_NSSP_FRM_IN      (82 | GPIO_ALT_FN_1_IN)
+#define GPIO83_NSSP_TX          (83 | GPIO_ALT_FN_1_OUT)
+#define GPIO83_NSSP_RX          (83 | GPIO_ALT_FN_2_IN)
+#define GPIO84_NSSP_TX          (84 | GPIO_ALT_FN_1_OUT)
+#define GPIO84_NSSP_RX          (84 | GPIO_ALT_FN_2_IN)
+#define GPIO85_nPCE_1_MD        (85 | GPIO_ALT_FN_1_OUT)
+#define GPIO92_MMCDAT0_MD       (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO109_MMCDAT1_MD      (109 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCDAT2_MD      (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS0_MD       (110 | GPIO_ALT_FN_1_OUT)
+#define GPIO111_MMCDAT3_MD      (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO110_MMCCS1_MD       (111 | GPIO_ALT_FN_1_OUT)
+#define GPIO112_MMCCMD_MD       (112 | GPIO_ALT_FN_1_OUT)
+#define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT)
+#define GPIO117_I2CSCL_MD       (117 | GPIO_ALT_FN_1_OUT)
+#define GPIO118_I2CSDA_MD       (118 | GPIO_ALT_FN_1_IN)
+
+/*
+ * Power Manager
+ */
+
+#define PMCR            __REG(0x40F00000)  /* Power Manager Control Register */
+#define PSSR            __REG(0x40F00004)  /* Power Manager Sleep Status Register */
+#define PSPR            __REG(0x40F00008)  /* Power Manager Scratch Pad Register */
+#define PWER            __REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */
+#define PRER            __REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */
+#define PFER            __REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */
+#define PEDR            __REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */
+#define PCFR            __REG(0x40F0001C)  /* Power Manager General Configuration Register */
+#define PGSR0           __REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */
+#define PGSR1           __REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */
+#define PGSR2           __REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */
+#define PGSR3           __REG(0x40F0002C)  /* Power Manager GPIO Sleep State Register for GP[118-96] */
+#define RCSR            __REG(0x40F00030)  /* Reset Controller Status Register */
+
+#define PSLR            __REG(0x40F00034)       /* Power Manager Sleep Config Register */
+#define PSTR            __REG(0x40F00038)       /*Power Manager Standby Config Register */
+#define PSNR            __REG(0x40F0003C)       /*Power Manager Sense Config Register */
+#define PVCR            __REG(0x40F00040)       /*Power Manager VoltageControl Register */
+#define PKWR            __REG(0x40F00050)       /* Power Manager KB Wake-up Enable Reg */
+#define PKSR            __REG(0x40F00054)       /* Power Manager KB Level-Detect Register */
+#define PCMD(x) __REG2(0x40F00080, (x)<<2)
+#define PCMD0   __REG(0x40F00080 + 0 * 4)
+#define PCMD1   __REG(0x40F00080 + 1 * 4)
+#define PCMD2   __REG(0x40F00080 + 2 * 4)
+#define PCMD3   __REG(0x40F00080 + 3 * 4)
+#define PCMD4   __REG(0x40F00080 + 4 * 4)
+#define PCMD5   __REG(0x40F00080 + 5 * 4)
+#define PCMD6   __REG(0x40F00080 + 6 * 4)
+#define PCMD7   __REG(0x40F00080 + 7 * 4)
+#define PCMD8   __REG(0x40F00080 + 8 * 4)
+#define PCMD9   __REG(0x40F00080 + 9 * 4)
+#define PCMD10  __REG(0x40F00080 + 10 * 4)
+#define PCMD11  __REG(0x40F00080 + 11 * 4)
+#define PCMD12  __REG(0x40F00080 + 12 * 4)
+#define PCMD13  __REG(0x40F00080 + 13 * 4)
+#define PCMD14  __REG(0x40F00080 + 14 * 4)
+#define PCMD15  __REG(0x40F00080 + 15 * 4)
+#define PCMD16  __REG(0x40F00080 + 16 * 4)
+#define PCMD17  __REG(0x40F00080 + 17 * 4)
+#define PCMD18  __REG(0x40F00080 + 18 * 4)
+#define PCMD19  __REG(0x40F00080 + 19 * 4)
+#define PCMD20  __REG(0x40F00080 + 20 * 4)
+#define PCMD21  __REG(0x40F00080 + 21 * 4)
+#define PCMD22  __REG(0x40F00080 + 22 * 4)
+#define PCMD23  __REG(0x40F00080 + 23 * 4)
+#define PCMD24  __REG(0x40F00080 + 24 * 4)
+#define PCMD25  __REG(0x40F00080 + 25 * 4)
+#define PCMD26  __REG(0x40F00080 + 26 * 4)
+#define PCMD27  __REG(0x40F00080 + 27 * 4)
+#define PCMD28  __REG(0x40F00080 + 28 * 4)
+#define PCMD29  __REG(0x40F00080 + 29 * 4)
+#define PCMD30  __REG(0x40F00080 + 30 * 4)
+#define PCMD31  __REG(0x40F00080 + 31 * 4)
+
+#define PCMD_MBC        (1<<12)
+#define PCMD_DCE        (1<<11)
+#define PCMD_LC (1<<10)
+/* FIXME:  PCMD_SQC need be checked.   */
+#define PCMD_SQC        (3<<8)  /* currently only bit 8 is changeable,
+                                   bit 9 should be 0 all day. */
+#define PVCR_VCSA       (0x1<<14)
+#define PVCR_CommandDelay (0xf80)
+#define PCFR_PI2C_EN    (0x1 << 6)
+
+#define PSSR_OTGPH      (1 << 6)        /* OTG Peripheral control Hold */
+#define PSSR_RDH        (1 << 5)        /* Read Disable Hold */
+#define PSSR_PH         (1 << 4)        /* Peripheral Control Hold */
+#define PSSR_VFS        (1 << 2)        /* VDD Fault Status */
+#define PSSR_BFS        (1 << 1)        /* Battery Fault Status */
+#define PSSR_SSS        (1 << 0)        /* Software Sleep Status */
+
+#define PCFR_RO         (1 << 15)       /* RDH Override */
+#define PCFR_PO         (1 << 14)       /* PH Override */
+#define PCFR_GPROD      (1 << 12)       /* GPIO nRESET_OUT Disable */
+#define PCFR_L1_EN      (1 << 11)       /* Sleep Mode L1 converter Enable */
+#define PCFR_FVC        (1 << 10)       /* Frequency/Voltage Change */
+#define PCFR_DC_EN      (1 << 7)        /* Sleep/deep-sleep DC-DC Converter Enable */
+#define PCFR_PI2CEN     (1 << 6)        /* Enable PI2C controller */
+#define PCFR_DS         (1 << 3)        /* Deep Sleep Mode */
+#define PCFR_FS         (1 << 2)        /* Float Static Chip Selects */
+#define PCFR_FP         (1 << 1)        /* Float PCMCIA controls */
+#define PCFR_OPDE       (1 << 0)        /* 3.6864 MHz oscillator power-down enable */
+
+#define RCSR_GPR        (1 << 3)        /* GPIO Reset */
+#define RCSR_SMR        (1 << 2)        /* Sleep Mode */
+#define RCSR_WDR        (1 << 1)        /* Watchdog Reset */
+#define RCSR_HWR        (1 << 0)        /* Hardware Reset */
+
+#define PWER_GPIO(Nb)   (1 << Nb)       /* GPIO [0..15] wake-up enable     */
+#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
+#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
+#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
+#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
+#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
+#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
+#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
+#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
+#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
+#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
+#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
+#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
+#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
+#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
+#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
+#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
+#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
+
+
+/*
+ * SSP Serial Port Registers
+ * PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
+ * PXA255, PXA26x and PXA27x have extra ports, registers and bits.
+ */
+
+ /* Common PXA2xx bits first */
+#define SSCR0_DSS       (0x0000000f)    /* Data Size Select (mask) */
+#define SSCR0_DataSize(x)  ((x) - 1)    /* Data Size Select [4..16] */
+#define SSCR0_FRF       (0x00000030)    /* FRame Format (mask) */
+#define SSCR0_Motorola  (0x0 << 4)      /* Motorola's Serial Peripheral Interface (SPI) */
+#define SSCR0_TI        (0x1 << 4)      /* Texas Instruments' Synchronous Serial Protocol (SSP) */
+#define SSCR0_National  (0x2 << 4)      /* National Microwire */
+#define SSCR0_ECS       (1 << 6)        /* External clock select */
+#define SSCR0_SSE       (1 << 7)        /* Synchronous Serial Port Enable */
+#define SSCR0_SCR       (0x0000ff00)    /* Serial Clock Rate (mask) */
+#define SSCR0_SerClkDiv(x) ((((x) - 2)/2) << 8) /* Divisor [2..512] */
+
+#define SSCR1_RIE       (1 << 0)        /* Receive FIFO Interrupt Enable */
+#define SSCR1_TIE       (1 << 1)        /* Transmit FIFO Interrupt Enable */
+#define SSCR1_LBM       (1 << 2)        /* Loop-Back Mode */
+#define SSCR1_SPO       (1 << 3)        /* Motorola SPI SSPSCLK polarity setting */
+#define SSCR1_SPH       (1 << 4)        /* Motorola SPI SSPSCLK phase setting */
+#define SSCR1_MWDS      (1 << 5)        /* Microwire Transmit Data Size */
+#define SSCR1_TFT       (0x000003c0)    /* Transmit FIFO Threshold (mask) */
+#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
+#define SSCR1_RFT       (0x00003c00)    /* Receive FIFO Threshold (mask) */
+#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
+
+#define SSSR_TNF        (1 << 2)        /* Transmit FIFO Not Full */
+#define SSSR_RNE        (1 << 3)        /* Receive FIFO Not Empty */
+#define SSSR_BSY        (1 << 4)        /* SSP Busy */
+#define SSSR_TFS        (1 << 5)        /* Transmit FIFO Service Request */
+#define SSSR_RFS        (1 << 6)        /* Receive FIFO Service Request */
+#define SSSR_ROR        (1 << 7)        /* Receive FIFO Overrun */
+
+#define SSCR0_TIM               (1 << 23)       /* Transmit FIFO Under Run Interrupt Mask */
+#define SSCR0_RIM               (1 << 22)       /* Receive FIFO Over Run interrupt Mask */
+#define SSCR0_NCS               (1 << 21)       /* Network Clock Select */
+#define SSCR0_EDSS              (1 << 20)       /* Extended Data Size Select */
+
+/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
+#define SSCR0_PSP               (3 << 4)        /* PSP - Programmable Serial Protocol */
+#define SSCR1_TTELP             (1 << 31)       /* TXD Tristate Enable Last Phase */
+#define SSCR1_TTE               (1 << 30)       /* TXD Tristate Enable */
+#define SSCR1_EBCEI             (1 << 29)       /* Enable Bit Count Error interrupt */
+#define SSCR1_SCFR              (1 << 28)       /* Slave Clock free Running */
+#define SSCR1_ECRA              (1 << 27)       /* Enable Clock Request A */
+#define SSCR1_ECRB              (1 << 26)       /* Enable Clock request B */
+#define SSCR1_SCLKDIR   (1 << 25)       /* Serial Bit Rate Clock Direction */
+#define SSCR1_SFRMDIR   (1 << 24)       /* Frame Direction */
+#define SSCR1_RWOT              (1 << 23)       /* Receive Without Transmit */
+#define SSCR1_TRAIL             (1 << 22)       /* Trailing Byte */
+#define SSCR1_TSRE              (1 << 21)       /* Transmit Service Request Enable */
+#define SSCR1_RSRE              (1 << 20)       /* Receive Service Request Enable */
+#define SSCR1_TINTE             (1 << 19)       /* Receiver Time-out Interrupt enable */
+#define SSCR1_PINTE             (1 << 18)       /* Peripheral Trailing Byte Interupt Enable */
+#define SSCR1_STRF              (1 << 15)       /* Select FIFO or EFWR */
+#define SSCR1_EFWR              (1 << 14)       /* Enable FIFO Write/Read */
+
+#define SSSR_BCE                (1 << 23)       /* Bit Count Error */
+#define SSSR_CSS                (1 << 22)       /* Clock Synchronisation Status */
+#define SSSR_TUR                (1 << 21)       /* Transmit FIFO Under Run */
+#define SSSR_EOC                (1 << 20)       /* End Of Chain */
+#define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
+#define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
+
+#define SSPSP_DMYSTOP(x)        (x << 23)       /* Dummy Stop */
+#define SSPSP_SFRMWDTH(x)       (x << 16)       /* Serial Frame Width */
+#define SSPSP_SFRMDLY(x)        (x << 9)        /* Serial Frame Delay */
+#define SSPSP_DMYSTRT(x)        (x << 7)        /* Dummy Start */
+#define SSPSP_STRTDLY(x)        (x << 4)        /* Start Delay */
+#define SSPSP_ETDS                      (1 << 3)        /* End of Transfer data State */
+#define SSPSP_SFRMP                     (1 << 2)        /* Serial Frame Polarity */
+#define SSPSP_SCMODE(x)         (x << 0)        /* Serial Bit Rate Clock Mode */
+
+
+#define SSCR0_P1        __REG(0x41000000)  /* SSP Port 1 Control Register 0 */
+#define SSCR1_P1        __REG(0x41000004)  /* SSP Port 1 Control Register 1 */
+#define SSSR_P1         __REG(0x41000008)  /* SSP Port 1 Status Register */
+#define SSITR_P1        __REG(0x4100000C)  /* SSP Port 1 Interrupt Test Register */
+#define SSDR_P1         __REG(0x41000010)  /* (Write / Read) SSP Port 1 Data Write Register/SSP Data Read Register */
+
+/* Support existing PXA25x drivers */
+#define SSCR0           SSCR0_P1  /* SSP Control Register 0 */
+#define SSCR1           SSCR1_P1  /* SSP Control Register 1 */
+#define SSSR            SSSR_P1   /* SSP Status Register */
+#define SSITR           SSITR_P1  /* SSP Interrupt Test Register */
+#define SSDR            SSDR_P1   /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
+
+/* PXA27x ports */
+#if defined (CONFIG_PXA27x)
+#define SSTO_P1         __REG(0x41000028)  /* SSP Port 1 Time Out Register */
+#define SSPSP_P1        __REG(0x4100002C)  /* SSP Port 1 Programmable Serial Protocol */
+#define SSCR0_P2        __REG(0x41700000)  /* SSP Port 2 Control Register 0 */
+#define SSCR1_P2        __REG(0x41700004)  /* SSP Port 2 Control Register 1 */
+#define SSSR_P2         __REG(0x41700008)  /* SSP Port 2 Status Register */
+#define SSITR_P2        __REG(0x4170000C)  /* SSP Port 2 Interrupt Test Register */
+#define SSDR_P2         __REG(0x41700010)  /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
+#define SSTO_P2         __REG(0x41700028)  /* SSP Port 2 Time Out Register */
+#define SSPSP_P2        __REG(0x4170002C)  /* SSP Port 2 Programmable Serial Protocol */
+#define SSCR0_P3        __REG(0x41900000)  /* SSP Port 3 Control Register 0 */
+#define SSCR1_P3        __REG(0x41900004)  /* SSP Port 3 Control Register 1 */
+#define SSSR_P3         __REG(0x41900008)  /* SSP Port 3 Status Register */
+#define SSITR_P3        __REG(0x4190000C)  /* SSP Port 3 Interrupt Test Register */
+#define SSDR_P3         __REG(0x41900010)  /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
+#define SSTO_P3         __REG(0x41900028)  /* SSP Port 3 Time Out Register */
+#define SSPSP_P3        __REG(0x4190002C)  /* SSP Port 3 Programmable Serial Protocol */
+#else /* PXA255 (only port 2) and PXA26x ports*/
+#define SSTO_P1         __REG(0x41000028)  /* SSP Port 1 Time Out Register */
+#define SSPSP_P1        __REG(0x4100002C)  /* SSP Port 1 Programmable Serial Protocol */
+#define SSCR0_P2        __REG(0x41400000)  /* SSP Port 2 Control Register 0 */
+#define SSCR1_P2        __REG(0x41400004)  /* SSP Port 2 Control Register 1 */
+#define SSSR_P2         __REG(0x41400008)  /* SSP Port 2 Status Register */
+#define SSITR_P2        __REG(0x4140000C)  /* SSP Port 2 Interrupt Test Register */
+#define SSDR_P2         __REG(0x41400010)  /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
+#define SSTO_P2         __REG(0x41400028)  /* SSP Port 2 Time Out Register */
+#define SSPSP_P2        __REG(0x4140002C)  /* SSP Port 2 Programmable Serial Protocol */
+#define SSCR0_P3        __REG(0x41500000)  /* SSP Port 3 Control Register 0 */
+#define SSCR1_P3        __REG(0x41500004)  /* SSP Port 3 Control Register 1 */
+#define SSSR_P3         __REG(0x41500008)  /* SSP Port 3 Status Register */
+#define SSITR_P3        __REG(0x4150000C)  /* SSP Port 3 Interrupt Test Register */
+#define SSDR_P3         __REG(0x41500010)  /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
+#define SSTO_P3         __REG(0x41500028)  /* SSP Port 3 Time Out Register */
+#define SSPSP_P3        __REG(0x4150002C)  /* SSP Port 3 Programmable Serial Protocol */
+#endif
+
+#define SSCR0_P(x) (*(((x) == 1) ? &SSCR0_P1 : ((x) == 2) ? &SSCR0_P2 : ((x) == 3) ? &SSCR0_P3 : NULL))
+#define SSCR1_P(x) (*(((x) == 1) ? &SSCR1_P1 : ((x) == 2) ? &SSCR1_P2 : ((x) == 3) ? &SSCR1_P3 : NULL))
+#define SSSR_P(x) (*(((x) == 1) ? &SSSR_P1 : ((x) == 2) ? &SSSR_P2 : ((x) == 3) ? &SSSR_P3 : NULL))
+#define SSITR_P(x) (*(((x) == 1) ? &SSITR_P1 : ((x) == 2) ? &SSITR_P2 : ((x) == 3) ? &SSITR_P3 : NULL))
+#define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
+#define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
+#define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
+
+/*
+ * MultiMediaCard (MMC) controller
+ */
+
+#define MMC_STRPCL      __REG(0x41100000)  /* Control to start and stop MMC clock */
+#define MMC_STAT        __REG(0x41100004)  /* MMC Status Register (read only) */
+#define MMC_CLKRT       __REG(0x41100008)  /* MMC clock rate */
+#define MMC_SPI         __REG(0x4110000c)  /* SPI mode control bits */
+#define MMC_CMDAT       __REG(0x41100010)  /* Command/response/data sequence control */
+#define MMC_RESTO       __REG(0x41100014)  /* Expected response time out */
+#define MMC_RDTO        __REG(0x41100018)  /* Expected data read time out */
+#define MMC_BLKLEN      __REG(0x4110001c)  /* Block length of data transaction */
+#define MMC_NOB         __REG(0x41100020)  /* Number of blocks, for block mode */
+#define MMC_PRTBUF      __REG(0x41100024)  /* Partial MMC_TXFIFO FIFO written */
+#define MMC_I_MASK      __REG(0x41100028)  /* Interrupt Mask */
+#define MMC_I_REG       __REG(0x4110002c)  /* Interrupt Register (read only) */
+#define MMC_CMD         __REG(0x41100030)  /* Index of current command */
+#define MMC_ARGH        __REG(0x41100034)  /* MSW part of the current command argument */
+#define MMC_ARGL        __REG(0x41100038)  /* LSW part of the current command argument */
+#define MMC_RES         __REG(0x4110003c)  /* Response FIFO (read only) */
+#define MMC_RXFIFO      __REG(0x41100040)  /* Receive FIFO (read only) */
+#define MMC_TXFIFO      __REG(0x41100044)  /* Transmit FIFO (write only) */
+
+
+/*
+ * Core Clock
+ */
+
+#define CCCR            __REG(0x41300000)  /* Core Clock Configuration Register */
+#define CKEN            __REG(0x41300004)  /* Clock Enable Register */
+#define OSCC            __REG(0x41300008)  /* Oscillator Configuration Register */
+#define CCSR            __REG(0x4130000C)  /* Core Clock Status Register */
+
+#define CCCR_N_MASK     0x0380          /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
+#define CCCR_M_MASK     0x0060          /* Memory Frequency to Run Mode Frequency Multiplier */
+#define CCCR_L_MASK     0x001f          /* Crystal Frequency to Memory Frequency Multiplier */
+
+#define CKEN24_CAMERA   (1 << 24)       /* Camera Interface Clock Enable */
+#define CKEN23_SSP1     (1 << 23)       /* SSP1 Unit Clock Enable */
+#define CKEN22_MEMC     (1 << 22)       /* Memory Controller Clock Enable */
+#define CKEN21_MEMSTK   (1 << 21)       /* Memory Stick Host Controller */
+#define CKEN20_IM       (1 << 20)       /* Internal Memory Clock Enable */
+#define CKEN19_KEYPAD   (1 << 19)       /* Keypad Interface Clock Enable */
+#define CKEN18_USIM     (1 << 18)       /* USIM Unit Clock Enable */
+#define CKEN17_MSL      (1 << 17)       /* MSL Unit Clock Enable */
+#define CKEN16_LCD      (1 << 16)       /* LCD Unit Clock Enable */
+#define CKEN15_PWRI2C   (1 << 15)       /* PWR I2C Unit Clock Enable */
+#define CKEN14_I2C      (1 << 14)       /* I2C Unit Clock Enable */
+#define CKEN13_FICP     (1 << 13)       /* FICP Unit Clock Enable */
+#define CKEN12_MMC      (1 << 12)       /* MMC Unit Clock Enable */
+#define CKEN11_USB      (1 << 11)       /* USB Unit Clock Enable */
+#define CKEN10_ASSP     (1 << 10)       /* ASSP (SSP3) Clock Enable */
+#define CKEN10_USBHOST  (1 << 10)       /* USB Host Unit Clock Enable */
+#define CKEN9_OSTIMER   (1 << 9)        /* OS Timer Unit Clock Enable */
+#define CKEN9_NSSP      (1 << 9)        /* NSSP (SSP2) Clock Enable */
+#define CKEN8_I2S       (1 << 8)        /* I2S Unit Clock Enable */
+#define CKEN7_BTUART    (1 << 7)        /* BTUART Unit Clock Enable */
+#define CKEN6_FFUART    (1 << 6)        /* FFUART Unit Clock Enable */
+#define CKEN5_STUART    (1 << 5)        /* STUART Unit Clock Enable */
+#define CKEN4_SSP3      (1 << 4)        /* SSP3 Unit Clock Enable */
+#define CKEN3_SSP       (1 << 3)        /* SSP Unit Clock Enable */
+#define CKEN3_SSP2      (1 << 3)        /* SSP2 Unit Clock Enable */
+#define CKEN2_AC97      (1 << 2)        /* AC97 Unit Clock Enable */
+#define CKEN1_PWM1      (1 << 1)        /* PWM1 Clock Enable */
+#define CKEN0_PWM0      (1 << 0)        /* PWM0 Clock Enable */
+
+#define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
+#define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
+
+
+/*
+ * LCD
+ */
+
+#define LCCR0           __REG(0x44000000)  /* LCD Controller Control Register 0 */
+#define LCCR1           __REG(0x44000004)  /* LCD Controller Control Register 1 */
+#define LCCR2           __REG(0x44000008)  /* LCD Controller Control Register 2 */
+#define LCCR3           __REG(0x4400000C)  /* LCD Controller Control Register 3 */
+#define DFBR0           __REG(0x44000020)  /* DMA Channel 0 Frame Branch Register */
+#define DFBR1           __REG(0x44000024)  /* DMA Channel 1 Frame Branch Register */
+#define LCSR            __REG(0x44000038)  /* LCD Controller Status Register */
+#define LIIDR           __REG(0x4400003C)  /* LCD Controller Interrupt ID Register */
+#define TMEDRGBR        __REG(0x44000040)  /* TMED RGB Seed Register */
+#define TMEDCR          __REG(0x44000044)  /* TMED Control Register */
+
+#define LCCR3_1BPP (0 << 24)
+#define LCCR3_2BPP (1 << 24)
+#define LCCR3_4BPP (2 << 24)
+#define LCCR3_8BPP (3 << 24)
+#define LCCR3_16BPP (4 << 24)
+
+#define FDADR0          __REG(0x44000200)  /* DMA Channel 0 Frame Descriptor Address Register */
+#define FSADR0          __REG(0x44000204)  /* DMA Channel 0 Frame Source Address Register */
+#define FIDR0           __REG(0x44000208)  /* DMA Channel 0 Frame ID Register */
+#define LDCMD0          __REG(0x4400020C)  /* DMA Channel 0 Command Register */
+#define FDADR1          __REG(0x44000210)  /* DMA Channel 1 Frame Descriptor Address Register */
+#define FSADR1          __REG(0x44000214)  /* DMA Channel 1 Frame Source Address Register */
+#define FIDR1           __REG(0x44000218)  /* DMA Channel 1 Frame ID Register */
+#define LDCMD1          __REG(0x4400021C)  /* DMA Channel 1 Command Register */
+
+#define LCCR0_ENB       (1 << 0)        /* LCD Controller enable */
+#define LCCR0_CMS       (1 << 1)        /* Color/Monochrome Display Select */
+#define LCCR0_Color     (LCCR0_CMS*0)   /*  Color display                  */
+#define LCCR0_Mono      (LCCR0_CMS*1)   /*  Monochrome display             */
+#define LCCR0_SDS       (1 << 2)        /* Single/Dual Panel Display       */
+                                        /* Select                          */
+#define LCCR0_Sngl      (LCCR0_SDS*0)   /*  Single panel display           */
+#define LCCR0_Dual      (LCCR0_SDS*1)   /*  Dual panel display             */
+
+#define LCCR0_LDM       (1 << 3)        /* LCD Disable Done Mask */
+#define LCCR0_SFM       (1 << 4)        /* Start of frame mask */
+#define LCCR0_IUM       (1 << 5)        /* Input FIFO underrun mask */
+#define LCCR0_EFM       (1 << 6)        /* End of Frame mask */
+#define LCCR0_PAS       (1 << 7)        /* Passive/Active display Select   */
+#define LCCR0_Pas       (LCCR0_PAS*0)   /*  Passive display (STN)          */
+#define LCCR0_Act       (LCCR0_PAS*1)   /*  Active display (TFT)           */
+#define LCCR0_DPD       (1 << 9)        /* Double Pixel Data (monochrome   */
+                                        /* display mode)                   */
+#define LCCR0_4PixMono  (LCCR0_DPD*0)   /*  4-Pixel/clock Monochrome       */
+                                        /*  display                        */
+#define LCCR0_8PixMono  (LCCR0_DPD*1)   /*  8-Pixel/clock Monochrome       */
+                                        /*  display                        */
+#define LCCR0_DIS       (1 << 10)       /* LCD Disable */
+#define LCCR0_QDM       (1 << 11)       /* LCD Quick Disable mask */
+#define LCCR0_PDD       (0xff << 12)    /* Palette DMA request delay */
+#define LCCR0_PDD_S     12
+#define LCCR0_BM        (1 << 20)       /* Branch mask */
+#define LCCR0_OUM       (1 << 21)       /* Output FIFO underrun mask */
+
+#define LCCR1_PPL       Fld (10, 0)      /* Pixels Per Line - 1 */
+#define LCCR1_DisWdth(Pixel)            /* Display Width [1..800 pix.]  */ \
+                        (((Pixel) - 1) << FShft (LCCR1_PPL))
+
+#define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization     */
+#define LCCR1_HorSnchWdth(Tpix)         /* Horizontal Synchronization     */ \
+                                        /* pulse Width [1..64 Tpix]       */ \
+                        (((Tpix) - 1) << FShft (LCCR1_HSW))
+
+#define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait    */
+                                        /* count - 1 [Tpix]                */
+#define LCCR1_EndLnDel(Tpix)            /*  End-of-Line Delay              */ \
+                                        /*  [1..256 Tpix]                  */ \
+                        (((Tpix) - 1) << FShft (LCCR1_ELW))
+
+#define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock   */
+                                        /* Wait count - 1 [Tpix]           */
+#define LCCR1_BegLnDel(Tpix)            /*  Beginning-of-Line Delay        */ \
+                                        /*  [1..256 Tpix]                  */ \
+                        (((Tpix) - 1) << FShft (LCCR1_BLW))
+
+
+#define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1              */
+#define LCCR2_DisHght(Line)             /*  Display Height [1..1024 lines] */ \
+                        (((Line) - 1) << FShft (LCCR2_LPP))
+
+#define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse  */
+                                        /* Width - 1 [Tln] (L_FCLK)        */
+#define LCCR2_VrtSnchWdth(Tln)          /*  Vertical Synchronization pulse */ \
+                                        /*  Width [1..64 Tln]              */ \
+                        (((Tln) - 1) << FShft (LCCR2_VSW))
+
+#define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait    */
+                                        /* count [Tln]                     */
+#define LCCR2_EndFrmDel(Tln)            /*  End-of-Frame Delay             */ \
+                                        /*  [0..255 Tln]                   */ \
+                        ((Tln) << FShft (LCCR2_EFW))
+
+#define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock   */
+                                        /* Wait count [Tln]                */
+#define LCCR2_BegFrmDel(Tln)            /*  Beginning-of-Frame Delay       */ \
+                                        /*  [0..255 Tln]                   */ \
+                        ((Tln) << FShft (LCCR2_BFW))
+
+#if 0
+#define LCCR3_PCD       (0xff)          /* Pixel clock divisor */
+#define LCCR3_ACB       (0xff << 8)     /* AC Bias pin frequency */
+#define LCCR3_ACB_S     8
+#endif
+
+#define LCCR3_API       (0xf << 16)     /* AC Bias pin trasitions per interrupt */
+#define LCCR3_API_S     16
+#define LCCR3_VSP       (1 << 20)       /* vertical sync polarity */
+#define LCCR3_HSP       (1 << 21)       /* horizontal sync polarity */
+#define LCCR3_PCP       (1 << 22)       /* Pixel Clock Polarity (L_PCLK)   */
+#define LCCR3_PixRsEdg  (LCCR3_PCP*0)   /*  Pixel clock Rising-Edge        */
+#define LCCR3_PixFlEdg  (LCCR3_PCP*1)   /*  Pixel clock Falling-Edge       */
+
+#define LCCR3_OEP       (1 << 23)       /* Output Enable Polarity (L_BIAS, */
+                                        /* active display mode)            */
+#define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High      */
+#define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low       */
+
+#if 0
+#define LCCR3_BPP       (7 << 24)       /* bits per pixel */
+#define LCCR3_BPP_S     24
+#endif
+#define LCCR3_DPC       (1 << 27)       /* double pixel clock mode */
+
+
+#define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor */
+#define LCCR3_PixClkDiv(Div)            /* Pixel Clock Divisor */ \
+                        (((Div) << FShft (LCCR3_PCD)))
+
+
+#define LCCR3_BPP       Fld (3, 24)     /* Bit Per Pixel */
+#define LCCR3_Bpp(Bpp)                  /* Bit Per Pixel */ \
+                        (((Bpp) << FShft (LCCR3_BPP)))
+
+#define LCCR3_ACB       Fld (8, 8)      /* AC Bias */
+#define LCCR3_Acb(Acb)                  /* BAC Bias */ \
+                        (((Acb) << FShft (LCCR3_ACB)))
+
+#define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  Horizontal Synchronization     */
+                                        /*  pulse active High              */
+#define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  Horizontal Synchronization     */
+
+#define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  Vertical Synchronization pulse */
+                                        /*  active High                    */
+#define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  Vertical Synchronization pulse */
+                                        /*  active Low                     */
+
+#define LCSR_LDD        (1 << 0)        /* LCD Disable Done */
+#define LCSR_SOF        (1 << 1)        /* Start of frame */
+#define LCSR_BER        (1 << 2)        /* Bus error */
+#define LCSR_ABC        (1 << 3)        /* AC Bias count */
+#define LCSR_IUL        (1 << 4)        /* input FIFO underrun Lower panel */
+#define LCSR_IUU        (1 << 5)        /* input FIFO underrun Upper panel */
+#define LCSR_OU         (1 << 6)        /* output FIFO underrun */
+#define LCSR_QD         (1 << 7)        /* quick disable */
+#define LCSR_EOF        (1 << 8)        /* end of frame */
+#define LCSR_BS         (1 << 9)        /* branch status */
+#define LCSR_SINT       (1 << 10)       /* subsequent interrupt */
+
+#define LDCMD_PAL       (1 << 26)       /* instructs DMA to load palette buffer */
+
+#define LCSR_LDD        (1 << 0)        /* LCD Disable Done */
+#define LCSR_SOF        (1 << 1)        /* Start of frame */
+#define LCSR_BER        (1 << 2)        /* Bus error */
+#define LCSR_ABC        (1 << 3)        /* AC Bias count */
+#define LCSR_IUL        (1 << 4)        /* input FIFO underrun Lower panel */
+#define LCSR_IUU        (1 << 5)        /* input FIFO underrun Upper panel */
+#define LCSR_OU         (1 << 6)        /* output FIFO underrun */
+#define LCSR_QD         (1 << 7)        /* quick disable */
+#define LCSR_EOF        (1 << 8)        /* end of frame */
+#define LCSR_BS         (1 << 9)        /* branch status */
+#define LCSR_SINT       (1 << 10)       /* subsequent interrupt */
+
+#define LDCMD_PAL       (1 << 26)       /* instructs DMA to load palette buffer */
+
+/*
+ * Memory controller
+ */
+
+#define MDCNFG          __REG(0x48000000)  /* SDRAM Configuration Register 0 */
+#define MDREFR          __REG(0x48000004)  /* SDRAM Refresh Control Register */
+#define MSC0            __REG(0x48000008)  /* Static Memory Control Register 0 */
+#define MSC1            __REG(0x4800000C)  /* Static Memory Control Register 1 */
+#define MSC2            __REG(0x48000010)  /* Static Memory Control Register 2 */
+#define MECR            __REG(0x48000014)  /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
+#define SXLCR           __REG(0x48000018)  /* LCR value to be written to SDRAM-Timing Synchronous Flash */
+#define SXCNFG          __REG(0x4800001C)  /* Synchronous Static Memory Control Register */
+#define SXMRS           __REG(0x48000024)  /* MRS value to be written to Synchronous Flash or SMROM */
+#define MCMEM0          __REG(0x48000028)  /* Card interface Common Memory Space Socket 0 Timing */
+#define MCMEM1          __REG(0x4800002C)  /* Card interface Common Memory Space Socket 1 Timing */
+#define MCATT0          __REG(0x48000030)  /* Card interface Attribute Space Socket 0 Timing Configuration */
+#define MCATT1          __REG(0x48000034)  /* Card interface Attribute Space Socket 1 Timing Configuration */
+#define MCIO0           __REG(0x48000038)  /* Card interface I/O Space Socket 0 Timing Configuration */
+#define MCIO1           __REG(0x4800003C)  /* Card interface I/O Space Socket 1 Timing Configuration */
+#define MDMRS           __REG(0x48000040)  /* MRS value to be written to SDRAM */
+#define BOOT_DEF        __REG(0x48000044)  /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
+
+/*
+ * More handy macros for PCMCIA
+ *
+ * Arg is socket number
+ */
+#define MCMEM(s)        __REG2(0x48000028, (s)<<2 )  /* Card interface Common Memory Space Socket s Timing */
+#define MCATT(s)        __REG2(0x48000030, (s)<<2 )  /* Card interface Attribute Space Socket s Timing Configuration */
+#define MCIO(s)         __REG2(0x48000038, (s)<<2 )  /* Card interface I/O Space Socket s Timing Configuration */
+
+/* MECR register defines */
+#define MECR_NOS        (1 << 0)        /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
+#define MECR_CIT        (1 << 1)        /* Card Is There: 0 -> no card, 1 -> card inserted */
+
+#define MDREFR_K2FREE   (1 << 25)       /* SDRAM Free-Running Control */
+#define MDREFR_K1FREE   (1 << 24)       /* SDRAM Free-Running Control */
+#define MDREFR_K0FREE   (1 << 23)       /* SDRAM Free-Running Control */
+#define MDREFR_SLFRSH   (1 << 22)       /* SDRAM Self-Refresh Control/Status */
+#define MDREFR_APD      (1 << 20)       /* SDRAM/SSRAM Auto-Power-Down Enable */
+#define MDREFR_K2DB2    (1 << 19)       /* SDCLK2 Divide by 2 Control/Status */
+#define MDREFR_K2RUN    (1 << 18)       /* SDCLK2 Run Control/Status */
+#define MDREFR_K1DB2    (1 << 17)       /* SDCLK1 Divide by 2 Control/Status */
+#define MDREFR_K1RUN    (1 << 16)       /* SDCLK1 Run Control/Status */
+#define MDREFR_E1PIN    (1 << 15)       /* SDCKE1 Level Control/Status */
+#define MDREFR_K0DB2    (1 << 14)       /* SDCLK0 Divide by 2 Control/Status */
+#define MDREFR_K0RUN    (1 << 13)       /* SDCLK0 Run Control/Status */
+#define MDREFR_E0PIN    (1 << 12)       /* SDCKE0 Level Control/Status */
+
+
+#ifdef CONFIG_PXA27x
+
+/*
+ * Keypad
+ */
+#define KPC             __REG(0x41500000) /* Keypad Interface Control register */
+#define KPDK            __REG(0x41500008) /* Keypad Interface Direct Key register */
+#define KPREC           __REG(0x41500010) /* Keypad Interface Rotary Encoder register */
+#define KPMK            __REG(0x41500018) /* Keypad Interface Matrix Key register */
+#define KPAS            __REG(0x41500020) /* Keypad Interface Automatic Scan register */
+#define KPASMKP0        __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
+#define KPASMKP1        __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
+#define KPASMKP2        __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
+#define KPASMKP3        __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
+#define KPKDI           __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
+
+#define KPC_AS          (0x1 << 30)  /* Automatic Scan bit */
+#define KPC_ASACT       (0x1 << 29)  /* Automatic Scan on Activity */
+#define KPC_MI          (0x1 << 22)  /* Matrix interrupt bit */
+#define KPC_IMKP        (0x1 << 21)  /* Ignore Multiple Key Press */
+#define KPC_MS7         (0x1 << 20)  /* Matrix scan line 7 */
+#define KPC_MS6         (0x1 << 19)  /* Matrix scan line 6 */
+#define KPC_MS5         (0x1 << 18)  /* Matrix scan line 5 */
+#define KPC_MS4         (0x1 << 17)  /* Matrix scan line 4 */
+#define KPC_MS3         (0x1 << 16)  /* Matrix scan line 3 */
+#define KPC_MS2         (0x1 << 15)  /* Matrix scan line 2 */
+#define KPC_MS1         (0x1 << 14)  /* Matrix scan line 1 */
+#define KPC_MS0         (0x1 << 13)  /* Matrix scan line 0 */
+#define KPC_MS_ALL      (KPC_MS0 | KPC_MS1 | KPC_MS2 | KPC_MS3 | KPC_MS4 | KPC_MS5 | KPC_MS6 | KPC_MS7)
+#define KPC_ME          (0x1 << 12)  /* Matrix Keypad Enable */
+#define KPC_MIE         (0x1 << 11)  /* Matrix Interrupt Enable */
+#define KPC_DK_DEB_SEL  (0x1 <<  9)  /* Direct Keypad Debounce Select */
+#define KPC_DI          (0x1 <<  5)  /* Direct key interrupt bit */
+#define KPC_RE_ZERO_DEB (0x1 <<  4)  /* Rotary Encoder Zero Debounce */
+#define KPC_REE1        (0x1 <<  3)  /* Rotary Encoder1 Enable */
+#define KPC_REE0        (0x1 <<  2)  /* Rotary Encoder0 Enable */
+#define KPC_DE          (0x1 <<  1)  /* Direct Keypad Enable */
+#define KPC_DIE         (0x1 <<  0)  /* Direct Keypad interrupt Enable */
+
+#define KPDK_DKP        (0x1 << 31)
+#define KPDK_DK7        (0x1 <<  7)
+#define KPDK_DK6        (0x1 <<  6)
+#define KPDK_DK5        (0x1 <<  5)
+#define KPDK_DK4        (0x1 <<  4)
+#define KPDK_DK3        (0x1 <<  3)
+#define KPDK_DK2        (0x1 <<  2)
+#define KPDK_DK1        (0x1 <<  1)
+#define KPDK_DK0        (0x1 <<  0)
+
+#define KPREC_OF1       (0x1 << 31)
+#define kPREC_UF1       (0x1 << 30)
+#define KPREC_OF0       (0x1 << 15)
+#define KPREC_UF0       (0x1 << 14)
+
+#define KPMK_MKP        (0x1 << 31)
+#define KPAS_SO         (0x1 << 31)
+#define KPASMKPx_SO     (0x1 << 31)
+
+/*
+ * UHC: USB Host Controller (OHCI-like) register definitions
+ */
+#define UHC_BASE_PHYS   (0x4C000000)
+#define UHCREV          __REG(0x4C000000) /* UHC HCI Spec Revision */
+#define UHCHCON         __REG(0x4C000004) /* UHC Host Control Register */
+#define UHCCOMS         __REG(0x4C000008) /* UHC Command Status Register */
+#define UHCINTS         __REG(0x4C00000C) /* UHC Interrupt Status Register */
+#define UHCINTE         __REG(0x4C000010) /* UHC Interrupt Enable */
+#define UHCINTD         __REG(0x4C000014) /* UHC Interrupt Disable */
+#define UHCHCCA         __REG(0x4C000018) /* UHC Host Controller Comm. Area */
+#define UHCPCED         __REG(0x4C00001C) /* UHC Period Current Endpt Descr */
+#define UHCCHED         __REG(0x4C000020) /* UHC Control Head Endpt Descr */
+#define UHCCCED         __REG(0x4C000024) /* UHC Control Current Endpt Descr */
+#define UHCBHED         __REG(0x4C000028) /* UHC Bulk Head Endpt Descr */
+#define UHCBCED         __REG(0x4C00002C) /* UHC Bulk Current Endpt Descr */
+#define UHCDHEAD        __REG(0x4C000030) /* UHC Done Head */
+#define UHCFMI          __REG(0x4C000034) /* UHC Frame Interval */
+#define UHCFMR          __REG(0x4C000038) /* UHC Frame Remaining */
+#define UHCFMN          __REG(0x4C00003C) /* UHC Frame Number */
+#define UHCPERS         __REG(0x4C000040) /* UHC Periodic Start */
+#define UHCLS           __REG(0x4C000044) /* UHC Low Speed Threshold */
+#define UHCRHDA         __REG(0x4C000048) /* UHC Root Hub Descriptor A */
+#define UHCRHDB         __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
+#define UHCRHS          __REG(0x4C000050) /* UHC Root Hub Status */
+#define UHCRHPS1        __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
+#define UHCRHPS2        __REG(0x4C000058) /* UHC Root Hub Port 2 Status */
+#define UHCRHPS3        __REG(0x4C00005C) /* UHC Root Hub Port 3 Status */
+
+#define UHCSTAT         __REG(0x4C000060) /* UHC Status Register */
+#define UHCSTAT_UPS3    (1 << 16)       /* USB Power Sense Port3 */
+#define UHCSTAT_SBMAI   (1 << 15)       /* System Bus Master Abort Interrupt*/
+#define UHCSTAT_SBTAI   (1 << 14)       /* System Bus Target Abort Interrupt*/
+#define UHCSTAT_UPRI    (1 << 13)       /* USB Port Resume Interrupt */
+#define UHCSTAT_UPS2    (1 << 12)       /* USB Power Sense Port 2 */
+#define UHCSTAT_UPS1    (1 << 11)       /* USB Power Sense Port 1 */
+#define UHCSTAT_HTA     (1 << 10)       /* HCI Target Abort */
+#define UHCSTAT_HBA     (1 << 8)        /* HCI Buffer Active */
+#define UHCSTAT_RWUE    (1 << 7)        /* HCI Remote Wake Up Event */
+
+#define UHCHR           __REG(0x4C000064) /* UHC Reset Register */
+#define UHCHR_SSEP3     (1 << 11)       /* Sleep Standby Enable for Port3 */
+#define UHCHR_SSEP2     (1 << 10)       /* Sleep Standby Enable for Port2 */
+#define UHCHR_SSEP1     (1 << 9)        /* Sleep Standby Enable for Port1 */
+#define UHCHR_PCPL      (1 << 7)        /* Power control polarity low */
+#define UHCHR_PSPL      (1 << 6)        /* Power sense polarity low */
+#define UHCHR_SSE       (1 << 5)        /* Sleep Standby Enable */
+#define UHCHR_UIT       (1 << 4)        /* USB Interrupt Test */
+#define UHCHR_SSDC      (1 << 3)        /* Simulation Scale Down Clock */
+#define UHCHR_CGR       (1 << 2)        /* Clock Generation Reset */
+#define UHCHR_FHR       (1 << 1)        /* Force Host Controller Reset */
+#define UHCHR_FSBIR     (1 << 0)        /* Force System Bus Iface Reset */
+
+#define UHCHIE          __REG(0x4C000068) /* UHC Interrupt Enable Register*/
+#define UHCHIE_UPS3IE   (1 << 14)       /* Power Sense Port3 IntEn */
+#define UHCHIE_UPRIE    (1 << 13)       /* Port Resume IntEn */
+#define UHCHIE_UPS2IE   (1 << 12)       /* Power Sense Port2 IntEn */
+#define UHCHIE_UPS1IE   (1 << 11)       /* Power Sense Port1 IntEn */
+#define UHCHIE_TAIE     (1 << 10)       /* HCI Interface Transfer Abort
+                                           Interrupt Enable*/
+#define UHCHIE_HBAIE    (1 << 8)        /* HCI Buffer Active IntEn */
+#define UHCHIE_RWIE     (1 << 7)        /* Remote Wake-up IntEn */
+
+#define UHCHIT          __REG(0x4C00006C) /* UHC Interrupt Test register */
+
+/* Camera Interface */
+#define CICR0           __REG(0x50000000)
+#define CICR1           __REG(0x50000004)
+#define CICR2           __REG(0x50000008)
+#define CICR3           __REG(0x5000000C)
+#define CICR4           __REG(0x50000010)
+#define CISR            __REG(0x50000014)
+#define CIFR            __REG(0x50000018)
+#define CITOR           __REG(0x5000001C)
+#define CIBR0           __REG(0x50000028)
+#define CIBR1           __REG(0x50000030)
+#define CIBR2           __REG(0x50000038)
+
+#define CICR0_DMAEN     (1 << 31)       /* DMA request enable */
+#define CICR0_PAR_EN    (1 << 30)       /* Parity enable */
+#define CICR0_SL_CAP_EN (1 << 29)       /* Capture enable for slave mode */
+#define CICR0_ENB       (1 << 28)       /* Camera interface enable */
+#define CICR0_DIS       (1 << 27)       /* Camera interface disable */
+#define CICR0_SIM       (0x7 << 24)     /* Sensor interface mode mask */
+#define CICR0_TOM       (1 << 9)        /* Time-out mask */
+#define CICR0_RDAVM     (1 << 8)        /* Receive-data-available mask */
+#define CICR0_FEM       (1 << 7)        /* FIFO-empty mask */
+#define CICR0_EOLM      (1 << 6)        /* End-of-line mask */
+#define CICR0_PERRM     (1 << 5)        /* Parity-error mask */
+#define CICR0_QDM       (1 << 4)        /* Quick-disable mask */
+#define CICR0_CDM       (1 << 3)        /* Disable-done mask */
+#define CICR0_SOFM      (1 << 2)        /* Start-of-frame mask */
+#define CICR0_EOFM      (1 << 1)        /* End-of-frame mask */
+#define CICR0_FOM       (1 << 0)        /* FIFO-overrun mask */
+
+#define CICR1_TBIT      (1 << 31)       /* Transparency bit */
+#define CICR1_RGBT_CONV (0x3 << 30)     /* RGBT conversion mask */
+#define CICR1_PPL       (0x3f << 15)    /* Pixels per line mask */
+#define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
+#define CICR1_RGB_F     (1 << 11)       /* RGB format */
+#define CICR1_YCBCR_F   (1 << 10)       /* YCbCr format */
+#define CICR1_RGB_BPP   (0x7 << 7)      /* RGB bis per pixel mask */
+#define CICR1_RAW_BPP   (0x3 << 5)      /* Raw bis per pixel mask */
+#define CICR1_COLOR_SP  (0x3 << 3)      /* Color space mask */
+#define CICR1_DW        (0x7 << 0)      /* Data width mask */
+
+#define CICR2_BLW       (0xff << 24)    /* Beginning-of-line pixel clock
+                                           wait count mask */
+#define CICR2_ELW       (0xff << 16)    /* End-of-line pixel clock
+                                           wait count mask */
+#define CICR2_HSW       (0x3f << 10)    /* Horizontal sync pulse width mask */
+#define CICR2_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
+                                           wait count mask */
+#define CICR2_FSW       (0x7 << 0)      /* Frame stabilization
+                                           wait count mask */
+
+#define CICR3_BFW       (0xff << 24)    /* Beginning-of-frame line clock
+                                           wait count mask */
+#define CICR3_EFW       (0xff << 16)    /* End-of-frame line clock
+                                           wait count mask */
+#define CICR3_VSW       (0x3f << 10)    /* Vertical sync pulse width mask */
+#define CICR3_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
+                                           wait count mask */
+#define CICR3_LPF       (0x3ff << 0)    /* Lines per frame mask */
+
+#define CICR4_MCLK_DLY  (0x3 << 24)     /* MCLK Data Capture Delay mask */
+#define CICR4_PCLK_EN   (1 << 23)       /* Pixel clock enable */
+#define CICR4_PCP       (1 << 22)       /* Pixel clock polarity */
+#define CICR4_HSP       (1 << 21)       /* Horizontal sync polarity */
+#define CICR4_VSP       (1 << 20)       /* Vertical sync polarity */
+#define CICR4_MCLK_EN   (1 << 19)       /* MCLK enable */
+#define CICR4_FR_RATE   (0x7 << 8)      /* Frame rate mask */
+#define CICR4_DIV       (0xff << 0)     /* Clock divisor mask */
+
+#define CISR_FTO        (1 << 15)       /* FIFO time-out */
+#define CISR_RDAV_2     (1 << 14)       /* Channel 2 receive data available */
+#define CISR_RDAV_1     (1 << 13)       /* Channel 1 receive data available */
+#define CISR_RDAV_0     (1 << 12)       /* Channel 0 receive data available */
+#define CISR_FEMPTY_2   (1 << 11)       /* Channel 2 FIFO empty */
+#define CISR_FEMPTY_1   (1 << 10)       /* Channel 1 FIFO empty */
+#define CISR_FEMPTY_0   (1 << 9)        /* Channel 0 FIFO empty */
+#define CISR_EOL        (1 << 8)        /* End of line */
+#define CISR_PAR_ERR    (1 << 7)        /* Parity error */
+#define CISR_CQD        (1 << 6)        /* Camera interface quick disable */
+#define CISR_SOF        (1 << 5)        /* Start of frame */
+#define CISR_CDD        (1 << 4)        /* Camera interface disable done */
+#define CISR_EOF        (1 << 3)        /* End of frame */
+#define CISR_IFO_2      (1 << 2)        /* FIFO overrun for Channel 2 */
+#define CISR_IFO_1      (1 << 1)        /* FIFO overrun for Channel 1 */
+#define CISR_IFO_0      (1 << 0)        /* FIFO overrun for Channel 0 */
+
+#define CIFR_FLVL2      (0x7f << 23)    /* FIFO 2 level mask */
+#define CIFR_FLVL1      (0x7f << 16)    /* FIFO 1 level mask */
+#define CIFR_FLVL0      (0xff << 8)     /* FIFO 0 level mask */
+#define CIFR_THL_0      (0x3 << 4)      /* Threshold Level for Channel 0 FIFO */
+#define CIFR_RESET_F    (1 << 3)        /* Reset input FIFOs */
+#define CIFR_FEN2       (1 << 2)        /* FIFO enable for channel 2 */
+#define CIFR_FEN1       (1 << 1)        /* FIFO enable for channel 1 */
+#define CIFR_FEN0       (1 << 0)        /* FIFO enable for channel 0 */
+
+#define SRAM_SIZE               0x40000 /* 4x64K  */
+
+#define SRAM_MEM_PHYS           0x5C000000
+
+#define IMPMCR          __REG(0x58000000) /* IM Power Management Control Reg */
+#define IMPMSR          __REG(0x58000008) /* IM Power Management Status Reg */
+
+#define IMPMCR_PC3              (0x3 << 22) /* Bank 3 Power Control */
+#define IMPMCR_PC3_RUN_MODE     (0x0 << 22) /*   Run mode */
+#define IMPMCR_PC3_STANDBY_MODE (0x1 << 22) /*   Standby mode */
+#define IMPMCR_PC3_AUTO_MODE    (0x3 << 22) /*   Automatically controlled */
+
+#define IMPMCR_PC2              (0x3 << 20) /* Bank 2 Power Control */
+#define IMPMCR_PC2_RUN_MODE     (0x0 << 20) /*   Run mode */
+#define IMPMCR_PC2_STANDBY_MODE (0x1 << 20) /*   Standby mode */
+#define IMPMCR_PC2_AUTO_MODE    (0x3 << 20) /*   Automatically controlled */
+
+#define IMPMCR_PC1              (0x3 << 18) /* Bank 1 Power Control */
+#define IMPMCR_PC1_RUN_MODE     (0x0 << 18) /*   Run mode */
+#define IMPMCR_PC1_STANDBY_MODE (0x1 << 18) /*   Standby mode */
+#define IMPMCR_PC1_AUTO_MODE    (0x3 << 18) /*   Automatically controlled */
+
+#define IMPMCR_PC0              (0x3 << 16) /* Bank 0 Power Control */
+#define IMPMCR_PC0_RUN_MODE     (0x0 << 16) /*   Run mode */
+#define IMPMCR_PC0_STANDBY_MODE (0x1 << 16) /*   Standby mode */
+#define IMPMCR_PC0_AUTO_MODE    (0x3 << 16) /*   Automatically controlled */
+
+#define IMPMCR_AW3              (1 << 11) /* Bank 3 Automatic Wake-up enable */
+#define IMPMCR_AW2              (1 << 10) /* Bank 2 Automatic Wake-up enable */
+#define IMPMCR_AW1              (1 << 9)  /* Bank 1 Automatic Wake-up enable */
+#define IMPMCR_AW0              (1 << 8)  /* Bank 0 Automatic Wake-up enable */
+
+#define IMPMCR_DST              (0xFF << 0) /* Delay Standby Time, ms */
+
+#define IMPMSR_PS3              (0x3 << 6) /* Bank 3 Power Status: */
+#define IMPMSR_PS3_RUN_MODE     (0x0 << 6) /*    Run mode */
+#define IMPMSR_PS3_STANDBY_MODE (0x1 << 6) /*    Standby mode */
+
+#define IMPMSR_PS2              (0x3 << 4) /* Bank 2 Power Status: */
+#define IMPMSR_PS2_RUN_MODE     (0x0 << 4) /*    Run mode */
+#define IMPMSR_PS2_STANDBY_MODE (0x1 << 4) /*    Standby mode */
+
+#define IMPMSR_PS1              (0x3 << 2) /* Bank 1 Power Status: */
+#define IMPMSR_PS1_RUN_MODE     (0x0 << 2) /*    Run mode */
+#define IMPMSR_PS1_STANDBY_MODE (0x1 << 2) /*    Standby mode */
+
+#define IMPMSR_PS0              (0x3 << 0) /* Bank 0 Power Status: */
+#define IMPMSR_PS0_RUN_MODE     (0x0 << 0) /*    Run mode */
+#define IMPMSR_PS0_STANDBY_MODE (0x1 << 0) /*    Standby mode */
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
new file mode 100644
index 000000000000..27d71e9d413b
--- /dev/null
+++ b/include/asm-arm/arch-pxa/pxafb.h
@@ -0,0 +1,68 @@
+/*
+ *  linux/include/asm-arm/arch-pxa/pxafb.h
+ *
+ *  Support for the xscale frame buffer.
+ *
+ *  Author:     Jean-Frederic Clere
+ *  Created:    Sep 22, 2003
+ *  Copyright:  jfclere@sinix.net
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ */
+
+/*
+ * This structure describes the machine which we are running on.
+ * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
+ * of linux/drivers/video/pxafb.c
+ */
+struct pxafb_mach_info {
+        u_long          pixclock;
+
+        u_short         xres;
+        u_short         yres;
+
+        u_char          bpp;
+        u_char          hsync_len;
+        u_char          left_margin;
+        u_char          right_margin;
+
+        u_char          vsync_len;
+        u_char          upper_margin;
+        u_char          lower_margin;
+        u_char          sync;
+
+        u_int           cmap_greyscale:1,
+                        cmap_inverse:1,
+                        cmap_static:1,
+                        unused:29;
+
+        /* The following should be defined in LCCR0
+         *      LCCR0_Act or LCCR0_Pas          Active or Passive
+         *      LCCR0_Sngl or LCCR0_Dual        Single/Dual panel
+         *      LCCR0_Mono or LCCR0_Color       Mono/Color
+         *      LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
+         *      LCCR0_DMADel(Tcpu) (optional)   DMA request delay
+         *
+         * The following should not be defined in LCCR0:
+         *      LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
+         *      LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
+         */
+        u_int           lccr0;
+        /* The following should be defined in LCCR3
+         *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
+         *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
+         *      LCCR3_Acb(X)                    AB Bias pin frequency
+         *      LCCR3_DPC (optional)            Double Pixel Clock mode (untested)
+         *
+         * The following should not be defined in LCCR3
+         *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
+         */
+        u_int           lccr3;
+
+        void (*pxafb_backlight_power)(int);
+        void (*pxafb_lcd_power)(int);
+
+};
+void set_pxa_fb_info(struct pxafb_mach_info *hard_pxa_fb_info);
diff --git a/include/asm-arm/arch-pxa/ssp.h b/include/asm-arm/arch-pxa/ssp.h
new file mode 100644
index 000000000000..6ec67b018c09
--- /dev/null
+++ b/include/asm-arm/arch-pxa/ssp.h
@@ -0,0 +1,47 @@
+/*
+ *  ssp.h
+ *
+ *  Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This driver supports the following PXA CPU/SSP ports:-
+ *
+ *       PXA250     SSP
+ *       PXA255     SSP, NSSP
+ *       PXA26x     SSP, NSSP, ASSP
+ *       PXA27x     SSP1, SSP2, SSP3
+ */
+
+#ifndef SSP_H
+#define SSP_H
+
+struct ssp_state {
+        u32     cr0;
+        u32 cr1;
+        u32 to;
+        u32 psp;
+};
+
+struct ssp_dev {
+        u32 port;
+        u32 mode;
+        u32 flags;
+        u32 psp_flags;
+        u32 speed;
+};
+
+int ssp_write_word(struct ssp_dev *dev, u32 data);
+int ssp_read_word(struct ssp_dev *dev);
+void ssp_flush(struct ssp_dev *dev);
+void ssp_enable(struct ssp_dev *dev);
+void ssp_disable(struct ssp_dev *dev);
+void ssp_save_state(struct ssp_dev *dev, struct ssp_state *ssp);
+void ssp_restore_state(struct ssp_dev *dev, struct ssp_state *ssp);
+int ssp_init(struct ssp_dev *dev, u32 port);
+int ssp_config(struct ssp_dev *dev, u32 mode, u32 flags, u32 psp_flags, u32 speed);
+void ssp_exit(struct ssp_dev *dev);
+
+#endif
diff --git a/include/asm-arm/arch-pxa/system.h b/include/asm-arm/arch-pxa/system.h
new file mode 100644
index 000000000000..840a46bfbc54
--- /dev/null
+++ b/include/asm-arm/arch-pxa/system.h
@@ -0,0 +1,34 @@
+/*
+ * linux/include/asm-arm/arch-pxa/system.h
+ *
+ * Author:      Nicolas Pitre
+ * Created:     Jun 15, 2001
+ * Copyright:   MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "hardware.h"
+#include "pxa-regs.h"
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+
+static inline void arch_reset(char mode)
+{
+        if (mode == 's') {
+                /* Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                /* Initialize the watchdog and let it fire */
+                OWER = OWER_WME;
+                OSSR = OSSR_M3;
+                OSMR3 = OSCR + 368640;  /* ... in 100 ms */
+        }
+}
+
diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h
new file mode 100644
index 000000000000..aa125ec56a32
--- /dev/null
+++ b/include/asm-arm/arch-pxa/timex.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/arch-pxa/timex.h
+ *
+ * Author:      Nicolas Pitre
+ * Created:     Jun 15, 2001
+ * Copyright:   MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/config.h>
+
+#if defined(CONFIG_PXA25x)
+/* PXA250/210 timer base */
+#define CLOCK_TICK_RATE 3686400
+#elif defined(CONFIG_PXA27x)
+/* PXA27x timer base */
+#ifdef CONFIG_MACH_MAINSTONE
+#define CLOCK_TICK_RATE 3249600
+#else
+#define CLOCK_TICK_RATE 3250000
+#endif
+#endif
diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h
new file mode 100644
index 000000000000..30548a30c773
--- /dev/null
+++ b/include/asm-arm/arch-pxa/udc.h
@@ -0,0 +1,18 @@
+/*
+ * linux/include/asm-arm/arch-pxa/udc.h
+ *
+ * This supports machine-specific differences in how the PXA2xx
+ * USB Device Controller (UDC) is wired.
+ *
+ * It is set in linux/arch/arm/mach-pxa/<machine>.c and used in
+ * the probe routine of linux/drivers/usb/gadget/pxa2xx_udc.c
+ */
+struct pxa2xx_udc_mach_info {
+        int  (*udc_is_connected)(void);         /* do we see host? */
+        void (*udc_command)(int cmd);
+#define PXA2XX_UDC_CMD_CONNECT          0       /* let host see us */
+#define PXA2XX_UDC_CMD_DISCONNECT       1       /* so host won't see us */
+};
+
+extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
+
diff --git a/include/asm-arm/arch-pxa/uncompress.h b/include/asm-arm/arch-pxa/uncompress.h
new file mode 100644
index 000000000000..4428d3eb7432
--- /dev/null
+++ b/include/asm-arm/arch-pxa/uncompress.h
@@ -0,0 +1,42 @@
+/*
+ * linux/include/asm-arm/arch-pxa/uncompress.h
+ *
+ * Author:      Nicolas Pitre
+ * Copyright:   (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define FFUART          ((volatile unsigned long *)0x40100000)
+#define BTUART          ((volatile unsigned long *)0x40200000)
+#define STUART          ((volatile unsigned long *)0x40700000)
+
+#define UART            FFUART
+
+
+static __inline__ void putc(char c)
+{
+        while (!(UART[5] & 0x20));
+        UART[0] = c;
+}
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                putc(*s);
+                if (*s == '\n')
+                        putc('\r');
+                s++;
+        }
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pxa/vmalloc.h b/include/asm-arm/arch-pxa/vmalloc.h
new file mode 100644
index 000000000000..3381af6ddb0d
--- /dev/null
+++ b/include/asm-arm/arch-pxa/vmalloc.h
@@ -0,0 +1,22 @@
+/*
+ * linux/include/asm-arm/arch-pxa/vmalloc.h
+ *
+ * Author:      Nicolas Pitre
+ * Copyright:   (C) 2001 MontaVista Software Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-rpc/acornfb.h b/include/asm-arm/arch-rpc/acornfb.h
new file mode 100644
index 000000000000..ecb7733a0949
--- /dev/null
+++ b/include/asm-arm/arch-rpc/acornfb.h
@@ -0,0 +1,140 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/acornfb.h
+ *
+ *  Copyright (C) 1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  AcornFB architecture specific code
+ */
+
+#define acornfb_bandwidth(var) ((var)->pixclock * 8 / (var)->bits_per_pixel)
+
+static inline int
+acornfb_valid_pixrate(struct fb_var_screeninfo *var)
+{
+        u_long limit;
+
+        if (!var->pixclock)
+                return 0;
+
+        /*
+         * Limits below are taken from RISC OS bandwidthlimit file
+         */
+        if (current_par.using_vram) {
+                if (current_par.vram_half_sam == 2048)
+                        limit = 6578;
+                else
+                        limit = 13157;
+        } else {
+                limit = 26315;
+        }
+
+        return acornfb_bandwidth(var) >= limit;
+}
+
+/*
+ * Try to find the best PLL parameters for the pixel clock.
+ * This algorithm seems to give best predictable results,
+ * and produces the same values as detailed in the VIDC20
+ * data sheet.
+ */
+static inline u_int
+acornfb_vidc20_find_pll(u_int pixclk)
+{
+        u_int r, best_r = 2, best_v = 2;
+        int best_d = 0x7fffffff;
+
+        for (r = 2; r <= 32; r++) {
+                u_int rr, v, p;
+                int d;
+
+                rr = 41667 * r;
+
+                v = (rr + pixclk / 2) / pixclk;
+
+                if (v > 32 || v < 2)
+                        continue;
+
+                p = (rr + v / 2) / v;
+
+                d = pixclk - p;
+
+                if (d < 0)
+                        d = -d;
+
+                if (d < best_d) {
+                        best_d = d;
+                        best_v = v - 1;
+                        best_r = r - 1;
+                }
+
+                if (d == 0)
+                        break;
+        }
+
+        return best_v << 8 | best_r;
+}
+
+static inline void
+acornfb_vidc20_find_rates(struct vidc_timing *vidc,
+                          struct fb_var_screeninfo *var)
+{
+        u_int div;
+
+        /* Select pixel-clock divisor to keep PLL in range */
+        div = var->pixclock / 9090; /*9921*/
+
+        /* Limit divisor */
+        if (div == 0)
+                div = 1;
+        if (div > 8)
+                div = 8;
+
+        /* Encode divisor to VIDC20 setting */
+        switch (div) {
+        case 1: vidc->control |= VIDC20_CTRL_PIX_CK;  break;
+        case 2: vidc->control |= VIDC20_CTRL_PIX_CK2; break;
+        case 3: vidc->control |= VIDC20_CTRL_PIX_CK3; break;
+        case 4: vidc->control |= VIDC20_CTRL_PIX_CK4; break;
+        case 5: vidc->control |= VIDC20_CTRL_PIX_CK5; break;
+        case 6: vidc->control |= VIDC20_CTRL_PIX_CK6; break;
+        case 7: vidc->control |= VIDC20_CTRL_PIX_CK7; break;
+        case 8: vidc->control |= VIDC20_CTRL_PIX_CK8; break;
+        }
+
+        /*
+         * With VRAM, the FIFO can be set to the highest possible setting
+         * because there are no latency considerations for other memory
+         * accesses. However, in 64 bit bus mode the FIFO preload value
+         * must not be set to VIDC20_CTRL_FIFO_28 because this will let
+         * the FIFO overflow. See VIDC20 manual page 33 (6.0 Setting the
+         * FIFO preload value).
+         */
+        if (current_par.using_vram) {
+                if (current_par.vram_half_sam == 2048)
+                        vidc->control |= VIDC20_CTRL_FIFO_24;
+                else
+                        vidc->control |= VIDC20_CTRL_FIFO_28;
+        } else {
+                unsigned long bandwidth = acornfb_bandwidth(var);
+
+                /* Encode bandwidth as VIDC20 setting */
+                if (bandwidth > 33334)          /* < 30.0MB/s */
+                        vidc->control |= VIDC20_CTRL_FIFO_16;
+                else if (bandwidth > 26666)     /* < 37.5MB/s */
+                        vidc->control |= VIDC20_CTRL_FIFO_20;
+                else if (bandwidth > 22222)     /* < 45.0MB/s */
+                        vidc->control |= VIDC20_CTRL_FIFO_24;
+                else                            /* > 45.0MB/s */
+                        vidc->control |= VIDC20_CTRL_FIFO_28;
+        }
+
+        /* Find the PLL values */
+        vidc->pll_ctl = acornfb_vidc20_find_pll(var->pixclock / div);
+}
+
+#define acornfb_default_control()       (VIDC20_CTRL_PIX_VCLK)
+#define acornfb_default_econtrol()      (VIDC20_ECTL_DAC | VIDC20_ECTL_REG(3))
diff --git a/include/asm-arm/arch-rpc/debug-macro.S b/include/asm-arm/arch-rpc/debug-macro.S
new file mode 100644
index 000000000000..0711828164cd
--- /dev/null
+++ b/include/asm-arm/arch-rpc/debug-macro.S
@@ -0,0 +1,35 @@
+/* linux/include/asm-arm/arch-rpc/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mov     \rx, #0xe0000000
+                orr     \rx, \rx, #0x00010000
+                orr     \rx, \rx, #0x00000fe0
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldrb    \rd, [\rx, #0x14]
+                and     \rd, \rd, #0x60
+                teq     \rd, #0x60
+                bne     1001b
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldrb    \rd, [\rx, #0x18]
+                tst     \rd, #0x10
+                beq     1001b
+                .endm
diff --git a/include/asm-arm/arch-rpc/dma.h b/include/asm-arm/arch-rpc/dma.h
new file mode 100644
index 000000000000..d24a27e30b93
--- /dev/null
+++ b/include/asm-arm/arch-rpc/dma.h
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/dma.h
+ *
+ *  Copyright (C) 1997 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ * There should not be more than (0xd0000000 - 0xc0000000)
+ * bytes of RAM.
+ */
+#define MAX_DMA_ADDRESS         0xd0000000
+#define MAX_DMA_CHANNELS        8
+
+#define DMA_0                   0
+#define DMA_1                   1
+#define DMA_2                   2
+#define DMA_3                   3
+#define DMA_S0                  4
+#define DMA_S1                  5
+#define DMA_VIRTUAL_FLOPPY      6
+#define DMA_VIRTUAL_SOUND       7
+
+#define DMA_FLOPPY              DMA_VIRTUAL_FLOPPY
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/include/asm-arm/arch-rpc/entry-macro.S b/include/asm-arm/arch-rpc/entry-macro.S
new file mode 100644
index 000000000000..686f413f82d6
--- /dev/null
+++ b/include/asm-arm/arch-rpc/entry-macro.S
@@ -0,0 +1,3 @@
+
+#include <asm/hardware/entry-macro-iomd.S>
+
diff --git a/include/asm-arm/arch-rpc/hardware.h b/include/asm-arm/arch-rpc/hardware.h
new file mode 100644
index 000000000000..be9754a05c19
--- /dev/null
+++ b/include/asm-arm/arch-rpc/hardware.h
@@ -0,0 +1,86 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/hardware.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains the hardware definitions of the RiscPC series machines.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/arch/memory.h>
+
+#ifndef __ASSEMBLY__
+#define IOMEM(x) ((void __iomem *)(x))
+#else
+#define IOMEM(x) x
+#endif /* __ASSEMBLY__ */
+
+/*
+ * What hardware must be present
+ */
+#define HAS_IOMD
+#define HAS_VIDC20
+
+/* Hardware addresses of major areas.
+ *  *_START is the physical address
+ *  *_SIZE  is the size of the region
+ *  *_BASE  is the virtual address
+ */
+#define RAM_SIZE                0x10000000
+#define RAM_START               0x10000000
+
+#define EASI_SIZE               0x08000000      /* EASI I/O */
+#define EASI_START              0x08000000
+#define EASI_BASE               0xe5000000
+
+#define IO_START                0x03000000      /* I/O */
+#define IO_SIZE                 0x01000000
+#define IO_BASE                 IOMEM(0xe0000000)
+
+#define SCREEN_START            0x02000000      /* VRAM */
+#define SCREEN_END              0xdfc00000
+#define SCREEN_BASE             0xdf800000
+
+#define FLUSH_BASE              0xdf000000
+#define UNCACHEABLE_ADDR        0xdf010000
+
+/*
+ * IO Addresses
+ */
+#define VIDC_BASE               (void __iomem *)0xe0400000
+#define EXPMASK_BASE            0xe0360000
+#define IOMD_BASE               IOMEM(0xe0200000)
+#define IOC_BASE                IOMEM(0xe0200000)
+#define PCIO_BASE               IOMEM(0xe0010000)
+#define FLOPPYDMA_BASE          IOMEM(0xe002a000)
+
+#define FLUSH_BASE_PHYS         0x00000000      /* ROM */
+
+#define vidc_writel(val)        __raw_writel(val, VIDC_BASE)
+
+#define IO_EC_EASI_BASE         0x81400000
+#define IO_EC_IOC4_BASE         0x8009c000
+#define IO_EC_IOC_BASE          0x80090000
+#define IO_EC_MEMC8_BASE        0x8000ac00
+#define IO_EC_MEMC_BASE         0x80000000
+
+#define NETSLOT_BASE            0x0302b000
+#define NETSLOT_SIZE            0x00001000
+
+#define PODSLOT_IOC0_BASE       0x03240000
+#define PODSLOT_IOC4_BASE       0x03270000
+#define PODSLOT_IOC_SIZE        (1 << 14)
+#define PODSLOT_MEMC_BASE       0x03000000
+#define PODSLOT_MEMC_SIZE       (1 << 14)
+#define PODSLOT_EASI_BASE       0x08000000
+#define PODSLOT_EASI_SIZE       (1 << 24)
+
+#define EXPMASK_STATUS          (EXPMASK_BASE + 0x00)
+#define EXPMASK_ENABLE          (EXPMASK_BASE + 0x04)
+
+#endif
diff --git a/include/asm-arm/arch-rpc/io.h b/include/asm-arm/arch-rpc/io.h
new file mode 100644
index 000000000000..24453c405a87
--- /dev/null
+++ b/include/asm-arm/arch-rpc/io.h
@@ -0,0 +1,257 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/io.h
+ *
+ *  Copyright (C) 1997 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  06-Dec-1997 RMK     Created.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * GCC is totally crap at loading/storing data.  We try to persuade it
+ * to do the right thing by using these whereever possible instead of
+ * the above.
+ */
+#define __arch_base_getb(b,o)                   \
+ ({                                             \
+        unsigned int __v, __r = (b);            \
+        __asm__ __volatile__(                   \
+                "ldrb   %0, [%1, %2]"           \
+                : "=r" (__v)                    \
+                : "r" (__r), "Ir" (o));         \
+        __v;                                    \
+ })
+
+#define __arch_base_getl(b,o)                   \
+ ({                                             \
+        unsigned int __v, __r = (b);            \
+        __asm__ __volatile__(                   \
+                "ldr    %0, [%1, %2]"           \
+                : "=r" (__v)                    \
+                : "r" (__r), "Ir" (o));         \
+        __v;                                    \
+ })
+
+#define __arch_base_putb(v,b,o)                 \
+ ({                                             \
+        unsigned int __r = (b);                 \
+        __asm__ __volatile__(                   \
+                "strb   %0, [%1, %2]"           \
+                :                               \
+                : "r" (v), "r" (__r), "Ir" (o));\
+ })
+
+#define __arch_base_putl(v,b,o)                 \
+ ({                                             \
+        unsigned int __r = (b);                 \
+        __asm__ __volatile__(                   \
+                "str    %0, [%1, %2]"           \
+                :                               \
+                : "r" (v), "r" (__r), "Ir" (o));\
+ })
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
+ * and are translated to the start of IO.  Note that all addresses are
+ * shifted left!
+ */
+#define __PORT_PCIO(x)  (!((x) & 0x80000000))
+
+/*
+ * Dynamic IO functions.
+ */
+static inline void __outb (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "strb   %1, [%0, %2, lsl #2]    @ outb"
+        : "=&r" (temp)
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+static inline void __outw (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "str    %1, [%0, %2, lsl #2]    @ outw"
+        : "=&r" (temp)
+        : "r" (value|value<<16), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+static inline void __outl (unsigned int value, unsigned int port)
+{
+        unsigned long temp;
+        __asm__ __volatile__(
+        "tst    %2, #0x80000000\n\t"
+        "mov    %0, %4\n\t"
+        "addeq  %0, %0, %3\n\t"
+        "str    %1, [%0, %2, lsl #2]    @ outl"
+        : "=&r" (temp)
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)
+        : "cc");
+}
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
+static inline unsigned sz __in##fnsuffix (unsigned int port)            \
+{                                                                               \
+        unsigned long temp, value;                                              \
+        __asm__ __volatile__(                                                   \
+        "tst    %2, #0x80000000\n\t"                                            \
+        "mov    %0, %4\n\t"                                                     \
+        "addeq  %0, %0, %3\n\t"                                                 \
+        "ldr" instr "   %1, [%0, %2, lsl #2]    @ in" #fnsuffix                 \
+        : "=&r" (temp), "=r" (value)                                            \
+        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
+        : "cc");                                                                \
+        return (unsigned sz)value;                                              \
+}
+
+static inline void __iomem *__ioaddr(unsigned int port)
+{
+        void __iomem *ret;
+        if (__PORT_PCIO(port))
+                ret = PCIO_BASE;
+        else
+                ret = IO_BASE;
+        return ret + (port << 2);
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)   \
+        DECLARE_DYN_IN(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"")
+DECLARE_IO(int,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)                                                     \
+({                                                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]    @ outbc"                                \
+                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port) << 2));          \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]    @ outbc"                                \
+                : : "r" (value), "r" (IO_BASE), "r" ((port) << 2));             \
+})
+
+#define __inbc(port)                                                            \
+({                                                                              \
+        unsigned char result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]    @ inbc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]    @ inbc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result;                                                                 \
+})
+
+#define __outwc(value,port)                                                     \
+({                                                                              \
+        unsigned long __v = value;                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outwc"                                \
+                : : "r" (__v|__v<<16), "r" (PCIO_BASE), "Jr" ((port) << 2));    \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outwc"                                \
+                : : "r" (__v|__v<<16), "r" (IO_BASE), "r" ((port) << 2));               \
+})
+
+#define __inwc(port)                                                            \
+({                                                                              \
+        unsigned short result;                                                  \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inwc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inwc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result & 0xffff;                                                        \
+})
+
+#define __outlc(value,port)                                                     \
+({                                                                              \
+        unsigned long __v = value;                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outlc"                                \
+                : : "r" (__v), "r" (PCIO_BASE), "Jr" ((port) << 2));            \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]    @ outlc"                                \
+                : : "r" (__v), "r" (IO_BASE), "r" ((port) << 2));               \
+})
+
+#define __inlc(port)                                                            \
+({                                                                              \
+        unsigned long result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inlc"                                 \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port) << 2));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]    @ inlc"                                 \
+                : "=r" (result) : "r" (IO_BASE), "r" ((port) << 2));            \
+        result;                                                                 \
+})
+
+#define __ioaddrc(port)         \
+        ((__PORT_PCIO(port) ? PCIO_BASE : IO_BASE) + ((port) << 2))
+
+#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
+#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
+#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
+#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
+/* the following macro is deprecated */
+#define ioaddr(port)    ((unsigned long)__ioaddr((port)))
+
+#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
+#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
+
+#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
+#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)    (x)
+
+#endif
diff --git a/include/asm-arm/arch-rpc/irqs.h b/include/asm-arm/arch-rpc/irqs.h
new file mode 100644
index 000000000000..27c35b05b27d
--- /dev/null
+++ b/include/asm-arm/arch-rpc/irqs.h
@@ -0,0 +1,46 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/irqs.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define IRQ_PRINTER             0
+#define IRQ_BATLOW              1
+#define IRQ_FLOPPYINDEX         2
+#define IRQ_VSYNCPULSE          3
+#define IRQ_POWERON             4
+#define IRQ_TIMER0              5
+#define IRQ_TIMER1              6
+#define IRQ_IMMEDIATE           7
+#define IRQ_EXPCARDFIQ          8
+#define IRQ_HARDDISK            9
+#define IRQ_SERIALPORT          10
+#define IRQ_FLOPPYDISK          12
+#define IRQ_EXPANSIONCARD       13
+#define IRQ_KEYBOARDTX          14
+#define IRQ_KEYBOARDRX          15
+
+#define IRQ_DMA0                16
+#define IRQ_DMA1                17
+#define IRQ_DMA2                18
+#define IRQ_DMA3                19
+#define IRQ_DMAS0               20
+#define IRQ_DMAS1               21
+
+#define FIQ_FLOPPYDATA          0
+#define FIQ_ECONET              2
+#define FIQ_SERIALPORT          4
+#define FIQ_EXPANSIONCARD       6
+#define FIQ_FORCE               7
+
+/*
+ * This is the offset of the FIQ "IRQ" numbers
+ */
+#define FIQ_START               64
+
+#define IRQ_TIMER               IRQ_TIMER0
+
diff --git a/include/asm-arm/arch-rpc/memory.h b/include/asm-arm/arch-rpc/memory.h
new file mode 100644
index 000000000000..33fc75cdead0
--- /dev/null
+++ b/include/asm-arm/arch-rpc/memory.h
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/memory.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-Oct-1996 RMK    Created
+ *   31-Dec-1997 RMK    Fixed definitions to reduce warnings
+ *   11-Jan-1998 RMK    Uninlined to reduce hits on cache
+ *   08-Feb-1998 RMK    Added __virt_to_bus and __bus_to_virt
+ *   21-Mar-1999 RMK    Renamed to memory.h
+ *               RMK    Added TASK_SIZE and PAGE_OFFSET
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x10000000UL)
+
+/*
+ * These are exactly the same on the RiscPC as the
+ * physical memory view.
+ */
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-rpc/param.h b/include/asm-arm/arch-rpc/param.h
new file mode 100644
index 000000000000..721dcd658858
--- /dev/null
+++ b/include/asm-arm/arch-rpc/param.h
@@ -0,0 +1,3 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/param.h
+ */
diff --git a/include/asm-arm/arch-rpc/system.h b/include/asm-arm/arch-rpc/system.h
new file mode 100644
index 000000000000..ca3277d1d5ea
--- /dev/null
+++ b/include/asm-arm/arch-rpc/system.h
@@ -0,0 +1,27 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/system.h
+ *
+ *  Copyright (C) 1996-1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/arch/hardware.h>
+#include <asm/hardware/iomd.h>
+#include <asm/io.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        iomd_writeb(0, IOMD_ROMCR0);
+
+        /*
+         * Jump into the ROM
+         */
+        cpu_reset(0);
+}
diff --git a/include/asm-arm/arch-rpc/timex.h b/include/asm-arm/arch-rpc/timex.h
new file mode 100644
index 000000000000..ed7df64d960b
--- /dev/null
+++ b/include/asm-arm/arch-rpc/timex.h
@@ -0,0 +1,17 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/timex.h
+ *
+ *  Copyright (C) 1997, 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  RiscPC architecture timex specifications
+ */
+
+/*
+ * On the RiscPC, the clock ticks at 2MHz.
+ */
+#define CLOCK_TICK_RATE         2000000
+
diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h
new file mode 100644
index 000000000000..43035fec64d2
--- /dev/null
+++ b/include/asm-arm/arch-rpc/uncompress.h
@@ -0,0 +1,155 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/uncompress.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define VIDMEM ((char *)SCREEN_START)
+ 
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+int video_num_columns, video_num_lines, video_size_row;
+int white, bytes_per_char_h;
+extern unsigned long con_charconvtable[256];
+
+struct param_struct {
+        unsigned long page_size;
+        unsigned long nr_pages;
+        unsigned long ramdisk_size;
+        unsigned long mountrootrdonly;
+        unsigned long rootdev;
+        unsigned long video_num_cols;
+        unsigned long video_num_rows;
+        unsigned long video_x;
+        unsigned long video_y;
+        unsigned long memc_control_reg;
+        unsigned char sounddefault;
+        unsigned char adfsdrives;
+        unsigned char bytes_per_char_h;
+        unsigned char bytes_per_char_v;
+        unsigned long unused[256/4-11];
+};
+
+static const unsigned long palette_4[16] = {
+        0x00000000,
+        0x000000cc,
+        0x0000cc00,             /* Green   */
+        0x0000cccc,             /* Yellow  */
+        0x00cc0000,             /* Blue    */
+        0x00cc00cc,             /* Magenta */
+        0x00cccc00,             /* Cyan    */
+        0x00cccccc,             /* White   */
+        0x00000000,
+        0x000000ff,
+        0x0000ff00,
+        0x0000ffff,
+        0x00ff0000,
+        0x00ff00ff,
+        0x00ffff00,
+        0x00ffffff
+};
+
+#define palette_setpixel(p)     *(unsigned long *)(IO_START+0x00400000) = 0x10000000|((p) & 255)
+#define palette_write(v)        *(unsigned long *)(IO_START+0x00400000) = 0x00000000|((v) & 0x00ffffff)
+
+/*
+ * params_phys is a linker defined symbol - see
+ * arch/arm/boot/compressed/Makefile
+ */
+extern __attribute__((pure)) struct param_struct *params(void);
+#define params (params())
+
+#ifndef STANDALONE_DEBUG 
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        extern void ll_write_char(char *, char c, char white);
+        int x,y;
+        unsigned char c;
+        char *ptr;
+
+        x = params->video_x;
+        y = params->video_y;
+
+        while ( ( c = *(unsigned char *)s++ ) != '\0' ) {
+                if ( c == '\n' ) {
+                        x = 0;
+                        if ( ++y >= video_num_lines ) {
+                                y--;
+                        }
+                } else {
+                        ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h);
+                        ll_write_char(ptr, c, white);
+                        if ( ++x >= video_num_columns ) {
+                                x = 0;
+                                if ( ++y >= video_num_lines ) {
+                                        y--;
+                                }
+                        }
+                }
+        }
+
+        params->video_x = x;
+        params->video_y = y;
+}
+
+static void error(char *x);
+
+/*
+ * Setup for decompression
+ */
+static void arch_decomp_setup(void)
+{
+        int i;
+        
+        video_num_lines = params->video_num_rows;
+        video_num_columns = params->video_num_cols;
+        bytes_per_char_h = params->bytes_per_char_h;
+        video_size_row = video_num_columns * bytes_per_char_h;
+        if (bytes_per_char_h == 4)
+                for (i = 0; i < 256; i++)
+                        con_charconvtable[i] =
+                                (i & 128 ? 1 << 0  : 0) |
+                                (i & 64  ? 1 << 4  : 0) |
+                                (i & 32  ? 1 << 8  : 0) |
+                                (i & 16  ? 1 << 12 : 0) |
+                                (i & 8   ? 1 << 16 : 0) |
+                                (i & 4   ? 1 << 20 : 0) |
+                                (i & 2   ? 1 << 24 : 0) |
+                                (i & 1   ? 1 << 28 : 0);
+        else
+                for (i = 0; i < 16; i++)
+                        con_charconvtable[i] =
+                                (i & 8   ? 1 << 0  : 0) |
+                                (i & 4   ? 1 << 8  : 0) |
+                                (i & 2   ? 1 << 16 : 0) |
+                                (i & 1   ? 1 << 24 : 0);
+
+
+        palette_setpixel(0);
+        if (bytes_per_char_h == 1) {
+                palette_write (0);
+                palette_write (0x00ffffff);
+                for (i = 2; i < 256; i++)
+                        palette_write (0);
+                white = 1;
+        } else {
+                for (i = 0; i < 256; i++)
+                        palette_write (i < 16 ? palette_4[i] : 0);
+                white = 7;
+        }
+
+        if (params->nr_pages * params->page_size < 4096*1024) error("<4M of mem\n");
+}
+#endif
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-rpc/vmalloc.h b/include/asm-arm/arch-rpc/vmalloc.h
new file mode 100644
index 000000000000..a13c27f37d71
--- /dev/null
+++ b/include/asm-arm/arch-rpc/vmalloc.h
@@ -0,0 +1,21 @@
+/*
+ *  linux/include/asm-arm/arch-rpc/vmalloc.h
+ *
+ *  Copyright (C) 1997 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (PAGE_OFFSET + 0x1c000000)
diff --git a/include/asm-arm/arch-s3c2410/bast-cpld.h b/include/asm-arm/arch-s3c2410/bast-cpld.h
new file mode 100644
index 000000000000..e28ca51a4975
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/bast-cpld.h
@@ -0,0 +1,58 @@
+/* linux/include/asm-arm/arch-s3c2410/bast-cpld.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * BAST - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  25-May-2003 BJD  Created file, added CTRL1 registers
+ *  30-Aug-2004 BJD  Updated definitions from 2.4.26 port
+ *  30-Aug-2004 BJD  Added CTRL3 and CTRL4 definitions
+*/
+
+#ifndef __ASM_ARCH_BASTCPLD_H
+#define __ASM_ARCH_BASTCPLD_H
+
+/* CTRL1 - Audio LR routing */
+
+#define BAST_CPLD_CTRL1_LRCOFF      (0x00)
+#define BAST_CPLD_CTRL1_LRCADC      (0x01)
+#define BAST_CPLD_CTRL1_LRCDAC      (0x02)
+#define BAST_CPLD_CTRL1_LRCARM      (0x03)
+#define BAST_CPLD_CTRL1_LRMASK      (0x03)
+
+/* CTRL2 - NAND WP control, IDE Reset assert/check */
+
+#define BAST_CPLD_CTRL2_WNAND       (0x04)
+#define BAST_CPLD_CTLR2_IDERST      (0x08)
+
+/* CTRL3 - rom write control, CPLD identity */
+
+#define BAST_CPLD_CTRL3_IDMASK      (0x0e)
+#define BAST_CPLD_CTRL3_ROMWEN      (0x01)
+
+/* CTRL4 - 8bit LCD interface control/status */
+
+#define BAST_CPLD_CTRL4_LLAT        (0x01)
+#define BAST_CPLD_CTRL4_LCDRW       (0x02)
+#define BAST_CPLD_CTRL4_LCDCMD      (0x04)
+#define BAST_CPLD_CTRL4_LCDE2       (0x01)
+
+/* CTRL5 - DMA routing */
+
+#define BAST_CPLD_DMA0_PRIIDE      (0<<0)
+#define BAST_CPLD_DMA0_SECIDE      (1<<0)
+#define BAST_CPLD_DMA0_ISA15       (2<<0)
+#define BAST_CPLD_DMA0_ISA36       (3<<0)
+
+#define BAST_CPLD_DMA1_PRIIDE      (0<<2)
+#define BAST_CPLD_DMA1_SECIDE      (1<<2)
+#define BAST_CPLD_DMA1_ISA15       (2<<2)
+#define BAST_CPLD_DMA1_ISA36       (3<<2)
+
+#endif /* __ASM_ARCH_BASTCPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-irq.h b/include/asm-arm/arch-s3c2410/bast-irq.h
new file mode 100644
index 000000000000..b79b47f0d126
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/bast-irq.h
@@ -0,0 +1,33 @@
+/* linux/include/asm-arm/arch-s3c2410/bast-irq.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine BAST - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  14-Sep-2004 BJD  Fixed IRQ_USBOC definition
+ *  06-Jan-2003 BJD  Linux 2.6.0 version
+ */
+
+#ifndef __ASM_ARCH_BASTIRQ_H
+#define __ASM_ARCH_BASTIRQ_H
+
+/* irq numbers to onboard peripherals */
+
+#define IRQ_USBOC      IRQ_EINT18
+#define IRQ_IDE0       IRQ_EINT16
+#define IRQ_IDE1       IRQ_EINT17
+#define IRQ_PCSERIAL1  IRQ_EINT15
+#define IRQ_PCSERIAL2  IRQ_EINT14
+#define IRQ_PCPARALLEL IRQ_EINT13
+#define IRQ_ASIX       IRQ_EINT11
+#define IRQ_DM9000     IRQ_EINT10
+#define IRQ_ISA        IRQ_EINT9
+#define IRQ_SMALERT    IRQ_EINT8
+
+#endif /* __ASM_ARCH_BASTIRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-map.h b/include/asm-arm/arch-s3c2410/bast-map.h
new file mode 100644
index 000000000000..29c07e302b04
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/bast-map.h
@@ -0,0 +1,150 @@
+/* linux/include/asm-arm/arch-s3c2410/bast-map.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine BAST - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  06-Jan-2003 BJD  Linux 2.6.0 version, moved bast specifics from arch/map.h
+ *  12-Mar-2004 BJD  Fixed header include protection
+*/
+
+/* needs arch/map.h including with this */
+
+/* ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+
+#ifndef __ASM_ARCH_BASTMAP_H
+#define __ASM_ARCH_BASTMAP_H
+
+#define BAST_IOADDR(x)     (S3C2410_ADDR((x) + 0x01300000))
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define BAST_VA_CTRL1       BAST_IOADDR(0x00000000)      /* 0x01300000 */
+#define BAST_PA_CTRL1       (S3C2410_CS5 | 0x7800000)
+
+#define BAST_VA_CTRL2       BAST_IOADDR(0x00100000)      /* 0x01400000 */
+#define BAST_PA_CTRL2       (S3C2410_CS1 | 0x6000000)
+
+#define BAST_VA_CTRL3       BAST_IOADDR(0x00200000)      /* 0x01500000 */
+#define BAST_PA_CTRL3       (S3C2410_CS1 | 0x6800000)
+
+#define BAST_VA_CTRL4       BAST_IOADDR(0x00300000)      /* 0x01600000 */
+#define BAST_PA_CTRL4       (S3C2410_CS1 | 0x7000000)
+
+/* next, we have the PC104 ISA interrupt registers */
+
+#define BAST_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define BAST_VA_PC104_IRQREQ  BAST_IOADDR(0x00400000)
+
+#define BAST_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define BAST_VA_PC104_IRQRAW  BAST_IOADDR(0x00500000)
+
+#define BAST_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define BAST_VA_PC104_IRQMASK BAST_IOADDR(0x00600000)
+
+#define BAST_PA_LCD_RCMD1     (0x8800000)
+#define BAST_VA_LCD_RCMD1     BAST_IOADDR(0x00700000)
+
+#define BAST_PA_LCD_WCMD1     (0x8000000)
+#define BAST_VA_LCD_WCMD1     BAST_IOADDR(0x00800000)
+
+#define BAST_PA_LCD_RDATA1    (0x9800000)
+#define BAST_VA_LCD_RDATA1    BAST_IOADDR(0x00900000)
+
+#define BAST_PA_LCD_WDATA1    (0x9000000)
+#define BAST_VA_LCD_WDATA1    BAST_IOADDR(0x00A00000)
+
+#define BAST_PA_LCD_RCMD2     (0xA800000)
+#define BAST_VA_LCD_RCMD2     BAST_IOADDR(0x00B00000)
+
+#define BAST_PA_LCD_WCMD2     (0xA000000)
+#define BAST_VA_LCD_WCMD2     BAST_IOADDR(0x00C00000)
+
+#define BAST_PA_LCD_RDATA2    (0xB800000)
+#define BAST_VA_LCD_RDATA2    BAST_IOADDR(0x00D00000)
+
+#define BAST_PA_LCD_WDATA2    (0xB000000)
+#define BAST_VA_LCD_WDATA2    BAST_IOADDR(0x00E00000)
+
+
+/* 0xE0000000 contains the IO space that is split by speed and
+ * wether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x00000000 to 0x01000000 16MB ISA IO space
+ * 0x01000000 to 0x02000000 16MB ISA memory space
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02400000 to 0x02500000 1MB  ASIX ethernet controller
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controller
+ * 0x02600000 to 0x02700000 1MB  PC SuperIO controller
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+
+#define BAST_VA_MULTISPACE (0xE0000000)
+
+#define BAST_VA_ISAIO      (BAST_VA_MULTISPACE + 0x00000000)
+#define BAST_VA_ISAMEM     (BAST_VA_MULTISPACE + 0x01000000)
+#define BAST_VA_IDEPRI     (BAST_VA_MULTISPACE + 0x02000000)
+#define BAST_VA_IDEPRIAUX  (BAST_VA_MULTISPACE + 0x02100000)
+#define BAST_VA_IDESEC     (BAST_VA_MULTISPACE + 0x02200000)
+#define BAST_VA_IDESECAUX  (BAST_VA_MULTISPACE + 0x02300000)
+#define BAST_VA_ASIXNET    (BAST_VA_MULTISPACE + 0x02400000)
+#define BAST_VA_DM9000     (BAST_VA_MULTISPACE + 0x02500000)
+#define BAST_VA_SUPERIO    (BAST_VA_MULTISPACE + 0x02600000)
+
+#define BAST_VA_MULTISPACE (0xE0000000)
+
+#define BAST_VAM_CS2 (0x00000000)
+#define BAST_VAM_CS3 (0x04000000)
+#define BAST_VAM_CS4 (0x08000000)
+#define BAST_VAM_CS5 (0x0C000000)
+
+/* physical offset addresses for the peripherals */
+
+#define BAST_PA_ISAIO     (0x00000000)
+#define BAST_PA_ASIXNET   (0x01000000)
+#define BAST_PA_SUPERIO   (0x01800000)
+#define BAST_PA_IDEPRI    (0x02000000)
+#define BAST_PA_IDEPRIAUX (0x02800000)
+#define BAST_PA_IDESEC    (0x03000000)
+#define BAST_PA_IDESECAUX (0x03800000)
+#define BAST_PA_ISAMEM    (0x04000000)
+#define BAST_PA_DM9000    (0x05000000)
+
+/* some configurations for the peripherals */
+
+#define BAST_PCSIO (BAST_VA_SUPERIO + BAST_VAM_CS2)
+/*  */
+
+#define BAST_ASIXNET_CS  BAST_VAM_CS5
+#define BAST_IDE_CS      BAST_VAM_CS5
+#define BAST_DM9000_CS   BAST_VAM_CS4
+
+#endif /* __ASM_ARCH_BASTMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/bast-pmu.h b/include/asm-arm/arch-s3c2410/bast-pmu.h
new file mode 100644
index 000000000000..758c5c59d4bf
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/bast-pmu.h
@@ -0,0 +1,43 @@
+/* linux/include/asm-arm/arch-s3c2410/bast-pmu.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *      Vincent Sanders <vince@simtec.co.uk>
+ *
+ * Machine BAST - Power Management chip
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *      08-Oct-2003     BJD     Initial creation
+*/
+
+#ifndef __ASM_ARCH_BASTPMU_H
+#define __ASM_ARCH_BASTPMU_H "08_OCT_2004"
+
+#define BASTPMU_REG_IDENT       (0x00)
+#define BASTPMU_REG_VERSION     (0x01)
+#define BASTPMU_REG_DDCCTRL     (0x02)
+#define BASTPMU_REG_POWER       (0x03)
+#define BASTPMU_REG_RESET       (0x04)
+#define BASTPMU_REG_GWO         (0x05)
+#define BASTPMU_REG_WOL         (0x06)
+#define BASTPMU_REG_WOR         (0x07)
+#define BASTPMU_REG_UID         (0x09)
+
+#define BASTPMU_EEPROM          (0xC0)
+
+#define BASTPMU_EEP_UID         (BASTPMU_EEPROM + 0)
+#define BASTPMU_EEP_WOL         (BASTPMU_EEPROM + 8)
+#define BASTPMU_EEP_WOR         (BASTPMU_EEPROM + 9)
+
+#define BASTPMU_IDENT_0         0x53
+#define BASTPMU_IDENT_1         0x42
+#define BASTPMU_IDENT_2         0x50
+#define BASTPMU_IDENT_3         0x4d
+
+#define BASTPMU_RESET_GUARD     (0x55)
+
+#endif /* __ASM_ARCH_BASTPMU_H */
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
new file mode 100644
index 000000000000..abfbe45cd17c
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -0,0 +1,99 @@
+/* linux/include/asm-arm/arch-s3c2410/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Copyright (C) 2005 Simtec Electronics
+ *
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *     10-Mar-2005 LCVR  Changed S3C2410_VA to S3C24XX_VA
+*/
+
+#include <asm/arch/map.h>
+#include <asm/arch/regs-serial.h>
+#include <asm/arch/regs-gpio.h>
+
+#define S3C2410_UART1_OFF (0x4000)
+#define SHIFT_2440TXF (14-9)
+
+                .macro addruart, rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1
+                ldreq   \rx, = S3C2410_PA_UART
+                ldrne   \rx, = S3C24XX_VA_UART
+#if CONFIG_DEBUG_S3C2410_UART != 0
+                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART)
+#endif
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, # S3C2410_UTXH ]
+                .endm
+
+                .macro  busyuart, rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                beq     1001f                           @
+                @ FIFO enabled...
+1003:
+                mrc     p15, 0, \rd, c1, c0
+                tst     \rd, #1
+                addeq   \rd, \rx, #(S3C2410_PA_GPIO - S3C2410_PA_UART)
+                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
+                bic     \rd, \rd, #0xff000
+                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+                and     \rd, \rd, #0x00ff0000
+                teq     \rd, #0x00440000                @ is it 2440?
+
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                moveq   \rd, \rd, lsr #SHIFT_2440TXF
+                tst     \rd, #S3C2410_UFSTAT_TXFULL
+                bne     1003b
+                b       1002f
+
+1001:
+                @ busy waiting for non fifo
+                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                tst     \rd, #S3C2410_UTRSTAT_TXFE
+                beq     1001b
+
+1002:           @ exit busyuart
+                .endm
+
+                .macro  waituart,rd,rx
+
+                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                beq     1001f                           @
+                @ FIFO enabled...
+1003:
+                mrc     p15, 0, \rd, c1, c0
+                tst     \rd, #1
+                addeq   \rd, \rx, #(S3C2410_PA_GPIO - S3C2410_PA_UART)
+                addne   \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
+                bic     \rd, \rd, #0xff000
+                ldr     \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
+                and     \rd, \rd, #0x00ff0000
+                teq     \rd, #0x00440000                @ is it 2440?
+
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
+                andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
+                teq     \rd, #0
+                bne     1003b
+                b       1002f
+
+1001:
+                @ idle waiting for non fifo
+                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                tst     \rd, #S3C2410_UTRSTAT_TXFE
+                beq     1001b
+
+1002:           @ exit busyuart
+                .endm
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h
new file mode 100644
index 000000000000..e830a40e573a
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/dma.h
@@ -0,0 +1,376 @@
+/* linux/include/asm-arm/arch-bast/dma.h
+ *
+ * Copyright (C) 2003,2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Samsung S3C2410X DMA support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  ??-May-2003 BJD   Created file
+ *  ??-Jun-2003 BJD   Added more dma functionality to go with arch
+ *  10-Nov-2004 BJD   Added sys_device support
+*/
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H __FILE__
+
+#include <linux/config.h>
+#include <linux/sysdev.h>
+#include "hardware.h"
+
+
+/*
+ * This is the maximum DMA address(physical address) that can be DMAd to.
+ *
+ */
+#define MAX_DMA_ADDRESS         0x20000000
+#define MAX_DMA_TRANSFER_SIZE   0x100000 /* Data Unit is half word  */
+
+
+/* according to the samsung port, we cannot use the regular
+ * dma channels... we must therefore provide our own interface
+ * for DMA, and allow our drivers to use that.
+ */
+
+#define MAX_DMA_CHANNELS        0
+
+
+/* we have 4 dma channels */
+#define S3C2410_DMA_CHANNELS        (4)
+
+/* types */
+
+typedef enum {
+        S3C2410_DMA_IDLE,
+        S3C2410_DMA_RUNNING,
+        S3C2410_DMA_PAUSED
+} s3c2410_dma_state_t;
+
+
+/* s3c2410_dma_loadst_t
+ *
+ * This represents the state of the DMA engine, wrt to the loaded / running
+ * transfers. Since we don't have any way of knowing exactly the state of
+ * the DMA transfers, we need to know the state to make decisions on wether
+ * we can
+ *
+ * S3C2410_DMA_NONE
+ *
+ * There are no buffers loaded (the channel should be inactive)
+ *
+ * S3C2410_DMA_1LOADED
+ *
+ * There is one buffer loaded, however it has not been confirmed to be
+ * loaded by the DMA engine. This may be because the channel is not
+ * yet running, or the DMA driver decided that it was too costly to
+ * sit and wait for it to happen.
+ *
+ * S3C2410_DMA_1RUNNING
+ *
+ * The buffer has been confirmed running, and not finisged
+ *
+ * S3C2410_DMA_1LOADED_1RUNNING
+ *
+ * There is a buffer waiting to be loaded by the DMA engine, and one
+ * currently running.
+*/
+
+typedef enum {
+        S3C2410_DMALOAD_NONE,
+        S3C2410_DMALOAD_1LOADED,
+        S3C2410_DMALOAD_1RUNNING,
+        S3C2410_DMALOAD_1LOADED_1RUNNING,
+} s3c2410_dma_loadst_t;
+
+typedef enum {
+        S3C2410_RES_OK,
+        S3C2410_RES_ERR,
+        S3C2410_RES_ABORT
+} s3c2410_dma_buffresult_t;
+
+
+typedef enum s3c2410_dmasrc_e s3c2410_dmasrc_t;
+
+enum s3c2410_dmasrc_e {
+        S3C2410_DMASRC_HW,      /* source is memory */
+        S3C2410_DMASRC_MEM      /* source is hardware */
+};
+
+/* enum s3c2410_chan_op_e
+ *
+ * operation codes passed to the DMA code by the user, and also used
+ * to inform the current channel owner of any changes to the system state
+*/
+
+enum s3c2410_chan_op_e {
+        S3C2410_DMAOP_START,
+        S3C2410_DMAOP_STOP,
+        S3C2410_DMAOP_PAUSE,
+        S3C2410_DMAOP_RESUME,
+        S3C2410_DMAOP_FLUSH,
+        S3C2410_DMAOP_TIMEOUT,           /* internal signal to handler */
+};
+
+typedef enum s3c2410_chan_op_e s3c2410_chan_op_t;
+
+/* flags */
+
+#define S3C2410_DMAF_SLOW         (1<<0)   /* slow, so don't worry about
+                                            * waiting for reloads */
+#define S3C2410_DMAF_AUTOSTART    (1<<1)   /* auto-start if buffer queued */
+
+/* dma buffer */
+
+typedef struct s3c2410_dma_buf_s s3c2410_dma_buf_t;
+
+struct s3c2410_dma_client {
+        char                *name;
+};
+
+typedef struct s3c2410_dma_client s3c2410_dma_client_t;
+
+/* s3c2410_dma_buf_s
+ *
+ * internally used buffer structure to describe a queued or running
+ * buffer.
+*/
+
+struct s3c2410_dma_buf_s {
+        s3c2410_dma_buf_t   *next;
+        int                  magic;        /* magic */
+        int                  size;         /* buffer size in bytes */
+        dma_addr_t           data;         /* start of DMA data */
+        dma_addr_t           ptr;          /* where the DMA got to [1] */
+        void                *id;           /* client's id */
+};
+
+/* [1] is this updated for both recv/send modes? */
+
+typedef struct s3c2410_dma_chan_s s3c2410_dma_chan_t;
+
+/* s3c2410_dma_cbfn_t
+ *
+ * buffer callback routine type
+*/
+
+typedef void (*s3c2410_dma_cbfn_t)(s3c2410_dma_chan_t *, void *buf, int size,
+                                   s3c2410_dma_buffresult_t result);
+
+typedef int  (*s3c2410_dma_opfn_t)(s3c2410_dma_chan_t *,
+                                   s3c2410_chan_op_t );
+
+struct s3c2410_dma_stats_s {
+        unsigned long          loads;
+        unsigned long          timeout_longest;
+        unsigned long          timeout_shortest;
+        unsigned long          timeout_avg;
+        unsigned long          timeout_failed;
+};
+
+typedef struct s3c2410_dma_stats_s s3c2410_dma_stats_t;
+
+/* struct s3c2410_dma_chan_s
+ *
+ * full state information for each DMA channel
+*/
+
+struct s3c2410_dma_chan_s {
+        /* channel state flags and information */
+        unsigned char          number;      /* number of this dma channel */
+        unsigned char          in_use;      /* channel allocated */
+        unsigned char          irq_claimed; /* irq claimed for channel */
+        unsigned char          irq_enabled; /* irq enabled for channel */
+        unsigned char          xfer_unit;   /* size of an transfer */
+
+        /* channel state */
+
+        s3c2410_dma_state_t    state;
+        s3c2410_dma_loadst_t   load_state;
+        s3c2410_dma_client_t  *client;
+
+        /* channel configuration */
+        s3c2410_dmasrc_t       source;
+        unsigned long          dev_addr;
+        unsigned long          load_timeout;
+        unsigned int           flags;        /* channel flags */
+
+        /* channel's hardware position and configuration */
+        void __iomem           *regs;        /* channels registers */
+        void __iomem           *addr_reg;    /* data address register */
+        unsigned int           irq;          /* channel irq */
+        unsigned long          dcon;         /* default value of DCON */
+
+        /* driver handles */
+        s3c2410_dma_cbfn_t     callback_fn;  /* buffer done callback */
+        s3c2410_dma_opfn_t     op_fn;        /* channel operation callback */
+
+        /* stats gathering */
+        s3c2410_dma_stats_t   *stats;
+        s3c2410_dma_stats_t    stats_store;
+
+        /* buffer list and information */
+        s3c2410_dma_buf_t      *curr;        /* current dma buffer */
+        s3c2410_dma_buf_t      *next;        /* next buffer to load */
+        s3c2410_dma_buf_t      *end;         /* end of queue */
+
+        /* system device */
+        struct sys_device       dev;
+};
+
+/* the currently allocated channel information */
+extern s3c2410_dma_chan_t s3c2410_chans[];
+
+/* note, we don't really use dma_device_t at the moment */
+typedef unsigned long dma_device_t;
+
+/* functions --------------------------------------------------------------- */
+
+/* s3c2410_dma_request
+ *
+ * request a dma channel exclusivley
+*/
+
+extern int s3c2410_dma_request(dmach_t channel,
+                               s3c2410_dma_client_t *, void *dev);
+
+
+/* s3c2410_dma_ctrl
+ *
+ * change the state of the dma channel
+*/
+
+extern int s3c2410_dma_ctrl(dmach_t channel, s3c2410_chan_op_t op);
+
+/* s3c2410_dma_setflags
+ *
+ * set the channel's flags to a given state
+*/
+
+extern int s3c2410_dma_setflags(dmach_t channel,
+                                unsigned int flags);
+
+/* s3c2410_dma_free
+ *
+ * free the dma channel (will also abort any outstanding operations)
+*/
+
+extern int s3c2410_dma_free(dmach_t channel, s3c2410_dma_client_t *);
+
+/* s3c2410_dma_enqueue
+ *
+ * place the given buffer onto the queue of operations for the channel.
+ * The buffer must be allocated from dma coherent memory, or the Dcache/WB
+ * drained before the buffer is given to the DMA system.
+*/
+
+extern int s3c2410_dma_enqueue(dmach_t channel, void *id,
+                               dma_addr_t data, int size);
+
+/* s3c2410_dma_config
+ *
+ * configure the dma channel
+*/
+
+extern int s3c2410_dma_config(dmach_t channel, int xferunit, int dcon);
+
+/* s3c2410_dma_devconfig
+ *
+ * configure the device we're talking to
+*/
+
+extern int s3c2410_dma_devconfig(int channel, s3c2410_dmasrc_t source,
+                                 int hwcfg, unsigned long devaddr);
+
+/* s3c2410_dma_getposition
+ *
+ * get the position that the dma transfer is currently at
+*/
+
+extern int s3c2410_dma_getposition(dmach_t channel,
+                                   dma_addr_t *src, dma_addr_t *dest);
+
+extern int s3c2410_dma_set_opfn(dmach_t, s3c2410_dma_opfn_t rtn);
+extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
+
+/* DMA Register definitions */
+
+#define S3C2410_DMA_DISRC       (0x00)
+#define S3C2410_DMA_DISRCC      (0x04)
+#define S3C2410_DMA_DIDST       (0x08)
+#define S3C2410_DMA_DIDSTC      (0x0C)
+#define S3C2410_DMA_DCON        (0x10)
+#define S3C2410_DMA_DSTAT       (0x14)
+#define S3C2410_DMA_DCSRC       (0x18)
+#define S3C2410_DMA_DCDST       (0x1C)
+#define S3C2410_DMA_DMASKTRIG   (0x20)
+
+#define S3C2410_DISRCC_INC      (1<<0)
+#define S3C2410_DISRCC_APB      (1<<1)
+
+#define S3C2410_DMASKTRIG_STOP   (1<<2)
+#define S3C2410_DMASKTRIG_ON     (1<<1)
+#define S3C2410_DMASKTRIG_SWTRIG (1<<0)
+
+#define S3C2410_DCON_DEMAND     (0<<31)
+#define S3C2410_DCON_HANDSHAKE  (1<<31)
+#define S3C2410_DCON_SYNC_PCLK  (0<<30)
+#define S3C2410_DCON_SYNC_HCLK  (1<<30)
+
+#define S3C2410_DCON_INTREQ     (1<<29)
+
+#define S3C2410_DCON_CH0_XDREQ0 (0<<24)
+#define S3C2410_DCON_CH0_UART0  (1<<24)
+#define S3C2410_DCON_CH0_SDI    (2<<24)
+#define S3C2410_DCON_CH0_TIMER  (3<<24)
+#define S3C2410_DCON_CH0_USBEP1 (4<<24)
+
+#define S3C2410_DCON_CH1_XDREQ1 (0<<24)
+#define S3C2410_DCON_CH1_UART1  (1<<24)
+#define S3C2410_DCON_CH1_I2SSDI (2<<24)
+#define S3C2410_DCON_CH1_SPI    (3<<24)
+#define S3C2410_DCON_CH1_USBEP2 (4<<24)
+
+#define S3C2410_DCON_CH2_I2SSDO (0<<24)
+#define S3C2410_DCON_CH2_I2SSDI (1<<24)
+#define S3C2410_DCON_CH2_SDI    (2<<24)
+#define S3C2410_DCON_CH2_TIMER  (3<<24)
+#define S3C2410_DCON_CH2_USBEP3 (4<<24)
+
+#define S3C2410_DCON_CH3_UART2  (0<<24)
+#define S3C2410_DCON_CH3_SDI    (1<<24)
+#define S3C2410_DCON_CH3_SPI    (2<<24)
+#define S3C2410_DCON_CH3_TIMER  (3<<24)
+#define S3C2410_DCON_CH3_USBEP4 (4<<24)
+
+#define S3C2410_DCON_SRCSHIFT   (24)
+#define S3C2410_DCON_SRCMASK    (7<<24)
+
+#define S3C2410_DCON_BYTE       (0<<20)
+#define S3C2410_DCON_HALFWORD   (1<<20)
+#define S3C2410_DCON_WORD       (2<<20)
+
+#define S3C2410_DCON_AUTORELOAD (0<<22)
+#define S3C2410_DCON_NORELOAD   (1<<22)
+#define S3C2410_DCON_HWTRIG     (1<<23)
+
+#ifdef CONFIG_CPU_S3C2440
+#define S3C2440_DIDSTC_CHKINT   (1<<2)
+
+#define S3C2440_DCON_CH0_I2SSDO (5<<24)
+#define S3C2440_DCON_CH0_PCMIN  (6<<24)
+
+#define S3C2440_DCON_CH1_PCMOUT (5<<24)
+#define S3C2440_DCON_CH1_SDI    (6<<24)
+
+#define S3C2440_DCON_CH2_PCMIN  (5<<24)
+#define S3C2440_DCON_CH2_MICIN  (6<<24)
+
+#define S3C2440_DCON_CH3_MICIN  (5<<24)
+#define S3C2440_DCON_CH3_PCMOUT (6<<24)
+#endif
+
+#endif /* __ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-s3c2410/entry-macro.S b/include/asm-arm/arch-s3c2410/entry-macro.S
new file mode 100644
index 000000000000..b7d4d7f4422d
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/entry-macro.S
@@ -0,0 +1,119 @@
+/*
+ * include/asm-arm/arch-s3c2410/entry-macro.S
+ *
+ * Low-level IRQ helper macros for S3C2410-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+
+ * Modifications:
+ *     10-Mar-2005 LCVR  Changed S3C2410_VA to S3C24XX_VA
+ */
+
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+
+                mov     \tmp, #S3C24XX_VA_IRQ
+                ldr     \irqnr, [ \tmp, #0x14 ]         @ get irq no
+30000:
+                teq     \irqnr, #4
+                teqne   \irqnr, #5
+                beq     1002f                           @ external irq reg
+
+                @ debug check to see if interrupt reported is the same
+                @ as the offset....
+
+                teq     \irqnr, #0
+                beq     20002f
+                ldr     \irqstat, [ \tmp, #0x10 ]       @ INTPND
+                mov     \irqstat, \irqstat, lsr \irqnr
+                tst     \irqstat, #1
+                bne     20002f
+
+                /* debug/warning if we get an invalud response from the
+                 * INTOFFSET register */
+#if 1
+                stmfd   r13!, { r0 - r4 , r8-r12, r14 }
+                ldr     r1,     [ \tmp, #0x14 ]         @ INTOFFSET
+                ldr     r2,     [ \tmp, #0x10 ]         @ INTPND
+                ldr     r3,     [ \tmp, #0x00 ]         @ SRCPND
+                adr     r0, 20003f
+                bl      printk
+                b       20004f
+
+20003:
+                .ascii  "<7>irq: err - bad offset %d, intpnd=%08x, srcpnd=%08x\n"
+                .byte   0
+                .align  4
+20004:
+                mov     r1, #1
+                mov     \tmp, #S3C24XX_VA_IRQ
+                ldmfd   r13!, { r0 - r4 , r8-r12, r14 }
+#endif
+
+                @ try working out interrupt number for ourselves
+                mov     \irqnr, #0
+                ldr     \irqstat, [ \tmp, #0x10 ]       @ INTPND
+10021:
+                movs    \irqstat, \irqstat, lsr#1
+                bcs     30000b          @ try and re-start the proccess
+                add     \irqnr, \irqnr, #1
+                cmp     \irqnr, #32
+                ble     10021b
+
+                @ found no interrupt, set Z flag and leave
+                movs    \irqnr, #0
+                b       1001f
+
+20005:
+20002:          @ exit
+                @ we base the s3c2410x interrupts at 16 and above to allow
+                @ isa peripherals to have their standard interrupts, also
+                @ ensure that Z flag is un-set on exit
+
+                @ note, we cannot be sure if we get IRQ_EINT0 (0) that
+                @ there is simply no interrupt pending, so in all other
+                @ cases we jump to say we have found something, otherwise
+                @ we check to see if the interrupt really is assrted
+                adds    \irqnr, \irqnr, #IRQ_EINT0
+                teq     \irqnr, #IRQ_EINT0
+                bne     1001f                           @ exit
+                ldr     \irqstat, [ \tmp, #0x10 ]       @ INTPND
+                teq     \irqstat, #0
+                moveq   \irqnr, #0
+                b       1001f
+
+                @ we get here from no main or external interrupts pending
+1002:
+                add     \tmp, \tmp, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
+                ldr     \irqstat, [ \tmp, # 0xa8 ]      @ EXTINTPEND
+                ldr     \irqnr, [ \tmp, # 0xa4 ]        @ EXTINTMASK
+
+                bic     \irqstat, \irqstat, \irqnr      @ clear masked irqs
+
+                mov     \irqnr, #IRQ_EINT4              @ start extint nos
+                mov     \irqstat, \irqstat, lsr#4       @ ignore bottom 4 bits
+10021:
+                movs    \irqstat, \irqstat, lsr#1
+                bcs     1004f
+                add     \irqnr, \irqnr, #1
+                cmp     \irqnr, #IRQ_EINT23
+                ble     10021b
+
+                @ found no interrupt, set Z flag and leave
+                movs    \irqnr, #0
+
+1004:           @ ensure Z flag clear in case our MOVS shifted out the last bit
+                teq     \irqnr, #0
+1001:
+                @ exit irq routine
+                .endm
+
+
+                /* currently don't need an disable_fiq macro */
+
+                .macro  disable_fiq
+                .endm
+
+
diff --git a/include/asm-arm/arch-s3c2410/hardware.h b/include/asm-arm/arch-s3c2410/hardware.h
new file mode 100644
index 000000000000..48a39918a760
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/hardware.h
@@ -0,0 +1,105 @@
+/* linux/include/asm-arm/arch-s3c2410/hardware.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - hardware
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  21-May-2003 BJD  Created file
+ *  06-Jun-2003 BJD  Added CPU frequency settings
+ *  03-Sep-2003 BJD  Linux v2.6 support
+ *  12-Mar-2004 BJD  Fixed include protection, fixed type of clock vars
+ *  14-Sep-2004 BJD  Added misccr and getpin to gpio
+ *  01-Oct-2004 BJD  Added the new gpio functions
+ *  16-Oct-2004 BJD  Removed the clock variables
+*/
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+/* external functions for GPIO support
+ *
+ * These allow various different clients to access the same GPIO
+ * registers without conflicting. If your driver only owns the entire
+ * GPIO register, then it is safe to ioremap/__raw_{read|write} to it.
+*/
+
+/* s3c2410_gpio_cfgpin
+ *
+ * set the configuration of the given pin to the value passed.
+ *
+ * eg:
+ *    s3c2410_gpio_cfgpin(S3C2410_GPA0, S3C2410_GPA0_ADDR0);
+ *    s3c2410_gpio_cfgpin(S3C2410_GPE8, S3C2410_GPE8_SDDAT1);
+*/
+
+extern void s3c2410_gpio_cfgpin(unsigned int pin, unsigned int function);
+
+extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
+
+/* s3c2410_gpio_getirq
+ *
+ * turn the given pin number into the corresponding IRQ number
+ *
+ * returns:
+ *      < 0 = no interrupt for this pin
+ *      >=0 = interrupt number for the pin
+*/
+
+extern int s3c2410_gpio_getirq(unsigned int pin);
+
+/* s3c2410_gpio_irqfilter
+ *
+ * set the irq filtering on the given pin
+ *
+ * on = 0 => disable filtering
+ *      1 => enable filtering
+ *
+ * config = S3C2410_EINTFLT_PCLK or S3C2410_EINTFLT_EXTCLK orred with
+ *          width of filter (0 through 63)
+ *
+ *
+*/
+
+extern int s3c2410_gpio_irqfilter(unsigned int pin, unsigned int on,
+                                  unsigned int config);
+
+/* s3c2410_gpio_pullup
+ *
+ * configure the pull-up control on the given pin
+ *
+ * to = 1 => disable the pull-up
+ *      0 => enable the pull-up
+ *
+ * eg;
+ *
+ *   s3c2410_gpio_pullup(S3C2410_GPB0, 0);
+ *   s3c2410_gpio_pullup(S3C2410_GPE8, 0);
+*/
+
+extern void s3c2410_gpio_pullup(unsigned int pin, unsigned int to);
+
+extern void s3c2410_gpio_setpin(unsigned int pin, unsigned int to);
+
+extern unsigned int s3c2410_gpio_getpin(unsigned int pin);
+
+extern unsigned int s3c2410_modify_misccr(unsigned int clr, unsigned int chg);
+
+#endif /* __ASSEMBLY__ */
+
+#include <asm/sizes.h>
+#include <asm/arch/map.h>
+
+/* machine specific hardware definitions should go after this */
+
+/* currently here until moved into config (todo) */
+#define CONFIG_NO_MULTIWORD_IO
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-s3c2410/idle.h b/include/asm-arm/arch-s3c2410/idle.h
new file mode 100644
index 000000000000..749227c09576
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/idle.h
@@ -0,0 +1,28 @@
+/* linux/include/asm-arm/arch-s3c2410/idle.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 CPU Idle controls
+ *
+ *  Changelog:
+ *      28-Oct-2004  BJD  Initial version
+ *
+*/
+
+#ifndef __ASM_ARCH_IDLE_H
+#define __ASM_ARCH_IDLE_H __FILE__
+
+/* This allows the over-ride of the default idle code, in case there
+ * is any other things to be done over idle (like DVS)
+*/
+
+extern void (*s3c24xx_idle)(void);
+
+extern void s3c24xx_default_idle(void);
+
+#endif /* __ASM_ARCH_IDLE_H */
diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/arch-s3c2410/iic.h
new file mode 100644
index 000000000000..518547f6d7a7
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/iic.h
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-s3c2410/iic.h
+ *
+ * (c) 2004 Simtec Electronics
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - I2C Controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *      05-Oct-2004 BJD  Created file
+ *      19-Oct-2004 BJD  Updated for s3c2440
+*/
+
+#ifndef __ASM_ARCH_IIC_H
+#define __ASM_ARCH_IIC_H __FILE__
+
+#define S3C_IICFLG_FILTER       (1<<0)  /* enable s3c2440 filter */
+
+/* Notes:
+ *      1) All frequencies are expressed in Hz
+ *      2) A value of zero is `do not care`
+*/
+
+struct s3c2410_platform_i2c {
+        unsigned int    flags;
+        unsigned int    slave_addr;     /* slave address for controller */
+        unsigned long   bus_freq;       /* standard bus frequency */
+        unsigned long   max_freq;       /* max frequency for the bus */
+        unsigned long   min_freq;       /* min frequency for the bus */
+        unsigned int    sda_delay;      /* pclks (s3c2440 only) */
+};
+
+#endif /* __ASM_ARCH_IIC_H */
diff --git a/include/asm-arm/arch-s3c2410/io.h b/include/asm-arm/arch-s3c2410/io.h
new file mode 100644
index 000000000000..418233a7ee6f
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/io.h
@@ -0,0 +1,196 @@
+/*
+ * linux/include/asm-arm/arch-s3c2410/io.h
+ *  from linux/include/asm-arm/arch-rpc/io.h
+ *
+ * Copyright (C) 1997 Russell King
+ *           (C) 2003 Simtec Electronics
+ *
+ * Modifications:
+ *  06-Dec-1997 RMK     Created.
+ *  02-Sep-2003 BJD     Modified for S3C2410
+ *  10-Mar-2005 LCVR    Changed S3C2410_VA to S3C24XX_VA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are above A28
+ * and are translated to the start of IO.  Note that all addresses are
+ * not shifted left!
+ */
+
+#define __PORT_PCIO(x)  ((x) < (1<<28))
+
+#define PCIO_BASE        (S3C24XX_VA_ISA_WORD)
+#define PCIO_BASE_b      (S3C24XX_VA_ISA_BYTE)
+#define PCIO_BASE_w      (S3C24XX_VA_ISA_WORD)
+#define PCIO_BASE_l      (S3C24XX_VA_ISA_WORD)
+/*
+ * Dynamic IO functions - let the compiler
+ * optimize the expressions
+ */
+
+#define DECLARE_DYN_OUT(sz,fnsuffix,instr) \
+static inline void __out##fnsuffix (unsigned int val, unsigned int port) \
+{ \
+        unsigned long temp;                                   \
+        __asm__ __volatile__(                                 \
+        "cmp    %2, #(1<<28)\n\t"                             \
+        "mov    %0, %2\n\t"                                   \
+        "addcc  %0, %0, %3\n\t"                               \
+        "str" instr " %1, [%0, #0 ]     @ out" #fnsuffix      \
+        : "=&r" (temp)                                        \
+        : "r" (val), "r" (port), "Ir" (PCIO_BASE_##fnsuffix)  \
+        : "cc");                                              \
+}
+
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)                               \
+static inline unsigned sz __in##fnsuffix (unsigned int port)            \
+{                                                                       \
+        unsigned long temp, value;                                      \
+        __asm__ __volatile__(                                           \
+        "cmp    %2, #(1<<28)\n\t"                                       \
+        "mov    %0, %2\n\t"                                             \
+        "addcc  %0, %0, %3\n\t"                                         \
+        "ldr" instr "   %1, [%0, #0 ]   @ in" #fnsuffix         \
+        : "=&r" (temp), "=r" (value)                                    \
+        : "r" (port), "Ir" (PCIO_BASE_##fnsuffix)       \
+        : "cc");                                                        \
+        return (unsigned sz)value;                                      \
+}
+
+static inline void __iomem *__ioaddr (unsigned long port)
+{
+        return __PORT_PCIO(port) ? (PCIO_BASE + port) : (void __iomem *)port;
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)   \
+        DECLARE_DYN_IN(sz,fnsuffix,instr) \
+        DECLARE_DYN_OUT(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"h")
+DECLARE_IO(int,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)                                             \
+({                                                                      \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "strb   %0, [%1, %2]    @ outbc"                        \
+                : : "r" (value), "r" (PCIO_BASE), "Jr" ((port)));       \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "strb   %0, [%1, #0]    @ outbc"                        \
+                : : "r" (value), "r" ((port)));         \
+})
+
+#define __inbc(port)                                                    \
+({                                                                      \
+        unsigned char result;                                           \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "ldrb   %0, [%1, %2]    @ inbc"                         \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));      \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "ldrb   %0, [%1, #0]    @ inbc"                         \
+                : "=r" (result) : "r" ((port)));        \
+        result;                                                         \
+})
+
+#define __outwc(value,port)                                             \
+({                                                                      \
+        unsigned long v = value;                                        \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "strh   %0, [%1, %2]    @ outwc"                        \
+                : : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));   \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "strh   %0, [%1, #0]    @ outwc"                        \
+                : : "r" (v), "r" ((port)));     \
+})
+
+#define __inwc(port)                                                    \
+({                                                                      \
+        unsigned short result;                                          \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "ldrh   %0, [%1, %2]    @ inwc"                         \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));      \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "ldrh   %0, [%1, #0]    @ inwc"                         \
+                : "=r" (result) : "r" ((port)));                \
+        result;                                         \
+})
+
+#define __outlc(value,port)                                             \
+({                                                                      \
+        unsigned long v = value;                                        \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "str    %0, [%1, %2]    @ outlc"                        \
+                : : "r" (v), "r" (PCIO_BASE), "Jr" ((port)));   \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "str    %0, [%1, #0]    @ outlc"                        \
+                : : "r" (v), "r" ((port)));             \
+})
+
+#define __inlc(port)                                                    \
+({                                                                      \
+        unsigned long result;                                           \
+        if (__PORT_PCIO((port)))                                        \
+                __asm__ __volatile__(                                   \
+                "ldr    %0, [%1, %2]    @ inlc"                         \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" ((port)));      \
+        else                                                            \
+                __asm__ __volatile__(                                   \
+                "ldr    %0, [%1, #0]    @ inlc"                         \
+                : "=r" (result) : "r" ((port)));                \
+        result;                                                         \
+})
+
+#define __ioaddrc(port) ((__PORT_PCIO(port) ? PCIO_BASE + (port) : (void __iomem *)(port)))
+
+#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)     : __inb(p))
+#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)     : __inw(p))
+#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)     : __inl(p))
+#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+#define __ioaddr(p)     (__builtin_constant_p((p)) ? __ioaddr(p)  : __ioaddrc(p))
+/* the following macro is deprecated */
+#define ioaddr(port)    __ioaddr((port))
+
+#define insb(p,d,l)     __raw_readsb(__ioaddr(p),d,l)
+#define insw(p,d,l)     __raw_readsw(__ioaddr(p),d,l)
+#define insl(p,d,l)     __raw_readsl(__ioaddr(p),d,l)
+
+#define outsb(p,d,l)    __raw_writesb(__ioaddr(p),d,l)
+#define outsw(p,d,l)    __raw_writesw(__ioaddr(p),d,l)
+#define outsl(p,d,l)    __raw_writesl(__ioaddr(p),d,l)
+
+/*
+ * 1:1 mapping for ioremapped regions.
+ */
+#define __mem_pci(x)    (x)
+
+#endif
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
new file mode 100644
index 000000000000..d9773d697268
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/irqs.h
@@ -0,0 +1,126 @@
+/* linux/include/asm-arm/arch-s3c2410/irqs.h
+ *
+ * Copyright (c) 2003-2005 Simtec Electronics
+ *   Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  12-May-2003 BJD  Created file
+ *  08-Jan-2003 BJD  Linux 2.6.0 version, moved BAST bits out
+ *  12-Mar-2004 BJD  Fixed bug in header protection
+ *  10-Feb-2005 BJD  Added camera IRQ from guillaume.gourat@nexvision.tv
+ *  28-Feb-2005 BJD  Updated s3c2440 IRQs
+ */
+
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H __FILE__
+
+
+/* we keep the first set of CPU IRQs out of the range of
+ * the ISA space, so that the PC104 has them to itself
+ * and we don't end up having to do horrible things to the
+ * standard ISA drivers....
+ */
+
+#define S3C2410_CPUIRQ_OFFSET    (16)
+
+#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
+
+/* main cpu interrupts */
+#define IRQ_EINT0      S3C2410_IRQ(0)       /* 16 */
+#define IRQ_EINT1      S3C2410_IRQ(1)
+#define IRQ_EINT2      S3C2410_IRQ(2)
+#define IRQ_EINT3      S3C2410_IRQ(3)
+#define IRQ_EINT4t7    S3C2410_IRQ(4)       /* 20 */
+#define IRQ_EINT8t23   S3C2410_IRQ(5)
+#define IRQ_RESERVED6  S3C2410_IRQ(6)       /* for s3c2410 */
+#define IRQ_CAM        S3C2410_IRQ(6)       /* for s3c2440 */
+#define IRQ_BATT_FLT   S3C2410_IRQ(7)
+#define IRQ_TICK       S3C2410_IRQ(8)       /* 24 */
+#define IRQ_WDT        S3C2410_IRQ(9)
+#define IRQ_TIMER0     S3C2410_IRQ(10)
+#define IRQ_TIMER1     S3C2410_IRQ(11)
+#define IRQ_TIMER2     S3C2410_IRQ(12)
+#define IRQ_TIMER3     S3C2410_IRQ(13)
+#define IRQ_TIMER4     S3C2410_IRQ(14)
+#define IRQ_UART2      S3C2410_IRQ(15)
+#define IRQ_LCD        S3C2410_IRQ(16)      /* 32 */
+#define IRQ_DMA0       S3C2410_IRQ(17)
+#define IRQ_DMA1       S3C2410_IRQ(18)
+#define IRQ_DMA2       S3C2410_IRQ(19)
+#define IRQ_DMA3       S3C2410_IRQ(20)
+#define IRQ_SDI        S3C2410_IRQ(21)
+#define IRQ_SPI0       S3C2410_IRQ(22)
+#define IRQ_UART1      S3C2410_IRQ(23)
+#define IRQ_RESERVED24 S3C2410_IRQ(24)      /* 40 */
+#define IRQ_NFCON      S3C2410_IRQ(24)      /* for s3c2440 */
+#define IRQ_USBD       S3C2410_IRQ(25)
+#define IRQ_USBH       S3C2410_IRQ(26)
+#define IRQ_IIC        S3C2410_IRQ(27)
+#define IRQ_UART0      S3C2410_IRQ(28)      /* 44 */
+#define IRQ_SPI1       S3C2410_IRQ(29)
+#define IRQ_RTC        S3C2410_IRQ(30)
+#define IRQ_ADCPARENT  S3C2410_IRQ(31)
+
+/* interrupts generated from the external interrupts sources */
+#define IRQ_EINT4      S3C2410_IRQ(32)     /* 48 */
+#define IRQ_EINT5      S3C2410_IRQ(33)
+#define IRQ_EINT6      S3C2410_IRQ(34)
+#define IRQ_EINT7      S3C2410_IRQ(35)
+#define IRQ_EINT8      S3C2410_IRQ(36)
+#define IRQ_EINT9      S3C2410_IRQ(37)
+#define IRQ_EINT10     S3C2410_IRQ(38)
+#define IRQ_EINT11     S3C2410_IRQ(39)
+#define IRQ_EINT12     S3C2410_IRQ(40)
+#define IRQ_EINT13     S3C2410_IRQ(41)
+#define IRQ_EINT14     S3C2410_IRQ(42)
+#define IRQ_EINT15     S3C2410_IRQ(43)
+#define IRQ_EINT16     S3C2410_IRQ(44)
+#define IRQ_EINT17     S3C2410_IRQ(45)
+#define IRQ_EINT18     S3C2410_IRQ(46)
+#define IRQ_EINT19     S3C2410_IRQ(47)
+#define IRQ_EINT20     S3C2410_IRQ(48)     /* 64 */
+#define IRQ_EINT21     S3C2410_IRQ(49)
+#define IRQ_EINT22     S3C2410_IRQ(50)
+#define IRQ_EINT23     S3C2410_IRQ(51)
+
+
+#define IRQ_EINT(x)    S3C2410_IRQ((x >= 4) ? (IRQ_EINT4 + (x) - 4) : (S3C2410_IRQ(0) + (x)))
+
+#define IRQ_LCD_FIFO   S3C2410_IRQ(52)
+#define IRQ_LCD_FRAME  S3C2410_IRQ(53)
+
+/* IRQs for the interal UARTs, and ADC
+ * these need to be ordered in number of appearance in the
+ * SUBSRC mask register
+*/
+#define IRQ_S3CUART_RX0  S3C2410_IRQ(54)   /* 70 */
+#define IRQ_S3CUART_TX0  S3C2410_IRQ(55)   /* 71 */
+#define IRQ_S3CUART_ERR0 S3C2410_IRQ(56)
+
+#define IRQ_S3CUART_RX1  S3C2410_IRQ(57)
+#define IRQ_S3CUART_TX1  S3C2410_IRQ(58)
+#define IRQ_S3CUART_ERR1 S3C2410_IRQ(59)
+
+#define IRQ_S3CUART_RX2  S3C2410_IRQ(60)
+#define IRQ_S3CUART_TX2  S3C2410_IRQ(61)
+#define IRQ_S3CUART_ERR2 S3C2410_IRQ(62)
+
+#define IRQ_TC           S3C2410_IRQ(63)
+#define IRQ_ADC          S3C2410_IRQ(64)
+
+/* extra irqs for s3c2440 */
+
+#define IRQ_S3C2440_CAM_C       S3C2410_IRQ(65)
+#define IRQ_S3C2440_CAM_P       S3C2410_IRQ(66)
+#define IRQ_S3C2440_WDT         S3C2410_IRQ(67)
+#define IRQ_S3C2440_AC97        S3C2410_IRQ(68)
+
+#define NR_IRQS (IRQ_S3C2440_AC97+1)
+
+
+#endif /* __ASM_ARCH_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
new file mode 100644
index 000000000000..1833ea5c4220
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -0,0 +1,192 @@
+/* linux/include/asm-arm/arch-s3c2410/map.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  12-May-2003 BJD   Created file
+ *  06-Jan-2003 BJD   Linux 2.6.0 version, moved bast specifics out
+ *  10-Feb-2005 BJD   Added CAMIF definition from guillaume.gourat@nexvision.tv
+ *  10-Mar-2005 LCVR  Added support to S3C2400, changed {VA,SZ} names
+*/
+
+#ifndef __ASM_ARCH_MAP_H
+#define __ASM_ARCH_MAP_H
+
+/* we have a bit of a tight squeeze to fit all our registers from
+ * 0xF00000000 upwards, since we use all of the nGCS space in some
+ * capacity, and also need to fit the S3C2410 registers in as well...
+ *
+ * we try to ensure stuff like the IRQ registers are available for
+ * an single MOVS instruction (ie, only 8 bits of set data)
+ *
+ * Note, we are trying to remove some of these from the implementation
+ * as they are only useful to certain drivers...
+ */
+
+#ifndef __ASSEMBLY__
+#define S3C2410_ADDR(x)   ((void __iomem *)0xF0000000 + (x))
+#else
+#define S3C2410_ADDR(x)   (0xF0000000 + (x))
+#endif
+
+#define S3C2400_ADDR(x)   S3C2410_ADDR(x)
+
+/* interrupt controller is the first thing we put in, to make
+ * the assembly code for the irq detection easier
+ */
+#define S3C24XX_VA_IRQ     S3C2410_ADDR(0x00000000)
+#define S3C2400_PA_IRQ     (0x14400000)
+#define S3C2410_PA_IRQ     (0x4A000000)
+#define S3C24XX_SZ_IRQ     SZ_1M
+
+/* memory controller registers */
+#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
+#define S3C2400_PA_MEMCTRL (0x14000000)
+#define S3C2410_PA_MEMCTRL (0x48000000)
+#define S3C24XX_SZ_MEMCTRL SZ_1M
+
+/* USB host controller */
+#define S3C24XX_VA_USBHOST S3C2410_ADDR(0x00200000)
+#define S3C2400_PA_USBHOST (0x14200000)
+#define S3C2410_PA_USBHOST (0x49000000)
+#define S3C24XX_SZ_USBHOST SZ_1M
+
+/* DMA controller */
+#define S3C24XX_VA_DMA     S3C2410_ADDR(0x00300000)
+#define S3C2400_PA_DMA     (0x14600000)
+#define S3C2410_PA_DMA     (0x4B000000)
+#define S3C24XX_SZ_DMA     SZ_1M
+
+/* Clock and Power management */
+#define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00400000)
+#define S3C2400_PA_CLKPWR  (0x14800000)
+#define S3C2410_PA_CLKPWR  (0x4C000000)
+#define S3C24XX_SZ_CLKPWR  SZ_1M
+
+/* LCD controller */
+#define S3C24XX_VA_LCD     S3C2410_ADDR(0x00600000)
+#define S3C2400_PA_LCD     (0x14A00000)
+#define S3C2410_PA_LCD     (0x4D000000)
+#define S3C24XX_SZ_LCD     SZ_1M
+
+/* NAND flash controller */
+#define S3C24XX_VA_NAND    S3C2410_ADDR(0x00700000)
+#define S3C2410_PA_NAND    (0x4E000000)
+#define S3C24XX_SZ_NAND    SZ_1M
+
+/* MMC controller - available on the S3C2400 */
+#define S3C2400_VA_MMC     S3C2400_ADDR(0x00700000)
+#define S3C2400_PA_MMC     (0x15A00000)
+#define S3C2400_SZ_MMC     SZ_1M
+
+/* UARTs */
+#define S3C24XX_VA_UART    S3C2410_ADDR(0x00800000)
+#define S3C2400_PA_UART    (0x15000000)
+#define S3C2410_PA_UART    (0x50000000)
+#define S3C24XX_SZ_UART    SZ_1M
+
+/* Timers */
+#define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00900000)
+#define S3C2400_PA_TIMER   (0x15100000)
+#define S3C2410_PA_TIMER   (0x51000000)
+#define S3C24XX_SZ_TIMER   SZ_1M
+
+/* USB Device port */
+#define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00A00000)
+#define S3C2400_PA_USBDEV  (0x15200140)
+#define S3C2410_PA_USBDEV  (0x52000000)
+#define S3C24XX_SZ_USBDEV  SZ_1M
+
+/* Watchdog */
+#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00B00000)
+#define S3C2400_PA_WATCHDOG (0x15300000)
+#define S3C2410_PA_WATCHDOG (0x53000000)
+#define S3C24XX_SZ_WATCHDOG SZ_1M
+
+/* IIC hardware controller */
+#define S3C24XX_VA_IIC     S3C2410_ADDR(0x00C00000)
+#define S3C2400_PA_IIC     (0x15400000)
+#define S3C2410_PA_IIC     (0x54000000)
+#define S3C24XX_SZ_IIC     SZ_1M
+
+#define VA_IIC_BASE        (S3C24XX_VA_IIC)
+
+/* IIS controller */
+#define S3C24XX_VA_IIS     S3C2410_ADDR(0x00D00000)
+#define S3C2400_PA_IIS     (0x15508000)
+#define S3C2410_PA_IIS     (0x55000000)
+#define S3C24XX_SZ_IIS     SZ_1M
+
+/* GPIO ports */
+#define S3C24XX_VA_GPIO    S3C2410_ADDR(0x00E00000)
+#define S3C2400_PA_GPIO    (0x15600000)
+#define S3C2410_PA_GPIO    (0x56000000)
+#define S3C24XX_SZ_GPIO    SZ_1M
+
+/* RTC */
+#define S3C24XX_VA_RTC     S3C2410_ADDR(0x00F00000)
+#define S3C2400_PA_RTC     (0x15700040)
+#define S3C2410_PA_RTC     (0x57000000)
+#define S3C24XX_SZ_RTC     SZ_1M
+
+/* ADC */
+#define S3C24XX_VA_ADC     S3C2410_ADDR(0x01000000)
+#define S3C2400_PA_ADC     (0x15800000)
+#define S3C2410_PA_ADC     (0x58000000)
+#define S3C24XX_SZ_ADC     SZ_1M
+
+/* SPI */
+#define S3C24XX_VA_SPI     S3C2410_ADDR(0x01100000)
+#define S3C2400_PA_SPI     (0x15900000)
+#define S3C2410_PA_SPI     (0x59000000)
+#define S3C24XX_SZ_SPI     SZ_1M
+
+/* SDI */
+#define S3C24XX_VA_SDI     S3C2410_ADDR(0x01200000)
+#define S3C2410_PA_SDI     (0x5A000000)
+#define S3C24XX_SZ_SDI     SZ_1M
+
+/* CAMIF */
+#define S3C2440_PA_CAMIF   (0x4F000000)
+#define S3C2440_SZ_CAMIF   SZ_1M
+
+/* ISA style IO, for each machine to sort out mappings for, if it
+ * implements it. We reserve two 16M regions for ISA.
+ */
+
+#define S3C24XX_VA_ISA_WORD  S3C2410_ADDR(0x02000000)
+#define S3C24XX_VA_ISA_BYTE  S3C2410_ADDR(0x03000000)
+
+/* physical addresses of all the chip-select areas */
+
+#define S3C2410_CS0 (0x00000000)
+#define S3C2410_CS1 (0x08000000)
+#define S3C2410_CS2 (0x10000000)
+#define S3C2410_CS3 (0x18000000)
+#define S3C2410_CS4 (0x20000000)
+#define S3C2410_CS5 (0x28000000)
+#define S3C2410_CS6 (0x30000000)
+#define S3C2410_CS7 (0x38000000)
+
+#define S3C2410_SDRAM_PA    (S3C2410_CS6)
+
+#define S3C2400_CS0 (0x00000000)
+#define S3C2400_CS1 (0x02000000)
+#define S3C2400_CS2 (0x04000000)
+#define S3C2400_CS3 (0x06000000)
+#define S3C2400_CS4 (0x08000000)
+#define S3C2400_CS5 (0x0A000000)
+#define S3C2400_CS6 (0x0C000000)
+#define S3C2400_CS7 (0x0E000000)
+
+#define S3C2400_SDRAM_PA    (S3C2400_CS6)
+
+
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
new file mode 100644
index 000000000000..3380ab1d0749
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -0,0 +1,44 @@
+/*
+ *  linux/include/asm-arm/arch-s3c2410/memory.h
+ *
+ *  from linux/include/asm-arm/arch-rpc/memory.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   20-Oct-1996 RMK    Created
+ *   31-Dec-1997 RMK    Fixed definitions to reduce warnings
+ *   11-Jan-1998 RMK    Uninlined to reduce hits on cache
+ *   08-Feb-1998 RMK    Added __virt_to_bus and __bus_to_virt
+ *   21-Mar-1999 RMK    Renamed to memory.h
+ *               RMK    Added TASK_SIZE and PAGE_OFFSET
+ *   05-Apr-2004 BJD    Copied and altered for arch-s3c2410
+ *   17-Mar-2005 LCVR   Modified for S3C2400
+*/
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * DRAM starts at 0x30000000 for S3C2410/S3C2440
+ * and at 0x0C000000 for S3C2400
+ */
+#ifdef CONFIG_CPU_S3C2400
+#define PHYS_OFFSET     (0x0C000000UL)
+#else
+#define PHYS_OFFSET     (0x30000000UL)
+#endif
+
+/*
+ * These are exactly the same on the S3C2410 as the
+ * physical memory view.
+*/
+
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/arch-s3c2410/nand.h
new file mode 100644
index 000000000000..9148ac045b0d
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/nand.h
@@ -0,0 +1,48 @@
+/* linux/include/asm-arm/arch-s3c2410/nand.h
+ *
+ * (c) 2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - NAND device controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *      23-Sep-2004 BJD  Created file
+*/
+
+/* struct s3c2410_nand_set
+ *
+ * define an set of one or more nand chips registered with an unique mtd
+ *
+ * nr_chips      = number of chips in this set
+ * nr_partitions = number of partitions pointed to be partitoons (or zero)
+ * name          = name of set (optional)
+ * nr_map        = map for low-layer logical to physical chip numbers (option)
+ * partitions    = mtd partition list
+*/
+
+struct s3c2410_nand_set {
+        int                     nr_chips;
+        int                     nr_partitions;
+        char                    *name;
+        int                     *nr_map;
+        struct mtd_partition    *partitions;
+};
+
+struct s3c2410_platform_nand {
+        /* timing information for controller, all times in nanoseconds */
+
+        int     tacls;  /* time for active CLE/ALE to nWE/nOE */
+        int     twrph0; /* active time for nWE/nOE */
+        int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
+
+        int                     nr_sets;
+        struct s3c2410_nand_set *sets;
+
+        void                    (*select_chip)(struct s3c2410_nand_set *,
+                                               int chip);
+};
+
diff --git a/include/asm-arm/arch-s3c2410/otom-map.h b/include/asm-arm/arch-s3c2410/otom-map.h
new file mode 100644
index 000000000000..e40c93429854
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/otom-map.h
@@ -0,0 +1,30 @@
+/* linux/include/asm-arm/arch-s3c2410/otom-map.h
+ *
+ * (c) 2005 Guillaume GOURAT / NexVision
+ *          guillaume.gourat@nexvision.fr
+ *
+ * NexVision OTOM board memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* needs arch/map.h including with this */
+
+/* ok, we've used up to 0x01300000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space.
+ */
+
+#ifndef __ASM_ARCH_OTOMMAP_H
+#define __ASM_ARCH_OTOMMAP_H
+
+#define OTOM_PA_CS8900A_BASE       (S3C2410_CS3 + 0x01000000)   /* nGCS3 +0x01000000 */
+#define OTOM_VA_CS8900A_BASE       S3C2410_ADDR(0x04000000)             /* 0xF4000000 */
+
+/* physical offset addresses for the peripherals */
+
+#define OTOM_PA_FLASH0_BASE        (S3C2410_CS0)                                /* Bank 0 */
+
+#endif /* __ASM_ARCH_OTOMMAP_H */
diff --git a/include/asm-arm/arch-s3c2410/param.h b/include/asm-arm/arch-s3c2410/param.h
new file mode 100644
index 000000000000..483d3f149883
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/param.h
@@ -0,0 +1,27 @@
+/* linux/include/asm-arm/arch-s3c2410/param.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - Machine parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  02-Sep-2003 BJD  Created file
+ *  12-Mar-2004 BJD  Added include protection
+*/
+
+#ifndef __ASM_ARCH_PARAM_H
+#define __ASM_ARCH_PARAM_H
+
+/* we cannot get our timer down to 100Hz with the setup as is, but we can
+ * manage 200 clock ticks per second... if this is a problem, we can always
+ * add a software pre-scaler to the evil timer systems.
+*/
+
+#define HZ   200
+
+#endif /* __ASM_ARCH_PARAM_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/arch-s3c2410/regs-adc.h
new file mode 100644
index 000000000000..15bfc2f5754e
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-adc.h
@@ -0,0 +1,63 @@
+/* linux/include/asm/arch-s3c2410/regs-adc.h
+ *
+ * Copyright (c) 2004 Shannon Holland <holland@loser.net>
+ *
+ * This program is free software; yosu can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 ADC registers
+ *
+ *  Changelog:
+ *    27-09-2004     SAH     Created file
+*/
+
+#ifndef __ASM_ARCH_REGS_ADC_H
+#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
+
+#define S3C2410_ADCREG(x) (x)
+
+#define S3C2410_ADCCON     S3C2410_ADCREG(0x00)
+#define S3C2410_ADCTSC     S3C2410_ADCREG(0x04)
+#define S3C2410_ADCDLY     S3C2410_ADCREG(0x08)
+#define S3C2410_ADCDAT0    S3C2410_ADCREG(0x0C)
+#define S3C2410_ADCDAT1    S3C2410_ADCREG(0x10)
+
+
+/* ADCCON Register Bits */
+#define S3C2410_ADCCON_ECFLG            (1<<15)
+#define S3C2410_ADCCON_PRSCEN           (1<<14)
+#define S3C2410_ADCCON_PRSCVL(x)        (((x)&0xFF)<<6)
+#define S3C2410_ADCCON_PRSCVLMASK       (0xFF<<6)
+#define S3C2410_ADCCON_SELMUX(x)        (((x)&0x7)<<3)
+#define S3C2410_ADCCON_MUXMASK          (0x7<<3)
+#define S3C2410_ADCCON_STDBM            (1<<2)
+#define S3C2410_ADCCON_READ_START       (1<<1)
+#define S3C2410_ADCCON_ENABLE_START     (1<<0)
+#define S3C2410_ADCCON_STARTMASK        (0x3<<0)
+
+
+/* ADCTSC Register Bits */
+#define S3C2410_ADCTSC_YM_SEN           (1<<7)
+#define S3C2410_ADCTSC_YP_SEN           (1<<6)
+#define S3C2410_ADCTSC_XM_SEN           (1<<5)
+#define S3C2410_ADCTSC_XP_SEN           (1<<4)
+#define S3C2410_ADCTSC_PULL_UP_DISABLE  (1<<3)
+#define S3C2410_ADCTSC_AUTO_PST         (1<<2)
+#define S3C2410_ADCTSC_XY_PST           (0x3<<0)
+
+/* ADCDAT0 Bits */
+#define S3C2410_ADCDAT0_UPDOWN          (1<<15)
+#define S3C2410_ADCDAT0_AUTO_PST        (1<<14)
+#define S3C2410_ADCDAT0_XY_PST          (0x3<<12)
+#define S3C2410_ADCDAT0_XPDATA_MASK     (0x03FF)
+
+/* ADCDAT1 Bits */
+#define S3C2410_ADCDAT1_UPDOWN          (1<<15)
+#define S3C2410_ADCDAT1_AUTO_PST        (1<<14)
+#define S3C2410_ADCDAT1_XY_PST          (0x3<<12)
+#define S3C2410_ADCDAT1_YPDATA_MASK     (0x03FF)
+
+#endif /* __ASM_ARCH_REGS_ADC_H */
+
+
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
new file mode 100644
index 000000000000..e5e938b79acc
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -0,0 +1,122 @@
+/* linux/include/asm/arch-s3c2410/regs-clock.h
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 clock register definitions
+ *
+ *  Changelog:
+ *    18-Aug-2004 Ben Dooks         Added 2440 definitions
+ *    08-Aug-2004 Herbert Pötzl     Added CLKCON definitions
+ *    19-06-2003  Ben Dooks         Created file
+ *    12-03-2004  Ben Dooks         Updated include protection
+ *    29-Sep-2004 Ben Dooks         Fixed usage for assembly inclusion
+ *    10-Feb-2005 Ben Dooks         Fixed CAMDIVN address (Guillaume Gourat)
+ *    10-Mar-2005 Lucas Villa Real  Changed S3C2410_VA to S3C24XX_VA
+ */
+
+#ifndef __ASM_ARM_REGS_CLOCK
+#define __ASM_ARM_REGS_CLOCK "$Id: clock.h,v 1.4 2003/04/30 14:50:51 ben Exp $"
+
+#define S3C2410_CLKREG(x) ((x) + S3C24XX_VA_CLKPWR)
+
+#define S3C2410_PLLVAL(_m,_p,_s) ((_m) << 12 | ((_p) << 4) | ((_s)))
+
+#define S3C2410_LOCKTIME    S3C2410_CLKREG(0x00)
+#define S3C2410_MPLLCON     S3C2410_CLKREG(0x04)
+#define S3C2410_UPLLCON     S3C2410_CLKREG(0x08)
+#define S3C2410_CLKCON      S3C2410_CLKREG(0x0C)
+#define S3C2410_CLKSLOW     S3C2410_CLKREG(0x10)
+#define S3C2410_CLKDIVN     S3C2410_CLKREG(0x14)
+
+#define S3C2410_CLKCON_IDLE          (1<<2)
+#define S3C2410_CLKCON_POWER         (1<<3)
+#define S3C2410_CLKCON_NAND          (1<<4)
+#define S3C2410_CLKCON_LCDC          (1<<5)
+#define S3C2410_CLKCON_USBH          (1<<6)
+#define S3C2410_CLKCON_USBD          (1<<7)
+#define S3C2410_CLKCON_PWMT          (1<<8)
+#define S3C2410_CLKCON_SDI           (1<<9)
+#define S3C2410_CLKCON_UART0         (1<<10)
+#define S3C2410_CLKCON_UART1         (1<<11)
+#define S3C2410_CLKCON_UART2         (1<<12)
+#define S3C2410_CLKCON_GPIO          (1<<13)
+#define S3C2410_CLKCON_RTC           (1<<14)
+#define S3C2410_CLKCON_ADC           (1<<15)
+#define S3C2410_CLKCON_IIC           (1<<16)
+#define S3C2410_CLKCON_IIS           (1<<17)
+#define S3C2410_CLKCON_SPI           (1<<18)
+
+#define S3C2410_PLLCON_MDIVSHIFT     12
+#define S3C2410_PLLCON_PDIVSHIFT     4
+#define S3C2410_PLLCON_SDIVSHIFT     0
+#define S3C2410_PLLCON_MDIVMASK      ((1<<(1+(19-12)))-1)
+#define S3C2410_PLLCON_PDIVMASK      ((1<<5)-1)
+#define S3C2410_PLLCON_SDIVMASK      3
+
+/* DCLKCON register addresses in gpio.h */
+
+#define S3C2410_DCLKCON_DCLK0EN      (1<<0)
+#define S3C2410_DCLKCON_DCLK0_PCLK   (0<<1)
+#define S3C2410_DCLKCON_DCLK0_UCLK   (1<<1)
+#define S3C2410_DCLKCON_DCLK0_DIV(x) (((x) - 1 )<<4)
+#define S3C2410_DCLKCON_DCLK0_CMP(x) (((x) - 1 )<<8)
+
+#define S3C2410_DCLKCON_DCLK1EN      (1<<16)
+#define S3C2410_DCLKCON_DCLK1_PCLK   (0<<17)
+#define S3C2410_DCLKCON_DCLK1_UCLK   (1<<17)
+#define S3C2410_DCLKCON_DCLK1_DIV(x) (((x) - 1) <<20)
+
+#define S3C2410_CLKDIVN_PDIVN        (1<<0)
+#define S3C2410_CLKDIVN_HDIVN        (1<<1)
+
+#ifndef __ASSEMBLY__
+
+static inline unsigned int
+s3c2410_get_pll(int pllval, int baseclk)
+{
+        int mdiv, pdiv, sdiv;
+
+        mdiv = pllval >> S3C2410_PLLCON_MDIVSHIFT;
+        pdiv = pllval >> S3C2410_PLLCON_PDIVSHIFT;
+        sdiv = pllval >> S3C2410_PLLCON_SDIVSHIFT;
+
+        mdiv &= S3C2410_PLLCON_MDIVMASK;
+        pdiv &= S3C2410_PLLCON_PDIVMASK;
+        sdiv &= S3C2410_PLLCON_SDIVMASK;
+
+        return (baseclk * (mdiv + 8)) / ((pdiv + 2) << sdiv);
+}
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_CPU_S3C2440
+
+/* extra registers */
+#define S3C2440_CAMDIVN     S3C2410_CLKREG(0x18)
+
+#define S3C2440_CLKCON_CAMERA        (1<<19)
+#define S3C2440_CLKCON_AC97          (1<<20)
+
+#define S3C2440_CLKDIVN_PDIVN        (1<<0)
+#define S3C2440_CLKDIVN_HDIVN_MASK   (3<<1)
+#define S3C2440_CLKDIVN_HDIVN_1      (0<<1)
+#define S3C2440_CLKDIVN_HDIVN_2      (1<<1)
+#define S3C2440_CLKDIVN_HDIVN_4_8    (2<<1)
+#define S3C2440_CLKDIVN_HDIVN_3_6    (3<<1)
+#define S3C2440_CLKDIVN_UCLK         (1<<3)
+
+#define S3C2440_CAMDIVN_CAMCLK_MASK  (0xf<<0)
+#define S3C2440_CAMDIVN_CAMCLK_SEL   (1<<4)
+#define S3C2440_CAMDIVN_HCLK3_HALF   (1<<8)
+#define S3C2440_CAMDIVN_HCLK4_HALF   (1<<9)
+#define S3C2440_CAMDIVN_DVSEN        (1<<12)
+
+#endif /* CONFIG_CPU_S3C2440 */
+
+
+#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/include/asm-arm/arch-s3c2410/regs-dsc.h b/include/asm-arm/arch-s3c2410/regs-dsc.h
new file mode 100644
index 000000000000..a023b0434efe
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-dsc.h
@@ -0,0 +1,183 @@
+/* linux/include/asm/hardware/s3c2410/regs-dsc.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 Signal Drive Strength Control
+ *
+ *  Changelog:
+ *    11-Aug-2004     BJD     Created file
+ *    25-Aug-2004     BJD     Added the _SELECT_* defs for using with functions
+*/
+
+
+#ifndef __ASM_ARCH_REGS_DSC_H
+#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
+
+#ifdef CONFIG_CPU_S3C2440
+
+#define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
+#define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
+
+#define S3C2440_SELECT_DSC0 (0)
+#define S3C2440_SELECT_DSC1 (1<<31)
+
+#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
+
+#define S3C2440_DSC0_DISABLE    (1<<31)
+
+#define S3C2440_DSC0_ADDR       (S3C2440_SELECT_DSC0 | 8)
+#define S3C2440_DSC0_ADDR_12mA  (0<<8)
+#define S3C2440_DSC0_ADDR_10mA  (1<<8)
+#define S3C2440_DSC0_ADDR_8mA   (2<<8)
+#define S3C2440_DSC0_ADDR_6mA   (3<<8)
+#define S3C2440_DSC0_ADDR_MASK  (3<<8)
+
+/* D24..D31 */
+#define S3C2440_DSC0_DATA3      (S3C2440_SELECT_DSC0 | 6)
+#define S3C2440_DSC0_DATA3_12mA (0<<6)
+#define S3C2440_DSC0_DATA3_10mA (1<<6)
+#define S3C2440_DSC0_DATA3_8mA  (2<<6)
+#define S3C2440_DSC0_DATA3_6mA  (3<<6)
+#define S3C2440_DSC0_DATA3_MASK (3<<6)
+
+/* D16..D23 */
+#define S3C2440_DSC0_DATA2      (S3C2440_SELECT_DSC0 | 4)
+#define S3C2440_DSC0_DATA2_12mA (0<<4)
+#define S3C2440_DSC0_DATA2_10mA (1<<4)
+#define S3C2440_DSC0_DATA2_8mA  (2<<4)
+#define S3C2440_DSC0_DATA2_6mA  (3<<4)
+#define S3C2440_DSC0_DATA2_MASK (3<<4)
+
+/* D8..D15 */
+#define S3C2440_DSC0_DATA1      (S3C2440_SELECT_DSC0 | 2)
+#define S3C2440_DSC0_DATA1_12mA (0<<2)
+#define S3C2440_DSC0_DATA1_10mA (1<<2)
+#define S3C2440_DSC0_DATA1_8mA  (2<<2)
+#define S3C2440_DSC0_DATA1_6mA  (3<<2)
+#define S3C2440_DSC0_DATA1_MASK (3<<2)
+
+/* D0..D7 */
+#define S3C2440_DSC0_DATA0      (S3C2440_SELECT_DSC0 | 0)
+#define S3C2440_DSC0_DATA0_12mA (0<<0)
+#define S3C2440_DSC0_DATA0_10mA (1<<0)
+#define S3C2440_DSC0_DATA0_8mA  (2<<0)
+#define S3C2440_DSC0_DATA0_6mA  (3<<0)
+#define S3C2440_DSC0_DATA0_MASK (3<<0)
+
+#define S3C2440_DSC1_SCK1       (S3C2440_SELECT_DSC1 | 28)
+#define S3C2440_DSC1_SCK1_12mA  (0<<28)
+#define S3C2440_DSC1_SCK1_10mA  (1<<28)
+#define S3C2440_DSC1_SCK1_8mA   (2<<28)
+#define S3C2440_DSC1_SCK1_6mA   (3<<28)
+#define S3C2440_DSC1_SCK1_MASK  (3<<28)
+
+#define S3C2440_DSC1_SCK0       (S3C2440_SELECT_DSC1 | 26)
+#define S3C2440_DSC1_SCK0_12mA  (0<<26)
+#define S3C2440_DSC1_SCK0_10mA  (1<<26)
+#define S3C2440_DSC1_SCK0_8mA   (2<<26)
+#define S3C2440_DSC1_SCK0_6mA   (3<<26)
+#define S3C2440_DSC1_SCK0_MASK  (3<<26)
+
+#define S3C2440_DSC1_SCKE       (S3C2440_SELECT_DSC1 | 24)
+#define S3C2440_DSC1_SCKE_10mA  (0<<24)
+#define S3C2440_DSC1_SCKE_8mA   (1<<24)
+#define S3C2440_DSC1_SCKE_6mA   (2<<24)
+#define S3C2440_DSC1_SCKE_4mA   (3<<24)
+#define S3C2440_DSC1_SCKE_MASK  (3<<24)
+
+/* SDRAM nRAS/nCAS */
+#define S3C2440_DSC1_SDR        (S3C2440_SELECT_DSC1 | 22)
+#define S3C2440_DSC1_SDR_10mA   (0<<22)
+#define S3C2440_DSC1_SDR_8mA    (1<<22)
+#define S3C2440_DSC1_SDR_6mA    (2<<22)
+#define S3C2440_DSC1_SDR_4mA    (3<<22)
+#define S3C2440_DSC1_SDR_MASK   (3<<22)
+
+/* NAND Flash Controller */
+#define S3C2440_DSC1_NFC        (S3C2440_SELECT_DSC1 | 20)
+#define S3C2440_DSC1_NFC_10mA   (0<<20)
+#define S3C2440_DSC1_NFC_8mA    (1<<20)
+#define S3C2440_DSC1_NFC_6mA    (2<<20)
+#define S3C2440_DSC1_NFC_4mA    (3<<20)
+#define S3C2440_DSC1_NFC_MASK   (3<<20)
+
+/* nBE[0..3] */
+#define S3C2440_DSC1_nBE        (S3C2440_SELECT_DSC1 | 18)
+#define S3C2440_DSC1_nBE_10mA   (0<<18)
+#define S3C2440_DSC1_nBE_8mA    (1<<18)
+#define S3C2440_DSC1_nBE_6mA    (2<<18)
+#define S3C2440_DSC1_nBE_4mA    (3<<18)
+#define S3C2440_DSC1_nBE_MASK   (3<<18)
+
+#define S3C2440_DSC1_WOE        (S3C2440_SELECT_DSC1 | 16)
+#define S3C2440_DSC1_WOE_10mA   (0<<16)
+#define S3C2440_DSC1_WOE_8mA    (1<<16)
+#define S3C2440_DSC1_WOE_6mA    (2<<16)
+#define S3C2440_DSC1_WOE_4mA    (3<<16)
+#define S3C2440_DSC1_WOE_MASK   (3<<16)
+
+#define S3C2440_DSC1_CS7        (S3C2440_SELECT_DSC1 | 14)
+#define S3C2440_DSC1_CS7_10mA   (0<<14)
+#define S3C2440_DSC1_CS7_8mA    (1<<14)
+#define S3C2440_DSC1_CS7_6mA    (2<<14)
+#define S3C2440_DSC1_CS7_4mA    (3<<14)
+#define S3C2440_DSC1_CS7_MASK   (3<<14)
+
+#define S3C2440_DSC1_CS6        (S3C2440_SELECT_DSC1 | 12)
+#define S3C2440_DSC1_CS6_10mA   (0<<12)
+#define S3C2440_DSC1_CS6_8mA    (1<<12)
+#define S3C2440_DSC1_CS6_6mA    (2<<12)
+#define S3C2440_DSC1_CS6_4mA    (3<<12)
+#define S3C2440_DSC1_CS6_MASK   (3<<12)
+
+#define S3C2440_DSC1_CS5        (S3C2440_SELECT_DSC1 | 10)
+#define S3C2440_DSC1_CS5_10mA   (0<<10)
+#define S3C2440_DSC1_CS5_8mA    (1<<10)
+#define S3C2440_DSC1_CS5_6mA    (2<<10)
+#define S3C2440_DSC1_CS5_4mA    (3<<10)
+#define S3C2440_DSC1_CS5_MASK   (3<<10)
+
+#define S3C2440_DSC1_CS4        (S3C2440_SELECT_DSC1 | 8)
+#define S3C2440_DSC1_CS4_10mA   (0<<8)
+#define S3C2440_DSC1_CS4_8mA    (1<<8)
+#define S3C2440_DSC1_CS4_6mA    (2<<8)
+#define S3C2440_DSC1_CS4_4mA    (3<<8)
+#define S3C2440_DSC1_CS4_MASK   (3<<8)
+
+#define S3C2440_DSC1_CS3        (S3C2440_SELECT_DSC1 | 6)
+#define S3C2440_DSC1_CS3_10mA   (0<<6)
+#define S3C2440_DSC1_CS3_8mA    (1<<6)
+#define S3C2440_DSC1_CS3_6mA    (2<<6)
+#define S3C2440_DSC1_CS3_4mA    (3<<6)
+#define S3C2440_DSC1_CS3_MASK   (3<<6)
+
+#define S3C2440_DSC1_CS2        (S3C2440_SELECT_DSC1 | 4)
+#define S3C2440_DSC1_CS2_10mA   (0<<4)
+#define S3C2440_DSC1_CS2_8mA    (1<<4)
+#define S3C2440_DSC1_CS2_6mA    (2<<4)
+#define S3C2440_DSC1_CS2_4mA    (3<<4)
+#define S3C2440_DSC1_CS2_MASK   (3<<4)
+
+#define S3C2440_DSC1_CS1        (S3C2440_SELECT_DSC1 | 2)
+#define S3C2440_DSC1_CS1_10mA   (0<<2)
+#define S3C2440_DSC1_CS1_8mA    (1<<2)
+#define S3C2440_DSC1_CS1_6mA    (2<<2)
+#define S3C2440_DSC1_CS1_4mA    (3<<2)
+#define S3C2440_DSC1_CS1_MASK   (3<<2)
+
+#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0
+#define S3C2440_DSC1_CS0_10mA   (0<<0)
+#define S3C2440_DSC1_CS0_8mA    (1<<0)
+#define S3C2440_DSC1_CS0_6mA    (2<<0)
+#define S3C2440_DSC1_CS0_4mA    (3<<0)
+#define S3C2440_DSC1_CS0_MASK   (3<<0)
+
+#endif /* CONFIG_CPU_S3C2440 */
+
+#endif  /* __ASM_ARCH_REGS_DSC_H */
+
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
new file mode 100644
index 000000000000..2053cbacffc3
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -0,0 +1,831 @@
+/* linux/include/asm/hardware/s3c2410/regs-gpio.h
+ *
+ * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk>
+ *                         http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 GPIO register definitions
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    23-06-2003     BJD     Updated GSTATUS registers
+ *    12-03-2004     BJD     Updated include protection
+ *    20-07-2004     BJD     Added GPIO pin numbers, added Port A definitions
+ *    04-10-2004     BJD     Fixed number of bugs, added EXT IRQ filter defs
+ *    17-10-2004     BJD     Added GSTATUS1 register definitions
+ *    18-11-2004     BJD     Fixed definitions of GPE3, GPE4, GPE5 and GPE6
+ *    18-11-2004     BJD     Added S3C2440 AC97 controls
+ *    10-Mar-2005    LCVR    Changed S3C2410_VA to S3C24XX_VA
+ *    28-Mar-2005    LCVR    Fixed definition of GPB10
+*/
+
+
+#ifndef __ASM_ARCH_REGS_GPIO_H
+#define __ASM_ARCH_REGS_GPIO_H "$Id: gpio.h,v 1.5 2003/05/19 12:51:08 ben Exp $"
+
+#define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
+
+#define S3C2410_GPIO_BANKA   (32*0)
+#define S3C2410_GPIO_BANKB   (32*1)
+#define S3C2410_GPIO_BANKC   (32*2)
+#define S3C2410_GPIO_BANKD   (32*3)
+#define S3C2410_GPIO_BANKE   (32*4)
+#define S3C2410_GPIO_BANKF   (32*5)
+#define S3C2410_GPIO_BANKG   (32*6)
+#define S3C2410_GPIO_BANKH   (32*7)
+
+#define S3C2410_GPIO_BASE(pin)   ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
+#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
+
+/* general configuration options */
+
+#define S3C2410_GPIO_LEAVE   (0xFFFFFFFF)
+
+/* configure GPIO ports A..G */
+
+#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
+
+/* port A - 22bits, zero in bit X makes pin X output
+ * 1 makes port special function, this is default
+*/
+#define S3C2410_GPACON     S3C2410_GPIOREG(0x00)
+#define S3C2410_GPADAT     S3C2410_GPIOREG(0x04)
+
+#define S3C2410_GPA0         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
+#define S3C2410_GPA0_OUT     (0<<0)
+#define S3C2410_GPA0_ADDR0   (1<<0)
+
+#define S3C2410_GPA1         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 1)
+#define S3C2410_GPA1_OUT     (0<<1)
+#define S3C2410_GPA1_ADDR16  (1<<1)
+
+#define S3C2410_GPA2         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 2)
+#define S3C2410_GPA2_OUT     (0<<2)
+#define S3C2410_GPA2_ADDR17  (1<<2)
+
+#define S3C2410_GPA3         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 3)
+#define S3C2410_GPA3_OUT     (0<<3)
+#define S3C2410_GPA3_ADDR18  (1<<3)
+
+#define S3C2410_GPA4         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 4)
+#define S3C2410_GPA4_OUT     (0<<4)
+#define S3C2410_GPA4_ADDR19  (1<<4)
+
+#define S3C2410_GPA5         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 5)
+#define S3C2410_GPA5_OUT     (0<<5)
+#define S3C2410_GPA5_ADDR20  (1<<5)
+
+#define S3C2410_GPA6         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 6)
+#define S3C2410_GPA6_OUT     (0<<6)
+#define S3C2410_GPA6_ADDR21  (1<<6)
+
+#define S3C2410_GPA7         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 7)
+#define S3C2410_GPA7_OUT     (0<<7)
+#define S3C2410_GPA7_ADDR22  (1<<7)
+
+#define S3C2410_GPA8         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 8)
+#define S3C2410_GPA8_OUT     (0<<8)
+#define S3C2410_GPA8_ADDR23  (1<<8)
+
+#define S3C2410_GPA9         S3C2410_GPIONO(S3C2410_GPIO_BANKA, 9)
+#define S3C2410_GPA9_OUT     (0<<9)
+#define S3C2410_GPA9_ADDR24  (1<<9)
+
+#define S3C2410_GPA10        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
+#define S3C2410_GPA10_OUT    (0<<10)
+#define S3C2410_GPA10_ADDR25 (1<<10)
+
+#define S3C2410_GPA11        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
+#define S3C2410_GPA11_OUT    (0<<11)
+#define S3C2410_GPA11_ADDR26 (1<<11)
+
+#define S3C2410_GPA12        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
+#define S3C2410_GPA12_OUT    (0<<12)
+#define S3C2410_GPA12_nGCS1  (1<<12)
+
+#define S3C2410_GPA13        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
+#define S3C2410_GPA13_OUT    (0<<13)
+#define S3C2410_GPA13_nGCS2  (1<<13)
+
+#define S3C2410_GPA14        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
+#define S3C2410_GPA14_OUT    (0<<14)
+#define S3C2410_GPA14_nGCS3  (1<<14)
+
+#define S3C2410_GPA15        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
+#define S3C2410_GPA15_OUT    (0<<15)
+#define S3C2410_GPA15_nGCS4  (1<<15)
+
+#define S3C2410_GPA16        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
+#define S3C2410_GPA16_OUT    (0<<16)
+#define S3C2410_GPA16_nGCS5  (1<<16)
+
+#define S3C2410_GPA17        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
+#define S3C2410_GPA17_OUT    (0<<17)
+#define S3C2410_GPA17_CLE    (1<<17)
+
+#define S3C2410_GPA18        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
+#define S3C2410_GPA18_OUT    (0<<18)
+#define S3C2410_GPA18_ALE    (1<<18)
+
+#define S3C2410_GPA19        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 19)
+#define S3C2410_GPA19_OUT    (0<<19)
+#define S3C2410_GPA19_nFWE   (1<<19)
+
+#define S3C2410_GPA20        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 20)
+#define S3C2410_GPA20_OUT    (0<<20)
+#define S3C2410_GPA20_nFRE   (1<<20)
+
+#define S3C2410_GPA21        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 21)
+#define S3C2410_GPA21_OUT    (0<<21)
+#define S3C2410_GPA21_nRSTOUT (1<<21)
+
+#define S3C2410_GPA22        S3C2410_GPIONO(S3C2410_GPIO_BANKA, 22)
+#define S3C2410_GPA22_OUT    (0<<22)
+#define S3C2410_GPA22_nFCE   (1<<22)
+
+/* 0x08 and 0x0c are reserved */
+
+/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
+ *   00 = input, 01 = output, 10=special function, 11=reserved
+ * bit 0,1 = pin 0, 2,3= pin 1...
+ *
+ * CPBUP = pull up resistor control, 1=disabled, 0=enabled
+*/
+
+#define S3C2410_GPBCON     S3C2410_GPIOREG(0x10)
+#define S3C2410_GPBDAT     S3C2410_GPIOREG(0x14)
+#define S3C2410_GPBUP      S3C2410_GPIOREG(0x18)
+
+/* no i/o pin in port b can have value 3! */
+
+#define S3C2410_GPB0         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
+#define S3C2410_GPB0_INP     (0x00 << 0)
+#define S3C2410_GPB0_OUTP    (0x01 << 0)
+#define S3C2410_GPB0_TOUT0   (0x02 << 0)
+
+#define S3C2410_GPB1         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
+#define S3C2410_GPB1_INP     (0x00 << 2)
+#define S3C2410_GPB1_OUTP    (0x01 << 2)
+#define S3C2410_GPB1_TOUT1   (0x02 << 2)
+
+#define S3C2410_GPB2         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
+#define S3C2410_GPB2_INP     (0x00 << 4)
+#define S3C2410_GPB2_OUTP    (0x01 << 4)
+#define S3C2410_GPB2_TOUT2   (0x02 << 4)
+
+#define S3C2410_GPB3         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
+#define S3C2410_GPB3_INP     (0x00 << 6)
+#define S3C2410_GPB3_OUTP    (0x01 << 6)
+#define S3C2410_GPB3_TOUT3   (0x02 << 6)
+
+#define S3C2410_GPB4         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
+#define S3C2410_GPB4_INP     (0x00 << 8)
+#define S3C2410_GPB4_OUTP    (0x01 << 8)
+#define S3C2410_GPB4_TCLK0   (0x02 << 8)
+#define S3C2410_GPB4_MASK    (0x03 << 8)
+
+#define S3C2410_GPB5         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
+#define S3C2410_GPB5_INP     (0x00 << 10)
+#define S3C2410_GPB5_OUTP    (0x01 << 10)
+#define S3C2410_GPB5_nXBACK  (0x02 << 10)
+
+#define S3C2410_GPB6         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
+#define S3C2410_GPB6_INP     (0x00 << 12)
+#define S3C2410_GPB6_OUTP    (0x01 << 12)
+#define S3C2410_GPB6_nXBREQ  (0x02 << 12)
+
+#define S3C2410_GPB7         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
+#define S3C2410_GPB7_INP     (0x00 << 14)
+#define S3C2410_GPB7_OUTP    (0x01 << 14)
+#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
+
+#define S3C2410_GPB8         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
+#define S3C2410_GPB8_INP     (0x00 << 16)
+#define S3C2410_GPB8_OUTP    (0x01 << 16)
+#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
+
+#define S3C2410_GPB9         S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
+#define S3C2410_GPB9_INP     (0x00 << 18)
+#define S3C2410_GPB9_OUTP    (0x01 << 18)
+#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
+
+#define S3C2410_GPB10        S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
+#define S3C2410_GPB10_INP    (0x00 << 20)
+#define S3C2410_GPB10_OUTP   (0x01 << 20)
+#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
+
+/* Port C consits of 16 GPIO/Special function
+ *
+ * almost identical setup to port b, but the special functions are mostly
+ * to do with the video system's sync/etc.
+*/
+
+#define S3C2410_GPCCON     S3C2410_GPIOREG(0x20)
+#define S3C2410_GPCDAT     S3C2410_GPIOREG(0x24)
+#define S3C2410_GPCUP      S3C2410_GPIOREG(0x28)
+
+#define S3C2410_GPC0            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
+#define S3C2410_GPC0_INP        (0x00 << 0)
+#define S3C2410_GPC0_OUTP       (0x01 << 0)
+#define S3C2410_GPC0_LEND       (0x02 << 0)
+
+#define S3C2410_GPC1            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
+#define S3C2410_GPC1_INP        (0x00 << 2)
+#define S3C2410_GPC1_OUTP       (0x01 << 2)
+#define S3C2410_GPC1_VCLK       (0x02 << 2)
+
+#define S3C2410_GPC2            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
+#define S3C2410_GPC2_INP        (0x00 << 4)
+#define S3C2410_GPC2_OUTP       (0x01 << 4)
+#define S3C2410_GPC2_VLINE      (0x02 << 4)
+
+#define S3C2410_GPC3            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
+#define S3C2410_GPC3_INP        (0x00 << 6)
+#define S3C2410_GPC3_OUTP       (0x01 << 6)
+#define S3C2410_GPC3_VFRAME     (0x02 << 6)
+
+#define S3C2410_GPC4            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
+#define S3C2410_GPC4_INP        (0x00 << 8)
+#define S3C2410_GPC4_OUTP       (0x01 << 8)
+#define S3C2410_GPC4_VM         (0x02 << 8)
+
+#define S3C2410_GPC5            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
+#define S3C2410_GPC5_INP        (0x00 << 10)
+#define S3C2410_GPC5_OUTP       (0x01 << 10)
+#define S3C2410_GPC5_LCDVF0     (0x02 << 10)
+
+#define S3C2410_GPC6            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
+#define S3C2410_GPC6_INP        (0x00 << 12)
+#define S3C2410_GPC6_OUTP       (0x01 << 12)
+#define S3C2410_GPC6_LCDVF1     (0x02 << 12)
+
+#define S3C2410_GPC7            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
+#define S3C2410_GPC7_INP        (0x00 << 14)
+#define S3C2410_GPC7_OUTP       (0x01 << 14)
+#define S3C2410_GPC7_LCDVF2     (0x02 << 14)
+
+#define S3C2410_GPC8            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
+#define S3C2410_GPC8_INP        (0x00 << 16)
+#define S3C2410_GPC8_OUTP       (0x01 << 16)
+#define S3C2410_GPC8_VD0        (0x02 << 16)
+
+#define S3C2410_GPC9            S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
+#define S3C2410_GPC9_INP        (0x00 << 18)
+#define S3C2410_GPC9_OUTP       (0x01 << 18)
+#define S3C2410_GPC9_VD1        (0x02 << 18)
+
+#define S3C2410_GPC10           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
+#define S3C2410_GPC10_INP       (0x00 << 20)
+#define S3C2410_GPC10_OUTP      (0x01 << 20)
+#define S3C2410_GPC10_VD2       (0x02 << 20)
+
+#define S3C2410_GPC11           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
+#define S3C2410_GPC11_INP       (0x00 << 22)
+#define S3C2410_GPC11_OUTP      (0x01 << 22)
+#define S3C2410_GPC11_VD3       (0x02 << 22)
+
+#define S3C2410_GPC12           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
+#define S3C2410_GPC12_INP       (0x00 << 24)
+#define S3C2410_GPC12_OUTP      (0x01 << 24)
+#define S3C2410_GPC12_VD4       (0x02 << 24)
+
+#define S3C2410_GPC13           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
+#define S3C2410_GPC13_INP       (0x00 << 26)
+#define S3C2410_GPC13_OUTP      (0x01 << 26)
+#define S3C2410_GPC13_VD5       (0x02 << 26)
+
+#define S3C2410_GPC14           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
+#define S3C2410_GPC14_INP       (0x00 << 28)
+#define S3C2410_GPC14_OUTP      (0x01 << 28)
+#define S3C2410_GPC14_VD6       (0x02 << 28)
+
+#define S3C2410_GPC15           S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
+#define S3C2410_GPC15_INP       (0x00 << 30)
+#define S3C2410_GPC15_OUTP      (0x01 << 30)
+#define S3C2410_GPC15_VD7       (0x02 << 30)
+
+/* Port D consists of 16 GPIO/Special function
+ *
+ * almost identical setup to port b, but the special functions are mostly
+ * to do with the video system's data.
+*/
+
+#define S3C2410_GPDCON     S3C2410_GPIOREG(0x30)
+#define S3C2410_GPDDAT     S3C2410_GPIOREG(0x34)
+#define S3C2410_GPDUP      S3C2410_GPIOREG(0x38)
+
+#define S3C2410_GPD0            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
+#define S3C2410_GPD0_INP        (0x00 << 0)
+#define S3C2410_GPD0_OUTP       (0x01 << 0)
+#define S3C2410_GPD0_VD8        (0x02 << 0)
+
+#define S3C2410_GPD1            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
+#define S3C2410_GPD1_INP        (0x00 << 2)
+#define S3C2410_GPD1_OUTP       (0x01 << 2)
+#define S3C2410_GPD1_VD9        (0x02 << 2)
+
+#define S3C2410_GPD2            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
+#define S3C2410_GPD2_INP        (0x00 << 4)
+#define S3C2410_GPD2_OUTP       (0x01 << 4)
+#define S3C2410_GPD2_VD10       (0x02 << 4)
+
+#define S3C2410_GPD3            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
+#define S3C2410_GPD3_INP        (0x00 << 6)
+#define S3C2410_GPD3_OUTP       (0x01 << 6)
+#define S3C2410_GPD3_VD11       (0x02 << 6)
+
+#define S3C2410_GPD4            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
+#define S3C2410_GPD4_INP        (0x00 << 8)
+#define S3C2410_GPD4_OUTP       (0x01 << 8)
+#define S3C2410_GPD4_VD12       (0x02 << 8)
+
+#define S3C2410_GPD5            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
+#define S3C2410_GPD5_INP        (0x00 << 10)
+#define S3C2410_GPD5_OUTP       (0x01 << 10)
+#define S3C2410_GPD5_VD13       (0x02 << 10)
+
+#define S3C2410_GPD6            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
+#define S3C2410_GPD6_INP        (0x00 << 12)
+#define S3C2410_GPD6_OUTP       (0x01 << 12)
+#define S3C2410_GPD6_VD14       (0x02 << 12)
+
+#define S3C2410_GPD7            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
+#define S3C2410_GPD7_INP        (0x00 << 14)
+#define S3C2410_GPD7_OUTP       (0x01 << 14)
+#define S3C2410_GPD7_VD15       (0x02 << 14)
+
+#define S3C2410_GPD8            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
+#define S3C2410_GPD8_INP        (0x00 << 16)
+#define S3C2410_GPD8_OUTP       (0x01 << 16)
+#define S3C2410_GPD8_VD16       (0x02 << 16)
+
+#define S3C2410_GPD9            S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
+#define S3C2410_GPD9_INP        (0x00 << 18)
+#define S3C2410_GPD9_OUTP       (0x01 << 18)
+#define S3C2410_GPD9_VD17       (0x02 << 18)
+
+#define S3C2410_GPD10           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
+#define S3C2410_GPD10_INP       (0x00 << 20)
+#define S3C2410_GPD10_OUTP      (0x01 << 20)
+#define S3C2410_GPD10_VD18      (0x02 << 20)
+
+#define S3C2410_GPD11           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
+#define S3C2410_GPD11_INP       (0x00 << 22)
+#define S3C2410_GPD11_OUTP      (0x01 << 22)
+#define S3C2410_GPD11_VD19      (0x02 << 22)
+
+#define S3C2410_GPD12           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 12)
+#define S3C2410_GPD12_INP       (0x00 << 24)
+#define S3C2410_GPD12_OUTP      (0x01 << 24)
+#define S3C2410_GPD12_VD20      (0x02 << 24)
+
+#define S3C2410_GPD13           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 13)
+#define S3C2410_GPD13_INP       (0x00 << 26)
+#define S3C2410_GPD13_OUTP      (0x01 << 26)
+#define S3C2410_GPD13_VD21      (0x02 << 26)
+
+#define S3C2410_GPD14           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 14)
+#define S3C2410_GPD14_INP       (0x00 << 28)
+#define S3C2410_GPD14_OUTP      (0x01 << 28)
+#define S3C2410_GPD14_VD22      (0x02 << 28)
+
+#define S3C2410_GPD15           S3C2410_GPIONO(S3C2410_GPIO_BANKD, 15)
+#define S3C2410_GPD15_INP       (0x00 << 30)
+#define S3C2410_GPD15_OUTP      (0x01 << 30)
+#define S3C2410_GPD15_VD23      (0x02 << 30)
+
+/* Port E consists of 16 GPIO/Special function
+ *
+ * again, the same as port B, but dealing with I2S, SDI, and
+ * more miscellaneous functions
+*/
+
+#define S3C2410_GPECON     S3C2410_GPIOREG(0x40)
+#define S3C2410_GPEDAT     S3C2410_GPIOREG(0x44)
+#define S3C2410_GPEUP      S3C2410_GPIOREG(0x48)
+
+#define S3C2410_GPE0           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
+#define S3C2410_GPE0_INP       (0x00 << 0)
+#define S3C2410_GPE0_OUTP      (0x01 << 0)
+#define S3C2410_GPE0_I2SLRCK   (0x02 << 0)
+#define S3C2410_GPE0_MASK      (0x03 << 0)
+
+#define S3C2410_GPE1           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
+#define S3C2410_GPE1_INP       (0x00 << 2)
+#define S3C2410_GPE1_OUTP      (0x01 << 2)
+#define S3C2410_GPE1_I2SSCLK   (0x02 << 2)
+#define S3C2410_GPE1_MASK      (0x03 << 2)
+
+#define S3C2410_GPE2           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
+#define S3C2410_GPE2_INP       (0x00 << 4)
+#define S3C2410_GPE2_OUTP      (0x01 << 4)
+#define S3C2410_GPE2_CDCLK     (0x02 << 4)
+
+#define S3C2410_GPE3           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
+#define S3C2410_GPE3_INP       (0x00 << 6)
+#define S3C2410_GPE3_OUTP      (0x01 << 6)
+#define S3C2410_GPE3_I2SSDI    (0x02 << 6)
+#define S3C2410_GPE3_nSS0      (0x03 << 6)
+#define S3C2410_GPE3_MASK      (0x03 << 6)
+
+#define S3C2410_GPE4           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 4)
+#define S3C2410_GPE4_INP       (0x00 << 8)
+#define S3C2410_GPE4_OUTP      (0x01 << 8)
+#define S3C2410_GPE4_I2SSDO    (0x02 << 8)
+#define S3C2410_GPE4_I2SSDI    (0x03 << 8)
+#define S3C2410_GPE4_MASK      (0x03 << 8)
+
+#define S3C2410_GPE5           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 5)
+#define S3C2410_GPE5_INP       (0x00 << 10)
+#define S3C2410_GPE5_OUTP      (0x01 << 10)
+#define S3C2410_GPE5_SDCLK     (0x02 << 10)
+
+#define S3C2410_GPE6           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
+#define S3C2410_GPE6_INP       (0x00 << 12)
+#define S3C2410_GPE6_OUTP      (0x01 << 12)
+#define S3C2410_GPE6_SDCMD     (0x02 << 12)
+
+#define S3C2410_GPE7           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
+#define S3C2410_GPE7_INP       (0x00 << 14)
+#define S3C2410_GPE7_OUTP      (0x01 << 14)
+#define S3C2410_GPE7_SDDAT0    (0x02 << 14)
+
+#define S3C2410_GPE8           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
+#define S3C2410_GPE8_INP       (0x00 << 16)
+#define S3C2410_GPE8_OUTP      (0x01 << 16)
+#define S3C2410_GPE8_SDDAT1    (0x02 << 16)
+
+#define S3C2410_GPE9           S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
+#define S3C2410_GPE9_INP       (0x00 << 18)
+#define S3C2410_GPE9_OUTP      (0x01 << 18)
+#define S3C2410_GPE9_SDDAT2    (0x02 << 18)
+
+#define S3C2410_GPE10          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
+#define S3C2410_GPE10_INP      (0x00 << 20)
+#define S3C2410_GPE10_OUTP     (0x01 << 20)
+#define S3C2410_GPE10_SDDAT3   (0x02 << 20)
+
+#define S3C2410_GPE11          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
+#define S3C2410_GPE11_INP      (0x00 << 22)
+#define S3C2410_GPE11_OUTP     (0x01 << 22)
+#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
+
+#define S3C2410_GPE12          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
+#define S3C2410_GPE12_INP      (0x00 << 24)
+#define S3C2410_GPE12_OUTP     (0x01 << 24)
+#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
+
+#define S3C2410_GPE13          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 13)
+#define S3C2410_GPE13_INP      (0x00 << 26)
+#define S3C2410_GPE13_OUTP     (0x01 << 26)
+#define S3C2410_GPE13_SPICLK0  (0x02 << 26)
+
+#define S3C2410_GPE14          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 14)
+#define S3C2410_GPE14_INP      (0x00 << 28)
+#define S3C2410_GPE14_OUTP     (0x01 << 28)
+#define S3C2410_GPE14_IICSCL   (0x02 << 28)
+#define S3C2410_GPE14_MASK     (0x03 << 28)
+
+#define S3C2410_GPE15          S3C2410_GPIONO(S3C2410_GPIO_BANKE, 15)
+#define S3C2410_GPE15_INP      (0x00 << 30)
+#define S3C2410_GPE15_OUTP     (0x01 << 30)
+#define S3C2410_GPE15_IICSDA   (0x02 << 30)
+#define S3C2410_GPE15_MASK     (0x03 << 30)
+
+#define S3C2440_GPE0_ACSYNC    (0x03 << 0)
+#define S3C2440_GPE1_ACBITCLK  (0x03 << 2)
+#define S3C2440_GPE2_ACRESET   (0x03 << 4)
+#define S3C2440_GPE3_ACIN      (0x03 << 6)
+#define S3C2440_GPE4_ACOUT     (0x03 << 8)
+
+#define S3C2410_GPE_PUPDIS(x)  (1<<(x))
+
+/* Port F consists of 8 GPIO/Special function
+ *
+ * GPIO / interrupt inputs
+ *
+ * GPFCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2410_GPFCON     S3C2410_GPIOREG(0x50)
+#define S3C2410_GPFDAT     S3C2410_GPIOREG(0x54)
+#define S3C2410_GPFUP      S3C2410_GPIOREG(0x58)
+
+#define S3C2410_GPF0        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
+#define S3C2410_GPF0_INP    (0x00 << 0)
+#define S3C2410_GPF0_OUTP   (0x01 << 0)
+#define S3C2410_GPF0_EINT0  (0x02 << 0)
+
+#define S3C2410_GPF1        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
+#define S3C2410_GPF1_INP    (0x00 << 2)
+#define S3C2410_GPF1_OUTP   (0x01 << 2)
+#define S3C2410_GPF1_EINT1  (0x02 << 2)
+
+#define S3C2410_GPF2        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
+#define S3C2410_GPF2_INP    (0x00 << 4)
+#define S3C2410_GPF2_OUTP   (0x01 << 4)
+#define S3C2410_GPF2_EINT2  (0x02 << 4)
+
+#define S3C2410_GPF3        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
+#define S3C2410_GPF3_INP    (0x00 << 6)
+#define S3C2410_GPF3_OUTP   (0x01 << 6)
+#define S3C2410_GPF3_EINT3  (0x02 << 6)
+
+#define S3C2410_GPF4        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
+#define S3C2410_GPF4_INP    (0x00 << 8)
+#define S3C2410_GPF4_OUTP   (0x01 << 8)
+#define S3C2410_GPF4_EINT4  (0x02 << 8)
+
+#define S3C2410_GPF5        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
+#define S3C2410_GPF5_INP    (0x00 << 10)
+#define S3C2410_GPF5_OUTP   (0x01 << 10)
+#define S3C2410_GPF5_EINT5  (0x02 << 10)
+
+#define S3C2410_GPF6        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
+#define S3C2410_GPF6_INP    (0x00 << 12)
+#define S3C2410_GPF6_OUTP   (0x01 << 12)
+#define S3C2410_GPF6_EINT6  (0x02 << 12)
+
+#define S3C2410_GPF7        S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
+#define S3C2410_GPF7_INP    (0x00 << 14)
+#define S3C2410_GPF7_OUTP   (0x01 << 14)
+#define S3C2410_GPF7_EINT7  (0x02 << 14)
+
+/* Port G consists of 8 GPIO/IRQ/Special function
+ *
+ * GPGCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2410_GPGCON     S3C2410_GPIOREG(0x60)
+#define S3C2410_GPGDAT     S3C2410_GPIOREG(0x64)
+#define S3C2410_GPGUP      S3C2410_GPIOREG(0x68)
+
+#define S3C2410_GPG0          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
+#define S3C2410_GPG0_INP      (0x00 << 0)
+#define S3C2410_GPG0_OUTP     (0x01 << 0)
+#define S3C2410_GPG0_EINT8    (0x02 << 0)
+
+#define S3C2410_GPG1          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
+#define S3C2410_GPG1_INP      (0x00 << 2)
+#define S3C2410_GPG1_OUTP     (0x01 << 2)
+#define S3C2410_GPG1_EINT9    (0x02 << 2)
+
+#define S3C2410_GPG2          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
+#define S3C2410_GPG2_INP      (0x00 << 4)
+#define S3C2410_GPG2_OUTP     (0x01 << 4)
+#define S3C2410_GPG2_EINT10   (0x02 << 4)
+
+#define S3C2410_GPG3          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
+#define S3C2410_GPG3_INP      (0x00 << 6)
+#define S3C2410_GPG3_OUTP     (0x01 << 6)
+#define S3C2410_GPG3_EINT11   (0x02 << 6)
+
+#define S3C2410_GPG4          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
+#define S3C2410_GPG4_INP      (0x00 << 8)
+#define S3C2410_GPG4_OUTP     (0x01 << 8)
+#define S3C2410_GPG4_EINT12   (0x02 << 8)
+#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
+
+#define S3C2410_GPG5          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
+#define S3C2410_GPG5_INP      (0x00 << 10)
+#define S3C2410_GPG5_OUTP     (0x01 << 10)
+#define S3C2410_GPG5_EINT13   (0x02 << 10)
+#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
+
+#define S3C2410_GPG6          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
+#define S3C2410_GPG6_INP      (0x00 << 12)
+#define S3C2410_GPG6_OUTP     (0x01 << 12)
+#define S3C2410_GPG6_EINT14   (0x02 << 12)
+#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
+
+#define S3C2410_GPG7          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
+#define S3C2410_GPG7_INP      (0x00 << 14)
+#define S3C2410_GPG7_OUTP     (0x01 << 14)
+#define S3C2410_GPG7_EINT15   (0x02 << 14)
+#define S3C2410_GPG7_SPICLK1  (0x03 << 14)
+
+#define S3C2410_GPG8          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
+#define S3C2410_GPG8_INP      (0x00 << 16)
+#define S3C2410_GPG8_OUTP     (0x01 << 16)
+#define S3C2410_GPG8_EINT16   (0x02 << 16)
+
+#define S3C2410_GPG9          S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
+#define S3C2410_GPG9_INP      (0x00 << 18)
+#define S3C2410_GPG9_OUTP     (0x01 << 18)
+#define S3C2410_GPG9_EINT17   (0x02 << 18)
+
+#define S3C2410_GPG10         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
+#define S3C2410_GPG10_INP     (0x00 << 20)
+#define S3C2410_GPG10_OUTP    (0x01 << 20)
+#define S3C2410_GPG10_EINT18  (0x02 << 20)
+
+#define S3C2410_GPG11         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 11)
+#define S3C2410_GPG11_INP     (0x00 << 22)
+#define S3C2410_GPG11_OUTP    (0x01 << 22)
+#define S3C2410_GPG11_EINT19  (0x02 << 22)
+#define S3C2410_GPG11_TCLK1   (0x03 << 22)
+
+#define S3C2410_GPG12         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 12)
+#define S3C2410_GPG12_INP     (0x00 << 24)
+#define S3C2410_GPG12_OUTP    (0x01 << 24)
+#define S3C2410_GPG12_EINT20  (0x02 << 24)
+#define S3C2410_GPG12_XMON    (0x03 << 24)
+
+#define S3C2410_GPG13         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
+#define S3C2410_GPG13_INP     (0x00 << 26)
+#define S3C2410_GPG13_OUTP    (0x01 << 26)
+#define S3C2410_GPG13_EINT21  (0x02 << 26)
+#define S3C2410_GPG13_nXPON   (0x03 << 26)
+
+#define S3C2410_GPG14         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 14)
+#define S3C2410_GPG14_INP     (0x00 << 28)
+#define S3C2410_GPG14_OUTP    (0x01 << 28)
+#define S3C2410_GPG14_EINT22  (0x02 << 28)
+#define S3C2410_GPG14_YMON    (0x03 << 28)
+
+#define S3C2410_GPG15         S3C2410_GPIONO(S3C2410_GPIO_BANKG, 15)
+#define S3C2410_GPG15_INP     (0x00 << 30)
+#define S3C2410_GPG15_OUTP    (0x01 << 30)
+#define S3C2410_GPG15_EINT23  (0x02 << 30)
+#define S3C2410_GPG15_nYPON   (0x03 << 30)
+
+
+#define S3C2410_GPG_PUPDIS(x)  (1<<(x))
+
+/* Port H consists of11 GPIO/serial/Misc pins
+ *
+ * GPGCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2410_GPHCON     S3C2410_GPIOREG(0x70)
+#define S3C2410_GPHDAT     S3C2410_GPIOREG(0x74)
+#define S3C2410_GPHUP      S3C2410_GPIOREG(0x78)
+
+#define S3C2410_GPH0        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 0)
+#define S3C2410_GPH0_INP    (0x00 << 0)
+#define S3C2410_GPH0_OUTP   (0x01 << 0)
+#define S3C2410_GPH0_nCTS0  (0x02 << 0)
+
+#define S3C2410_GPH1        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 1)
+#define S3C2410_GPH1_INP    (0x00 << 2)
+#define S3C2410_GPH1_OUTP   (0x01 << 2)
+#define S3C2410_GPH1_nRTS0  (0x02 << 2)
+
+#define S3C2410_GPH2        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 2)
+#define S3C2410_GPH2_INP    (0x00 << 4)
+#define S3C2410_GPH2_OUTP   (0x01 << 4)
+#define S3C2410_GPH2_TXD0   (0x02 << 4)
+
+#define S3C2410_GPH3        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 3)
+#define S3C2410_GPH3_INP    (0x00 << 6)
+#define S3C2410_GPH3_OUTP   (0x01 << 6)
+#define S3C2410_GPH3_RXD0   (0x02 << 6)
+
+#define S3C2410_GPH4        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 4)
+#define S3C2410_GPH4_INP    (0x00 << 8)
+#define S3C2410_GPH4_OUTP   (0x01 << 8)
+#define S3C2410_GPH4_TXD1   (0x02 << 8)
+
+#define S3C2410_GPH5        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 5)
+#define S3C2410_GPH5_INP    (0x00 << 10)
+#define S3C2410_GPH5_OUTP   (0x01 << 10)
+#define S3C2410_GPH5_RXD1   (0x02 << 10)
+
+#define S3C2410_GPH6        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 6)
+#define S3C2410_GPH6_INP    (0x00 << 12)
+#define S3C2410_GPH6_OUTP   (0x01 << 12)
+#define S3C2410_GPH6_TXD2   (0x02 << 12)
+#define S3C2410_GPH6_nRTS1  (0x03 << 12)
+
+#define S3C2410_GPH7        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 7)
+#define S3C2410_GPH7_INP    (0x00 << 14)
+#define S3C2410_GPH7_OUTP   (0x01 << 14)
+#define S3C2410_GPH7_RXD2   (0x02 << 14)
+#define S3C2410_GPH7_nCTS1  (0x03 << 14)
+
+#define S3C2410_GPH8        S3C2410_GPIONO(S3C2410_GPIO_BANKH, 8)
+#define S3C2410_GPH8_INP    (0x00 << 16)
+#define S3C2410_GPH8_OUTP   (0x01 << 16)
+#define S3C2410_GPH8_UCLK   (0x02 << 16)
+
+#define S3C2410_GPH9          S3C2410_GPIONO(S3C2410_GPIO_BANKH, 9)
+#define S3C2410_GPH9_INP      (0x00 << 18)
+#define S3C2410_GPH9_OUTP     (0x01 << 18)
+#define S3C2410_GPH9_CLKOUT0  (0x02 << 18)
+
+#define S3C2410_GPH10         S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
+#define S3C2410_GPH10_INP     (0x00 << 20)
+#define S3C2410_GPH10_OUTP    (0x01 << 20)
+#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
+
+/* miscellaneous control */
+
+#define S3C2410_MISCCR     S3C2410_GPIOREG(0x80)
+#define S3C2410_DCLKCON    S3C2410_GPIOREG(0x84)
+
+/* see clock.h for dclk definitions */
+
+/* pullup control on databus */
+#define S3C2410_MISCCR_SPUCR_HEN    (0)
+#define S3C2410_MISCCR_SPUCR_HDIS   (1<<0)
+#define S3C2410_MISCCR_SPUCR_LEN    (0)
+#define S3C2410_MISCCR_SPUCR_LDIS   (1<<1)
+
+#define S3C2410_MISCCR_USBDEV       (0)
+#define S3C2410_MISCCR_USBHOST      (1<<3)
+
+#define S3C2410_MISCCR_CLK0_MPLL    (0<<4)
+#define S3C2410_MISCCR_CLK0_UPLL    (1<<4)
+#define S3C2410_MISCCR_CLK0_FCLK    (2<<4)
+#define S3C2410_MISCCR_CLK0_HCLK    (3<<4)
+#define S3C2410_MISCCR_CLK0_PCLK    (4<<4)
+#define S3C2410_MISCCR_CLK0_DCLK0   (5<<4)
+
+#define S3C2410_MISCCR_CLK1_MPLL    (0<<8)
+#define S3C2410_MISCCR_CLK1_UPLL    (1<<8)
+#define S3C2410_MISCCR_CLK1_FCLK    (2<<8)
+#define S3C2410_MISCCR_CLK1_HCLK    (3<<8)
+#define S3C2410_MISCCR_CLK1_PCLK    (4<<8)
+#define S3C2410_MISCCR_CLK1_DCLK1   (5<<8)
+
+#define S3C2410_MISCCR_USBSUSPND0   (1<<12)
+#define S3C2410_MISCCR_USBSUSPND1   (1<<13)
+
+#define S3C2410_MISCCR_nRSTCON      (1<<16)
+
+#define S3C2410_MISCCR_nEN_SCLK0    (1<<17)
+#define S3C2410_MISCCR_nEN_SCLK1    (1<<18)
+#define S3C2410_MISCCR_nEN_SCLKE    (1<<19)
+#define S3C2410_MISCCR_SDSLEEP      (7<<17)
+
+/* external interrupt control... */
+/* S3C2410_EXTINT0 -> irq sense control for EINT0..EINT7
+ * S3C2410_EXTINT1 -> irq sense control for EINT8..EINT15
+ * S3C2410_EXTINT2 -> irq sense control for EINT16..EINT23
+ *
+ * note S3C2410_EXTINT2 has filtering options for EINT16..EINT23
+ *
+ * Samsung datasheet p9-25
+*/
+
+#define S3C2410_EXTINT0    S3C2410_GPIOREG(0x88)
+#define S3C2410_EXTINT1    S3C2410_GPIOREG(0x8C)
+#define S3C2410_EXTINT2    S3C2410_GPIOREG(0x90)
+
+/* values for S3C2410_EXTINT0/1/2 */
+#define S3C2410_EXTINT_LOWLEV    (0x00)
+#define S3C2410_EXTINT_HILEV     (0x01)
+#define S3C2410_EXTINT_FALLEDGE  (0x02)
+#define S3C2410_EXTINT_RISEEDGE  (0x04)
+#define S3C2410_EXTINT_BOTHEDGE  (0x06)
+
+/* interrupt filtering conrrol for EINT16..EINT23 */
+#define S3C2410_EINFLT0    S3C2410_GPIOREG(0x94)
+#define S3C2410_EINFLT1    S3C2410_GPIOREG(0x98)
+#define S3C2410_EINFLT2    S3C2410_GPIOREG(0x9C)
+#define S3C2410_EINFLT3    S3C2410_GPIOREG(0xA0)
+
+/* values for interrupt filtering */
+#define S3C2410_EINTFLT_PCLK            (0x00)
+#define S3C2410_EINTFLT_EXTCLK          (1<<7)
+#define S3C2410_EINTFLT_WIDTHMSK(x)     ((x) & 0x3f)
+
+/* removed EINTxxxx defs from here, not meant for this */
+
+/* GSTATUS have miscellaneous information in them
+ *
+ */
+
+#define S3C2410_GSTATUS0   S3C2410_GPIOREG(0x0AC)
+#define S3C2410_GSTATUS1   S3C2410_GPIOREG(0x0B0)
+#define S3C2410_GSTATUS2   S3C2410_GPIOREG(0x0B4)
+#define S3C2410_GSTATUS3   S3C2410_GPIOREG(0x0B8)
+#define S3C2410_GSTATUS4   S3C2410_GPIOREG(0x0BC)
+
+#define S3C2410_GSTATUS0_nWAIT     (1<<3)
+#define S3C2410_GSTATUS0_NCON      (1<<2)
+#define S3C2410_GSTATUS0_RnB       (1<<1)
+#define S3C2410_GSTATUS0_nBATTFLT  (1<<0)
+
+#define S3C2410_GSTATUS1_IDMASK    (0xffff0000)
+#define S3C2410_GSTATUS1_2410      (0x32410000)
+#define S3C2410_GSTATUS1_2440      (0x32440000)
+
+#define S3C2410_GSTATUS2_WTRESET   (1<<2)
+#define S3C2410_GSTATUS2_OFFRESET  (1<<1)
+#define S3C2410_GSTATUS2_PONRESET  (1<<0)
+
+#endif  /* __ASM_ARCH_REGS_GPIO_H */
+
diff --git a/include/asm-arm/arch-s3c2410/regs-gpioj.h b/include/asm-arm/arch-s3c2410/regs-gpioj.h
new file mode 100644
index 000000000000..3ad2324acc39
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-gpioj.h
@@ -0,0 +1,101 @@
+/* linux/include/asm/hardware/s3c2410/regs-gpioj.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2440 GPIO J register definitions
+ *
+ *  Changelog:
+ *    11-Aug-2004     BJD     Created file
+ *    10-Feb-2005     BJD     Fix GPJ12 definition (Guillaume Gourat)
+*/
+
+
+#ifndef __ASM_ARCH_REGS_GPIOJ_H
+#define __ASM_ARCH_REGS_GPIOJ_H "gpioj"
+
+/* Port J consists of 13 GPIO/Camera pins
+ *
+ * GPJCON has 2 bits for each of the input pins on port F
+ *   00 = 0 input, 1 output, 2 Camera
+ *
+ * pull up works like all other ports.
+*/
+
+#define S3C2440_GPIO_BANKJ  (416)
+
+#define S3C2440_GPJCON      S3C2410_GPIOREG(0xd0)
+#define S3C2440_GPJDAT      S3C2410_GPIOREG(0xd4)
+#define S3C2440_GPJUP       S3C2410_GPIOREG(0xd8)
+
+#define S3C2440_GPJ0            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 0)
+#define S3C2440_GPJ0_INP        (0x00 << 0)
+#define S3C2440_GPJ0_OUTP       (0x01 << 0)
+#define S3C2440_GPJ0_CAMDATA0   (0x02 << 0)
+
+#define S3C2440_GPJ1            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 1)
+#define S3C2440_GPJ1_INP        (0x00 << 2)
+#define S3C2440_GPJ1_OUTP       (0x01 << 2)
+#define S3C2440_GPJ1_CAMDATA1   (0x02 << 2)
+
+#define S3C2440_GPJ2            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 2)
+#define S3C2440_GPJ2_INP        (0x00 << 4)
+#define S3C2440_GPJ2_OUTP       (0x01 << 4)
+#define S3C2440_GPJ2_CAMDATA2   (0x02 << 4)
+
+#define S3C2440_GPJ3            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 3)
+#define S3C2440_GPJ3_INP        (0x00 << 6)
+#define S3C2440_GPJ3_OUTP       (0x01 << 6)
+#define S3C2440_GPJ3_CAMDATA3   (0x02 << 6)
+
+#define S3C2440_GPJ4            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 4)
+#define S3C2440_GPJ4_INP        (0x00 << 8)
+#define S3C2440_GPJ4_OUTP       (0x01 << 8)
+#define S3C2440_GPJ4_CAMDATA4   (0x02 << 8)
+
+#define S3C2440_GPJ5            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 5)
+#define S3C2440_GPJ5_INP        (0x00 << 10)
+#define S3C2440_GPJ5_OUTP       (0x01 << 10)
+#define S3C2440_GPJ5_CAMDATA5   (0x02 << 10)
+
+#define S3C2440_GPJ6            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 6)
+#define S3C2440_GPJ6_INP        (0x00 << 12)
+#define S3C2440_GPJ6_OUTP       (0x01 << 12)
+#define S3C2440_GPJ6_CAMDATA6   (0x02 << 12)
+
+#define S3C2440_GPJ7            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 7)
+#define S3C2440_GPJ7_INP        (0x00 << 14)
+#define S3C2440_GPJ7_OUTP       (0x01 << 14)
+#define S3C2440_GPJ7_CAMDATA7   (0x02 << 14)
+
+#define S3C2440_GPJ8            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 8)
+#define S3C2440_GPJ8_INP        (0x00 << 16)
+#define S3C2440_GPJ8_OUTP       (0x01 << 16)
+#define S3C2440_GPJ8_CAMPCLK    (0x02 << 16)
+
+#define S3C2440_GPJ9            S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 9)
+#define S3C2440_GPJ9_INP        (0x00 << 18)
+#define S3C2440_GPJ9_OUTP       (0x01 << 18)
+#define S3C2440_GPJ9_CAMVSYNC   (0x02 << 18)
+
+#define S3C2440_GPJ10           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 10)
+#define S3C2440_GPJ10_INP       (0x00 << 20)
+#define S3C2440_GPJ10_OUTP      (0x01 << 20)
+#define S3C2440_GPJ10_CAMHREF   (0x02 << 20)
+
+#define S3C2440_GPJ11           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 11)
+#define S3C2440_GPJ11_INP       (0x00 << 22)
+#define S3C2440_GPJ11_OUTP      (0x01 << 22)
+#define S3C2440_GPJ11_CAMCLKOUT (0x02 << 22)
+
+#define S3C2440_GPJ12           S3C2410_GPIONO(S3C2440_GPIO_BANKJ, 12)
+#define S3C2440_GPJ12_INP       (0x00 << 24)
+#define S3C2440_GPJ12_OUTP      (0x01 << 24)
+#define S3C2440_GPJ12_CAMRESET  (0x02 << 24)
+
+#endif  /* __ASM_ARCH_REGS_GPIOJ_H */
+
diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/arch-s3c2410/regs-iic.h
new file mode 100644
index 000000000000..fed3288e2046
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-iic.h
@@ -0,0 +1,60 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 I2C Controller
+ *
+ *  Changelog:
+ *      03-Oct-2004  BJD  Initial include for Linux
+ *      08-Nov-2004  BJD  Added S3C2440 filter register
+*/
+
+#ifndef __ASM_ARCH_REGS_IIC_H
+#define __ASM_ARCH_REGS_IIC_H __FILE__
+
+/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
+
+#define S3C2410_IICREG(x) (x)
+
+#define S3C2410_IICCON    S3C2410_IICREG(0x00)
+#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
+#define S3C2410_IICADD    S3C2410_IICREG(0x08)
+#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
+#define S3C2440_IICLC     S3C2410_IICREG(0x10)
+
+#define S3C2410_IICCON_ACKEN            (1<<7)
+#define S3C2410_IICCON_TXDIV_16         (0<<6)
+#define S3C2410_IICCON_TXDIV_512        (1<<6)
+#define S3C2410_IICCON_IRQEN            (1<<5)
+#define S3C2410_IICCON_IRQPEND          (1<<4)
+#define S3C2410_IICCON_SCALE(x)         ((x)&15)
+#define S3C2410_IICCON_SCALEMASK        (0xf)
+
+#define S3C2410_IICSTAT_MASTER_RX       (2<<6)
+#define S3C2410_IICSTAT_MASTER_TX       (3<<6)
+#define S3C2410_IICSTAT_SLAVE_RX        (0<<6)
+#define S3C2410_IICSTAT_SLAVE_TX        (1<<6)
+#define S3C2410_IICSTAT_MODEMASK        (3<<6)
+
+#define S3C2410_IICSTAT_START           (1<<5)
+#define S3C2410_IICSTAT_BUSBUSY         (1<<5)
+#define S3C2410_IICSTAT_TXRXEN          (1<<4)
+#define S3C2410_IICSTAT_ARBITR          (1<<3)
+#define S3C2410_IICSTAT_ASSLAVE         (1<<2)
+#define S3C2410_IICSTAT_ADDR0           (1<<1)
+#define S3C2410_IICSTAT_LASTBIT         (1<<0)
+
+#define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
+#define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
+#define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
+#define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
+#define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
+
+#define S3C2410_IICLC_FILTER_ON         (1<<2)
+
+#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/arch-s3c2410/regs-iis.h
new file mode 100644
index 000000000000..7ae8e1f45bc1
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-iis.h
@@ -0,0 +1,72 @@
+/* linux/include/asm/arch-s3c2410/regs-iis.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 IIS register definition
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    26-06-2003     BJD     Finished off definitions for register addresses
+ *    12-03-2004     BJD     Updated include protection
+ *    07-03-2005     BJD     Added FIFO size flags and S3C2440 MPLL
+ */
+
+#ifndef __ASM_ARCH_REGS_IIS_H
+#define __ASM_ARCH_REGS_IIS_H
+
+#define S3C2410_IISCON   (0x00)
+
+#define S3C2440_IISCON_MPLL       (1<<9)
+#define S3C2410_IISCON_LRINDEX    (1<<8)
+#define S3C2410_IISCON_TXFIFORDY  (1<<7)
+#define S3C2410_IISCON_RXFIFORDY  (1<<6)
+#define S3C2410_IISCON_TXDMAEN    (1<<5)
+#define S3C2410_IISCON_RXDMAEN    (1<<4)
+#define S3C2410_IISCON_TXIDLE     (1<<3)
+#define S3C2410_IISCON_RXIDLE     (1<<2)
+#define S3C2410_IISCON_IISEN      (1<<0)
+
+#define S3C2410_IISMOD   (0x04)
+
+#define S3C2410_IISMOD_SLAVE      (1<<8)
+#define S3C2410_IISMOD_NOXFER     (0<<6)
+#define S3C2410_IISMOD_RXMODE     (1<<6)
+#define S3C2410_IISMOD_TXMODE     (2<<6)
+#define S3C2410_IISMOD_TXRXMODE   (3<<6)
+#define S3C2410_IISMOD_LR_LLOW    (0<<5)
+#define S3C2410_IISMOD_LR_RLOW    (1<<5)
+#define S3C2410_IISMOD_IIS        (0<<4)
+#define S3C2410_IISMOD_MSB        (1<<4)
+#define S3C2410_IISMOD_8BIT       (0<<3)
+#define S3C2410_IISMOD_16BIT      (1<<3)
+#define S3C2410_IISMOD_BITMASK    (1<<3)
+#define S3C2410_IISMOD_256FS      (0<<1)
+#define S3C2410_IISMOD_384FS      (1<<1)
+#define S3C2410_IISMOD_16FS       (0<<0)
+#define S3C2410_IISMOD_32FS       (1<<0)
+#define S3C2410_IISMOD_48FS       (2<<0)
+
+#define S3C2410_IISPSR          (0x08)
+#define S3C2410_IISPSR_INTMASK  (31<<5)
+#define S3C2410_IISPSR_INTSHIFT (5)
+#define S3C2410_IISPSR_EXTMASK  (31<<0)
+#define S3C2410_IISPSR_EXTSHFIT (0)
+
+#define S3C2410_IISFCON  (0x0c)
+
+#define S3C2410_IISFCON_TXDMA     (1<<15)
+#define S3C2410_IISFCON_RXDMA     (1<<14)
+#define S3C2410_IISFCON_TXENABLE  (1<<13)
+#define S3C2410_IISFCON_RXENABLE  (1<<12)
+#define S3C2410_IISFCON_TXMASK    (0x3f << 6)
+#define S3C2410_IISFCON_TXSHIFT   (6)
+#define S3C2410_IISFCON_RXMASK    (0x3f)
+#define S3C2410_IISFCON_RXSHIFT   (0)
+
+#define S3C2410_IISFIFO  (0x10)
+#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-irq.h b/include/asm-arm/arch-s3c2410/regs-irq.h
new file mode 100644
index 000000000000..24b7292df79e
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-irq.h
@@ -0,0 +1,44 @@
+/* linux/include/asm/arch-s3c2410/regs-irq.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    12-03-2004     BJD     Updated include protection
+ *    10-03-2005     LCVR    Changed S3C2410_VA to S3C24XX_VA
+ */
+
+
+#ifndef ___ASM_ARCH_REGS_IRQ_H
+#define ___ASM_ARCH_REGS_IRQ_H "$Id: irq.h,v 1.3 2003/03/25 21:29:06 ben Exp $"
+
+/* interrupt controller */
+
+#define S3C2410_IRQREG(x)   ((x) + S3C24XX_VA_IRQ)
+#define S3C2410_EINTREG(x)  ((x) + S3C24XX_VA_GPIO)
+
+#define S3C2410_SRCPND         S3C2410_IRQREG(0x000)
+#define S3C2410_INTMOD         S3C2410_IRQREG(0x004)
+#define S3C2410_INTMSK         S3C2410_IRQREG(0x008)
+#define S3C2410_PRIORITY       S3C2410_IRQREG(0x00C)
+#define S3C2410_INTPND         S3C2410_IRQREG(0x010)
+#define S3C2410_INTOFFSET      S3C2410_IRQREG(0x014)
+#define S3C2410_SUBSRCPND      S3C2410_IRQREG(0x018)
+#define S3C2410_INTSUBMSK      S3C2410_IRQREG(0x01C)
+
+/* mask: 0=enable, 1=disable
+ * 1 bit EINT, 4=EINT4, 23=EINT23
+ * EINT0,1,2,3 are not handled here.
+*/
+
+#define S3C2410_EINTMASK       S3C2410_EINTREG(0x0A4)
+#define S3C2410_EINTPEND       S3C2410_EINTREG(0X0A8)
+
+#endif /* ___ASM_ARCH_REGS_IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
new file mode 100644
index 000000000000..7f882ea92b2a
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -0,0 +1,114 @@
+/* linux/include/asm/arch-s3c2410/regs-lcd.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *
+ *
+ *  Changelog:
+ *    12-06-2003     BJD     Created file
+ *    26-06-2003     BJD     Updated LCDCON register definitions
+ *    12-03-2004     BJD     Updated include protection
+ *    10-03-2005     LCVR    Changed S3C2410_VA to S3C24XX_VA
+*/
+
+
+#ifndef ___ASM_ARCH_REGS_LCD_H
+#define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
+
+#define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD)
+
+/* LCD control registers */
+#define S3C2410_LCDCON1     S3C2410_LCDREG(0x00)
+#define S3C2410_LCDCON2     S3C2410_LCDREG(0x04)
+#define S3C2410_LCDCON3     S3C2410_LCDREG(0x08)
+#define S3C2410_LCDCON4     S3C2410_LCDREG(0x0C)
+#define S3C2410_LCDCON5     S3C2410_LCDREG(0x10)
+
+#define S3C2410_LCDCON1_CLKVAL(x)  ((x) << 8)
+#define S3C2410_LCDCON1_MMODE      (1<<7)
+#define S3C2410_LCDCON1_DSCAN4     (0<<5)
+#define S3C2410_LCDCON1_STN4       (1<<5)
+#define S3C2410_LCDCON1_STN8       (2<<5)
+#define S3C2410_LCDCON1_TFT        (3<<5)
+
+#define S3C2410_LCDCON1_STN1BPP    (0<<1)
+#define S3C2410_LCDCON1_STN2GREY   (1<<1)
+#define S3C2410_LCDCON1_STN4GREY   (2<<1)
+#define S3C2410_LCDCON1_STN8BPP    (3<<1)
+#define S3C2410_LCDCON1_STN12BPP   (4<<1)
+
+#define S3C2410_LCDCON1_TFT1BPP    (8<<1)
+#define S3C2410_LCDCON1_TFT2BPP    (9<<1)
+#define S3C2410_LCDCON1_TFT4BPP    (10<<1)
+#define S3C2410_LCDCON1_TFT8BPP    (11<<1)
+#define S3C2410_LCDCON1_TFT16BPP   (12<<1)
+#define S3C2410_LCDCON1_TFT24BPP   (13<<1)
+
+#define S3C2410_LCDCON1_ENVID      (1)
+
+#define S3C2410_LCDCON2_VBPD(x)     ((x) << 24)
+#define S3C2410_LCDCON2_LINEVAL(x)  ((x) << 14)
+#define S3C2410_LCDCON2_VFPD(x)     ((x) << 6)
+#define S3C2410_LCDCON2_VSPW(x)     ((x) << 0)
+
+#define S3C2410_LCDCON3_HBPD(x)     ((x) << 19)
+#define S3C2410_LCDCON3_WDLY(x)     ((x) << 19)
+#define S3C2410_LCDCON3_HOZVAL(x)   ((x) << 8)
+#define S3C2410_LCDCON3_HFPD(x)     ((x) << 0)
+#define S3C2410_LCDCON3_LINEBLANK(x)((x) << 0)
+
+#define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
+#define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
+#define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
+
+#define S3C2410_LCDCON5_BPP24BL     (1<<12)
+#define S3C2410_LCDCON5_FRM565      (1<<11)
+#define S3C2410_LCDCON5_INVVCLK     (1<<10)
+#define S3C2410_LCDCON5_INVVLINE    (1<<9)
+#define S3C2410_LCDCON5_INVVFRAME   (1<<8)
+#define S3C2410_LCDCON5_INVVD       (1<<7)
+#define S3C2410_LCDCON5_INVVDEN     (1<<6)
+#define S3C2410_LCDCON5_INVPWREN    (1<<5)
+#define S3C2410_LCDCON5_INVLEND     (1<<4)
+#define S3C2410_LCDCON5_PWREN       (1<<3)
+#define S3C2410_LCDCON5_ENLEND      (1<<2)
+#define S3C2410_LCDCON5_BSWP        (1<<1)
+#define S3C2410_LCDCON5_HWSWP       (1<<0)
+
+/* framebuffer start addressed */
+#define S3C2410_LCDSADDR1   S3C2410_LCDREG(0x14)
+#define S3C2410_LCDSADDR2   S3C2410_LCDREG(0x18)
+#define S3C2410_LCDSADDR3   S3C2410_LCDREG(0x1C)
+
+#define S3C2410_LCDBANK(x)      ((x) << 21)
+#define S3C2410_LCDBASEU(x)     (x)
+
+#define S3C2410_OFFSIZE(x)      ((x) << 11)
+#define S3C2410_PAGEWIDTH(x)    (x)
+
+/* colour lookup and miscellaneous controls */
+
+#define S3C2410_REDLUT     S3C2410_LCDREG(0x20)
+#define S3C2410_GREENLUT   S3C2410_LCDREG(0x24)
+#define S3C2410_BLUELUT    S3C2410_LCDREG(0x28)
+
+#define S3C2410_DITHMODE   S3C2410_LCDREG(0x4C)
+#define S3C2410_TPAL       S3C2410_LCDREG(0x50)
+
+/* interrupt info */
+#define S3C2410_LCDINTPND  S3C2410_LCDREG(0x54)
+#define S3C2410_LCDSRCPND  S3C2410_LCDREG(0x58)
+#define S3C2410_LCDINTMSK  S3C2410_LCDREG(0x5C)
+#define S3C2410_LPCSEL     S3C2410_LCDREG(0x60)
+
+#define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
+
+#endif /* ___ASM_ARCH_REGS_LCD_H */
+
+
+
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
new file mode 100644
index 000000000000..1a1328ac0d79
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -0,0 +1,212 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-mem.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *              http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Memory Control register definitions
+ *
+ *  Changelog:
+ *      29-Sep-2004  BJD  Initial include for Linux
+ *      10-Mar-2005  LCVR Changed S3C2410_VA to S3C24XX_VA
+ *
+*/
+
+#ifndef __ASM_ARM_MEMREGS_H
+#define __ASM_ARM_MEMREGS_H "$Id: regs.h,v 1.8 2003/05/01 15:55:41 ben Exp $"
+
+#ifndef S3C2410_MEMREG
+#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x))
+#endif
+
+/* bus width, and wait state control */
+#define S3C2410_BWSCON                  S3C2410_MEMREG(0x0000)
+
+/* bank zero config - note, pinstrapped from OM pins! */
+#define S3C2410_BWSCON_DW0_16           (1<<1)
+#define S3C2410_BWSCON_DW0_32           (2<<1)
+
+/* bank one configs */
+#define S3C2410_BWSCON_DW1_8            (0<<4)
+#define S3C2410_BWSCON_DW1_16           (1<<4)
+#define S3C2410_BWSCON_DW1_32           (2<<4)
+#define S3C2410_BWSCON_WS1              (1<<6)
+#define S3C2410_BWSCON_ST1              (1<<7)
+
+/* bank 2 configurations */
+#define S3C2410_BWSCON_DW2_8            (0<<8)
+#define S3C2410_BWSCON_DW2_16           (1<<8)
+#define S3C2410_BWSCON_DW2_32           (2<<8)
+#define S3C2410_BWSCON_WS2              (1<<10)
+#define S3C2410_BWSCON_ST2              (1<<11)
+
+/* bank 3 configurations */
+#define S3C2410_BWSCON_DW3_8            (0<<12)
+#define S3C2410_BWSCON_DW3_16           (1<<12)
+#define S3C2410_BWSCON_DW3_32           (2<<12)
+#define S3C2410_BWSCON_WS3              (1<<14)
+#define S3C2410_BWSCON_ST3              (1<<15)
+
+/* bank 4 configurations */
+#define S3C2410_BWSCON_DW4_8            (0<<16)
+#define S3C2410_BWSCON_DW4_16           (1<<16)
+#define S3C2410_BWSCON_DW4_32           (2<<16)
+#define S3C2410_BWSCON_WS4              (1<<18)
+#define S3C2410_BWSCON_ST4              (1<<19)
+
+/* bank 5 configurations */
+#define S3C2410_BWSCON_DW5_8            (0<<20)
+#define S3C2410_BWSCON_DW5_16           (1<<20)
+#define S3C2410_BWSCON_DW5_32           (2<<20)
+#define S3C2410_BWSCON_WS5              (1<<22)
+#define S3C2410_BWSCON_ST5              (1<<23)
+
+/* bank 6 configurations */
+#define S3C2410_BWSCON_DW6_8            (0<<24)
+#define S3C2410_BWSCON_DW6_16           (1<<24)
+#define S3C2410_BWSCON_DW6_32           (2<<24)
+#define S3C2410_BWSCON_WS6              (1<<26)
+#define S3C2410_BWSCON_ST6              (1<<27)
+
+/* bank 7 configurations */
+#define S3C2410_BWSCON_DW7_8            (0<<28)
+#define S3C2410_BWSCON_DW7_16           (1<<28)
+#define S3C2410_BWSCON_DW7_32           (2<<28)
+#define S3C2410_BWSCON_WS7              (1<<30)
+#define S3C2410_BWSCON_ST7              (1<<31)
+
+/* memory set (rom, ram) */
+#define S3C2410_BANKCON0                S3C2410_MEMREG(0x0004)
+#define S3C2410_BANKCON1                S3C2410_MEMREG(0x0008)
+#define S3C2410_BANKCON2                S3C2410_MEMREG(0x000C)
+#define S3C2410_BANKCON3                S3C2410_MEMREG(0x0010)
+#define S3C2410_BANKCON4                S3C2410_MEMREG(0x0014)
+#define S3C2410_BANKCON5                S3C2410_MEMREG(0x0018)
+#define S3C2410_BANKCON6                S3C2410_MEMREG(0x001C)
+#define S3C2410_BANKCON7                S3C2410_MEMREG(0x0020)
+
+/* bank configuration registers */
+
+#define S3C2410_BANKCON_PMCnorm         (0x00)
+#define S3C2410_BANKCON_PMC4            (0x01)
+#define S3C2410_BANKCON_PMC8            (0x02)
+#define S3C2410_BANKCON_PMC16           (0x03)
+
+/* bank configurations for banks 0..7, note banks
+ * 6 and 7 have differnt configurations depending on
+ * the memory type bits */
+
+#define S3C2410_BANKCON_Tacp2           (0x0 << 2)
+#define S3C2410_BANKCON_Tacp3           (0x1 << 2)
+#define S3C2410_BANKCON_Tacp4           (0x2 << 2)
+#define S3C2410_BANKCON_Tacp6           (0x3 << 2)
+
+#define S3C2410_BANKCON_Tcah0           (0x0 << 4)
+#define S3C2410_BANKCON_Tcah1           (0x1 << 4)
+#define S3C2410_BANKCON_Tcah2           (0x2 << 4)
+#define S3C2410_BANKCON_Tcah4           (0x3 << 4)
+
+#define S3C2410_BANKCON_Tcoh0           (0x0 << 6)
+#define S3C2410_BANKCON_Tcoh1           (0x1 << 6)
+#define S3C2410_BANKCON_Tcoh2           (0x2 << 6)
+#define S3C2410_BANKCON_Tcoh4           (0x3 << 6)
+
+#define S3C2410_BANKCON_Tacc1           (0x0 << 8)
+#define S3C2410_BANKCON_Tacc2           (0x1 << 8)
+#define S3C2410_BANKCON_Tacc3           (0x2 << 8)
+#define S3C2410_BANKCON_Tacc4           (0x3 << 8)
+#define S3C2410_BANKCON_Tacc6           (0x4 << 8)
+#define S3C2410_BANKCON_Tacc8           (0x5 << 8)
+#define S3C2410_BANKCON_Tacc10          (0x6 << 8)
+#define S3C2410_BANKCON_Tacc14          (0x7 << 8)
+
+#define S3C2410_BANKCON_Tcos0           (0x0 << 11)
+#define S3C2410_BANKCON_Tcos1           (0x1 << 11)
+#define S3C2410_BANKCON_Tcos2           (0x2 << 11)
+#define S3C2410_BANKCON_Tcos4           (0x3 << 11)
+
+#define S3C2410_BANKCON_Tacs0           (0x0 << 13)
+#define S3C2410_BANKCON_Tacs1           (0x1 << 13)
+#define S3C2410_BANKCON_Tacs2           (0x2 << 13)
+#define S3C2410_BANKCON_Tacs4           (0x3 << 13)
+
+#define S3C2410_BANKCON_SRAM            (0x0 << 15)
+#define S3C2400_BANKCON_EDODRAM         (0x2 << 15)
+#define S3C2410_BANKCON_SDRAM           (0x3 << 15)
+
+/* next bits only for EDO DRAM in 6,7 */
+#define S3C2400_BANKCON_EDO_Trdc1      (0x00 << 4)
+#define S3C2400_BANKCON_EDO_Trdc2      (0x01 << 4)
+#define S3C2400_BANKCON_EDO_Trdc3      (0x02 << 4)
+#define S3C2400_BANKCON_EDO_Trdc4      (0x03 << 4)
+
+/* CAS pulse width */
+#define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
+#define S3C2400_BANKCON_EDO_PULSE2     (0x01 << 3)
+
+/* CAS pre-charge */
+#define S3C2400_BANKCON_EDO_TCP1       (0x00 << 2)
+#define S3C2400_BANKCON_EDO_TCP2       (0x01 << 2)
+
+/* control column address select */
+#define S3C2400_BANKCON_EDO_SCANb8     (0x00 << 0)
+#define S3C2400_BANKCON_EDO_SCANb9     (0x01 << 0)
+#define S3C2400_BANKCON_EDO_SCANb10    (0x02 << 0)
+#define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)
+
+/* next bits only for SDRAM in 6,7 */
+#define S3C2410_BANKCON_Trdc2           (0x00 << 2)
+#define S3C2410_BANKCON_Trdc3           (0x01 << 2)
+#define S3C2410_BANKCON_Trdc4           (0x02 << 2)
+
+/* control column address select */
+#define S3C2410_BANKCON_SCANb8          (0x00 << 0)
+#define S3C2410_BANKCON_SCANb9          (0x01 << 0)
+#define S3C2410_BANKCON_SCANb10         (0x02 << 0)
+
+#define S3C2410_REFRESH                 S3C2410_MEMREG(0x0024)
+#define S3C2410_BANKSIZE                S3C2410_MEMREG(0x0028)
+#define S3C2410_MRSRB6                  S3C2410_MEMREG(0x002C)
+#define S3C2410_MRSRB7                  S3C2410_MEMREG(0x0030)
+
+/* refresh control */
+
+#define S3C2410_REFRESH_REFEN           (1<<23)
+#define S3C2410_REFRESH_SELF            (1<<22)
+#define S3C2410_REFRESH_REFCOUNTER      ((1<<11)-1)
+
+#define S3C2410_REFRESH_TRP_MASK        (3<<20)
+#define S3C2410_REFRESH_TRP_2clk        (0<<20)
+#define S3C2410_REFRESH_TRP_3clk        (1<<20)
+#define S3C2410_REFRESH_TRP_4clk        (2<<20)
+
+#define S3C2410_REFRESH_TSRC_MASK       (3<<18)
+#define S3C2410_REFRESH_TSRC_4clk       (0<<18)
+#define S3C2410_REFRESH_TSRC_5clk       (1<<18)
+#define S3C2410_REFRESH_TSRC_6clk       (2<<18)
+#define S3C2410_REFRESH_TSRC_7clk       (3<<18)
+
+
+/* mode select register(s) */
+
+#define  S3C2410_MRSRB_CL1              (0x00 << 4)
+#define  S3C2410_MRSRB_CL2              (0x02 << 4)
+#define  S3C2410_MRSRB_CL3              (0x03 << 4)
+
+/* bank size register */
+#define S3C2410_BANKSIZE_128M           (0x2 << 0)
+#define S3C2410_BANKSIZE_64M            (0x1 << 0)
+#define S3C2410_BANKSIZE_32M            (0x0 << 0)
+#define S3C2410_BANKSIZE_16M            (0x7 << 0)
+#define S3C2410_BANKSIZE_8M             (0x6 << 0)
+#define S3C2410_BANKSIZE_4M             (0x5 << 0)
+#define S3C2410_BANKSIZE_2M             (0x4 << 0)
+#define S3C2410_BANKSIZE_MASK           (0x7 << 0)
+#define S3C2410_BANKSIZE_SCLK_EN        (1<<4)
+#define S3C2410_BANKSIZE_SCKE_EN        (1<<5)
+#define S3C2410_BANKSIZE_BURST          (1<<7)
+
+#endif /* __ASM_ARM_MEMREGS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/arch-s3c2410/regs-nand.h
new file mode 100644
index 000000000000..c443ac834698
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-nand.h
@@ -0,0 +1,43 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 clock register definitions
+ *
+ *  Changelog:
+ *    18-Aug-2004    BJD     Copied file from 2.4 and updated
+*/
+
+#ifndef __ASM_ARM_REGS_NAND
+#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
+
+
+#define S3C2410_NFREG(x) (x)
+
+#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
+#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
+#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
+#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
+#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
+#define S3C2410_NFECC   S3C2410_NFREG(0x14)
+
+#define S3C2410_NFCONF_EN          (1<<15)
+#define S3C2410_NFCONF_512BYTE     (1<<14)
+#define S3C2410_NFCONF_4STEP       (1<<13)
+#define S3C2410_NFCONF_INITECC     (1<<12)
+#define S3C2410_NFCONF_nFCE        (1<<11)
+#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
+#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
+#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
+
+#define S3C2410_NFSTAT_BUSY        (1<<0)
+
+/* think ECC can only be 8bit read? */
+
+#endif /* __ASM_ARM_REGS_NAND */
+
diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/arch-s3c2410/regs-rtc.h
new file mode 100644
index 000000000000..228983f89bc8
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-rtc.h
@@ -0,0 +1,66 @@
+/* linux/include/asm/arch-s3c2410/regs-rtc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Internal RTC register definition
+ *
+ *  Changelog:
+ *    19-06-2003     BJD     Created file
+ *    12-03-2004     BJD     Updated include protection
+ *    15-01-2005     LCVR    Changed S3C2410_VA to S3C24XX_VA (s3c2400 support)
+*/
+
+#ifndef __ASM_ARCH_REGS_RTC_H
+#define __ASM_ARCH_REGS_RTC_H __FILE__
+
+#define S3C2410_RTCREG(x) ((x) + S3C24XX_VA_RTC)
+
+#define S3C2410_RTCCON        S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN  (1<<0)
+#define S3C2410_RTCCON_CLKSEL (1<<1)
+#define S3C2410_RTCCON_CNTSEL (1<<2)
+#define S3C2410_RTCCON_CLKRST (1<<3)
+
+#define S3C2410_TICNT         S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE  (1<<7)
+
+#define S3C2410_RTCALM        S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN  (1<<6)
+#define S3C2410_RTCALM_YEAREN (1<<5)
+#define S3C2410_RTCALM_MONEN  (1<<4)
+#define S3C2410_RTCALM_DAYEN  (1<<3)
+#define S3C2410_RTCALM_HOUREN (1<<2)
+#define S3C2410_RTCALM_MINEN  (1<<1)
+#define S3C2410_RTCALM_SECEN  (1<<0)
+
+#define S3C2410_RTCALM_ALL \
+  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
+  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
+  S3C2410_RTCALM_SECEN
+
+
+#define S3C2410_ALMSEC        S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN        S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR       S3C2410_RTCREG(0x5c)
+
+#define S3C2410_ALMDATE       S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON        S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR       S3C2410_RTCREG(0x68)
+
+#define S3C2410_RTCRST        S3C2410_RTCREG(0x6c)
+
+#define S3C2410_RTCSEC        S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN        S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR       S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE       S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCDAY        S3C2410_RTCREG(0x80)
+#define S3C2410_RTCMON        S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR       S3C2410_RTCREG(0x88)
+
+
+#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-sdi.h b/include/asm-arm/arch-s3c2410/regs-sdi.h
new file mode 100644
index 000000000000..ca9a26fbecec
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-sdi.h
@@ -0,0 +1,118 @@
+/* linux/include/asm/arch-s3c2410/regs-sdi.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 MMC/SDIO register definitions
+ *
+ *  Changelog:
+ *    18-Aug-2004 Ben Dooks      Created initial file
+ *    29-Nov-2004 Koen Martens   Added some missing defines, fixed duplicates
+ *    29-Nov-2004 Ben Dooks      Updated Koen's patch
+*/
+
+#ifndef __ASM_ARM_REGS_SDI
+#define __ASM_ARM_REGS_SDI "regs-sdi.h"
+
+#define S3C2410_SDICON                (0x00)
+#define S3C2410_SDIPRE                (0x04)
+#define S3C2410_SDICMDARG             (0x08)
+#define S3C2410_SDICMDCON             (0x0C)
+#define S3C2410_SDICMDSTAT            (0x10)
+#define S3C2410_SDIRSP0               (0x14)
+#define S3C2410_SDIRSP1               (0x18)
+#define S3C2410_SDIRSP2               (0x1C)
+#define S3C2410_SDIRSP3               (0x20)
+#define S3C2410_SDITIMER              (0x24)
+#define S3C2410_SDIBSIZE              (0x28)
+#define S3C2410_SDIDCON               (0x2C)
+#define S3C2410_SDIDCNT               (0x30)
+#define S3C2410_SDIDSTA               (0x34)
+#define S3C2410_SDIFSTA               (0x38)
+#define S3C2410_SDIDATA               (0x3C)
+#define S3C2410_SDIIMSK               (0x40)
+
+#define S3C2410_SDICON_BYTEORDER      (1<<4)
+#define S3C2410_SDICON_SDIOIRQ        (1<<3)
+#define S3C2410_SDICON_RWAITEN        (1<<2)
+#define S3C2410_SDICON_FIFORESET      (1<<1)
+#define S3C2410_SDICON_CLOCKTYPE      (1<<0)
+
+#define S3C2410_SDICMDCON_ABORT       (1<<12)
+#define S3C2410_SDICMDCON_WITHDATA    (1<<11)
+#define S3C2410_SDICMDCON_LONGRSP     (1<<10)
+#define S3C2410_SDICMDCON_WAITRSP     (1<<9)
+#define S3C2410_SDICMDCON_CMDSTART    (1<<8)
+#define S3C2410_SDICMDCON_INDEX       (0xff)
+
+#define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
+#define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
+#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
+#define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
+#define S3C2410_SDICMDSTAT_XFERING    (1<<8)
+#define S3C2410_SDICMDSTAT_INDEX      (0xff)
+
+#define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
+#define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
+#define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
+#define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
+#define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
+#define S3C2410_SDIDCON_WIDEBUS       (1<<16)
+#define S3C2410_SDIDCON_DMAEN         (1<<15)
+#define S3C2410_SDIDCON_STOP          (1<<14)
+#define S3C2410_SDIDCON_DATMODE       (3<<12)
+#define S3C2410_SDIDCON_BLKNUM        (0x7ff)
+
+/* constants for S3C2410_SDIDCON_DATMODE */
+#define S3C2410_SDIDCON_XFER_READY    (0<<12)
+#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
+#define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
+#define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
+
+#define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
+
+#define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
+#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
+#define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
+#define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
+#define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
+#define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
+#define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
+#define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
+#define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
+#define S3C2410_SDIDSTA_TXDATAON      (1<<1)
+#define S3C2410_SDIDSTA_RXDATAON      (1<<0)
+
+#define S3C2410_SDIFSTA_TFDET          (1<<13)
+#define S3C2410_SDIFSTA_RFDET          (1<<12)
+#define S3C2410_SDIFSTA_TXHALF         (1<<11)
+#define S3C2410_SDIFSTA_TXEMPTY        (1<<10)
+#define S3C2410_SDIFSTA_RFLAST         (1<<9)
+#define S3C2410_SDIFSTA_RFFULL         (1<<8)
+#define S3C2410_SDIFSTA_RFHALF         (1<<7)
+#define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
+
+#define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
+#define S3C2410_SDIIMSK_CMDSENT        (1<<16)
+#define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
+#define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
+#define S3C2410_SDIIMSK_READWAIT       (1<<13)
+#define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
+#define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
+#define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
+#define S3C2410_SDIIMSK_DATACRC        (1<<9)
+#define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
+#define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
+#define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
+#define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
+#define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
+#define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
+#define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
+#define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
+#define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
+
+#endif /* __ASM_ARM_REGS_SDI */
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
new file mode 100644
index 000000000000..ce1bbbaad6d3
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -0,0 +1,209 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
+ *
+ *  From linux/include/asm-arm/hardware/serial_s3c2410.h
+ *
+ *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
+ *
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
+ *
+ *  Adapted from:
+ *
+ *  Internal header file for MX1ADS serial ports (UART1 & 2)
+ *
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ * Modifications:
+ *     10-Mar-2005 LCVR  Changed S3C2410_VA to S3C24XX_VA (s3c2400 support)
+ */
+
+#ifndef __ASM_ARM_REGS_SERIAL_H
+#define __ASM_ARM_REGS_SERIAL_H
+
+#define S3C24XX_VA_UART0      (S3C24XX_VA_UART)
+#define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )
+#define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )
+
+#define S3C2410_PA_UART0      (S3C2410_PA_UART)
+#define S3C2410_PA_UART1      (S3C2410_PA_UART + 0x4000 )
+#define S3C2410_PA_UART2      (S3C2410_PA_UART + 0x8000 )
+
+#define S3C2410_URXH      (0x24)
+#define S3C2410_UTXH      (0x20)
+#define S3C2410_ULCON     (0x00)
+#define S3C2410_UCON      (0x04)
+#define S3C2410_UFCON     (0x08)
+#define S3C2410_UMCON     (0x0C)
+#define S3C2410_UBRDIV    (0x28)
+#define S3C2410_UTRSTAT   (0x10)
+#define S3C2410_UERSTAT   (0x14)
+#define S3C2410_UFSTAT    (0x18)
+#define S3C2410_UMSTAT    (0x1C)
+
+#define S3C2410_LCON_CFGMASK      ((0xF<<3)|(0x3))
+
+#define S3C2410_LCON_CS5          (0x0)
+#define S3C2410_LCON_CS6          (0x1)
+#define S3C2410_LCON_CS7          (0x2)
+#define S3C2410_LCON_CS8          (0x3)
+#define S3C2410_LCON_CSMASK       (0x3)
+
+#define S3C2410_LCON_PNONE        (0x0)
+#define S3C2410_LCON_PEVEN        (0x5 << 3)
+#define S3C2410_LCON_PODD         (0x4 << 3)
+#define S3C2410_LCON_PMASK        (0x7 << 3)
+
+#define S3C2410_LCON_STOPB        (1<<2)
+#define S3C2410_LCON_IRM          (1<<6)
+
+#define S3C2440_UCON_CLKMASK      (3<<10)
+#define S3C2440_UCON_PCLK         (0<<10)
+#define S3C2440_UCON_UCLK         (1<<10)
+#define S3C2440_UCON_PCLK2        (2<<10)
+#define S3C2440_UCON_FCLK         (3<<10)
+#define S3C2440_UCON2_FCLK_EN     (1<<15)
+#define S3C2440_UCON0_DIVMASK     (15 << 12)
+#define S3C2440_UCON1_DIVMASK     (15 << 12)
+#define S3C2440_UCON2_DIVMASK     (7 << 12)
+#define S3C2440_UCON_DIVSHIFT     (12)
+
+#define S3C2410_UCON_UCLK         (1<<10)
+#define S3C2410_UCON_SBREAK       (1<<4)
+
+#define S3C2410_UCON_TXILEVEL     (1<<9)
+#define S3C2410_UCON_RXILEVEL     (1<<8)
+#define S3C2410_UCON_TXIRQMODE    (1<<2)
+#define S3C2410_UCON_RXIRQMODE    (1<<0)
+#define S3C2410_UCON_RXFIFO_TOI   (1<<7)
+
+#define S3C2410_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL  | \
+                                   S3C2410_UCON_RXILEVEL  | \
+                                   S3C2410_UCON_TXIRQMODE | \
+                                   S3C2410_UCON_RXIRQMODE | \
+                                   S3C2410_UCON_RXFIFO_TOI)
+
+#define S3C2410_UFCON_FIFOMODE    (1<<0)
+#define S3C2410_UFCON_TXTRIG0     (0<<6)
+#define S3C2410_UFCON_RXTRIG8     (1<<4)
+#define S3C2410_UFCON_RXTRIG12    (2<<4)
+
+/* S3C2440 FIFO trigger levels */
+#define S3C2440_UFCON_RXTRIG1     (0<<4)
+#define S3C2440_UFCON_RXTRIG8     (1<<4)
+#define S3C2440_UFCON_RXTRIG16    (2<<4)
+#define S3C2440_UFCON_RXTRIG32    (3<<4)
+
+#define S3C2440_UFCON_TXTRIG0     (0<<6)
+#define S3C2440_UFCON_TXTRIG16    (1<<6)
+#define S3C2440_UFCON_TXTRIG32    (2<<6)
+#define S3C2440_UFCON_TXTRIG48    (3<<6)
+
+#define S3C2410_UFCON_RESETBOTH   (3<<1)
+#define S3C2410_UFCON_RESETTX     (1<<2)
+#define S3C2410_UFCON_RESETRX     (1<<1)
+
+#define S3C2410_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE | \
+                                   S3C2410_UFCON_TXTRIG0  | \
+                                   S3C2410_UFCON_RXTRIG8 )
+
+#define S3C2410_UMCOM_AFC         (1<<4)
+#define S3C2410_UMCOM_RTS_LOW     (1<<0)
+
+#define S3C2410_UFSTAT_TXFULL     (1<<9)
+#define S3C2410_UFSTAT_RXFULL     (1<<8)
+#define S3C2410_UFSTAT_TXMASK     (15<<4)
+#define S3C2410_UFSTAT_TXSHIFT    (4)
+#define S3C2410_UFSTAT_RXMASK     (15<<0)
+#define S3C2410_UFSTAT_RXSHIFT    (0)
+
+#define S3C2440_UFSTAT_TXFULL     (1<<14)
+#define S3C2440_UFSTAT_RXFULL     (1<<6)
+#define S3C2440_UFSTAT_TXSHIFT    (8)
+#define S3C2440_UFSTAT_RXSHIFT    (0)
+#define S3C2440_UFSTAT_TXMASK     (63<<8)
+#define S3C2440_UFSTAT_RXMASK     (63)
+
+#define S3C2410_UTRSTAT_TXE       (1<<2)
+#define S3C2410_UTRSTAT_TXFE      (1<<1)
+#define S3C2410_UTRSTAT_RXDR      (1<<0)
+
+#define S3C2410_UERSTAT_OVERRUN   (1<<0)
+#define S3C2410_UERSTAT_FRAME     (1<<2)
+#define S3C2410_UERSTAT_BREAK     (1<<3)
+#define S3C2410_UERSTAT_ANY       (S3C2410_UERSTAT_OVERRUN | \
+                                   S3C2410_UERSTAT_FRAME | \
+                                   S3C2410_UERSTAT_BREAK)
+
+#define S3C2410_UMSTAT_CTS        (1<<0)
+#define S3C2410_UMSTAT_DeltaCTS   (1<<2)
+
+#ifndef __ASSEMBLY__
+
+/* struct s3c24xx_uart_clksrc
+ *
+ * this structure defines a named clock source that can be used for the
+ * uart, so that the best clock can be selected for the requested baud
+ * rate.
+ *
+ * min_baud and max_baud define the range of baud-rates this clock is
+ * acceptable for, if they are both zero, it is assumed any baud rate that
+ * can be generated from this clock will be used.
+ *
+ * divisor gives the divisor from the clock to the one seen by the uart
+*/
+
+struct s3c24xx_uart_clksrc {
+        const char      *name;
+        unsigned int     divisor;
+        unsigned int     min_baud;
+        unsigned int     max_baud;
+};
+
+/* configuration structure for per-machine configurations for the
+ * serial port
+ *
+ * the pointer is setup by the machine specific initialisation from the
+ * arch/arm/mach-s3c2410/ directory.
+*/
+
+struct s3c2410_uartcfg {
+        unsigned char      hwport;       /* hardware port number */
+        unsigned char      unused;
+        unsigned short     flags;
+        unsigned long      uart_flags;   /* default uart flags */
+
+        unsigned long      ucon;         /* value of ucon for port */
+        unsigned long      ulcon;        /* value of ulcon for port */
+        unsigned long      ufcon;        /* value of ufcon for port */
+
+        struct s3c24xx_uart_clksrc *clocks;
+        unsigned int                clocks_size;
+};
+
+/* s3c24xx_uart_devs
+ *
+ * this is exported from the core as we cannot use driver_register(),
+ * or platform_add_device() before the console_initcall()
+*/
+
+extern struct platform_device *s3c24xx_uart_devs[3];
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_REGS_SERIAL_H */
+
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/arch-s3c2410/regs-spi.h
new file mode 100644
index 000000000000..cb502a88158b
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-spi.h
@@ -0,0 +1,56 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-spi.h
+ *
+ * Copyright (c) 2004 Fetron GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 SPI register definition
+ *
+ *  Changelog:
+ *    20-04-2004     KF      Created file
+ *    04-10-2004     BJD     Removed VA address (no longer mapped)
+ *                           tidied file for submission
+ */
+
+#ifndef __ASM_ARCH_REGS_SPI_H
+#define __ASM_ARCH_REGS_SPI_H
+
+
+#define S3C2410_SPCON   (0x00)
+
+#define S3C2410_SPCON_SMOD_DMA    (2<<5)        /* DMA mode */
+#define S3C2410_SPCON_SMOD_INT    (1<<5)        /* interrupt mode */
+#define S3C2410_SPCON_SMOD_POLL   (0<<5)        /* polling mode */
+#define S3C2410_SPCON_ENSCK       (1<<4)        /* Enable SCK */
+#define S3C2410_SPCON_MSTR        (1<<3)        /* Master/Slave select
+                                                   0: slave, 1: master */
+#define S3C2410_SPCON_CPOL_HIGH   (1<<2)        /* Clock polarity select */
+#define S3C2410_SPCON_CPOL_LOW    (0<<2)        /* Clock polarity select */
+
+#define S3C2410_SPCON_CPHA_FMTB   (1<<1)        /* Clock Phase Select */
+#define S3C2410_SPCON_CPHA_FMTA   (0<<1)        /* Clock Phase Select */
+
+#define S3C2410_SPCON_TAGD        (1<<0)        /* Tx auto garbage data mode */
+
+
+#define S3C2410_SPSTA    (0x04)
+
+#define S3C2410_SPSTA_DCOL        (1<<2)        /* Data Collision Error */
+#define S3C2410_SPSTA_MULD        (1<<1)        /* Multi Master Error */
+#define S3C2410_SPSTA_READY       (1<<0)        /* Data Tx/Rx ready */
+
+
+#define S3C2410_SPPIN    (0x08)
+
+#define S3C2410_SPPIN_ENMUL       (1<<2)        /* Multi Master Error detect */
+#define S3C2410_SPPIN_RESERVED    (1<<1)
+#define S3C2410_SPPIN_KEEP        (1<<0)        /* Master Out keep */
+
+
+#define S3C2410_SPPRE    (0x0C)
+#define S3C2410_SPTDAT   (0x10)
+#define S3C2410_SPRDAT   (0x14)
+
+#endif /* __ASM_ARCH_REGS_SPI_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/arch-s3c2410/regs-timer.h
new file mode 100644
index 000000000000..169064e27520
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-timer.h
@@ -0,0 +1,113 @@
+/* linux/include/asm/arch-s3c2410/regs-timer.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Timer configuration
+ *
+ *  Changelog:
+ *    05-06-2003     BJD     Created file
+ *    26-06-2003     BJD     Added more timer definitions to mux / control
+ *    12-03-2004     BJD     Updated include protection
+ *    10-02-2005     BJD     Added S3C2410_TCFG1_MUX4_SHIFT (Guillaume Gourat)
+ *    10-03-2005     LCVR    Changed S3C2410_VA to S3C24XX_VA
+*/
+
+
+#ifndef __ASM_ARCH_REGS_TIMER_H
+#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
+
+#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
+#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
+
+#define S3C2410_TCFG0         S3C2410_TIMERREG(0x00)
+#define S3C2410_TCFG1         S3C2410_TIMERREG(0x04)
+#define S3C2410_TCON          S3C2410_TIMERREG(0x08)
+
+#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
+#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
+#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
+#define S3C2410_TCFG_DEADZONE_MASK   (255<<16)
+#define S3C2410_TCFG_DEADZONE_SHIFT  (16)
+
+#define S3C2410_TCFG1_MUX4_DIV2   (0<<16)
+#define S3C2410_TCFG1_MUX4_DIV4   (1<<16)
+#define S3C2410_TCFG1_MUX4_DIV8   (2<<16)
+#define S3C2410_TCFG1_MUX4_DIV16  (3<<16)
+#define S3C2410_TCFG1_MUX4_TCLK1  (4<<16)
+#define S3C2410_TCFG1_MUX4_MASK   (15<<16)
+#define S3C2410_TCFG1_MUX4_SHIFT  (16)
+
+#define S3C2410_TCFG1_MUX3_DIV2   (0<<12)
+#define S3C2410_TCFG1_MUX3_DIV4   (1<<12)
+#define S3C2410_TCFG1_MUX3_DIV8   (2<<12)
+#define S3C2410_TCFG1_MUX3_DIV16  (3<<12)
+#define S3C2410_TCFG1_MUX3_TCLK1  (4<<12)
+#define S3C2410_TCFG1_MUX3_MASK   (15<<12)
+
+
+#define S3C2410_TCFG1_MUX2_DIV2   (0<<8)
+#define S3C2410_TCFG1_MUX2_DIV4   (1<<8)
+#define S3C2410_TCFG1_MUX2_DIV8   (2<<8)
+#define S3C2410_TCFG1_MUX2_DIV16  (3<<8)
+#define S3C2410_TCFG1_MUX2_TCLK1  (4<<8)
+#define S3C2410_TCFG1_MUX2_MASK   (15<<8)
+
+
+#define S3C2410_TCFG1_MUX1_DIV2   (0<<4)
+#define S3C2410_TCFG1_MUX1_DIV4   (1<<4)
+#define S3C2410_TCFG1_MUX1_DIV8   (2<<4)
+#define S3C2410_TCFG1_MUX1_DIV16  (3<<4)
+#define S3C2410_TCFG1_MUX1_TCLK0  (4<<4)
+#define S3C2410_TCFG1_MUX1_MASK   (15<<4)
+
+#define S3C2410_TCFG1_MUX0_DIV2   (0<<0)
+#define S3C2410_TCFG1_MUX0_DIV4   (1<<0)
+#define S3C2410_TCFG1_MUX0_DIV8   (2<<0)
+#define S3C2410_TCFG1_MUX0_DIV16  (3<<0)
+#define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
+#define S3C2410_TCFG1_MUX0_MASK   (15<<0)
+
+/* for each timer, we have an count buffer, an compare buffer and
+ * an observation buffer
+*/
+
+/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
+
+#define S3C2410_TCNTB(tmr)    S3C2410_TIMERREG2(tmr, 0x00)
+#define S3C2410_TCMPB(tmr)    S3C2410_TIMERREG2(tmr, 0x04)
+#define S3C2410_TCNTO(tmr)    S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
+
+#define S3C2410_TCON_T4RELOAD     (1<<22)
+#define S3C2410_TCON_T4MANUALUPD  (1<<21)
+#define S3C2410_TCON_T4START      (1<<20)
+
+#define S3C2410_TCON_T3RELOAD     (1<<19)
+#define S3C2410_TCON_T3INVERT     (1<<18)
+#define S3C2410_TCON_T3MANUALUPD  (1<<17)
+#define S3C2410_TCON_T3START      (1<<16)
+
+#define S3C2410_TCON_T2RELOAD     (1<<15)
+#define S3C2410_TCON_T2INVERT     (1<<14)
+#define S3C2410_TCON_T2MANUALUPD  (1<<13)
+#define S3C2410_TCON_T2START      (1<<12)
+
+#define S3C2410_TCON_T1RELOAD     (1<<11)
+#define S3C2410_TCON_T1INVERT     (1<<10)
+#define S3C2410_TCON_T1MANUALUPD  (1<<9)
+#define S3C2410_TCON_T1START      (1<<8)
+
+#define S3C2410_TCON_T0DEADZONE   (1<<4)
+#define S3C2410_TCON_T0RELOAD     (1<<3)
+#define S3C2410_TCON_T0INVERT     (1<<2)
+#define S3C2410_TCON_T0MANUALUPD  (1<<1)
+#define S3C2410_TCON_T0START      (1<<0)
+
+#endif /*  __ASM_ARCH_REGS_TIMER_H */
+
+
+
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/arch-s3c2410/regs-udc.h
new file mode 100644
index 000000000000..bf315b763252
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-udc.h
@@ -0,0 +1,164 @@
+/* linux/include/asm/arch-s3c2410/regs-udc.h
+ *
+ * Copyright (C) 2004 Herbert Poetzl <herbert@13thfloor.at>
+ *
+ * This include file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ *  Changelog:
+ *    01-08-2004        Initial creation
+ *    12-09-2004        Cleanup for submission
+ *    24-10-2004        Fixed S3C2410_UDC_MAXP_REG definition
+ *    10-03-2005        Changed S3C2410_VA to S3C24XX_VA
+ */
+
+#ifndef __ASM_ARCH_REGS_UDC_H
+#define __ASM_ARCH_REGS_UDC_H
+
+
+#define S3C2410_USBDREG(x) ((x) + S3C24XX_VA_USBDEV)
+
+#define S3C2410_UDC_FUNC_ADDR_REG       S3C2410_USBDREG(0x0140)
+#define S3C2410_UDC_PWR_REG             S3C2410_USBDREG(0x0144)
+#define S3C2410_UDC_EP_INT_REG          S3C2410_USBDREG(0x0148)
+
+#define S3C2410_UDC_USB_INT_REG         S3C2410_USBDREG(0x0158)
+#define S3C2410_UDC_EP_INT_EN_REG       S3C2410_USBDREG(0x015c)
+
+#define S3C2410_UDC_USB_INT_EN_REG      S3C2410_USBDREG(0x016c)
+
+#define S3C2410_UDC_FRAME_NUM1_REG      S3C2410_USBDREG(0x0170)
+#define S3C2410_UDC_FRAME_NUM2_REG      S3C2410_USBDREG(0x0174)
+
+#define S3C2410_UDC_EP0_FIFO_REG        S3C2410_USBDREG(0x01c0)
+#define S3C2410_UDC_EP1_FIFO_REG        S3C2410_USBDREG(0x01c4)
+#define S3C2410_UDC_EP2_FIFO_REG        S3C2410_USBDREG(0x01c8)
+#define S3C2410_UDC_EP3_FIFO_REG        S3C2410_USBDREG(0x01cc)
+#define S3C2410_UDC_EP4_FIFO_REG        S3C2410_USBDREG(0x01d0)
+
+#define S3C2410_UDC_EP1_DMA_CON         S3C2410_USBDREG(0x0200)
+#define S3C2410_UDC_EP1_DMA_UNIT        S3C2410_USBDREG(0x0204)
+#define S3C2410_UDC_EP1_DMA_FIFO        S3C2410_USBDREG(0x0208)
+#define S3C2410_UDC_EP1_DMA_TTC_L       S3C2410_USBDREG(0x020c)
+#define S3C2410_UDC_EP1_DMA_TTC_M       S3C2410_USBDREG(0x0210)
+#define S3C2410_UDC_EP1_DMA_TTC_H       S3C2410_USBDREG(0x0214)
+
+#define S3C2410_UDC_EP2_DMA_CON         S3C2410_USBDREG(0x0218)
+#define S3C2410_UDC_EP2_DMA_UNIT        S3C2410_USBDREG(0x021c)
+#define S3C2410_UDC_EP2_DMA_FIFO        S3C2410_USBDREG(0x0220)
+#define S3C2410_UDC_EP2_DMA_TTC_L       S3C2410_USBDREG(0x0224)
+#define S3C2410_UDC_EP2_DMA_TTC_M       S3C2410_USBDREG(0x0228)
+#define S3C2410_UDC_EP2_DMA_TTC_H       S3C2410_USBDREG(0x022c)
+
+#define S3C2410_UDC_EP3_DMA_CON         S3C2410_USBDREG(0x0240)
+#define S3C2410_UDC_EP3_DMA_UNIT        S3C2410_USBDREG(0x0244)
+#define S3C2410_UDC_EP3_DMA_FIFO        S3C2410_USBDREG(0x0248)
+#define S3C2410_UDC_EP3_DMA_TTC_L       S3C2410_USBDREG(0x024c)
+#define S3C2410_UDC_EP3_DMA_TTC_M       S3C2410_USBDREG(0x0250)
+#define S3C2410_UDC_EP3_DMA_TTC_H       S3C2410_USBDREG(0x0254)
+
+#define S3C2410_UDC_EP4_DMA_CON         S3C2410_USBDREG(0x0258)
+#define S3C2410_UDC_EP4_DMA_UNIT        S3C2410_USBDREG(0x025c)
+#define S3C2410_UDC_EP4_DMA_FIFO        S3C2410_USBDREG(0x0260)
+#define S3C2410_UDC_EP4_DMA_TTC_L       S3C2410_USBDREG(0x0264)
+#define S3C2410_UDC_EP4_DMA_TTC_M       S3C2410_USBDREG(0x0268)
+#define S3C2410_UDC_EP4_DMA_TTC_H       S3C2410_USBDREG(0x026c)
+
+#define S3C2410_UDC_INDEX_REG           S3C2410_USBDREG(0x0178)
+
+/* indexed registers */
+
+#define S3C2410_UDC_MAXP_REG            S3C2410_USBDREG(0x0180)
+
+#define S3C2410_UDC_EP0_CSR_REG         S3C2410_USBDREG(0x0184)
+
+#define S3C2410_UDC_IN_CSR1_REG         S3C2410_USBDREG(0x0184)
+#define S3C2410_UDC_IN_CSR2_REG         S3C2410_USBDREG(0x0188)
+
+#define S3C2410_UDC_OUT_CSR1_REG        S3C2410_USBDREG(0x0190)
+#define S3C2410_UDC_OUT_CSR2_REG        S3C2410_USBDREG(0x0194)
+#define S3C2410_UDC_OUT_FIFO_CNT1_REG   S3C2410_USBDREG(0x0198)
+#define S3C2410_UDC_OUT_FIFO_CNT2_REG   S3C2410_USBDREG(0x019c)
+
+
+
+#define S3C2410_UDC_PWR_ISOUP           (1<<7) // R/W
+#define S3C2410_UDC_PWR_RESET           (1<<3) // R
+#define S3C2410_UDC_PWR_RESUME          (1<<2) // R/W
+#define S3C2410_UDC_PWR_SUSPEND         (1<<1) // R
+#define S3C2410_UDC_PWR_ENSUSPEND       (1<<0) // R/W
+
+#define S3C2410_UDC_PWR_DEFAULT         0x00
+
+#define S3C2410_UDC_INT_EP4             (1<<4) // R/W (clear only)
+#define S3C2410_UDC_INT_EP3             (1<<3) // R/W (clear only)
+#define S3C2410_UDC_INT_EP2             (1<<2) // R/W (clear only)
+#define S3C2410_UDC_INT_EP1             (1<<1) // R/W (clear only)
+#define S3C2410_UDC_INT_EP0             (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_USBINT_RESET        (1<<2) // R/W (clear only)
+#define S3C2410_UDC_USBINT_RESUME       (1<<1) // R/W (clear only)
+#define S3C2410_UDC_USBINT_SUSPEND      (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_INTE_EP4            (1<<4) // R/W
+#define S3C2410_UDC_INTE_EP3            (1<<3) // R/W
+#define S3C2410_UDC_INTE_EP2            (1<<2) // R/W
+#define S3C2410_UDC_INTE_EP1            (1<<1) // R/W
+#define S3C2410_UDC_INTE_EP0            (1<<0) // R/W
+
+#define S3C2410_UDC_USBINTE_RESET       (1<<2) // R/W
+#define S3C2410_UDC_USBINTE_SUSPEND     (1<<0) // R/W
+
+
+#define S3C2410_UDC_INDEX_EP0           (0x00)
+#define S3C2410_UDC_INDEX_EP1           (0x01) // ??
+#define S3C2410_UDC_INDEX_EP2           (0x02) // ??
+#define S3C2410_UDC_INDEX_EP3           (0x03) // ??
+#define S3C2410_UDC_INDEX_EP4           (0x04) // ??
+
+#define S3C2410_UDC_ICSR1_CLRDT         (1<<6) // R/W
+#define S3C2410_UDC_ICSR1_SENTSTL       (1<<5) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_SENDSTL       (1<<4) // R/W
+#define S3C2410_UDC_ICSR1_FFLUSH        (1<<3) // W   (set only)
+#define S3C2410_UDC_ICSR1_UNDRUN        (1<<2) // R/W (clear only)
+#define S3C2410_UDC_ICSR1_PKTRDY        (1<<0) // R/W (set only)
+
+#define S3C2410_UDC_ICSR2_AUTOSET       (1<<7) // R/W
+#define S3C2410_UDC_ICSR2_ISO           (1<<6) // R/W
+#define S3C2410_UDC_ICSR2_MODEIN        (1<<5) // R/W
+#define S3C2410_UDC_ICSR2_DMAIEN        (1<<4) // R/W
+
+#define S3C2410_UDC_OCSR1_CLRDT         (1<<7) // R/W
+#define S3C2410_UDC_OCSR1_SENTSTL       (1<<6) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_SENDSTL       (1<<5) // R/W
+#define S3C2410_UDC_OCSR1_FFLUSH        (1<<4) // R/W
+#define S3C2410_UDC_OCSR1_DERROR        (1<<3) // R
+#define S3C2410_UDC_OCSR1_OVRRUN        (1<<2) // R/W (clear only)
+#define S3C2410_UDC_OCSR1_PKTRDY        (1<<0) // R/W (clear only)
+
+#define S3C2410_UDC_OCSR2_AUTOCLR       (1<<7) // R/W
+#define S3C2410_UDC_OCSR2_ISO           (1<<6) // R/W
+#define S3C2410_UDC_OCSR2_DMAIEN        (1<<5) // R/W
+
+#define S3C2410_UDC_SETIX(x)        \
+        __raw_writel(S3C2410_UDC_INDEX_ ## x, S3C2410_UDC_INDEX_REG);
+
+
+#define S3C2410_UDC_EP0_CSR_OPKRDY      (1<<0)
+#define S3C2410_UDC_EP0_CSR_IPKRDY      (1<<1)
+#define S3C2410_UDC_EP0_CSR_SENTSTL     (1<<2)
+#define S3C2410_UDC_EP0_CSR_DE          (1<<3)
+#define S3C2410_UDC_EP0_CSR_SE          (1<<4)
+#define S3C2410_UDC_EP0_CSR_SENDSTL     (1<<5)
+#define S3C2410_UDC_EP0_CSR_SOPKTRDY    (1<<6)
+#define S3C2410_UDC_EP0_CSR_SSE (1<<7)
+
+#define S3C2410_UDC_MAXP_8              (1<<0)
+#define S3C2410_UDC_MAXP_16             (1<<1)
+#define S3C2410_UDC_MAXP_32             (1<<2)
+#define S3C2410_UDC_MAXP_64             (1<<3)
+
+
+#endif
diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/arch-s3c2410/regs-watchdog.h
new file mode 100644
index 000000000000..d199ca6aff22
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/regs-watchdog.h
@@ -0,0 +1,46 @@
+/* linux/include/asm/arch-s3c2410/regs0watchdog.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Watchdog timer control
+ *
+ *  Changelog:
+ *    21-06-2003     BJD     Created file
+ *    12-03-2004     BJD     Updated include protection
+ *    10-03-2005     LCVR    Changed S3C2410_VA to S3C24XX_VA
+*/
+
+
+#ifndef __ASM_ARCH_REGS_WATCHDOG_H
+#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
+
+#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
+
+#define S3C2410_WTCON      S3C2410_WDOGREG(0x00)
+#define S3C2410_WTDAT      S3C2410_WDOGREG(0x04)
+#define S3C2410_WTCNT      S3C2410_WDOGREG(0x08)
+
+/* the watchdog can either generate a reset pulse, or an
+ * interrupt.
+ */
+
+#define S3C2410_WTCON_RSTEN   (0x01)
+#define S3C2410_WTCON_INTEN   (1<<2)
+#define S3C2410_WTCON_ENABLE  (1<<5)
+
+#define S3C2410_WTCON_DIV16   (0<<3)
+#define S3C2410_WTCON_DIV32   (1<<3)
+#define S3C2410_WTCON_DIV64   (2<<3)
+#define S3C2410_WTCON_DIV128  (3<<3)
+
+#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
+#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
+
+#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
+
+
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
new file mode 100644
index 000000000000..9b0d85024cb4
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -0,0 +1,90 @@
+/* linux/include/asm-arm/arch-s3c2410/system.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - System function defines and includes
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  12-May-2003 BJD  Created file
+ *  14-May-2003 BJD  Removed idle to aid debugging
+ *  12-Jun-2003 BJD  Added reset via watchdog
+ *  04-Sep-2003 BJD  Moved to v2.6
+ *  28-Oct-2004 BJD  Added over-ride for idle, and fixed reset panic()
+ */
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+#include <asm/arch/map.h>
+#include <asm/arch/idle.h>
+
+#include <asm/arch/regs-watchdog.h>
+#include <asm/arch/regs-clock.h>
+
+void (*s3c24xx_idle)(void);
+
+void s3c24xx_default_idle(void)
+{
+        void __iomem *reg = S3C2410_CLKCON;
+        unsigned long tmp;
+        int i;
+
+        /* idle the system by using the idle mode which will wait for an
+         * interrupt to happen before restarting the system.
+         */
+
+        /* Warning: going into idle state upsets jtag scanning */
+
+        __raw_writel(__raw_readl(reg) | (1<<2), reg);
+
+        /* the samsung port seems to do a loop and then unset idle.. */
+        for (i = 0; i < 50; i++) {
+                tmp += __raw_readl(reg); /* ensure loop not optimised out */
+        }
+
+        /* this bit is not cleared on re-start... */
+
+        __raw_writel(__raw_readl(reg) & ~(1<<2), reg);
+}
+
+static void arch_idle(void)
+{
+        if (s3c24xx_idle != NULL)
+                (s3c24xx_idle)();
+        else
+                s3c24xx_default_idle();
+}
+
+
+static void
+arch_reset(char mode)
+{
+        if (mode == 's') {
+                cpu_reset(0);
+        }
+
+        printk("arch_reset: attempting watchdog reset\n");
+
+        __raw_writel(0, S3C2410_WTCON);   /* disable watchdog, to be safe  */
+
+        /* put initial values into count and data */
+        __raw_writel(0x100, S3C2410_WTCNT);
+        __raw_writel(0x100, S3C2410_WTDAT);
+
+        /* set the watchdog to go and reset... */
+        __raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
+                     S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+
+        /* wait for reset to assert... */
+        mdelay(5000);
+
+        printk(KERN_ERR "Watchdog reset failed to assert reset\n");
+
+        /* we'll take a jump through zero as a poor second */
+        cpu_reset(0);
+}
diff --git a/include/asm-arm/arch-s3c2410/timex.h b/include/asm-arm/arch-s3c2410/timex.h
new file mode 100644
index 000000000000..3558a3a750bf
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/timex.h
@@ -0,0 +1,32 @@
+/* linux/include/asm-arm/arch-s3c2410/timex.h
+ *
+ * (c) 2003-2005 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - time parameters
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  02-Sep-2003 BJD  Created file
+ *  05-Jan-2004 BJD  Updated for Linux 2.6.0
+ *  22-Nov-2004 BJD  Fixed CLOCK_TICK_RATE
+ *  10-Jan-2004 BJD  Removed s3c2410_clock_tick_rate
+*/
+
+#ifndef __ASM_ARCH_TIMEX_H
+#define __ASM_ARCH_TIMEX_H
+
+/* CLOCK_TICK_RATE needs to be evaluatable by the cpp, so making it
+ * a variable is useless. It seems as long as we make our timers an
+ * exact multiple of HZ, any value that makes a 1->1 correspondence
+ * for the time conversion functions to/from jiffies is acceptable.
+*/
+
+
+#define CLOCK_TICK_RATE 12000000
+
+
+#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
new file mode 100644
index 000000000000..ad4252e27799
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -0,0 +1,158 @@
+/* linux/include/asm-arm/arch-s3c2410/uncompress.h
+ *
+ * (c) 2003 Simtec Electronics
+ *    Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  22-May-2003 BJD  Created
+ *  08-Sep-2003 BJD  Moved to linux v2.6
+ *  12-Mar-2004 BJD  Updated header protection
+ *  12-Oct-2004 BJD  Take account of debug uart configuration
+ *  15-Nov-2004 BJD  Fixed uart configuration
+ *  22-Feb-2005 BJD  Added watchdog to uncompress
+*/
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <linux/config.h>
+
+/* defines for UART registers */
+#include "asm/arch/regs-serial.h"
+#include "asm/arch/regs-gpio.h"
+#include "asm/arch/regs-watchdog.h"
+
+#include <asm/arch/map.h>
+
+/* working in physical space... */
+#undef S3C2410_GPIOREG
+#undef S3C2410_WDOGREG
+
+#define S3C2410_GPIOREG(x) ((S3C2410_PA_GPIO + (x)))
+#define S3C2410_WDOGREG(x) ((S3C2410_PA_WATCHDOG + (x)))
+
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX         (14)
+
+#define uart_base S3C2410_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
+
+static __inline__ void
+uart_wr(unsigned int reg, unsigned int val)
+{
+        volatile unsigned int *ptr;
+
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        *ptr = val;
+}
+
+static __inline__ unsigned int
+uart_rd(unsigned int reg)
+{
+        volatile unsigned int *ptr;
+
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        return *ptr;
+}
+
+
+/* we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+*/
+
+static void
+putc(char ch)
+{
+        int cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
+
+        cpuid &= S3C2410_GSTATUS1_IDMASK;
+
+        if (ch == '\n')
+                putc('\r');    /* expand newline to \r\n */
+
+        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+                int level;
+
+                while (1) {
+                        level = uart_rd(S3C2410_UFSTAT);
+
+                        if (cpuid == S3C2410_GSTATUS1_2440) {
+                                level &= S3C2440_UFSTAT_TXMASK;
+                                level >>= S3C2440_UFSTAT_TXSHIFT;
+                        } else {
+                                level &= S3C2410_UFSTAT_TXMASK;
+                                level >>= S3C2410_UFSTAT_TXSHIFT;
+                        }
+
+                        if (level < FIFO_MAX)
+                                break;
+                }
+
+        } else {
+                /* not using fifos */
+
+                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE);
+        }
+
+        /* write byte to transmission register */
+        uart_wr(S3C2410_UTXH, ch);
+}
+
+static void
+putstr(const char *ptr)
+{
+        for (; *ptr != '\0'; ptr++) {
+                putc(*ptr);
+        }
+}
+
+/* CONFIG_S3C2410_BOOT_WATCHDOG
+ *
+ * Simple boot-time watchdog setup, to reboot the system if there is
+ * any problem with the boot process
+*/
+
+#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
+
+#define WDOG_COUNT (0xff00)
+
+#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
+
+static inline void arch_decomp_wdog(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+}
+
+static void arch_decomp_wdog_start(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+}
+
+#else
+#define arch_decomp_wdog_start()
+#define arch_decomp_wdog()
+#endif
+
+static void error(char *err);
+
+static void
+arch_decomp_setup(void)
+{
+        /* we may need to setup the uart(s) here if we are not running
+         * on an BAST... the BAST will have left the uarts configured
+         * after calling linux.
+         */
+
+        arch_decomp_wdog_start();
+}
+
+
+#endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-s3c2410/usb-control.h b/include/asm-arm/arch-s3c2410/usb-control.h
new file mode 100644
index 000000000000..1cc85a096b23
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/usb-control.h
@@ -0,0 +1,45 @@
+/* linux/include/asm-arm/arch-s3c2410/usb-control.h
+ *
+ * (c) 2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - usb port information
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  11-Sep-2004 BJD  Created file
+ *  21-Sep-2004 BJD  Updated port info
+*/
+
+#ifndef __ASM_ARCH_USBCONTROL_H
+#define __ASM_ARCH_USBCONTROL_H "include/asm-arm/arch-s3c2410/usb-control.h"
+
+#define S3C_HCDFLG_USED (1)
+
+struct s3c2410_hcd_port {
+        unsigned char   flags;
+        unsigned char   power;
+        unsigned char   oc_status;
+        unsigned char   oc_changed;
+};
+
+struct s3c2410_hcd_info {
+        struct usb_hcd          *hcd;
+        struct s3c2410_hcd_port port[2];
+
+        void            (*power_control)(int port, int to);
+        void            (*enable_oc)(struct s3c2410_hcd_info *, int on);
+        void            (*report_oc)(struct s3c2410_hcd_info *, int ports);
+};
+
+static void inline s3c2410_report_oc(struct s3c2410_hcd_info *info, int ports)
+{
+        if (info->report_oc != NULL) {
+                (info->report_oc)(info, ports);
+        }
+}
+
+#endif /*__ASM_ARCH_USBCONTROL_H */
diff --git a/include/asm-arm/arch-s3c2410/vmalloc.h b/include/asm-arm/arch-s3c2410/vmalloc.h
new file mode 100644
index 000000000000..5fe72ad70904
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/vmalloc.h
@@ -0,0 +1,36 @@
+/* linux/include/asm-arm/arch-s3c2410/vmalloc.h
+ *
+ * from linux/include/asm-arm/arch-iop3xx/vmalloc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                    http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 vmalloc definition
+ *
+ *  Changelog:
+ *    12-Mar-2004 BJD   Fixed header, added include protection
+ *    12=Mar-2004 BJD   Fixed VMALLOC_END definitions
+ */
+
+#ifndef __ASM_ARCH_VMALLOC_H
+#define __ASM_ARCH_VMALLOC_H
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x) ((unsigned long)(x))
+#define VMALLOC_END       (0xE0000000)
+
+#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-cpld.h b/include/asm-arm/arch-s3c2410/vr1000-cpld.h
new file mode 100644
index 000000000000..0ee373ac60d4
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/vr1000-cpld.h
@@ -0,0 +1,22 @@
+/* linux/include/asm-arm/arch-s3c2410/vr1000-cpld.h
+ *
+ * (c) 2003 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * VR1000 - CPLD control constants
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  25-May-2003 BJD  Created file, added CTRL1 registers
+ *  19-Mar-2004 BJD  Added VR1000 CPLD definitions
+*/
+
+#ifndef __ASM_ARCH_VR1000CPLD_H
+#define __ASM_ARCH_VR1000CPLD_H
+
+#define VR1000_CPLD_CTRL2_RAMWEN     (0x04)   /* SRAM Write Enable */
+
+#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-irq.h b/include/asm-arm/arch-s3c2410/vr1000-irq.h
new file mode 100644
index 000000000000..694f7715d2da
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/vr1000-irq.h
@@ -0,0 +1,30 @@
+/* linux/include/asm-arm/arch-s3c2410/vr1000-irq.h
+ *
+ * (c) 2003,2004 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine VR1000 - IRQ Number definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  06-Jan-2003 BJD  Linux 2.6.0 version
+ *  19-Mar-2004 BJD  Updates for VR1000
+ */
+
+#ifndef __ASM_ARCH_VR1000IRQ_H
+#define __ASM_ARCH_VR1000IRQ_H
+
+/* irq numbers to onboard peripherals */
+
+#define IRQ_USBOC            IRQ_EINT19
+#define IRQ_IDE0             IRQ_EINT16
+#define IRQ_IDE1             IRQ_EINT17
+#define IRQ_VR1000_SERIAL    IRQ_EINT12
+#define IRQ_VR1000_DM9000A   IRQ_EINT10
+#define IRQ_VR1000_DM9000N   IRQ_EINT9
+#define IRQ_SMALERT          IRQ_EINT8
+
+#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/include/asm-arm/arch-s3c2410/vr1000-map.h b/include/asm-arm/arch-s3c2410/vr1000-map.h
new file mode 100644
index 000000000000..867c9355fd39
--- /dev/null
+++ b/include/asm-arm/arch-s3c2410/vr1000-map.h
@@ -0,0 +1,116 @@
+/* linux/include/asm-arm/arch-s3c2410/vr1000-map.h
+ *
+ * (c) 2003-2005 Simtec Electronics
+ *  Ben Dooks <ben@simtec.co.uk>
+ *
+ * Machine VR1000 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Changelog:
+ *  06-Jan-2003 BJD  Linux 2.6.0 version, split specifics from arch/map.h
+ *  12-Mar-2004 BJD  Fixed header include protection
+ *  19-Mar-2004 BJD  Copied to VR1000 machine headers.
+ *  19-Jan-2005 BJD  Updated map definitions
+*/
+
+/* needs arch/map.h including with this */
+
+/* ok, we've used up to 0x13000000, now we need to find space for the
+ * peripherals that live in the nGCS[x] areas, which are quite numerous
+ * in their space. We also have the board's CPLD to find register space
+ * for.
+ */
+
+#ifndef __ASM_ARCH_VR1000MAP_H
+#define __ASM_ARCH_VR1000MAP_H
+
+#include <asm/arch/bast-map.h>
+
+#define VR1000_IOADDR(x) BAST_IOADDR(x)
+
+/* we put the CPLD registers next, to get them out of the way */
+
+#define VR1000_VA_CTRL1     VR1000_IOADDR(0x00000000)    /* 0x01300000 */
+#define VR1000_PA_CTRL1     (S3C2410_CS5 | 0x7800000)
+
+#define VR1000_VA_CTRL2     VR1000_IOADDR(0x00100000)    /* 0x01400000 */
+#define VR1000_PA_CTRL2     (S3C2410_CS1 | 0x6000000)
+
+#define VR1000_VA_CTRL3     VR1000_IOADDR(0x00200000)    /* 0x01500000 */
+#define VR1000_PA_CTRL3     (S3C2410_CS1 | 0x6800000)
+
+#define VR1000_VA_CTRL4     VR1000_IOADDR(0x00300000)    /* 0x01600000 */
+#define VR1000_PA_CTRL4     (S3C2410_CS1 | 0x7000000)
+
+/* next, we have the PC104 ISA interrupt registers */
+
+#define VR1000_PA_PC104_IRQREQ  (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
+#define VR1000_VA_PC104_IRQREQ  VR1000_IOADDR(0x00400000)
+
+#define VR1000_PA_PC104_IRQRAW  (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
+#define VR1000_VA_PC104_IRQRAW  VR1000_IOADDR(0x00500000)
+
+#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
+#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
+
+/* 0xE0000000 contains the IO space that is split by speed and
+ * wether the access is for 8 or 16bit IO... this ensures that
+ * the correct access is made
+ *
+ * 0x10000000 of space, partitioned as so:
+ *
+ * 0x00000000 to 0x04000000  8bit,  slow
+ * 0x04000000 to 0x08000000  16bit, slow
+ * 0x08000000 to 0x0C000000  16bit, net
+ * 0x0C000000 to 0x10000000  16bit, fast
+ *
+ * each of these spaces has the following in:
+ *
+ * 0x02000000 to 0x02100000 1MB  IDE primary channel
+ * 0x02100000 to 0x02200000 1MB  IDE primary channel aux
+ * 0x02200000 to 0x02400000 1MB  IDE secondary channel
+ * 0x02300000 to 0x02400000 1MB  IDE secondary channel aux
+ * 0x02500000 to 0x02600000 1MB  Davicom DM9000 ethernet controllers
+ * 0x02600000 to 0x02700000 1MB
+ *
+ * the phyiscal layout of the zones are:
+ *  nGCS2 - 8bit, slow
+ *  nGCS3 - 16bit, slow
+ *  nGCS4 - 16bit, net
+ *  nGCS5 - 16bit, fast
+ */
+
+#define VR1000_VA_MULTISPACE (0xE0000000)
+
+#define VR1000_VA_ISAIO            (VR1000_VA_MULTISPACE + 0x00000000)
+#define VR1000_VA_ISAMEM           (VR1000_VA_MULTISPACE + 0x01000000)
+#define VR1000_VA_IDEPRI           (VR1000_VA_MULTISPACE + 0x02000000)
+#define VR1000_VA_IDEPRIAUX        (VR1000_VA_MULTISPACE + 0x02100000)
+#define VR1000_VA_IDESEC           (VR1000_VA_MULTISPACE + 0x02200000)
+#define VR1000_VA_IDESECAUX        (VR1000_VA_MULTISPACE + 0x02300000)
+#define VR1000_VA_ASIXNET          (VR1000_VA_MULTISPACE + 0x02400000)
+#define VR1000_VA_DM9000           (VR1000_VA_MULTISPACE + 0x02500000)
+#define VR1000_VA_SUPERIO          (VR1000_VA_MULTISPACE + 0x02600000)
+
+/* physical offset addresses for the peripherals */
+
+#define VR1000_PA_IDEPRI           (0x02000000)
+#define VR1000_PA_IDEPRIAUX        (0x02800000)
+#define VR1000_PA_IDESEC           (0x03000000)
+#define VR1000_PA_IDESECAUX        (0x03800000)
+#define VR1000_PA_DM9000           (0x05000000)
+
+#define VR1000_PA_SERIAL           (0x11800000)
+#define VR1000_VA_SERIAL           (VR1000_IOADDR(0x00700000))
+
+/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
+#define VR1000_PA_SRAM             (S3C2410_CS1 | 0x05000000)
+
+/* some configurations for the peripherals */
+
+#define VR1000_DM9000_CS         VR1000_VAM_CS4
+
+#endif /* __ASM_ARCH_VR1000MAP_H */
diff --git a/include/asm-arm/arch-sa1100/SA-1100.h b/include/asm-arm/arch-sa1100/SA-1100.h
new file mode 100644
index 000000000000..62aaf04a3906
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/SA-1100.h
@@ -0,0 +1,2072 @@
+/*
+ *      FILE            SA-1100.h
+ *
+ *      Version         1.2
+ *      Author          Copyright (c) Marc A. Viredaz, 1998
+ *                      DEC Western Research Laboratory, Palo Alto, CA
+ *      Date            January 1998 (April 1997)
+ *      System          StrongARM SA-1100
+ *      Language        C or ARM Assembly
+ *      Purpose         Definition of constants related to the StrongARM
+ *                      SA-1100 microprocessor (Advanced RISC Machine (ARM)
+ *                      architecture version 4). This file is based on the
+ *                      StrongARM SA-1100 data sheet version 2.2.
+ *
+ */
+
+
+/* Be sure that virtual mapping is defined right */
+#ifndef __ASM_ARCH_HARDWARE_H
+#error You must include hardware.h not SA-1100.h
+#endif
+
+#include "bitfield.h"
+
+/*
+ * SA1100 CS line to physical address
+ */
+
+#define SA1100_CS0_PHYS 0x00000000
+#define SA1100_CS1_PHYS 0x08000000
+#define SA1100_CS2_PHYS 0x10000000
+#define SA1100_CS3_PHYS 0x18000000
+#define SA1100_CS4_PHYS 0x40000000
+#define SA1100_CS5_PHYS 0x48000000
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) sockets
+ */
+
+#define PCMCIAPrtSp     0x04000000      /* PCMCIA Partition Space [byte]   */
+#define PCMCIASp        (4*PCMCIAPrtSp) /* PCMCIA Space [byte]             */
+#define PCMCIAIOSp      PCMCIAPrtSp     /* PCMCIA I/O Space [byte]         */
+#define PCMCIAAttrSp    PCMCIAPrtSp     /* PCMCIA Attribute Space [byte]   */
+#define PCMCIAMemSp     PCMCIAPrtSp     /* PCMCIA Memory Space [byte]      */
+
+#define PCMCIA0Sp       PCMCIASp        /* PCMCIA 0 Space [byte]           */
+#define PCMCIA0IOSp     PCMCIAIOSp      /* PCMCIA 0 I/O Space [byte]       */
+#define PCMCIA0AttrSp   PCMCIAAttrSp    /* PCMCIA 0 Attribute Space [byte] */
+#define PCMCIA0MemSp    PCMCIAMemSp     /* PCMCIA 0 Memory Space [byte]    */
+
+#define PCMCIA1Sp       PCMCIASp        /* PCMCIA 1 Space [byte]           */
+#define PCMCIA1IOSp     PCMCIAIOSp      /* PCMCIA 1 I/O Space [byte]       */
+#define PCMCIA1AttrSp   PCMCIAAttrSp    /* PCMCIA 1 Attribute Space [byte] */
+#define PCMCIA1MemSp    PCMCIAMemSp     /* PCMCIA 1 Memory Space [byte]    */
+
+#define _PCMCIA(Nb)                     /* PCMCIA [0..1]                   */ \
+                        (0x20000000 + (Nb)*PCMCIASp)
+#define _PCMCIAIO(Nb)   _PCMCIA (Nb)    /* PCMCIA I/O [0..1]               */
+#define _PCMCIAAttr(Nb)                 /* PCMCIA Attribute [0..1]         */ \
+                        (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
+#define _PCMCIAMem(Nb)                  /* PCMCIA Memory [0..1]            */ \
+                        (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
+
+#define _PCMCIA0        _PCMCIA (0)     /* PCMCIA 0                        */
+#define _PCMCIA0IO      _PCMCIAIO (0)   /* PCMCIA 0 I/O                    */
+#define _PCMCIA0Attr    _PCMCIAAttr (0) /* PCMCIA 0 Attribute              */
+#define _PCMCIA0Mem     _PCMCIAMem (0)  /* PCMCIA 0 Memory                 */
+
+#define _PCMCIA1        _PCMCIA (1)     /* PCMCIA 1                        */
+#define _PCMCIA1IO      _PCMCIAIO (1)   /* PCMCIA 1 I/O                    */
+#define _PCMCIA1Attr    _PCMCIAAttr (1) /* PCMCIA 1 Attribute              */
+#define _PCMCIA1Mem     _PCMCIAMem (1)  /* PCMCIA 1 Memory                 */
+
+
+/*
+ * Universal Serial Bus (USB) Device Controller (UDC) control registers
+ *
+ * Registers
+ *    Ser0UDCCR         Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Control Register (read/write).
+ *    Ser0UDCAR         Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Address Register (read/write).
+ *    Ser0UDCOMP        Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Output Maximum Packet size register
+ *                      (read/write).
+ *    Ser0UDCIMP        Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Input Maximum Packet size register
+ *                      (read/write).
+ *    Ser0UDCCS0        Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Control/Status register end-point 0
+ *                      (read/write).
+ *    Ser0UDCCS1        Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Control/Status register end-point 1
+ *                      (output, read/write).
+ *    Ser0UDCCS2        Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Control/Status register end-point 2
+ *                      (input, read/write).
+ *    Ser0UDCD0         Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Data register end-point 0
+ *                      (read/write).
+ *    Ser0UDCWC         Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Write Count register end-point 0
+ *                      (read).
+ *    Ser0UDCDR         Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Data Register (read/write).
+ *    Ser0UDCSR         Serial port 0 Universal Serial Bus (USB) Device
+ *                      Controller (UDC) Status Register (read/write).
+ */
+
+#define Ser0UDCCR       __REG(0x80000000)  /* Ser. port 0 UDC Control Reg. */
+#define Ser0UDCAR       __REG(0x80000004)  /* Ser. port 0 UDC Address Reg. */
+#define Ser0UDCOMP      __REG(0x80000008)  /* Ser. port 0 UDC Output Maximum Packet size reg. */
+#define Ser0UDCIMP      __REG(0x8000000C)  /* Ser. port 0 UDC Input Maximum Packet size reg. */
+#define Ser0UDCCS0      __REG(0x80000010)  /* Ser. port 0 UDC Control/Status reg. end-point 0 */
+#define Ser0UDCCS1      __REG(0x80000014)  /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
+#define Ser0UDCCS2      __REG(0x80000018)  /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
+#define Ser0UDCD0       __REG(0x8000001C)  /* Ser. port 0 UDC Data reg. end-point 0 */
+#define Ser0UDCWC       __REG(0x80000020)  /* Ser. port 0 UDC Write Count reg. end-point 0 */
+#define Ser0UDCDR       __REG(0x80000028)  /* Ser. port 0 UDC Data Reg. */
+#define Ser0UDCSR       __REG(0x80000030)  /* Ser. port 0 UDC Status Reg. */
+
+#define UDCCR_UDD       0x00000001      /* UDC Disable                     */
+#define UDCCR_UDA       0x00000002      /* UDC Active (read)               */
+#define UDCCR_RESIM     0x00000004      /* Resume Interrupt Mask, per errata */
+#define UDCCR_EIM       0x00000008      /* End-point 0 Interrupt Mask      */
+                                        /* (disable)                       */
+#define UDCCR_RIM       0x00000010      /* Receive Interrupt Mask          */
+                                        /* (disable)                       */
+#define UDCCR_TIM       0x00000020      /* Transmit Interrupt Mask         */
+                                        /* (disable)                       */
+#define UDCCR_SRM       0x00000040      /* Suspend/Resume interrupt Mask   */
+                                        /* (disable)                       */
+#define UDCCR_SUSIM     UDCCR_SRM       /* Per errata, SRM just masks suspend */
+#define UDCCR_REM       0x00000080      /* REset interrupt Mask (disable)  */
+
+#define UDCAR_ADD       Fld (7, 0)      /* function ADDress                */
+
+#define UDCOMP_OUTMAXP  Fld (8, 0)      /* OUTput MAXimum Packet size - 1  */
+                                        /* [byte]                          */
+#define UDCOMP_OutMaxPkt(Size)          /* Output Maximum Packet size      */ \
+                                        /* [1..256 byte]                   */ \
+                        (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
+
+#define UDCIMP_INMAXP   Fld (8, 0)      /* INput MAXimum Packet size - 1   */
+                                        /* [byte]                          */
+#define UDCIMP_InMaxPkt(Size)           /* Input Maximum Packet size       */ \
+                                        /* [1..256 byte]                   */ \
+                        (((Size) - 1) << FShft (UDCIMP_INMAXP))
+
+#define UDCCS0_OPR      0x00000001      /* Output Packet Ready (read)      */
+#define UDCCS0_IPR      0x00000002      /* Input Packet Ready              */
+#define UDCCS0_SST      0x00000004      /* Sent STall                      */
+#define UDCCS0_FST      0x00000008      /* Force STall                     */
+#define UDCCS0_DE       0x00000010      /* Data End                        */
+#define UDCCS0_SE       0x00000020      /* Setup End (read)                */
+#define UDCCS0_SO       0x00000040      /* Serviced Output packet ready    */
+                                        /* (write)                         */
+#define UDCCS0_SSE      0x00000080      /* Serviced Setup End (write)      */
+
+#define UDCCS1_RFS      0x00000001      /* Receive FIFO 12-bytes or more   */
+                                        /* Service request (read)          */
+#define UDCCS1_RPC      0x00000002      /* Receive Packet Complete         */
+#define UDCCS1_RPE      0x00000004      /* Receive Packet Error (read)     */
+#define UDCCS1_SST      0x00000008      /* Sent STall                      */
+#define UDCCS1_FST      0x00000010      /* Force STall                     */
+#define UDCCS1_RNE      0x00000020      /* Receive FIFO Not Empty (read)   */
+
+#define UDCCS2_TFS      0x00000001      /* Transmit FIFO 8-bytes or less   */
+                                        /* Service request (read)          */
+#define UDCCS2_TPC      0x00000002      /* Transmit Packet Complete        */
+#define UDCCS2_TPE      0x00000004      /* Transmit Packet Error (read)    */
+#define UDCCS2_TUR      0x00000008      /* Transmit FIFO Under-Run         */
+#define UDCCS2_SST      0x00000010      /* Sent STall                      */
+#define UDCCS2_FST      0x00000020      /* Force STall                     */
+
+#define UDCD0_DATA      Fld (8, 0)      /* receive/transmit DATA FIFOs     */
+
+#define UDCWC_WC        Fld (4, 0)      /* Write Count                     */
+
+#define UDCDR_DATA      Fld (8, 0)      /* receive/transmit DATA FIFOs     */
+
+#define UDCSR_EIR       0x00000001      /* End-point 0 Interrupt Request   */
+#define UDCSR_RIR       0x00000002      /* Receive Interrupt Request       */
+#define UDCSR_TIR       0x00000004      /* Transmit Interrupt Request      */
+#define UDCSR_SUSIR     0x00000008      /* SUSpend Interrupt Request       */
+#define UDCSR_RESIR     0x00000010      /* RESume Interrupt Request        */
+#define UDCSR_RSTIR     0x00000020      /* ReSeT Interrupt Request         */
+
+
+/*
+ * Universal Asynchronous Receiver/Transmitter (UART) control registers
+ *
+ * Registers
+ *    Ser1UTCR0         Serial port 1 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 0
+ *                      (read/write).
+ *    Ser1UTCR1         Serial port 1 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 1
+ *                      (read/write).
+ *    Ser1UTCR2         Serial port 1 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 2
+ *                      (read/write).
+ *    Ser1UTCR3         Serial port 1 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 3
+ *                      (read/write).
+ *    Ser1UTDR          Serial port 1 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Data Register
+ *                      (read/write).
+ *    Ser1UTSR0         Serial port 1 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Status Register 0
+ *                      (read/write).
+ *    Ser1UTSR1         Serial port 1 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ *    Ser2UTCR0         Serial port 2 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 0
+ *                      (read/write).
+ *    Ser2UTCR1         Serial port 2 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 1
+ *                      (read/write).
+ *    Ser2UTCR2         Serial port 2 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 2
+ *                      (read/write).
+ *    Ser2UTCR3         Serial port 2 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 3
+ *                      (read/write).
+ *    Ser2UTCR4         Serial port 2 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 4
+ *                      (read/write).
+ *    Ser2UTDR          Serial port 2 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Data Register
+ *                      (read/write).
+ *    Ser2UTSR0         Serial port 2 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Status Register 0
+ *                      (read/write).
+ *    Ser2UTSR1         Serial port 2 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ *    Ser3UTCR0         Serial port 3 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 0
+ *                      (read/write).
+ *    Ser3UTCR1         Serial port 3 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 1
+ *                      (read/write).
+ *    Ser3UTCR2         Serial port 3 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 2
+ *                      (read/write).
+ *    Ser3UTCR3         Serial port 3 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Control Register 3
+ *                      (read/write).
+ *    Ser3UTDR          Serial port 3 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Data Register
+ *                      (read/write).
+ *    Ser3UTSR0         Serial port 3 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Status Register 0
+ *                      (read/write).
+ *    Ser3UTSR1         Serial port 3 Universal Asynchronous
+ *                      Receiver/Transmitter (UART) Status Register 1 (read).
+ *
+ * Clocks
+ *    fxtl, Txtl        Frequency, period of the system crystal (3.6864 MHz
+ *                      or 3.5795 MHz).
+ *    fua, Tua          Frequency, period of the UART communication.
+ */
+
+#define _UTCR0(Nb)      __REG(0x80010000 + ((Nb) - 1)*0x00020000)  /* UART Control Reg. 0 [1..3] */
+#define _UTCR1(Nb)      __REG(0x80010004 + ((Nb) - 1)*0x00020000)  /* UART Control Reg. 1 [1..3] */
+#define _UTCR2(Nb)      __REG(0x80010008 + ((Nb) - 1)*0x00020000)  /* UART Control Reg. 2 [1..3] */
+#define _UTCR3(Nb)      __REG(0x8001000C + ((Nb) - 1)*0x00020000)  /* UART Control Reg. 3 [1..3] */
+#define _UTCR4(Nb)      __REG(0x80010010 + ((Nb) - 1)*0x00020000)  /* UART Control Reg. 4 [2] */
+#define _UTDR(Nb)       __REG(0x80010014 + ((Nb) - 1)*0x00020000)  /* UART Data Reg. [1..3] */
+#define _UTSR0(Nb)      __REG(0x8001001C + ((Nb) - 1)*0x00020000)  /* UART Status Reg. 0 [1..3] */
+#define _UTSR1(Nb)      __REG(0x80010020 + ((Nb) - 1)*0x00020000)  /* UART Status Reg. 1 [1..3] */
+
+#define Ser1UTCR0       _UTCR0 (1)      /* Ser. port 1 UART Control Reg. 0 */
+#define Ser1UTCR1       _UTCR1 (1)      /* Ser. port 1 UART Control Reg. 1 */
+#define Ser1UTCR2       _UTCR2 (1)      /* Ser. port 1 UART Control Reg. 2 */
+#define Ser1UTCR3       _UTCR3 (1)      /* Ser. port 1 UART Control Reg. 3 */
+#define Ser1UTDR        _UTDR (1)       /* Ser. port 1 UART Data Reg.      */
+#define Ser1UTSR0       _UTSR0 (1)      /* Ser. port 1 UART Status Reg. 0  */
+#define Ser1UTSR1       _UTSR1 (1)      /* Ser. port 1 UART Status Reg. 1  */
+
+#define Ser2UTCR0       _UTCR0 (2)      /* Ser. port 2 UART Control Reg. 0 */
+#define Ser2UTCR1       _UTCR1 (2)      /* Ser. port 2 UART Control Reg. 1 */
+#define Ser2UTCR2       _UTCR2 (2)      /* Ser. port 2 UART Control Reg. 2 */
+#define Ser2UTCR3       _UTCR3 (2)      /* Ser. port 2 UART Control Reg. 3 */
+#define Ser2UTCR4       _UTCR4 (2)      /* Ser. port 2 UART Control Reg. 4 */
+#define Ser2UTDR        _UTDR (2)       /* Ser. port 2 UART Data Reg.      */
+#define Ser2UTSR0       _UTSR0 (2)      /* Ser. port 2 UART Status Reg. 0  */
+#define Ser2UTSR1       _UTSR1 (2)      /* Ser. port 2 UART Status Reg. 1  */
+
+#define Ser3UTCR0       _UTCR0 (3)      /* Ser. port 3 UART Control Reg. 0 */
+#define Ser3UTCR1       _UTCR1 (3)      /* Ser. port 3 UART Control Reg. 1 */
+#define Ser3UTCR2       _UTCR2 (3)      /* Ser. port 3 UART Control Reg. 2 */
+#define Ser3UTCR3       _UTCR3 (3)      /* Ser. port 3 UART Control Reg. 3 */
+#define Ser3UTDR        _UTDR (3)       /* Ser. port 3 UART Data Reg.      */
+#define Ser3UTSR0       _UTSR0 (3)      /* Ser. port 3 UART Status Reg. 0  */
+#define Ser3UTSR1       _UTSR1 (3)      /* Ser. port 3 UART Status Reg. 1  */
+
+/* Those are still used in some places */
+#define _Ser1UTCR0      __PREG(Ser1UTCR0)
+#define _Ser2UTCR0      __PREG(Ser2UTCR0)
+#define _Ser3UTCR0      __PREG(Ser3UTCR0)
+
+/* Register offsets */
+#define UTCR0           0x00
+#define UTCR1           0x04
+#define UTCR2           0x08
+#define UTCR3           0x0c
+#define UTDR            0x14
+#define UTSR0           0x1c
+#define UTSR1           0x20
+
+#define UTCR0_PE        0x00000001      /* Parity Enable                   */
+#define UTCR0_OES       0x00000002      /* Odd/Even parity Select          */
+#define UTCR0_OddPar    (UTCR0_OES*0)   /*  Odd Parity                     */
+#define UTCR0_EvenPar   (UTCR0_OES*1)   /*  Even Parity                    */
+#define UTCR0_SBS       0x00000004      /* Stop Bit Select                 */
+#define UTCR0_1StpBit   (UTCR0_SBS*0)   /*  1 Stop Bit per frame           */
+#define UTCR0_2StpBit   (UTCR0_SBS*1)   /*  2 Stop Bits per frame          */
+#define UTCR0_DSS       0x00000008      /* Data Size Select                */
+#define UTCR0_7BitData  (UTCR0_DSS*0)   /*  7-Bit Data                     */
+#define UTCR0_8BitData  (UTCR0_DSS*1)   /*  8-Bit Data                     */
+#define UTCR0_SCE       0x00000010      /* Sample Clock Enable             */
+                                        /* (ser. port 1: GPIO [18],        */
+                                        /* ser. port 3: GPIO [20])         */
+#define UTCR0_RCE       0x00000020      /* Receive Clock Edge select       */
+#define UTCR0_RcRsEdg   (UTCR0_RCE*0)   /*  Receive clock Rising-Edge      */
+#define UTCR0_RcFlEdg   (UTCR0_RCE*1)   /*  Receive clock Falling-Edge     */
+#define UTCR0_TCE       0x00000040      /* Transmit Clock Edge select      */
+#define UTCR0_TrRsEdg   (UTCR0_TCE*0)   /*  Transmit clock Rising-Edge     */
+#define UTCR0_TrFlEdg   (UTCR0_TCE*1)   /*  Transmit clock Falling-Edge    */
+#define UTCR0_Ser2IrDA                  /* Ser. port 2 IrDA settings       */ \
+                        (UTCR0_1StpBit + UTCR0_8BitData)
+
+#define UTCR1_BRD       Fld (4, 0)      /* Baud Rate Divisor/16 - 1 [11:8] */
+#define UTCR2_BRD       Fld (8, 0)      /* Baud Rate Divisor/16 - 1  [7:0] */
+                                        /* fua = fxtl/(16*(BRD[11:0] + 1)) */
+                                        /* Tua = 16*(BRD [11:0] + 1)*Txtl  */
+#define UTCR1_BdRtDiv(Div)              /*  Baud Rate Divisor [16..65536]  */ \
+                        (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
+                         FShft (UTCR1_BRD))
+#define UTCR2_BdRtDiv(Div)              /*  Baud Rate Divisor [16..65536]  */ \
+                        (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
+                         FShft (UTCR2_BRD))
+                                        /*  fua = fxtl/(16*Floor (Div/16)) */
+                                        /*  Tua = 16*Floor (Div/16)*Txtl   */
+#define UTCR1_CeilBdRtDiv(Div)          /*  Ceil. of BdRtDiv [16..65536]   */ \
+                        (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
+                         FShft (UTCR1_BRD))
+#define UTCR2_CeilBdRtDiv(Div)          /*  Ceil. of BdRtDiv [16..65536]   */ \
+                        (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
+                         FShft (UTCR2_BRD))
+                                        /*  fua = fxtl/(16*Ceil (Div/16))  */
+                                        /*  Tua = 16*Ceil (Div/16)*Txtl    */
+
+#define UTCR3_RXE       0x00000001      /* Receive Enable                  */
+#define UTCR3_TXE       0x00000002      /* Transmit Enable                 */
+#define UTCR3_BRK       0x00000004      /* BReaK mode                      */
+#define UTCR3_RIE       0x00000008      /* Receive FIFO 1/3-to-2/3-full or */
+                                        /* more Interrupt Enable           */
+#define UTCR3_TIE       0x00000010      /* Transmit FIFO 1/2-full or less  */
+                                        /* Interrupt Enable                */
+#define UTCR3_LBM       0x00000020      /* Look-Back Mode                  */
+#define UTCR3_Ser2IrDA                  /* Ser. port 2 IrDA settings (RIE, */ \
+                                        /* TIE, LBM can be set or cleared) */ \
+                        (UTCR3_RXE + UTCR3_TXE)
+
+#define UTCR4_HSE       0x00000001      /* Hewlett-Packard Serial InfraRed */
+                                        /* (HP-SIR) modulation Enable      */
+#define UTCR4_NRZ       (UTCR4_HSE*0)   /*  Non-Return to Zero modulation  */
+#define UTCR4_HPSIR     (UTCR4_HSE*1)   /*  HP-SIR modulation              */
+#define UTCR4_LPM       0x00000002      /* Low-Power Mode                  */
+#define UTCR4_Z3_16Bit  (UTCR4_LPM*0)   /*  Zero pulse = 3/16 Bit time     */
+#define UTCR4_Z1_6us    (UTCR4_LPM*1)   /*  Zero pulse = 1.6 us            */
+
+#define UTDR_DATA       Fld (8, 0)      /* receive/transmit DATA FIFOs     */
+#if 0                                   /* Hidden receive FIFO bits        */
+#define UTDR_PRE        0x00000100      /*  receive PaRity Error (read)    */
+#define UTDR_FRE        0x00000200      /*  receive FRaming Error (read)   */
+#define UTDR_ROR        0x00000400      /*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define UTSR0_TFS       0x00000001      /* Transmit FIFO 1/2-full or less  */
+                                        /* Service request (read)          */
+#define UTSR0_RFS       0x00000002      /* Receive FIFO 1/3-to-2/3-full or */
+                                        /* more Service request (read)     */
+#define UTSR0_RID       0x00000004      /* Receiver IDle                   */
+#define UTSR0_RBB       0x00000008      /* Receive Beginning of Break      */
+#define UTSR0_REB       0x00000010      /* Receive End of Break            */
+#define UTSR0_EIF       0x00000020      /* Error In FIFO (read)            */
+
+#define UTSR1_TBY       0x00000001      /* Transmitter BusY (read)         */
+#define UTSR1_RNE       0x00000002      /* Receive FIFO Not Empty (read)   */
+#define UTSR1_TNF       0x00000004      /* Transmit FIFO Not Full (read)   */
+#define UTSR1_PRE       0x00000008      /* receive PaRity Error (read)     */
+#define UTSR1_FRE       0x00000010      /* receive FRaming Error (read)    */
+#define UTSR1_ROR       0x00000020      /* Receive FIFO Over-Run (read)    */
+
+
+/*
+ * Synchronous Data Link Controller (SDLC) control registers
+ *
+ * Registers
+ *    Ser1SDCR0         Serial port 1 Synchronous Data Link Controller (SDLC)
+ *                      Control Register 0 (read/write).
+ *    Ser1SDCR1         Serial port 1 Synchronous Data Link Controller (SDLC)
+ *                      Control Register 1 (read/write).
+ *    Ser1SDCR2         Serial port 1 Synchronous Data Link Controller (SDLC)
+ *                      Control Register 2 (read/write).
+ *    Ser1SDCR3         Serial port 1 Synchronous Data Link Controller (SDLC)
+ *                      Control Register 3 (read/write).
+ *    Ser1SDCR4         Serial port 1 Synchronous Data Link Controller (SDLC)
+ *                      Control Register 4 (read/write).
+ *    Ser1SDDR          Serial port 1 Synchronous Data Link Controller (SDLC)
+ *                      Data Register (read/write).
+ *    Ser1SDSR0         Serial port 1 Synchronous Data Link Controller (SDLC)
+ *                      Status Register 0 (read/write).
+ *    Ser1SDSR1         Serial port 1 Synchronous Data Link Controller (SDLC)
+ *                      Status Register 1 (read/write).
+ *
+ * Clocks
+ *    fxtl, Txtl        Frequency, period of the system crystal (3.6864 MHz
+ *                      or 3.5795 MHz).
+ *    fsd, Tsd          Frequency, period of the SDLC communication.
+ */
+
+#define Ser1SDCR0       __REG(0x80020060)  /* Ser. port 1 SDLC Control Reg. 0 */
+#define Ser1SDCR1       __REG(0x80020064)  /* Ser. port 1 SDLC Control Reg. 1 */
+#define Ser1SDCR2       __REG(0x80020068)  /* Ser. port 1 SDLC Control Reg. 2 */
+#define Ser1SDCR3       __REG(0x8002006C)  /* Ser. port 1 SDLC Control Reg. 3 */
+#define Ser1SDCR4       __REG(0x80020070)  /* Ser. port 1 SDLC Control Reg. 4 */
+#define Ser1SDDR        __REG(0x80020078)  /* Ser. port 1 SDLC Data Reg.      */
+#define Ser1SDSR0       __REG(0x80020080)  /* Ser. port 1 SDLC Status Reg. 0  */
+#define Ser1SDSR1       __REG(0x80020084)  /* Ser. port 1 SDLC Status Reg. 1  */
+
+#define SDCR0_SUS       0x00000001      /* SDLC/UART Select                */
+#define SDCR0_SDLC      (SDCR0_SUS*0)   /*  SDLC mode (TXD1 & RXD1)        */
+#define SDCR0_UART      (SDCR0_SUS*1)   /*  UART mode (TXD1 & RXD1)        */
+#define SDCR0_SDF       0x00000002      /* Single/Double start Flag select */
+#define SDCR0_SglFlg    (SDCR0_SDF*0)   /*  Single start Flag              */
+#define SDCR0_DblFlg    (SDCR0_SDF*1)   /*  Double start Flag              */
+#define SDCR0_LBM       0x00000004      /* Look-Back Mode                  */
+#define SDCR0_BMS       0x00000008      /* Bit Modulation Select           */
+#define SDCR0_FM0       (SDCR0_BMS*0)   /*  Freq. Modulation zero (0)      */
+#define SDCR0_NRZ       (SDCR0_BMS*1)   /*  Non-Return to Zero modulation  */
+#define SDCR0_SCE       0x00000010      /* Sample Clock Enable (GPIO [16]) */
+#define SDCR0_SCD       0x00000020      /* Sample Clock Direction select   */
+                                        /* (GPIO [16])                     */
+#define SDCR0_SClkIn    (SDCR0_SCD*0)   /*  Sample Clock Input             */
+#define SDCR0_SClkOut   (SDCR0_SCD*1)   /*  Sample Clock Output            */
+#define SDCR0_RCE       0x00000040      /* Receive Clock Edge select       */
+#define SDCR0_RcRsEdg   (SDCR0_RCE*0)   /*  Receive clock Rising-Edge      */
+#define SDCR0_RcFlEdg   (SDCR0_RCE*1)   /*  Receive clock Falling-Edge     */
+#define SDCR0_TCE       0x00000080      /* Transmit Clock Edge select      */
+#define SDCR0_TrRsEdg   (SDCR0_TCE*0)   /*  Transmit clock Rising-Edge     */
+#define SDCR0_TrFlEdg   (SDCR0_TCE*1)   /*  Transmit clock Falling-Edge    */
+
+#define SDCR1_AAF       0x00000001      /* Abort After Frame enable        */
+                                        /* (GPIO [17])                     */
+#define SDCR1_TXE       0x00000002      /* Transmit Enable                 */
+#define SDCR1_RXE       0x00000004      /* Receive Enable                  */
+#define SDCR1_RIE       0x00000008      /* Receive FIFO 1/3-to-2/3-full or */
+                                        /* more Interrupt Enable           */
+#define SDCR1_TIE       0x00000010      /* Transmit FIFO 1/2-full or less  */
+                                        /* Interrupt Enable                */
+#define SDCR1_AME       0x00000020      /* Address Match Enable            */
+#define SDCR1_TUS       0x00000040      /* Transmit FIFO Under-run Select  */
+#define SDCR1_EFrmURn   (SDCR1_TUS*0)   /*  End Frame on Under-Run         */
+#define SDCR1_AbortURn  (SDCR1_TUS*1)   /*  Abort on Under-Run             */
+#define SDCR1_RAE       0x00000080      /* Receive Abort interrupt Enable  */
+
+#define SDCR2_AMV       Fld (8, 0)      /* Address Match Value             */
+
+#define SDCR3_BRD       Fld (4, 0)      /* Baud Rate Divisor/16 - 1 [11:8] */
+#define SDCR4_BRD       Fld (8, 0)      /* Baud Rate Divisor/16 - 1  [7:0] */
+                                        /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
+                                        /* Tsd = 16*(BRD[11:0] + 1)*Txtl   */
+#define SDCR3_BdRtDiv(Div)              /*  Baud Rate Divisor [16..65536]  */ \
+                        (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
+                         FShft (SDCR3_BRD))
+#define SDCR4_BdRtDiv(Div)              /*  Baud Rate Divisor [16..65536]  */ \
+                        (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
+                         FShft (SDCR4_BRD))
+                                        /*  fsd = fxtl/(16*Floor (Div/16)) */
+                                        /*  Tsd = 16*Floor (Div/16)*Txtl   */
+#define SDCR3_CeilBdRtDiv(Div)          /*  Ceil. of BdRtDiv [16..65536]   */ \
+                        (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
+                         FShft (SDCR3_BRD))
+#define SDCR4_CeilBdRtDiv(Div)          /*  Ceil. of BdRtDiv [16..65536]   */ \
+                        (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
+                         FShft (SDCR4_BRD))
+                                        /*  fsd = fxtl/(16*Ceil (Div/16))  */
+                                        /*  Tsd = 16*Ceil (Div/16)*Txtl    */
+
+#define SDDR_DATA       Fld (8, 0)      /* receive/transmit DATA FIFOs     */
+#if 0                                   /* Hidden receive FIFO bits        */
+#define SDDR_EOF        0x00000100      /*  receive End-Of-Frame (read)    */
+#define SDDR_CRE        0x00000200      /*  receive CRC Error (read)       */
+#define SDDR_ROR        0x00000400      /*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define SDSR0_EIF       0x00000001      /* Error In FIFO (read)            */
+#define SDSR0_TUR       0x00000002      /* Transmit FIFO Under-Run         */
+#define SDSR0_RAB       0x00000004      /* Receive ABort                   */
+#define SDSR0_TFS       0x00000008      /* Transmit FIFO 1/2-full or less  */
+                                        /* Service request (read)          */
+#define SDSR0_RFS       0x00000010      /* Receive FIFO 1/3-to-2/3-full or */
+                                        /* more Service request (read)     */
+
+#define SDSR1_RSY       0x00000001      /* Receiver SYnchronized (read)    */
+#define SDSR1_TBY       0x00000002      /* Transmitter BusY (read)         */
+#define SDSR1_RNE       0x00000004      /* Receive FIFO Not Empty (read)   */
+#define SDSR1_TNF       0x00000008      /* Transmit FIFO Not Full (read)   */
+#define SDSR1_RTD       0x00000010      /* Receive Transition Detected     */
+#define SDSR1_EOF       0x00000020      /* receive End-Of-Frame (read)     */
+#define SDSR1_CRE       0x00000040      /* receive CRC Error (read)        */
+#define SDSR1_ROR       0x00000080      /* Receive FIFO Over-Run (read)    */
+
+
+/*
+ * High-Speed Serial to Parallel controller (HSSP) control registers
+ *
+ * Registers
+ *    Ser2HSCR0         Serial port 2 High-Speed Serial to Parallel
+ *                      controller (HSSP) Control Register 0 (read/write).
+ *    Ser2HSCR1         Serial port 2 High-Speed Serial to Parallel
+ *                      controller (HSSP) Control Register 1 (read/write).
+ *    Ser2HSDR          Serial port 2 High-Speed Serial to Parallel
+ *                      controller (HSSP) Data Register (read/write).
+ *    Ser2HSSR0         Serial port 2 High-Speed Serial to Parallel
+ *                      controller (HSSP) Status Register 0 (read/write).
+ *    Ser2HSSR1         Serial port 2 High-Speed Serial to Parallel
+ *                      controller (HSSP) Status Register 1 (read).
+ *    Ser2HSCR2         Serial port 2 High-Speed Serial to Parallel
+ *                      controller (HSSP) Control Register 2 (read/write).
+ *                      [The HSCR2 register is only implemented in
+ *                      versions 2.0 (rev. = 8) and higher of the StrongARM
+ *                      SA-1100.]
+ */
+
+#define Ser2HSCR0       __REG(0x80040060)  /* Ser. port 2 HSSP Control Reg. 0 */
+#define Ser2HSCR1       __REG(0x80040064)  /* Ser. port 2 HSSP Control Reg. 1 */
+#define Ser2HSDR        __REG(0x8004006C)  /* Ser. port 2 HSSP Data Reg.      */
+#define Ser2HSSR0       __REG(0x80040074)  /* Ser. port 2 HSSP Status Reg. 0  */
+#define Ser2HSSR1       __REG(0x80040078)  /* Ser. port 2 HSSP Status Reg. 1  */
+#define Ser2HSCR2       __REG(0x90060028)  /* Ser. port 2 HSSP Control Reg. 2 */
+
+#define HSCR0_ITR       0x00000001      /* IrDA Transmission Rate          */
+#define HSCR0_UART      (HSCR0_ITR*0)   /*  UART mode (115.2 kb/s if IrDA) */
+#define HSCR0_HSSP      (HSCR0_ITR*1)   /*  HSSP mode (4 Mb/s)             */
+#define HSCR0_LBM       0x00000002      /* Look-Back Mode                  */
+#define HSCR0_TUS       0x00000004      /* Transmit FIFO Under-run Select  */
+#define HSCR0_EFrmURn   (HSCR0_TUS*0)   /*  End Frame on Under-Run         */
+#define HSCR0_AbortURn  (HSCR0_TUS*1)   /*  Abort on Under-Run             */
+#define HSCR0_TXE       0x00000008      /* Transmit Enable                 */
+#define HSCR0_RXE       0x00000010      /* Receive Enable                  */
+#define HSCR0_RIE       0x00000020      /* Receive FIFO 2/5-to-3/5-full or */
+                                        /* more Interrupt Enable           */
+#define HSCR0_TIE       0x00000040      /* Transmit FIFO 1/2-full or less  */
+                                        /* Interrupt Enable                */
+#define HSCR0_AME       0x00000080      /* Address Match Enable            */
+
+#define HSCR1_AMV       Fld (8, 0)      /* Address Match Value             */
+
+#define HSDR_DATA       Fld (8, 0)      /* receive/transmit DATA FIFOs     */
+#if 0                                   /* Hidden receive FIFO bits        */
+#define HSDR_EOF        0x00000100      /*  receive End-Of-Frame (read)    */
+#define HSDR_CRE        0x00000200      /*  receive CRC Error (read)       */
+#define HSDR_ROR        0x00000400      /*  Receive FIFO Over-Run (read)   */
+#endif /* 0 */
+
+#define HSSR0_EIF       0x00000001      /* Error In FIFO (read)            */
+#define HSSR0_TUR       0x00000002      /* Transmit FIFO Under-Run         */
+#define HSSR0_RAB       0x00000004      /* Receive ABort                   */
+#define HSSR0_TFS       0x00000008      /* Transmit FIFO 1/2-full or less  */
+                                        /* Service request (read)          */
+#define HSSR0_RFS       0x00000010      /* Receive FIFO 2/5-to-3/5-full or */
+                                        /* more Service request (read)     */
+#define HSSR0_FRE       0x00000020      /* receive FRaming Error           */
+
+#define HSSR1_RSY       0x00000001      /* Receiver SYnchronized (read)    */
+#define HSSR1_TBY       0x00000002      /* Transmitter BusY (read)         */
+#define HSSR1_RNE       0x00000004      /* Receive FIFO Not Empty (read)   */
+#define HSSR1_TNF       0x00000008      /* Transmit FIFO Not Full (read)   */
+#define HSSR1_EOF       0x00000010      /* receive End-Of-Frame (read)     */
+#define HSSR1_CRE       0x00000020      /* receive CRC Error (read)        */
+#define HSSR1_ROR       0x00000040      /* Receive FIFO Over-Run (read)    */
+
+#define HSCR2_TXP       0x00040000      /* Transmit data Polarity (TXD_2)  */
+#define HSCR2_TrDataL   (HSCR2_TXP*0)   /*  Transmit Data active Low       */
+                                        /*  (inverted)                     */
+#define HSCR2_TrDataH   (HSCR2_TXP*1)   /*  Transmit Data active High      */
+                                        /*  (non-inverted)                 */
+#define HSCR2_RXP       0x00080000      /* Receive data Polarity (RXD_2)   */
+#define HSCR2_RcDataL   (HSCR2_RXP*0)   /*  Receive Data active Low        */
+                                        /*  (inverted)                     */
+#define HSCR2_RcDataH   (HSCR2_RXP*1)   /*  Receive Data active High       */
+                                        /*  (non-inverted)                 */
+
+
+/*
+ * Multi-media Communications Port (MCP) control registers
+ *
+ * Registers
+ *    Ser4MCCR0         Serial port 4 Multi-media Communications Port (MCP)
+ *                      Control Register 0 (read/write).
+ *    Ser4MCDR0         Serial port 4 Multi-media Communications Port (MCP)
+ *                      Data Register 0 (audio, read/write).
+ *    Ser4MCDR1         Serial port 4 Multi-media Communications Port (MCP)
+ *                      Data Register 1 (telecom, read/write).
+ *    Ser4MCDR2         Serial port 4 Multi-media Communications Port (MCP)
+ *                      Data Register 2 (CODEC registers, read/write).
+ *    Ser4MCSR          Serial port 4 Multi-media Communications Port (MCP)
+ *                      Status Register (read/write).
+ *    Ser4MCCR1         Serial port 4 Multi-media Communications Port (MCP)
+ *                      Control Register 1 (read/write).
+ *                      [The MCCR1 register is only implemented in
+ *                      versions 2.0 (rev. = 8) and higher of the StrongARM
+ *                      SA-1100.]
+ *
+ * Clocks
+ *    fmc, Tmc          Frequency, period of the MCP communication (10 MHz,
+ *                      12 MHz, or GPIO [21]).
+ *    faud, Taud        Frequency, period of the audio sampling.
+ *    ftcm, Ttcm        Frequency, period of the telecom sampling.
+ */
+
+#define Ser4MCCR0       __REG(0x80060000)  /* Ser. port 4 MCP Control Reg. 0 */
+#define Ser4MCDR0       __REG(0x80060008)  /* Ser. port 4 MCP Data Reg. 0 (audio) */
+#define Ser4MCDR1       __REG(0x8006000C)  /* Ser. port 4 MCP Data Reg. 1 (telecom) */
+#define Ser4MCDR2       __REG(0x80060010)  /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
+#define Ser4MCSR        __REG(0x80060018)  /* Ser. port 4 MCP Status Reg. */
+#define Ser4MCCR1       __REG(0x90060030)  /* Ser. port 4 MCP Control Reg. 1 */
+
+#define MCCR0_ASD       Fld (7, 0)      /* Audio Sampling rate Divisor/32  */
+                                        /* [6..127]                        */
+                                        /* faud = fmc/(32*ASD)             */
+                                        /* Taud = 32*ASD*Tmc               */
+#define MCCR0_AudSmpDiv(Div)            /*  Audio Sampling rate Divisor    */ \
+                                        /*  [192..4064]                    */ \
+                        ((Div)/32 << FShft (MCCR0_ASD))
+                                        /*  faud = fmc/(32*Floor (Div/32)) */
+                                        /*  Taud = 32*Floor (Div/32)*Tmc   */
+#define MCCR0_CeilAudSmpDiv(Div)        /*  Ceil. of AudSmpDiv [192..4064] */ \
+                        (((Div) + 31)/32 << FShft (MCCR0_ASD))
+                                        /*  faud = fmc/(32*Ceil (Div/32))  */
+                                        /*  Taud = 32*Ceil (Div/32)*Tmc    */
+#define MCCR0_TSD       Fld (7, 8)      /* Telecom Sampling rate           */
+                                        /* Divisor/32 [16..127]            */
+                                        /* ftcm = fmc/(32*TSD)             */
+                                        /* Ttcm = 32*TSD*Tmc               */
+#define MCCR0_TcmSmpDiv(Div)            /*  Telecom Sampling rate Divisor  */ \
+                                        /*  [512..4064]                    */ \
+                        ((Div)/32 << FShft (MCCR0_TSD))
+                                        /*  ftcm = fmc/(32*Floor (Div/32)) */
+                                        /*  Ttcm = 32*Floor (Div/32)*Tmc   */
+#define MCCR0_CeilTcmSmpDiv(Div)        /*  Ceil. of TcmSmpDiv [512..4064] */ \
+                        (((Div) + 31)/32 << FShft (MCCR0_TSD))
+                                        /*  ftcm = fmc/(32*Ceil (Div/32))  */
+                                        /*  Ttcm = 32*Ceil (Div/32)*Tmc    */
+#define MCCR0_MCE       0x00010000      /* MCP Enable                      */
+#define MCCR0_ECS       0x00020000      /* External Clock Select           */
+#define MCCR0_IntClk    (MCCR0_ECS*0)   /*  Internal Clock (10 or 12 MHz)  */
+#define MCCR0_ExtClk    (MCCR0_ECS*1)   /*  External Clock (GPIO [21])     */
+#define MCCR0_ADM       0x00040000      /* A/D (audio/telecom) data        */
+                                        /* sampling/storing Mode           */
+#define MCCR0_VldBit    (MCCR0_ADM*0)   /*  Valid Bit storing mode         */
+#define MCCR0_SmpCnt    (MCCR0_ADM*1)   /*  Sampling Counter storing mode  */
+#define MCCR0_TTE       0x00080000      /* Telecom Transmit FIFO 1/2-full  */
+                                        /* or less interrupt Enable        */
+#define MCCR0_TRE       0x00100000      /* Telecom Receive FIFO 1/2-full   */
+                                        /* or more interrupt Enable        */
+#define MCCR0_ATE       0x00200000      /* Audio Transmit FIFO 1/2-full    */
+                                        /* or less interrupt Enable        */
+#define MCCR0_ARE       0x00400000      /* Audio Receive FIFO 1/2-full or  */
+                                        /* more interrupt Enable           */
+#define MCCR0_LBM       0x00800000      /* Look-Back Mode                  */
+#define MCCR0_ECP       Fld (2, 24)     /* External Clock Prescaler - 1    */
+#define MCCR0_ExtClkDiv(Div)            /*  External Clock Divisor [1..4]  */ \
+                        (((Div) - 1) << FShft (MCCR0_ECP))
+
+#define MCDR0_DATA      Fld (12, 4)     /* receive/transmit audio DATA     */
+                                        /* FIFOs                           */
+
+#define MCDR1_DATA      Fld (14, 2)     /* receive/transmit telecom DATA   */
+                                        /* FIFOs                           */
+
+                                        /* receive/transmit CODEC reg.     */
+                                        /* FIFOs:                          */
+#define MCDR2_DATA      Fld (16, 0)     /*  reg. DATA                      */
+#define MCDR2_RW        0x00010000      /*  reg. Read/Write (transmit)     */
+#define MCDR2_Rd        (MCDR2_RW*0)    /*   reg. Read                     */
+#define MCDR2_Wr        (MCDR2_RW*1)    /*   reg. Write                    */
+#define MCDR2_ADD       Fld (4, 17)     /*  reg. ADDress                   */
+
+#define MCSR_ATS        0x00000001      /* Audio Transmit FIFO 1/2-full    */
+                                        /* or less Service request (read)  */
+#define MCSR_ARS        0x00000002      /* Audio Receive FIFO 1/2-full or  */
+                                        /* more Service request (read)     */
+#define MCSR_TTS        0x00000004      /* Telecom Transmit FIFO 1/2-full  */
+                                        /* or less Service request (read)  */
+#define MCSR_TRS        0x00000008      /* Telecom Receive FIFO 1/2-full   */
+                                        /* or more Service request (read)  */
+#define MCSR_ATU        0x00000010      /* Audio Transmit FIFO Under-run   */
+#define MCSR_ARO        0x00000020      /* Audio Receive FIFO Over-run     */
+#define MCSR_TTU        0x00000040      /* Telecom Transmit FIFO Under-run */
+#define MCSR_TRO        0x00000080      /* Telecom Receive FIFO Over-run   */
+#define MCSR_ANF        0x00000100      /* Audio transmit FIFO Not Full    */
+                                        /* (read)                          */
+#define MCSR_ANE        0x00000200      /* Audio receive FIFO Not Empty    */
+                                        /* (read)                          */
+#define MCSR_TNF        0x00000400      /* Telecom transmit FIFO Not Full  */
+                                        /* (read)                          */
+#define MCSR_TNE        0x00000800      /* Telecom receive FIFO Not Empty  */
+                                        /* (read)                          */
+#define MCSR_CWC        0x00001000      /* CODEC register Write Completed  */
+                                        /* (read)                          */
+#define MCSR_CRC        0x00002000      /* CODEC register Read Completed   */
+                                        /* (read)                          */
+#define MCSR_ACE        0x00004000      /* Audio CODEC Enabled (read)      */
+#define MCSR_TCE        0x00008000      /* Telecom CODEC Enabled (read)    */
+
+#define MCCR1_CFS       0x00100000      /* Clock Freq. Select              */
+#define MCCR1_F12MHz    (MCCR1_CFS*0)   /*  Freq. (fmc) = ~ 12 MHz         */
+                                        /*  (11.981 MHz)                   */
+#define MCCR1_F10MHz    (MCCR1_CFS*1)   /*  Freq. (fmc) = ~ 10 MHz         */
+                                        /*  (9.585 MHz)                    */
+
+
+/*
+ * Synchronous Serial Port (SSP) control registers
+ *
+ * Registers
+ *    Ser4SSCR0         Serial port 4 Synchronous Serial Port (SSP) Control
+ *                      Register 0 (read/write).
+ *    Ser4SSCR1         Serial port 4 Synchronous Serial Port (SSP) Control
+ *                      Register 1 (read/write).
+ *                      [Bits SPO and SP are only implemented in versions 2.0
+ *                      (rev. = 8) and higher of the StrongARM SA-1100.]
+ *    Ser4SSDR          Serial port 4 Synchronous Serial Port (SSP) Data
+ *                      Register (read/write).
+ *    Ser4SSSR          Serial port 4 Synchronous Serial Port (SSP) Status
+ *                      Register (read/write).
+ *
+ * Clocks
+ *    fxtl, Txtl        Frequency, period of the system crystal (3.6864 MHz
+ *                      or 3.5795 MHz).
+ *    fss, Tss          Frequency, period of the SSP communication.
+ */
+
+#define Ser4SSCR0       __REG(0x80070060)  /* Ser. port 4 SSP Control Reg. 0 */
+#define Ser4SSCR1       __REG(0x80070064)  /* Ser. port 4 SSP Control Reg. 1 */
+#define Ser4SSDR        __REG(0x8007006C)  /* Ser. port 4 SSP Data Reg. */
+#define Ser4SSSR        __REG(0x80070074)  /* Ser. port 4 SSP Status Reg. */
+
+#define SSCR0_DSS       Fld (4, 0)      /* Data Size - 1 Select [3..15]    */
+#define SSCR0_DataSize(Size)            /*  Data Size Select [4..16]       */ \
+                        (((Size) - 1) << FShft (SSCR0_DSS))
+#define SSCR0_FRF       Fld (2, 4)      /* FRame Format                    */
+#define SSCR0_Motorola                  /*  Motorola Serial Peripheral     */ \
+                                        /*  Interface (SPI) format         */ \
+                        (0 << FShft (SSCR0_FRF))
+#define SSCR0_TI                        /*  Texas Instruments Synchronous  */ \
+                                        /*  Serial format                  */ \
+                        (1 << FShft (SSCR0_FRF))
+#define SSCR0_National                  /*  National Microwire format      */ \
+                        (2 << FShft (SSCR0_FRF))
+#define SSCR0_SSE       0x00000080      /* SSP Enable                      */
+#define SSCR0_SCR       Fld (8, 8)      /* Serial Clock Rate divisor/2 - 1 */
+                                        /* fss = fxtl/(2*(SCR + 1))        */
+                                        /* Tss = 2*(SCR + 1)*Txtl          */
+#define SSCR0_SerClkDiv(Div)            /*  Serial Clock Divisor [2..512]  */ \
+                        (((Div) - 2)/2 << FShft (SSCR0_SCR))
+                                        /*  fss = fxtl/(2*Floor (Div/2))   */
+                                        /*  Tss = 2*Floor (Div/2)*Txtl     */
+#define SSCR0_CeilSerClkDiv(Div)        /*  Ceil. of SerClkDiv [2..512]    */ \
+                        (((Div) - 1)/2 << FShft (SSCR0_SCR))
+                                        /*  fss = fxtl/(2*Ceil (Div/2))    */
+                                        /*  Tss = 2*Ceil (Div/2)*Txtl      */
+
+#define SSCR1_RIE       0x00000001      /* Receive FIFO 1/2-full or more   */
+                                        /* Interrupt Enable                */
+#define SSCR1_TIE       0x00000002      /* Transmit FIFO 1/2-full or less  */
+                                        /* Interrupt Enable                */
+#define SSCR1_LBM       0x00000004      /* Look-Back Mode                  */
+#define SSCR1_SPO       0x00000008      /* Sample clock (SCLK) POlarity    */
+#define SSCR1_SClkIactL (SSCR1_SPO*0)   /*  Sample Clock Inactive Low      */
+#define SSCR1_SClkIactH (SSCR1_SPO*1)   /*  Sample Clock Inactive High     */
+#define SSCR1_SP        0x00000010      /* Sample clock (SCLK) Phase       */
+#define SSCR1_SClk1P    (SSCR1_SP*0)    /*  Sample Clock active 1 Period   */
+                                        /*  after frame (SFRM, 1st edge)   */
+#define SSCR1_SClk1_2P  (SSCR1_SP*1)    /*  Sample Clock active 1/2 Period */
+                                        /*  after frame (SFRM, 1st edge)   */
+#define SSCR1_ECS       0x00000020      /* External Clock Select           */
+#define SSCR1_IntClk    (SSCR1_ECS*0)   /*  Internal Clock                 */
+#define SSCR1_ExtClk    (SSCR1_ECS*1)   /*  External Clock (GPIO [19])     */
+
+#define SSDR_DATA       Fld (16, 0)     /* receive/transmit DATA FIFOs     */
+
+#define SSSR_TNF        0x00000002      /* Transmit FIFO Not Full (read)   */
+#define SSSR_RNE        0x00000004      /* Receive FIFO Not Empty (read)   */
+#define SSSR_BSY        0x00000008      /* SSP BuSY (read)                 */
+#define SSSR_TFS        0x00000010      /* Transmit FIFO 1/2-full or less  */
+                                        /* Service request (read)          */
+#define SSSR_RFS        0x00000020      /* Receive FIFO 1/2-full or more   */
+                                        /* Service request (read)          */
+#define SSSR_ROR        0x00000040      /* Receive FIFO Over-Run           */
+
+
+/*
+ * Operating System (OS) timer control registers
+ *
+ * Registers
+ *    OSMR0             Operating System (OS) timer Match Register 0
+ *                      (read/write).
+ *    OSMR1             Operating System (OS) timer Match Register 1
+ *                      (read/write).
+ *    OSMR2             Operating System (OS) timer Match Register 2
+ *                      (read/write).
+ *    OSMR3             Operating System (OS) timer Match Register 3
+ *                      (read/write).
+ *    OSCR              Operating System (OS) timer Counter Register
+ *                      (read/write).
+ *    OSSR              Operating System (OS) timer Status Register
+ *                      (read/write).
+ *    OWER              Operating System (OS) timer Watch-dog Enable Register
+ *                      (read/write).
+ *    OIER              Operating System (OS) timer Interrupt Enable Register
+ *                      (read/write).
+ */
+
+#define OSMR0           __REG(0x90000000)  /* OS timer Match Reg. 0 */
+#define OSMR1           __REG(0x90000004)  /* OS timer Match Reg. 1 */
+#define OSMR2           __REG(0x90000008)  /* OS timer Match Reg. 2 */
+#define OSMR3           __REG(0x9000000c)  /* OS timer Match Reg. 3 */
+#define OSCR    __REG(0x90000010)  /* OS timer Counter Reg. */
+#define OSSR    __REG(0x90000014        )  /* OS timer Status Reg. */
+#define OWER    __REG(0x90000018        )  /* OS timer Watch-dog Enable Reg. */
+#define OIER    __REG(0x9000001C        )  /* OS timer Interrupt Enable Reg. */
+
+#define OSSR_M(Nb)                      /* Match detected [0..3]           */ \
+                        (0x00000001 << (Nb))
+#define OSSR_M0         OSSR_M (0)      /* Match detected 0                */
+#define OSSR_M1         OSSR_M (1)      /* Match detected 1                */
+#define OSSR_M2         OSSR_M (2)      /* Match detected 2                */
+#define OSSR_M3         OSSR_M (3)      /* Match detected 3                */
+
+#define OWER_WME        0x00000001      /* Watch-dog Match Enable          */
+                                        /* (set only)                      */
+
+#define OIER_E(Nb)                      /* match interrupt Enable [0..3]   */ \
+                        (0x00000001 << (Nb))
+#define OIER_E0         OIER_E (0)      /* match interrupt Enable 0        */
+#define OIER_E1         OIER_E (1)      /* match interrupt Enable 1        */
+#define OIER_E2         OIER_E (2)      /* match interrupt Enable 2        */
+#define OIER_E3         OIER_E (3)      /* match interrupt Enable 3        */
+
+
+/*
+ * Real-Time Clock (RTC) control registers
+ *
+ * Registers
+ *    RTAR              Real-Time Clock (RTC) Alarm Register (read/write).
+ *    RCNR              Real-Time Clock (RTC) CouNt Register (read/write).
+ *    RTTR              Real-Time Clock (RTC) Trim Register (read/write).
+ *    RTSR              Real-Time Clock (RTC) Status Register (read/write).
+ *
+ * Clocks
+ *    frtx, Trtx        Frequency, period of the real-time clock crystal
+ *                      (32.768 kHz nominal).
+ *    frtc, Trtc        Frequency, period of the real-time clock counter
+ *                      (1 Hz nominal).
+ */
+
+#define RTAR            __REG(0x90010000)  /* RTC Alarm Reg. */
+#define RCNR            __REG(0x90010004)  /* RTC CouNt Reg. */
+#define RTTR            __REG(0x90010008)  /* RTC Trim Reg. */
+#define RTSR            __REG(0x90010010)  /* RTC Status Reg. */
+
+#define RTTR_C          Fld (16, 0)     /* clock divider Count - 1         */
+#define RTTR_D          Fld (10, 16)    /* trim Delete count               */
+                                        /* frtc = (1023*(C + 1) - D)*frtx/ */
+                                        /*        (1023*(C + 1)^2)         */
+                                        /* Trtc = (1023*(C + 1)^2)*Trtx/   */
+                                        /*        (1023*(C + 1) - D)       */
+
+#define RTSR_AL         0x00000001      /* ALarm detected                  */
+#define RTSR_HZ         0x00000002      /* 1 Hz clock detected             */
+#define RTSR_ALE        0x00000004      /* ALarm interrupt Enable          */
+#define RTSR_HZE        0x00000008      /* 1 Hz clock interrupt Enable     */
+
+
+/*
+ * Power Manager (PM) control registers
+ *
+ * Registers
+ *    PMCR              Power Manager (PM) Control Register (read/write).
+ *    PSSR              Power Manager (PM) Sleep Status Register (read/write).
+ *    PSPR              Power Manager (PM) Scratch-Pad Register (read/write).
+ *    PWER              Power Manager (PM) Wake-up Enable Register
+ *                      (read/write).
+ *    PCFR              Power Manager (PM) general ConFiguration Register
+ *                      (read/write).
+ *    PPCR              Power Manager (PM) Phase-Locked Loop (PLL)
+ *                      Configuration Register (read/write).
+ *    PGSR              Power Manager (PM) General-Purpose Input/Output (GPIO)
+ *                      Sleep state Register (read/write, see GPIO pins).
+ *    POSR              Power Manager (PM) Oscillator Status Register (read).
+ *
+ * Clocks
+ *    fxtl, Txtl        Frequency, period of the system crystal (3.6864 MHz
+ *                      or 3.5795 MHz).
+ *    fcpu, Tcpu        Frequency, period of the CPU core clock (CCLK).
+ */
+
+#define PMCR            __REG(0x90020000)  /* PM Control Reg. */
+#define PSSR            __REG(0x90020004)  /* PM Sleep Status Reg. */
+#define PSPR            __REG(0x90020008)  /* PM Scratch-Pad Reg. */
+#define PWER            __REG(0x9002000C)  /* PM Wake-up Enable Reg. */
+#define PCFR            __REG(0x90020010)  /* PM general ConFiguration Reg. */
+#define PPCR            __REG(0x90020014)  /* PM PLL Configuration Reg. */
+#define PGSR            __REG(0x90020018)  /* PM GPIO Sleep state Reg. */
+#define POSR            __REG(0x9002001C)  /* PM Oscillator Status Reg. */
+
+#define PMCR_SF         0x00000001      /* Sleep Force (set only)          */
+
+#define PSSR_SS         0x00000001      /* Software Sleep                  */
+#define PSSR_BFS        0x00000002      /* Battery Fault Status            */
+                                        /* (BATT_FAULT)                    */
+#define PSSR_VFS        0x00000004      /* Vdd Fault Status (VDD_FAULT)    */
+#define PSSR_DH         0x00000008      /* DRAM control Hold               */
+#define PSSR_PH         0x00000010      /* Peripheral control Hold         */
+
+#define PWER_GPIO(Nb)   GPIO_GPIO (Nb)  /* GPIO [0..27] wake-up enable     */
+#define PWER_GPIO0      PWER_GPIO (0)   /* GPIO  [0] wake-up enable        */
+#define PWER_GPIO1      PWER_GPIO (1)   /* GPIO  [1] wake-up enable        */
+#define PWER_GPIO2      PWER_GPIO (2)   /* GPIO  [2] wake-up enable        */
+#define PWER_GPIO3      PWER_GPIO (3)   /* GPIO  [3] wake-up enable        */
+#define PWER_GPIO4      PWER_GPIO (4)   /* GPIO  [4] wake-up enable        */
+#define PWER_GPIO5      PWER_GPIO (5)   /* GPIO  [5] wake-up enable        */
+#define PWER_GPIO6      PWER_GPIO (6)   /* GPIO  [6] wake-up enable        */
+#define PWER_GPIO7      PWER_GPIO (7)   /* GPIO  [7] wake-up enable        */
+#define PWER_GPIO8      PWER_GPIO (8)   /* GPIO  [8] wake-up enable        */
+#define PWER_GPIO9      PWER_GPIO (9)   /* GPIO  [9] wake-up enable        */
+#define PWER_GPIO10     PWER_GPIO (10)  /* GPIO [10] wake-up enable        */
+#define PWER_GPIO11     PWER_GPIO (11)  /* GPIO [11] wake-up enable        */
+#define PWER_GPIO12     PWER_GPIO (12)  /* GPIO [12] wake-up enable        */
+#define PWER_GPIO13     PWER_GPIO (13)  /* GPIO [13] wake-up enable        */
+#define PWER_GPIO14     PWER_GPIO (14)  /* GPIO [14] wake-up enable        */
+#define PWER_GPIO15     PWER_GPIO (15)  /* GPIO [15] wake-up enable        */
+#define PWER_GPIO16     PWER_GPIO (16)  /* GPIO [16] wake-up enable        */
+#define PWER_GPIO17     PWER_GPIO (17)  /* GPIO [17] wake-up enable        */
+#define PWER_GPIO18     PWER_GPIO (18)  /* GPIO [18] wake-up enable        */
+#define PWER_GPIO19     PWER_GPIO (19)  /* GPIO [19] wake-up enable        */
+#define PWER_GPIO20     PWER_GPIO (20)  /* GPIO [20] wake-up enable        */
+#define PWER_GPIO21     PWER_GPIO (21)  /* GPIO [21] wake-up enable        */
+#define PWER_GPIO22     PWER_GPIO (22)  /* GPIO [22] wake-up enable        */
+#define PWER_GPIO23     PWER_GPIO (23)  /* GPIO [23] wake-up enable        */
+#define PWER_GPIO24     PWER_GPIO (24)  /* GPIO [24] wake-up enable        */
+#define PWER_GPIO25     PWER_GPIO (25)  /* GPIO [25] wake-up enable        */
+#define PWER_GPIO26     PWER_GPIO (26)  /* GPIO [26] wake-up enable        */
+#define PWER_GPIO27     PWER_GPIO (27)  /* GPIO [27] wake-up enable        */
+#define PWER_RTC        0x80000000      /* RTC alarm wake-up enable        */
+
+#define PCFR_OPDE       0x00000001      /* Oscillator Power-Down Enable    */
+#define PCFR_ClkRun     (PCFR_OPDE*0)   /*  Clock Running in sleep mode    */
+#define PCFR_ClkStp     (PCFR_OPDE*1)   /*  Clock Stopped in sleep mode    */
+#define PCFR_FP         0x00000002      /* Float PCMCIA pins               */
+#define PCFR_PCMCIANeg  (PCFR_FP*0)     /*  PCMCIA pins Negated (1)        */
+#define PCFR_PCMCIAFlt  (PCFR_FP*1)     /*  PCMCIA pins Floating           */
+#define PCFR_FS         0x00000004      /* Float Static memory pins        */
+#define PCFR_StMemNeg   (PCFR_FS*0)     /*  Static Memory pins Negated (1) */
+#define PCFR_StMemFlt   (PCFR_FS*1)     /*  Static Memory pins Floating    */
+#define PCFR_FO         0x00000008      /* Force RTC oscillator            */
+                                        /* (32.768 kHz) enable On          */
+
+#define PPCR_CCF        Fld (5, 0)      /* CPU core Clock (CCLK) Freq.     */
+#define PPCR_Fx16                       /*  Freq. x 16 (fcpu = 16*fxtl)    */ \
+                        (0x00 << FShft (PPCR_CCF))
+#define PPCR_Fx20                       /*  Freq. x 20 (fcpu = 20*fxtl)    */ \
+                        (0x01 << FShft (PPCR_CCF))
+#define PPCR_Fx24                       /*  Freq. x 24 (fcpu = 24*fxtl)    */ \
+                        (0x02 << FShft (PPCR_CCF))
+#define PPCR_Fx28                       /*  Freq. x 28 (fcpu = 28*fxtl)    */ \
+                        (0x03 << FShft (PPCR_CCF))
+#define PPCR_Fx32                       /*  Freq. x 32 (fcpu = 32*fxtl)    */ \
+                        (0x04 << FShft (PPCR_CCF))
+#define PPCR_Fx36                       /*  Freq. x 36 (fcpu = 36*fxtl)    */ \
+                        (0x05 << FShft (PPCR_CCF))
+#define PPCR_Fx40                       /*  Freq. x 40 (fcpu = 40*fxtl)    */ \
+                        (0x06 << FShft (PPCR_CCF))
+#define PPCR_Fx44                       /*  Freq. x 44 (fcpu = 44*fxtl)    */ \
+                        (0x07 << FShft (PPCR_CCF))
+#define PPCR_Fx48                       /*  Freq. x 48 (fcpu = 48*fxtl)    */ \
+                        (0x08 << FShft (PPCR_CCF))
+#define PPCR_Fx52                       /*  Freq. x 52 (fcpu = 52*fxtl)    */ \
+                        (0x09 << FShft (PPCR_CCF))
+#define PPCR_Fx56                       /*  Freq. x 56 (fcpu = 56*fxtl)    */ \
+                        (0x0A << FShft (PPCR_CCF))
+#define PPCR_Fx60                       /*  Freq. x 60 (fcpu = 60*fxtl)    */ \
+                        (0x0B << FShft (PPCR_CCF))
+#define PPCR_Fx64                       /*  Freq. x 64 (fcpu = 64*fxtl)    */ \
+                        (0x0C << FShft (PPCR_CCF))
+#define PPCR_Fx68                       /*  Freq. x 68 (fcpu = 68*fxtl)    */ \
+                        (0x0D << FShft (PPCR_CCF))
+#define PPCR_Fx72                       /*  Freq. x 72 (fcpu = 72*fxtl)    */ \
+                        (0x0E << FShft (PPCR_CCF))
+#define PPCR_Fx76                       /*  Freq. x 76 (fcpu = 76*fxtl)    */ \
+                        (0x0F << FShft (PPCR_CCF))
+                                        /*  3.6864 MHz crystal (fxtl):     */
+#define PPCR_F59_0MHz   PPCR_Fx16       /*   Freq. (fcpu) =  59.0 MHz      */
+#define PPCR_F73_7MHz   PPCR_Fx20       /*   Freq. (fcpu) =  73.7 MHz      */
+#define PPCR_F88_5MHz   PPCR_Fx24       /*   Freq. (fcpu) =  88.5 MHz      */
+#define PPCR_F103_2MHz  PPCR_Fx28       /*   Freq. (fcpu) = 103.2 MHz      */
+#define PPCR_F118_0MHz  PPCR_Fx32       /*   Freq. (fcpu) = 118.0 MHz      */
+#define PPCR_F132_7MHz  PPCR_Fx36       /*   Freq. (fcpu) = 132.7 MHz      */
+#define PPCR_F147_5MHz  PPCR_Fx40       /*   Freq. (fcpu) = 147.5 MHz      */
+#define PPCR_F162_2MHz  PPCR_Fx44       /*   Freq. (fcpu) = 162.2 MHz      */
+#define PPCR_F176_9MHz  PPCR_Fx48       /*   Freq. (fcpu) = 176.9 MHz      */
+#define PPCR_F191_7MHz  PPCR_Fx52       /*   Freq. (fcpu) = 191.7 MHz      */
+#define PPCR_F206_4MHz  PPCR_Fx56       /*   Freq. (fcpu) = 206.4 MHz      */
+#define PPCR_F221_2MHz  PPCR_Fx60       /*   Freq. (fcpu) = 221.2 MHz      */
+#define PPCR_F239_6MHz  PPCR_Fx64       /*   Freq. (fcpu) = 239.6 MHz      */
+#define PPCR_F250_7MHz  PPCR_Fx68       /*   Freq. (fcpu) = 250.7 MHz      */
+#define PPCR_F265_4MHz  PPCR_Fx72       /*   Freq. (fcpu) = 265.4 MHz      */
+#define PPCR_F280_2MHz  PPCR_Fx76       /*   Freq. (fcpu) = 280.2 MHz      */
+                                        /*  3.5795 MHz crystal (fxtl):     */
+#define PPCR_F57_3MHz   PPCR_Fx16       /*   Freq. (fcpu) =  57.3 MHz      */
+#define PPCR_F71_6MHz   PPCR_Fx20       /*   Freq. (fcpu) =  71.6 MHz      */
+#define PPCR_F85_9MHz   PPCR_Fx24       /*   Freq. (fcpu) =  85.9 MHz      */
+#define PPCR_F100_2MHz  PPCR_Fx28       /*   Freq. (fcpu) = 100.2 MHz      */
+#define PPCR_F114_5MHz  PPCR_Fx32       /*   Freq. (fcpu) = 114.5 MHz      */
+#define PPCR_F128_9MHz  PPCR_Fx36       /*   Freq. (fcpu) = 128.9 MHz      */
+#define PPCR_F143_2MHz  PPCR_Fx40       /*   Freq. (fcpu) = 143.2 MHz      */
+#define PPCR_F157_5MHz  PPCR_Fx44       /*   Freq. (fcpu) = 157.5 MHz      */
+#define PPCR_F171_8MHz  PPCR_Fx48       /*   Freq. (fcpu) = 171.8 MHz      */
+#define PPCR_F186_1MHz  PPCR_Fx52       /*   Freq. (fcpu) = 186.1 MHz      */
+#define PPCR_F200_5MHz  PPCR_Fx56       /*   Freq. (fcpu) = 200.5 MHz      */
+#define PPCR_F214_8MHz  PPCR_Fx60       /*   Freq. (fcpu) = 214.8 MHz      */
+#define PPCR_F229_1MHz  PPCR_Fx64       /*   Freq. (fcpu) = 229.1 MHz      */
+#define PPCR_F243_4MHz  PPCR_Fx68       /*   Freq. (fcpu) = 243.4 MHz      */
+#define PPCR_F257_7MHz  PPCR_Fx72       /*   Freq. (fcpu) = 257.7 MHz      */
+#define PPCR_F272_0MHz  PPCR_Fx76       /*   Freq. (fcpu) = 272.0 MHz      */
+
+#define POSR_OOK        0x00000001      /* RTC Oscillator (32.768 kHz) OK  */
+
+
+/*
+ * Reset Controller (RC) control registers
+ *
+ * Registers
+ *    RSRR              Reset Controller (RC) Software Reset Register
+ *                      (read/write).
+ *    RCSR              Reset Controller (RC) Status Register (read/write).
+ */
+
+#define RSRR            __REG(0x90030000)  /* RC Software Reset Reg. */
+#define RCSR            __REG(0x90030004)  /* RC Status Reg. */
+
+#define RSRR_SWR        0x00000001      /* SoftWare Reset (set only)       */
+
+#define RCSR_HWR        0x00000001      /* HardWare Reset                  */
+#define RCSR_SWR        0x00000002      /* SoftWare Reset                  */
+#define RCSR_WDR        0x00000004      /* Watch-Dog Reset                 */
+#define RCSR_SMR        0x00000008      /* Sleep-Mode Reset                */
+
+
+/*
+ * Test unit control registers
+ *
+ * Registers
+ *    TUCR              Test Unit Control Register (read/write).
+ */
+
+#define TUCR            __REG(0x90030008)  /* Test Unit Control Reg. */
+
+#define TUCR_TIC        0x00000040      /* TIC mode                        */
+#define TUCR_TTST       0x00000080      /* Trim TeST mode                  */
+#define TUCR_RCRC       0x00000100      /* Richard's Cyclic Redundancy     */
+                                        /* Check                           */
+#define TUCR_PMD        0x00000200      /* Power Management Disable        */
+#define TUCR_MR         0x00000400      /* Memory Request mode             */
+#define TUCR_NoMB       (TUCR_MR*0)     /*  No Memory Bus request & grant  */
+#define TUCR_MBGPIO     (TUCR_MR*1)     /*  Memory Bus request (MBREQ) &   */
+                                        /*  grant (MBGNT) on GPIO [22:21]  */
+#define TUCR_CTB        Fld (3, 20)     /* Clock Test Bits                 */
+#define TUCR_FDC        0x00800000      /* RTC Force Delete Count          */
+#define TUCR_FMC        0x01000000      /* Force Michelle's Control mode   */
+#define TUCR_TMC        0x02000000      /* RTC Trimmer Multiplexer Control */
+#define TUCR_DPS        0x04000000      /* Disallow Pad Sleep              */
+#define TUCR_TSEL       Fld (3, 29)     /* clock Test SELect on GPIO [27]  */
+#define TUCR_32_768kHz                  /*  32.768 kHz osc. on GPIO [27]   */ \
+                        (0 << FShft (TUCR_TSEL))
+#define TUCR_3_6864MHz                  /*  3.6864 MHz osc. on GPIO [27]   */ \
+                        (1 << FShft (TUCR_TSEL))
+#define TUCR_VDD                        /*  VDD ring osc./16 on GPIO [27]  */ \
+                        (2 << FShft (TUCR_TSEL))
+#define TUCR_96MHzPLL                   /*  96 MHz PLL/4 on GPIO [27]      */ \
+                        (3 << FShft (TUCR_TSEL))
+#define TUCR_Clock                      /*  internal (fcpu/2) & 32.768 kHz */ \
+                                        /*  Clocks on GPIO [26:27]         */ \
+                        (4 << FShft (TUCR_TSEL))
+#define TUCR_3_6864MHzA                 /*  3.6864 MHz osc. on GPIO [27]   */ \
+                                        /*  (Alternative)                  */ \
+                        (5 << FShft (TUCR_TSEL))
+#define TUCR_MainPLL                    /*  Main PLL/16 on GPIO [27]       */ \
+                        (6 << FShft (TUCR_TSEL))
+#define TUCR_VDDL                       /*  VDDL ring osc./4 on GPIO [27]  */ \
+                        (7 << FShft (TUCR_TSEL))
+
+
+/*
+ * General-Purpose Input/Output (GPIO) control registers
+ *
+ * Registers
+ *    GPLR              General-Purpose Input/Output (GPIO) Pin Level
+ *                      Register (read).
+ *    GPDR              General-Purpose Input/Output (GPIO) Pin Direction
+ *                      Register (read/write).
+ *    GPSR              General-Purpose Input/Output (GPIO) Pin output Set
+ *                      Register (write).
+ *    GPCR              General-Purpose Input/Output (GPIO) Pin output Clear
+ *                      Register (write).
+ *    GRER              General-Purpose Input/Output (GPIO) Rising-Edge
+ *                      detect Register (read/write).
+ *    GFER              General-Purpose Input/Output (GPIO) Falling-Edge
+ *                      detect Register (read/write).
+ *    GEDR              General-Purpose Input/Output (GPIO) Edge Detect
+ *                      status Register (read/write).
+ *    GAFR              General-Purpose Input/Output (GPIO) Alternate
+ *                      Function Register (read/write).
+ *
+ * Clock
+ *    fcpu, Tcpu        Frequency, period of the CPU core clock (CCLK).
+ */
+
+#define GPLR            __REG(0x90040000)  /* GPIO Pin Level Reg.             */
+#define GPDR            __REG(0x90040004)  /* GPIO Pin Direction Reg.         */
+#define GPSR            __REG(0x90040008)  /* GPIO Pin output Set Reg.        */
+#define GPCR            __REG(0x9004000C)  /* GPIO Pin output Clear Reg.      */
+#define GRER            __REG(0x90040010)  /* GPIO Rising-Edge detect Reg.    */
+#define GFER            __REG(0x90040014)  /* GPIO Falling-Edge detect Reg.   */
+#define GEDR            __REG(0x90040018)  /* GPIO Edge Detect status Reg.    */
+#define GAFR            __REG(0x9004001C)  /* GPIO Alternate Function Reg.    */
+
+#define GPIO_MIN        (0)
+#define GPIO_MAX        (27)
+
+#define GPIO_GPIO(Nb)                   /* GPIO [0..27]                    */ \
+                        (0x00000001 << (Nb))
+#define GPIO_GPIO0      GPIO_GPIO (0)   /* GPIO  [0]                       */
+#define GPIO_GPIO1      GPIO_GPIO (1)   /* GPIO  [1]                       */
+#define GPIO_GPIO2      GPIO_GPIO (2)   /* GPIO  [2]                       */
+#define GPIO_GPIO3      GPIO_GPIO (3)   /* GPIO  [3]                       */
+#define GPIO_GPIO4      GPIO_GPIO (4)   /* GPIO  [4]                       */
+#define GPIO_GPIO5      GPIO_GPIO (5)   /* GPIO  [5]                       */
+#define GPIO_GPIO6      GPIO_GPIO (6)   /* GPIO  [6]                       */
+#define GPIO_GPIO7      GPIO_GPIO (7)   /* GPIO  [7]                       */
+#define GPIO_GPIO8      GPIO_GPIO (8)   /* GPIO  [8]                       */
+#define GPIO_GPIO9      GPIO_GPIO (9)   /* GPIO  [9]                       */
+#define GPIO_GPIO10     GPIO_GPIO (10)  /* GPIO [10]                       */
+#define GPIO_GPIO11     GPIO_GPIO (11)  /* GPIO [11]                       */
+#define GPIO_GPIO12     GPIO_GPIO (12)  /* GPIO [12]                       */
+#define GPIO_GPIO13     GPIO_GPIO (13)  /* GPIO [13]                       */
+#define GPIO_GPIO14     GPIO_GPIO (14)  /* GPIO [14]                       */
+#define GPIO_GPIO15     GPIO_GPIO (15)  /* GPIO [15]                       */
+#define GPIO_GPIO16     GPIO_GPIO (16)  /* GPIO [16]                       */
+#define GPIO_GPIO17     GPIO_GPIO (17)  /* GPIO [17]                       */
+#define GPIO_GPIO18     GPIO_GPIO (18)  /* GPIO [18]                       */
+#define GPIO_GPIO19     GPIO_GPIO (19)  /* GPIO [19]                       */
+#define GPIO_GPIO20     GPIO_GPIO (20)  /* GPIO [20]                       */
+#define GPIO_GPIO21     GPIO_GPIO (21)  /* GPIO [21]                       */
+#define GPIO_GPIO22     GPIO_GPIO (22)  /* GPIO [22]                       */
+#define GPIO_GPIO23     GPIO_GPIO (23)  /* GPIO [23]                       */
+#define GPIO_GPIO24     GPIO_GPIO (24)  /* GPIO [24]                       */
+#define GPIO_GPIO25     GPIO_GPIO (25)  /* GPIO [25]                       */
+#define GPIO_GPIO26     GPIO_GPIO (26)  /* GPIO [26]                       */
+#define GPIO_GPIO27     GPIO_GPIO (27)  /* GPIO [27]                       */
+
+#define GPIO_LDD(Nb)                    /* LCD Data [8..15] (O)            */ \
+                        GPIO_GPIO ((Nb) - 6)
+#define GPIO_LDD8       GPIO_LDD (8)    /* LCD Data  [8] (O)               */
+#define GPIO_LDD9       GPIO_LDD (9)    /* LCD Data  [9] (O)               */
+#define GPIO_LDD10      GPIO_LDD (10)   /* LCD Data [10] (O)               */
+#define GPIO_LDD11      GPIO_LDD (11)   /* LCD Data [11] (O)               */
+#define GPIO_LDD12      GPIO_LDD (12)   /* LCD Data [12] (O)               */
+#define GPIO_LDD13      GPIO_LDD (13)   /* LCD Data [13] (O)               */
+#define GPIO_LDD14      GPIO_LDD (14)   /* LCD Data [14] (O)               */
+#define GPIO_LDD15      GPIO_LDD (15)   /* LCD Data [15] (O)               */
+                                        /* ser. port 4:                    */
+#define GPIO_SSP_TXD    GPIO_GPIO (10)  /*  SSP Transmit Data (O)          */
+#define GPIO_SSP_RXD    GPIO_GPIO (11)  /*  SSP Receive Data (I)           */
+#define GPIO_SSP_SCLK   GPIO_GPIO (12)  /*  SSP Sample CLocK (O)           */
+#define GPIO_SSP_SFRM   GPIO_GPIO (13)  /*  SSP Sample FRaMe (O)           */
+                                        /* ser. port 1:                    */
+#define GPIO_UART_TXD   GPIO_GPIO (14)  /*  UART Transmit Data (O)         */
+#define GPIO_UART_RXD   GPIO_GPIO (15)  /*  UART Receive Data (I)          */
+#define GPIO_SDLC_SCLK  GPIO_GPIO (16)  /*  SDLC Sample CLocK (I/O)        */
+#define GPIO_SDLC_AAF   GPIO_GPIO (17)  /*  SDLC Abort After Frame (O)     */
+#define GPIO_UART_SCLK1 GPIO_GPIO (18)  /*  UART Sample CLocK 1 (I)        */
+                                        /* ser. port 4:                    */
+#define GPIO_SSP_CLK    GPIO_GPIO (19)  /*  SSP external CLocK (I)         */
+                                        /* ser. port 3:                    */
+#define GPIO_UART_SCLK3 GPIO_GPIO (20)  /*  UART Sample CLocK 3 (I)        */
+                                        /* ser. port 4:                    */
+#define GPIO_MCP_CLK    GPIO_GPIO (21)  /*  MCP CLocK (I)                  */
+                                        /* test controller:                */
+#define GPIO_TIC_ACK    GPIO_GPIO (21)  /*  TIC ACKnowledge (O)            */
+#define GPIO_MBGNT      GPIO_GPIO (21)  /*  Memory Bus GraNT (O)           */
+#define GPIO_TREQA      GPIO_GPIO (22)  /*  TIC REQuest A (I)              */
+#define GPIO_MBREQ      GPIO_GPIO (22)  /*  Memory Bus REQuest (I)         */
+#define GPIO_TREQB      GPIO_GPIO (23)  /*  TIC REQuest B (I)              */
+#define GPIO_1Hz        GPIO_GPIO (25)  /* 1 Hz clock (O)                  */
+#define GPIO_RCLK       GPIO_GPIO (26)  /* internal (R) CLocK (O, fcpu/2)  */
+#define GPIO_32_768kHz  GPIO_GPIO (27)  /* 32.768 kHz clock (O, RTC)       */
+
+#define GPDR_In         0               /* Input                           */
+#define GPDR_Out        1               /* Output                          */
+
+
+/*
+ * Interrupt Controller (IC) control registers
+ *
+ * Registers
+ *    ICIP              Interrupt Controller (IC) Interrupt ReQuest (IRQ)
+ *                      Pending register (read).
+ *    ICMR              Interrupt Controller (IC) Mask Register (read/write).
+ *    ICLR              Interrupt Controller (IC) Level Register (read/write).
+ *    ICCR              Interrupt Controller (IC) Control Register
+ *                      (read/write).
+ *                      [The ICCR register is only implemented in versions 2.0
+ *                      (rev. = 8) and higher of the StrongARM SA-1100.]
+ *    ICFP              Interrupt Controller (IC) Fast Interrupt reQuest
+ *                      (FIQ) Pending register (read).
+ *    ICPR              Interrupt Controller (IC) Pending Register (read).
+ *                      [The ICPR register is active low (inverted) in
+ *                      versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *                      StrongARM SA-1100, it is active high (non-inverted) in
+ *                      versions 2.0 (rev. = 8) and higher.]
+ */
+
+#define ICIP            __REG(0x90050000)  /* IC IRQ Pending reg.             */
+#define ICMR            __REG(0x90050004)  /* IC Mask Reg.                    */
+#define ICLR            __REG(0x90050008)  /* IC Level Reg.                   */
+#define ICCR            __REG(0x9005000C)  /* IC Control Reg.                 */
+#define ICFP            __REG(0x90050010)  /* IC FIQ Pending reg.             */
+#define ICPR            __REG(0x90050020)  /* IC Pending Reg.                 */
+
+#define IC_GPIO(Nb)                     /* GPIO [0..10]                    */ \
+                        (0x00000001 << (Nb))
+#define IC_GPIO0        IC_GPIO (0)     /* GPIO  [0]                       */
+#define IC_GPIO1        IC_GPIO (1)     /* GPIO  [1]                       */
+#define IC_GPIO2        IC_GPIO (2)     /* GPIO  [2]                       */
+#define IC_GPIO3        IC_GPIO (3)     /* GPIO  [3]                       */
+#define IC_GPIO4        IC_GPIO (4)     /* GPIO  [4]                       */
+#define IC_GPIO5        IC_GPIO (5)     /* GPIO  [5]                       */
+#define IC_GPIO6        IC_GPIO (6)     /* GPIO  [6]                       */
+#define IC_GPIO7        IC_GPIO (7)     /* GPIO  [7]                       */
+#define IC_GPIO8        IC_GPIO (8)     /* GPIO  [8]                       */
+#define IC_GPIO9        IC_GPIO (9)     /* GPIO  [9]                       */
+#define IC_GPIO10       IC_GPIO (10)    /* GPIO [10]                       */
+#define IC_GPIO11_27    0x00000800      /* GPIO [11:27] (ORed)             */
+#define IC_LCD          0x00001000      /* LCD controller                  */
+#define IC_Ser0UDC      0x00002000      /* Ser. port 0 UDC                 */
+#define IC_Ser1SDLC     0x00004000      /* Ser. port 1 SDLC                */
+#define IC_Ser1UART     0x00008000      /* Ser. port 1 UART                */
+#define IC_Ser2ICP      0x00010000      /* Ser. port 2 ICP                 */
+#define IC_Ser3UART     0x00020000      /* Ser. port 3 UART                */
+#define IC_Ser4MCP      0x00040000      /* Ser. port 4 MCP                 */
+#define IC_Ser4SSP      0x00080000      /* Ser. port 4 SSP                 */
+#define IC_DMA(Nb)                      /* DMA controller channel [0..5]   */ \
+                        (0x00100000 << (Nb))
+#define IC_DMA0         IC_DMA (0)      /* DMA controller channel 0        */
+#define IC_DMA1         IC_DMA (1)      /* DMA controller channel 1        */
+#define IC_DMA2         IC_DMA (2)      /* DMA controller channel 2        */
+#define IC_DMA3         IC_DMA (3)      /* DMA controller channel 3        */
+#define IC_DMA4         IC_DMA (4)      /* DMA controller channel 4        */
+#define IC_DMA5         IC_DMA (5)      /* DMA controller channel 5        */
+#define IC_OST(Nb)                      /* OS Timer match [0..3]           */ \
+                        (0x04000000 << (Nb))
+#define IC_OST0         IC_OST (0)      /* OS Timer match 0                */
+#define IC_OST1         IC_OST (1)      /* OS Timer match 1                */
+#define IC_OST2         IC_OST (2)      /* OS Timer match 2                */
+#define IC_OST3         IC_OST (3)      /* OS Timer match 3                */
+#define IC_RTC1Hz       0x40000000      /* RTC 1 Hz clock                  */
+#define IC_RTCAlrm      0x80000000      /* RTC Alarm                       */
+
+#define ICLR_IRQ        0               /* Interrupt ReQuest               */
+#define ICLR_FIQ        1               /* Fast Interrupt reQuest          */
+
+#define ICCR_DIM        0x00000001      /* Disable Idle-mode interrupt     */
+                                        /* Mask                            */
+#define ICCR_IdleAllInt (ICCR_DIM*0)    /*  Idle-mode All Interrupt enable */
+                                        /*  (ICMR ignored)                 */
+#define ICCR_IdleMskInt (ICCR_DIM*1)    /*  Idle-mode non-Masked Interrupt */
+                                        /*  enable (ICMR used)             */
+
+
+/*
+ * Peripheral Pin Controller (PPC) control registers
+ *
+ * Registers
+ *    PPDR              Peripheral Pin Controller (PPC) Pin Direction
+ *                      Register (read/write).
+ *    PPSR              Peripheral Pin Controller (PPC) Pin State Register
+ *                      (read/write).
+ *    PPAR              Peripheral Pin Controller (PPC) Pin Assignment
+ *                      Register (read/write).
+ *    PSDR              Peripheral Pin Controller (PPC) Sleep-mode pin
+ *                      Direction Register (read/write).
+ *    PPFR              Peripheral Pin Controller (PPC) Pin Flag Register
+ *                      (read).
+ */
+
+#define PPDR            __REG(0x90060000)  /* PPC Pin Direction Reg.          */
+#define PPSR            __REG(0x90060004)  /* PPC Pin State Reg.              */
+#define PPAR            __REG(0x90060008)  /* PPC Pin Assignment Reg.         */
+#define PSDR            __REG(0x9006000C)  /* PPC Sleep-mode pin Direction Reg. */
+#define PPFR            __REG(0x90060010)  /* PPC Pin Flag Reg.               */
+
+#define PPC_LDD(Nb)                     /* LCD Data [0..7]                 */ \
+                        (0x00000001 << (Nb))
+#define PPC_LDD0        PPC_LDD (0)     /* LCD Data [0]                    */
+#define PPC_LDD1        PPC_LDD (1)     /* LCD Data [1]                    */
+#define PPC_LDD2        PPC_LDD (2)     /* LCD Data [2]                    */
+#define PPC_LDD3        PPC_LDD (3)     /* LCD Data [3]                    */
+#define PPC_LDD4        PPC_LDD (4)     /* LCD Data [4]                    */
+#define PPC_LDD5        PPC_LDD (5)     /* LCD Data [5]                    */
+#define PPC_LDD6        PPC_LDD (6)     /* LCD Data [6]                    */
+#define PPC_LDD7        PPC_LDD (7)     /* LCD Data [7]                    */
+#define PPC_L_PCLK      0x00000100      /* LCD Pixel CLocK                 */
+#define PPC_L_LCLK      0x00000200      /* LCD Line CLocK                  */
+#define PPC_L_FCLK      0x00000400      /* LCD Frame CLocK                 */
+#define PPC_L_BIAS      0x00000800      /* LCD AC BIAS                     */
+                                        /* ser. port 1:                    */
+#define PPC_TXD1        0x00001000      /*  SDLC/UART Transmit Data 1      */
+#define PPC_RXD1        0x00002000      /*  SDLC/UART Receive Data 1       */
+                                        /* ser. port 2:                    */
+#define PPC_TXD2        0x00004000      /*  IPC Transmit Data 2            */
+#define PPC_RXD2        0x00008000      /*  IPC Receive Data 2             */
+                                        /* ser. port 3:                    */
+#define PPC_TXD3        0x00010000      /*  UART Transmit Data 3           */
+#define PPC_RXD3        0x00020000      /*  UART Receive Data 3            */
+                                        /* ser. port 4:                    */
+#define PPC_TXD4        0x00040000      /*  MCP/SSP Transmit Data 4        */
+#define PPC_RXD4        0x00080000      /*  MCP/SSP Receive Data 4         */
+#define PPC_SCLK        0x00100000      /*  MCP/SSP Sample CLocK           */
+#define PPC_SFRM        0x00200000      /*  MCP/SSP Sample FRaMe           */
+
+#define PPDR_In         0               /* Input                           */
+#define PPDR_Out        1               /* Output                          */
+
+                                        /* ser. port 1:                    */
+#define PPAR_UPR        0x00001000      /*  UART Pin Reassignment          */
+#define PPAR_UARTTR     (PPAR_UPR*0)    /*   UART on TXD_1 & RXD_1         */
+#define PPAR_UARTGPIO   (PPAR_UPR*1)    /*   UART on GPIO [14:15]          */
+                                        /* ser. port 4:                    */
+#define PPAR_SPR        0x00040000      /*  SSP Pin Reassignment           */
+#define PPAR_SSPTRSS    (PPAR_SPR*0)    /*   SSP on TXD_C, RXD_C, SCLK_C,  */
+                                        /*   & SFRM_C                      */
+#define PPAR_SSPGPIO    (PPAR_SPR*1)    /*   SSP on GPIO [10:13]           */
+
+#define PSDR_OutL       0               /* Output Low in sleep mode        */
+#define PSDR_Flt        1               /* Floating (input) in sleep mode  */
+
+#define PPFR_LCD        0x00000001      /* LCD controller                  */
+#define PPFR_SP1TX      0x00001000      /* Ser. Port 1 SDLC/UART Transmit  */
+#define PPFR_SP1RX      0x00002000      /* Ser. Port 1 SDLC/UART Receive   */
+#define PPFR_SP2TX      0x00004000      /* Ser. Port 2 ICP Transmit        */
+#define PPFR_SP2RX      0x00008000      /* Ser. Port 2 ICP Receive         */
+#define PPFR_SP3TX      0x00010000      /* Ser. Port 3 UART Transmit       */
+#define PPFR_SP3RX      0x00020000      /* Ser. Port 3 UART Receive        */
+#define PPFR_SP4        0x00040000      /* Ser. Port 4 MCP/SSP             */
+#define PPFR_PerEn      0               /* Peripheral Enabled              */
+#define PPFR_PPCEn      1               /* PPC Enabled                     */
+
+
+/*
+ * Dynamic Random-Access Memory (DRAM) control registers
+ *
+ * Registers
+ *    MDCNFG            Memory system: Dynamic Random-Access Memory (DRAM)
+ *                      CoNFiGuration register (read/write).
+ *    MDCAS0            Memory system: Dynamic Random-Access Memory (DRAM)
+ *                      Column Address Strobe (CAS) shift register 0
+ *                      (read/write).
+ *    MDCAS1            Memory system: Dynamic Random-Access Memory (DRAM)
+ *                      Column Address Strobe (CAS) shift register 1
+ *                      (read/write).
+ *    MDCAS2            Memory system: Dynamic Random-Access Memory (DRAM)
+ *                      Column Address Strobe (CAS) shift register 2
+ *                      (read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu        Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem        Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fcas, Tcas        Frequency, period of the DRAM CAS shift registers.
+ */
+
+#define MDCNFG          __REG(0xA0000000)  /*  DRAM CoNFiGuration reg. */
+#define MDCAS0          __REG(0xA0000004)  /* DRAM CAS shift reg. 0 */
+#define MDCAS1          __REG(0xA0000008)  /* DRAM CAS shift reg. 1 */
+#define MDCAS2          __REG(0xA000000c)  /* DRAM CAS shift reg. 2 */
+
+/* SA1100 MDCNFG values */
+#define MDCNFG_DE(Nb)                   /* DRAM Enable bank [0..3]         */ \
+                        (0x00000001 << (Nb))
+#define MDCNFG_DE0      MDCNFG_DE (0)   /* DRAM Enable bank 0              */
+#define MDCNFG_DE1      MDCNFG_DE (1)   /* DRAM Enable bank 1              */
+#define MDCNFG_DE2      MDCNFG_DE (2)   /* DRAM Enable bank 2              */
+#define MDCNFG_DE3      MDCNFG_DE (3)   /* DRAM Enable bank 3              */
+#define MDCNFG_DRAC     Fld (2, 4)      /* DRAM Row Address Count - 9      */
+#define MDCNFG_RowAdd(Add)              /*  Row Address count [9..12]      */ \
+                        (((Add) - 9) << FShft (MDCNFG_DRAC))
+#define MDCNFG_CDB2     0x00000040      /* shift reg. Clock Divide By 2    */
+                                        /* (fcas = fcpu/2)                 */
+#define MDCNFG_TRP      Fld (4, 7)      /* Time RAS Pre-charge - 1 [Tmem]  */
+#define MDCNFG_PrChrg(Tcpu)             /*  Pre-Charge time [2..32 Tcpu]   */ \
+                        (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
+#define MDCNFG_CeilPrChrg(Tcpu)         /*  Ceil. of PrChrg [2..32 Tcpu]   */ \
+                        (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
+#define MDCNFG_TRASR    Fld (4, 11)     /* Time RAS Refresh - 1 [Tmem]     */
+#define MDCNFG_Ref(Tcpu)                /*  Refresh time [2..32 Tcpu]      */ \
+                        (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
+#define MDCNFG_CeilRef(Tcpu)            /*  Ceil. of Ref [2..32 Tcpu]      */ \
+                        (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
+#define MDCNFG_TDL      Fld (2, 15)     /* Time Data Latch [Tcpu]          */
+#define MDCNFG_DataLtch(Tcpu)           /*  Data Latch delay [0..3 Tcpu]   */ \
+                        ((Tcpu) << FShft (MDCNFG_TDL))
+#define MDCNFG_DRI      Fld (15, 17)    /* min. DRAM Refresh Interval/4    */
+                                        /* [Tmem]                          */
+#define MDCNFG_RefInt(Tcpu)             /*  min. Refresh Interval          */ \
+                                        /*  [0..262136 Tcpu]               */ \
+                        ((Tcpu)/8 << FShft (MDCNFG_DRI))
+
+/* SA1110 MDCNFG values */
+#define MDCNFG_SA1110_DE0       0x00000001      /* DRAM Enable bank 0        */
+#define MDCNFG_SA1110_DE1       0x00000002      /* DRAM Enable bank 1        */
+#define MDCNFG_SA1110_DTIM0     0x00000004      /* DRAM timing type 0/1      */
+#define MDCNFG_SA1110_DWID0     0x00000008      /* DRAM bus width 0/1        */
+#define MDCNFG_SA1110_DRAC0     Fld(3, 4)       /* DRAM row addr bit count   */
+                                                /* bank 0/1                  */
+#define MDCNFG_SA1110_CDB20     0x00000080      /* Mem Clock divide by 2 0/1 */
+#define MDCNFG_SA1110_TRP0      Fld(3, 8)       /* RAS precharge 0/1         */
+#define MDCNFG_SA1110_TDL0      Fld(2, 12)      /* Data input latch after CAS*/
+                                                /* deassertion 0/1           */
+#define MDCNFG_SA1110_TWR0      Fld(2, 14)      /* SDRAM write recovery 0/1  */
+#define MDCNFG_SA1110_DE2       0x00010000      /* DRAM Enable bank 0        */
+#define MDCNFG_SA1110_DE3       0x00020000      /* DRAM Enable bank 1        */
+#define MDCNFG_SA1110_DTIM2     0x00040000      /* DRAM timing type 0/1      */
+#define MDCNFG_SA1110_DWID2     0x00080000      /* DRAM bus width 0/1        */
+#define MDCNFG_SA1110_DRAC2     Fld(3, 20)      /* DRAM row addr bit count   */
+                                                /* bank 0/1                  */
+#define MDCNFG_SA1110_CDB22     0x00800000      /* Mem Clock divide by 2 0/1 */
+#define MDCNFG_SA1110_TRP2      Fld(3, 24)      /* RAS precharge 0/1         */
+#define MDCNFG_SA1110_TDL2      Fld(2, 28)      /* Data input latch after CAS*/
+                                                /* deassertion 0/1           */
+#define MDCNFG_SA1110_TWR2      Fld(2, 30)      /* SDRAM write recovery 0/1  */
+
+
+/*
+ * Static memory control registers
+ *
+ * Registers
+ *    MSC0              Memory system: Static memory Control register 0
+ *                      (read/write).
+ *    MSC1              Memory system: Static memory Control register 1
+ *                      (read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu        Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem        Frequency, period of the memory clock (fmem = fcpu/2).
+ */
+
+#define MSC0            __REG(0xa0000010)  /* Static memory Control reg. 0 */
+#define MSC1            __REG(0xa0000014)  /* Static memory Control reg. 1 */
+#define MSC2            __REG(0xa000002c)  /* Static memory Control reg. 2, not contiguous   */
+
+#define MSC_Bnk(Nb)                     /* static memory Bank [0..3]       */ \
+                        Fld (16, ((Nb) Modulo 2)*16)
+#define MSC0_Bnk0       MSC_Bnk (0)     /* static memory Bank 0            */
+#define MSC0_Bnk1       MSC_Bnk (1)     /* static memory Bank 1            */
+#define MSC1_Bnk2       MSC_Bnk (2)     /* static memory Bank 2            */
+#define MSC1_Bnk3       MSC_Bnk (3)     /* static memory Bank 3            */
+
+#define MSC_RT          Fld (2, 0)      /* ROM/static memory Type          */
+#define MSC_NonBrst                     /*  Non-Burst static memory        */ \
+                        (0 << FShft (MSC_RT))
+#define MSC_SRAM                        /*  32-bit byte-writable SRAM      */ \
+                        (1 << FShft (MSC_RT))
+#define MSC_Brst4                       /*  Burst-of-4 static memory       */ \
+                        (2 << FShft (MSC_RT))
+#define MSC_Brst8                       /*  Burst-of-8 static memory       */ \
+                        (3 << FShft (MSC_RT))
+#define MSC_RBW         0x0004          /* ROM/static memory Bus Width     */
+#define MSC_32BitStMem  (MSC_RBW*0)     /*  32-Bit Static Memory           */
+#define MSC_16BitStMem  (MSC_RBW*1)     /*  16-Bit Static Memory           */
+#define MSC_RDF         Fld (5, 3)      /* ROM/static memory read Delay    */
+                                        /* First access - 1(.5) [Tmem]     */
+#define MSC_1stRdAcc(Tcpu)              /*  1st Read Access time (burst    */ \
+                                        /*  static memory) [3..65 Tcpu]    */ \
+                        ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
+#define MSC_Ceil1stRdAcc(Tcpu)          /*  Ceil. of 1stRdAcc [3..65 Tcpu] */ \
+                        ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
+#define MSC_RdAcc(Tcpu)                 /*  Read Access time (non-burst    */ \
+                                        /*  static memory) [2..64 Tcpu]    */ \
+                        ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
+#define MSC_CeilRdAcc(Tcpu)             /*  Ceil. of RdAcc [2..64 Tcpu]    */ \
+                        ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
+#define MSC_RDN         Fld (5, 8)      /* ROM/static memory read Delay    */
+                                        /* Next access - 1 [Tmem]          */
+#define MSC_NxtRdAcc(Tcpu)              /*  Next Read Access time (burst   */ \
+                                        /*  static memory) [2..64 Tcpu]    */ \
+                        ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
+#define MSC_CeilNxtRdAcc(Tcpu)          /*  Ceil. of NxtRdAcc [2..64 Tcpu] */ \
+                        ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
+#define MSC_WrAcc(Tcpu)                 /*  Write Access time (non-burst   */ \
+                                        /*  static memory) [2..64 Tcpu]    */ \
+                        ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
+#define MSC_CeilWrAcc(Tcpu)             /*  Ceil. of WrAcc [2..64 Tcpu]    */ \
+                        ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
+#define MSC_RRR         Fld (3, 13)     /* ROM/static memory RecoveRy      */
+                                        /* time/2 [Tmem]                   */
+#define MSC_Rec(Tcpu)                   /*  Recovery time [0..28 Tcpu]     */ \
+                        (((Tcpu)/4) << FShft (MSC_RRR))
+#define MSC_CeilRec(Tcpu)               /*  Ceil. of Rec [0..28 Tcpu]      */ \
+                        ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
+
+
+/*
+ * Personal Computer Memory Card International Association (PCMCIA) control
+ * register
+ *
+ * Register
+ *    MECR              Memory system: Expansion memory bus (PCMCIA)
+ *                      Configuration Register (read/write).
+ *
+ * Clocks
+ *    fcpu, Tcpu        Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem        Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fbclk, Tbclk      Frequency, period of the PCMCIA clock (BCLK).
+ */
+
+                                        /* Memory system:                  */
+#define MECR            __REG(0xA0000018)  /*  Expansion memory bus (PCMCIA) Configuration Reg.             */
+
+#define MECR_PCMCIA(Nb)                 /* PCMCIA [0..1]                   */ \
+                        Fld (15, (Nb)*16)
+#define MECR_PCMCIA0    MECR_PCMCIA (0) /* PCMCIA 0                        */
+#define MECR_PCMCIA1    MECR_PCMCIA (1) /* PCMCIA 1                        */
+
+#define MECR_BSIO       Fld (5, 0)      /* BCLK Select I/O - 1 [Tmem]      */
+#define MECR_IOClk(Tcpu)                /*  I/O Clock [2..64 Tcpu]         */ \
+                        ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
+#define MECR_CeilIOClk(Tcpu)            /*  Ceil. of IOClk [2..64 Tcpu]    */ \
+                        ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
+#define MECR_BSA        Fld (5, 5)      /* BCLK Select Attribute - 1       */
+                                        /* [Tmem]                          */
+#define MECR_AttrClk(Tcpu)              /*  Attribute Clock [2..64 Tcpu]   */ \
+                        ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
+#define MECR_CeilAttrClk(Tcpu)          /*  Ceil. of AttrClk [2..64 Tcpu]  */ \
+                        ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
+#define MECR_BSM        Fld (5, 10)     /* BCLK Select Memory - 1 [Tmem]   */
+#define MECR_MemClk(Tcpu)               /*  Memory Clock [2..64 Tcpu]      */ \
+                        ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
+#define MECR_CeilMemClk(Tcpu)           /*  Ceil. of MemClk [2..64 Tcpu]   */ \
+                        ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
+
+/*
+ * On SA1110 only
+ */
+
+#define MDREFR          __REG(0xA000001C)
+
+#define MDREFR_TRASR            Fld (4, 0)
+#define MDREFR_DRI              Fld (12, 4)
+#define MDREFR_E0PIN            (1 << 16)
+#define MDREFR_K0RUN            (1 << 17)
+#define MDREFR_K0DB2            (1 << 18)
+#define MDREFR_E1PIN            (1 << 20)
+#define MDREFR_K1RUN            (1 << 21)
+#define MDREFR_K1DB2            (1 << 22)
+#define MDREFR_K2RUN            (1 << 25)
+#define MDREFR_K2DB2            (1 << 26)
+#define MDREFR_EAPD             (1 << 28)
+#define MDREFR_KAPD             (1 << 29)
+#define MDREFR_SLFRSH           (1 << 31)
+
+
+/*
+ * Direct Memory Access (DMA) control registers
+ *
+ * Registers
+ *    DDAR0             Direct Memory Access (DMA) Device Address Register
+ *                      channel 0 (read/write).
+ *    DCSR0             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 0 (read/write).
+ *    DBSA0             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 0 (read/write).
+ *    DBTA0             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 0 (read/write).
+ *    DBSB0             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 0 (read/write).
+ *    DBTB0             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 0 (read/write).
+ *
+ *    DDAR1             Direct Memory Access (DMA) Device Address Register
+ *                      channel 1 (read/write).
+ *    DCSR1             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 1 (read/write).
+ *    DBSA1             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 1 (read/write).
+ *    DBTA1             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 1 (read/write).
+ *    DBSB1             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 1 (read/write).
+ *    DBTB1             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 1 (read/write).
+ *
+ *    DDAR2             Direct Memory Access (DMA) Device Address Register
+ *                      channel 2 (read/write).
+ *    DCSR2             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 2 (read/write).
+ *    DBSA2             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 2 (read/write).
+ *    DBTA2             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 2 (read/write).
+ *    DBSB2             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 2 (read/write).
+ *    DBTB2             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 2 (read/write).
+ *
+ *    DDAR3             Direct Memory Access (DMA) Device Address Register
+ *                      channel 3 (read/write).
+ *    DCSR3             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 3 (read/write).
+ *    DBSA3             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 3 (read/write).
+ *    DBTA3             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 3 (read/write).
+ *    DBSB3             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 3 (read/write).
+ *    DBTB3             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 3 (read/write).
+ *
+ *    DDAR4             Direct Memory Access (DMA) Device Address Register
+ *                      channel 4 (read/write).
+ *    DCSR4             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 4 (read/write).
+ *    DBSA4             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 4 (read/write).
+ *    DBTA4             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 4 (read/write).
+ *    DBSB4             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 4 (read/write).
+ *    DBTB4             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 4 (read/write).
+ *
+ *    DDAR5             Direct Memory Access (DMA) Device Address Register
+ *                      channel 5 (read/write).
+ *    DCSR5             Direct Memory Access (DMA) Control and Status
+ *                      Register channel 5 (read/write).
+ *    DBSA5             Direct Memory Access (DMA) Buffer Start address
+ *                      register A channel 5 (read/write).
+ *    DBTA5             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register A channel 5 (read/write).
+ *    DBSB5             Direct Memory Access (DMA) Buffer Start address
+ *                      register B channel 5 (read/write).
+ *    DBTB5             Direct Memory Access (DMA) Buffer Transfer count
+ *                      register B channel 5 (read/write).
+ */
+
+#define DMASp           0x00000020      /* DMA control reg. Space [byte]   */
+
+#define DDAR(Nb)        __REG(0xB0000000 + (Nb)*DMASp)  /* DMA Device Address Reg. channel [0..5] */
+#define SetDCSR(Nb)     __REG(0xB0000004 + (Nb)*DMASp)  /* Set DMA Control & Status Reg. channel [0..5] (write) */
+#define ClrDCSR(Nb)     __REG(0xB0000008 + (Nb)*DMASp)  /* Clear DMA Control & Status Reg. channel [0..5] (write) */
+#define RdDCSR(Nb)      __REG(0xB000000C + (Nb)*DMASp)  /* Read DMA Control & Status Reg. channel [0..5] (read) */
+#define DBSA(Nb)        __REG(0xB0000010 + (Nb)*DMASp)  /* DMA Buffer Start address reg. A channel [0..5] */
+#define DBTA(Nb)        __REG(0xB0000014 + (Nb)*DMASp)  /* DMA Buffer Transfer count reg. A channel [0..5] */
+#define DBSB(Nb)        __REG(0xB0000018 + (Nb)*DMASp)  /* DMA Buffer Start address reg. B channel [0..5] */
+#define DBTB(Nb)        __REG(0xB000001C + (Nb)*DMASp)  /* DMA Buffer Transfer count reg. B channel [0..5] */
+
+#define DDAR_RW         0x00000001      /* device data Read/Write          */
+#define DDAR_DevWr      (DDAR_RW*0)     /*  Device data Write              */
+                                        /*  (memory -> device)             */
+#define DDAR_DevRd      (DDAR_RW*1)     /*  Device data Read               */
+                                        /*  (device -> memory)             */
+#define DDAR_E          0x00000002      /* big/little Endian device        */
+#define DDAR_LtlEnd     (DDAR_E*0)      /*  Little Endian device           */
+#define DDAR_BigEnd     (DDAR_E*1)      /*  Big Endian device              */
+#define DDAR_BS         0x00000004      /* device Burst Size               */
+#define DDAR_Brst4      (DDAR_BS*0)     /*  Burst-of-4 device              */
+#define DDAR_Brst8      (DDAR_BS*1)     /*  Burst-of-8 device              */
+#define DDAR_DW         0x00000008      /* device Data Width               */
+#define DDAR_8BitDev    (DDAR_DW*0)     /*  8-Bit Device                   */
+#define DDAR_16BitDev   (DDAR_DW*1)     /*  16-Bit Device                  */
+#define DDAR_DS         Fld (4, 4)      /* Device Select                   */
+#define DDAR_Ser0UDCTr                  /*  Ser. port 0 UDC Transmit       */ \
+                        (0x0 << FShft (DDAR_DS))
+#define DDAR_Ser0UDCRc                  /*  Ser. port 0 UDC Receive        */ \
+                        (0x1 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCTr                 /*  Ser. port 1 SDLC Transmit      */ \
+                        (0x2 << FShft (DDAR_DS))
+#define DDAR_Ser1SDLCRc                 /*  Ser. port 1 SDLC Receive       */ \
+                        (0x3 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTTr                 /*  Ser. port 1 UART Transmit      */ \
+                        (0x4 << FShft (DDAR_DS))
+#define DDAR_Ser1UARTRc                 /*  Ser. port 1 UART Receive       */ \
+                        (0x5 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPTr                  /*  Ser. port 2 ICP Transmit       */ \
+                        (0x6 << FShft (DDAR_DS))
+#define DDAR_Ser2ICPRc                  /*  Ser. port 2 ICP Receive        */ \
+                        (0x7 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTTr                 /*  Ser. port 3 UART Transmit      */ \
+                        (0x8 << FShft (DDAR_DS))
+#define DDAR_Ser3UARTRc                 /*  Ser. port 3 UART Receive       */ \
+                        (0x9 << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Tr                 /*  Ser. port 4 MCP 0 Transmit     */ \
+                                        /*  (audio)                        */ \
+                        (0xA << FShft (DDAR_DS))
+#define DDAR_Ser4MCP0Rc                 /*  Ser. port 4 MCP 0 Receive      */ \
+                                        /*  (audio)                        */ \
+                        (0xB << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Tr                 /*  Ser. port 4 MCP 1 Transmit     */ \
+                                        /*  (telecom)                      */ \
+                        (0xC << FShft (DDAR_DS))
+#define DDAR_Ser4MCP1Rc                 /*  Ser. port 4 MCP 1 Receive      */ \
+                                        /*  (telecom)                      */ \
+                        (0xD << FShft (DDAR_DS))
+#define DDAR_Ser4SSPTr                  /*  Ser. port 4 SSP Transmit       */ \
+                        (0xE << FShft (DDAR_DS))
+#define DDAR_Ser4SSPRc                  /*  Ser. port 4 SSP Receive        */ \
+                        (0xF << FShft (DDAR_DS))
+#define DDAR_DA         Fld (24, 8)     /* Device Address                  */
+#define DDAR_DevAdd(Add)                /*  Device Address                 */ \
+                        (((Add) & 0xF0000000) | \
+                         (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
+#define DDAR_Ser0UDCWr                  /* Ser. port 0 UDC Write           */ \
+                        (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+                         DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
+#define DDAR_Ser0UDCRd                  /* Ser. port 0 UDC Read            */ \
+                        (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+                         DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
+#define DDAR_Ser1UARTWr                 /* Ser. port 1 UART Write          */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
+#define DDAR_Ser1UARTRd                 /* Ser. port 1 UART Read           */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
+#define DDAR_Ser1SDLCWr                 /* Ser. port 1 SDLC Write          */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
+#define DDAR_Ser1SDLCRd                 /* Ser. port 1 SDLC Read           */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
+#define DDAR_Ser2UARTWr                 /* Ser. port 2 UART Write          */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
+#define DDAR_Ser2UARTRd                 /* Ser. port 2 UART Read           */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
+#define DDAR_Ser2HSSPWr                 /* Ser. port 2 HSSP Write          */ \
+                        (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
+                         DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
+#define DDAR_Ser2HSSPRd                 /* Ser. port 2 HSSP Read           */ \
+                        (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
+                         DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
+#define DDAR_Ser3UARTWr                 /* Ser. port 3 UART Write          */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
+#define DDAR_Ser3UARTRd                 /* Ser. port 3 UART Read           */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
+                         DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
+#define DDAR_Ser4MCP0Wr                 /* Ser. port 4 MCP 0 Write (audio) */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
+#define DDAR_Ser4MCP0Rd                 /* Ser. port 4 MCP 0 Read (audio)  */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
+#define DDAR_Ser4MCP1Wr                 /* Ser. port 4 MCP 1 Write         */ \
+                                        /* (telecom)                       */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
+#define DDAR_Ser4MCP1Rd                 /* Ser. port 4 MCP 1 Read          */ \
+                                        /* (telecom)                       */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
+#define DDAR_Ser4SSPWr                  /* Ser. port 4 SSP Write (16 bits) */ \
+                        (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
+#define DDAR_Ser4SSPRd                  /* Ser. port 4 SSP Read (16 bits)  */ \
+                        (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
+                         DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
+
+#define DCSR_RUN        0x00000001      /* DMA RUNing                      */
+#define DCSR_IE         0x00000002      /* DMA Interrupt Enable            */
+#define DCSR_ERROR      0x00000004      /* DMA ERROR                       */
+#define DCSR_DONEA      0x00000008      /* DONE DMA transfer buffer A      */
+#define DCSR_STRTA      0x00000010      /* STaRTed DMA transfer buffer A   */
+#define DCSR_DONEB      0x00000020      /* DONE DMA transfer buffer B      */
+#define DCSR_STRTB      0x00000040      /* STaRTed DMA transfer buffer B   */
+#define DCSR_BIU        0x00000080      /* DMA Buffer In Use               */
+#define DCSR_BufA       (DCSR_BIU*0)    /*  DMA Buffer A in use            */
+#define DCSR_BufB       (DCSR_BIU*1)    /*  DMA Buffer B in use            */
+
+#define DBT_TC          Fld (13, 0)     /* Transfer Count                  */
+#define DBTA_TCA        DBT_TC          /* Transfer Count buffer A         */
+#define DBTB_TCB        DBT_TC          /* Transfer Count buffer B         */
+
+
+/*
+ * Liquid Crystal Display (LCD) control registers
+ *
+ * Registers
+ *    LCCR0             Liquid Crystal Display (LCD) Control Register 0
+ *                      (read/write).
+ *                      [Bits LDM, BAM, and ERM are only implemented in
+ *                      versions 2.0 (rev. = 8) and higher of the StrongARM
+ *                      SA-1100.]
+ *    LCSR              Liquid Crystal Display (LCD) Status Register
+ *                      (read/write).
+ *                      [Bit LDD can be only read in versions 1.0 (rev. = 1)
+ *                      and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
+ *                      read and written (cleared) in versions 2.0 (rev. = 8)
+ *                      and higher.]
+ *    DBAR1             Liquid Crystal Display (LCD) Direct Memory Access
+ *                      (DMA) Base Address Register channel 1 (read/write).
+ *    DCAR1             Liquid Crystal Display (LCD) Direct Memory Access
+ *                      (DMA) Current Address Register channel 1 (read).
+ *    DBAR2             Liquid Crystal Display (LCD) Direct Memory Access
+ *                      (DMA) Base Address Register channel 2 (read/write).
+ *    DCAR2             Liquid Crystal Display (LCD) Direct Memory Access
+ *                      (DMA) Current Address Register channel 2 (read).
+ *    LCCR1             Liquid Crystal Display (LCD) Control Register 1
+ *                      (read/write).
+ *                      [The LCCR1 register can be only written in
+ *                      versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *                      StrongARM SA-1100, it can be written and read in
+ *                      versions 2.0 (rev. = 8) and higher.]
+ *    LCCR2             Liquid Crystal Display (LCD) Control Register 2
+ *                      (read/write).
+ *                      [The LCCR1 register can be only written in
+ *                      versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *                      StrongARM SA-1100, it can be written and read in
+ *                      versions 2.0 (rev. = 8) and higher.]
+ *    LCCR3             Liquid Crystal Display (LCD) Control Register 3
+ *                      (read/write).
+ *                      [The LCCR1 register can be only written in
+ *                      versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
+ *                      StrongARM SA-1100, it can be written and read in
+ *                      versions 2.0 (rev. = 8) and higher. Bit PCP is only
+ *                      implemented in versions 2.0 (rev. = 8) and higher of
+ *                      the StrongARM SA-1100.]
+ *
+ * Clocks
+ *    fcpu, Tcpu        Frequency, period of the CPU core clock (CCLK).
+ *    fmem, Tmem        Frequency, period of the memory clock (fmem = fcpu/2).
+ *    fpix, Tpix        Frequency, period of the pixel clock.
+ *    fln, Tln          Frequency, period of the line clock.
+ *    fac, Tac          Frequency, period of the AC bias clock.
+ */
+
+#define LCD_PEntrySp    2               /* LCD Palette Entry Space [byte]  */
+#define LCD_4BitPSp                     /* LCD 4-Bit pixel Palette Space   */ \
+                                        /* [byte]                          */ \
+                        (16*LCD_PEntrySp)
+#define LCD_8BitPSp                     /* LCD 8-Bit pixel Palette Space   */ \
+                                        /* [byte]                          */ \
+                        (256*LCD_PEntrySp)
+#define LCD_12_16BitPSp                 /* LCD 12/16-Bit pixel             */ \
+                                        /* dummy-Palette Space [byte]      */ \
+                        (16*LCD_PEntrySp)
+
+#define LCD_PGrey       Fld (4, 0)      /* LCD Palette entry Grey value    */
+#define LCD_PBlue       Fld (4, 0)      /* LCD Palette entry Blue value    */
+#define LCD_PGreen      Fld (4, 4)      /* LCD Palette entry Green value   */
+#define LCD_PRed        Fld (4, 8)      /* LCD Palette entry Red value     */
+#define LCD_PBS         Fld (2, 12)     /* LCD Pixel Bit Size              */
+#define LCD_4Bit                        /*  LCD 4-Bit pixel mode           */ \
+                        (0 << FShft (LCD_PBS))
+#define LCD_8Bit                        /*  LCD 8-Bit pixel mode           */ \
+                        (1 << FShft (LCD_PBS))
+#define LCD_12_16Bit                    /*  LCD 12/16-Bit pixel mode       */ \
+                        (2 << FShft (LCD_PBS))
+
+#define LCD_Int0_0      0x0             /* LCD Intensity =   0.0% =  0     */
+#define LCD_Int11_1     0x1             /* LCD Intensity =  11.1% =  1/9   */
+#define LCD_Int20_0     0x2             /* LCD Intensity =  20.0% =  1/5   */
+#define LCD_Int26_7     0x3             /* LCD Intensity =  26.7% =  4/15  */
+#define LCD_Int33_3     0x4             /* LCD Intensity =  33.3% =  3/9   */
+#define LCD_Int40_0     0x5             /* LCD Intensity =  40.0% =  2/5   */
+#define LCD_Int44_4     0x6             /* LCD Intensity =  44.4% =  4/9   */
+#define LCD_Int50_0     0x7             /* LCD Intensity =  50.0% =  1/2   */
+#define LCD_Int55_6     0x8             /* LCD Intensity =  55.6% =  5/9   */
+#define LCD_Int60_0     0x9             /* LCD Intensity =  60.0% =  3/5   */
+#define LCD_Int66_7     0xA             /* LCD Intensity =  66.7% =  6/9   */
+#define LCD_Int73_3     0xB             /* LCD Intensity =  73.3% = 11/15  */
+#define LCD_Int80_0     0xC             /* LCD Intensity =  80.0% =  4/5   */
+#define LCD_Int88_9     0xD             /* LCD Intensity =  88.9% =  8/9   */
+#define LCD_Int100_0    0xE             /* LCD Intensity = 100.0% =  1     */
+#define LCD_Int100_0A   0xF             /* LCD Intensity = 100.0% =  1     */
+                                        /* (Alternative)                   */
+
+#define LCCR0           __REG(0xB0100000)  /* LCD Control Reg. 0 */
+#define LCSR            __REG(0xB0100004)  /* LCD Status Reg. */
+#define DBAR1           __REG(0xB0100010)  /* LCD DMA Base Address Reg. channel 1 */
+#define DCAR1           __REG(0xB0100014)  /* LCD DMA Current Address Reg. channel 1 */
+#define DBAR2           __REG(0xB0100018)  /* LCD DMA Base Address Reg.  channel 2 */
+#define DCAR2           __REG(0xB010001C)  /* LCD DMA Current Address Reg. channel 2 */
+#define LCCR1           __REG(0xB0100020)  /* LCD Control Reg. 1 */
+#define LCCR2           __REG(0xB0100024)  /* LCD Control Reg. 2 */
+#define LCCR3           __REG(0xB0100028)  /* LCD Control Reg. 3 */
+
+#define LCCR0_LEN       0x00000001      /* LCD ENable                      */
+#define LCCR0_CMS       0x00000002      /* Color/Monochrome display Select */
+#define LCCR0_Color     (LCCR0_CMS*0)   /*  Color display                  */
+#define LCCR0_Mono      (LCCR0_CMS*1)   /*  Monochrome display             */
+#define LCCR0_SDS       0x00000004      /* Single/Dual panel display       */
+                                        /* Select                          */
+#define LCCR0_Sngl      (LCCR0_SDS*0)   /*  Single panel display           */
+#define LCCR0_Dual      (LCCR0_SDS*1)   /*  Dual panel display             */
+#define LCCR0_LDM       0x00000008      /* LCD Disable done (LDD)          */
+                                        /* interrupt Mask (disable)        */
+#define LCCR0_BAM       0x00000010      /* Base Address update (BAU)       */
+                                        /* interrupt Mask (disable)        */
+#define LCCR0_ERM       0x00000020      /* LCD ERror (BER, IOL, IUL, IOU,  */
+                                        /* IUU, OOL, OUL, OOU, and OUU)    */
+                                        /* interrupt Mask (disable)        */
+#define LCCR0_PAS       0x00000080      /* Passive/Active display Select   */
+#define LCCR0_Pas       (LCCR0_PAS*0)   /*  Passive display (STN)          */
+#define LCCR0_Act       (LCCR0_PAS*1)   /*  Active display (TFT)           */
+#define LCCR0_BLE       0x00000100      /* Big/Little Endian select        */
+#define LCCR0_LtlEnd    (LCCR0_BLE*0)   /*  Little Endian frame buffer     */
+#define LCCR0_BigEnd    (LCCR0_BLE*1)   /*  Big Endian frame buffer        */
+#define LCCR0_DPD       0x00000200      /* Double Pixel Data (monochrome   */
+                                        /* display mode)                   */
+#define LCCR0_4PixMono  (LCCR0_DPD*0)   /*  4-Pixel/clock Monochrome       */
+                                        /*  display                        */
+#define LCCR0_8PixMono  (LCCR0_DPD*1)   /*  8-Pixel/clock Monochrome       */
+                                        /*  display                        */
+#define LCCR0_PDD       Fld (8, 12)     /* Palette DMA request Delay       */
+                                        /* [Tmem]                          */
+#define LCCR0_DMADel(Tcpu)              /*  palette DMA request Delay      */ \
+                                        /*  [0..510 Tcpu]                  */ \
+                        ((Tcpu)/2 << FShft (LCCR0_PDD))
+
+#define LCSR_LDD        0x00000001      /* LCD Disable Done                */
+#define LCSR_BAU        0x00000002      /* Base Address Update (read)      */
+#define LCSR_BER        0x00000004      /* Bus ERror                       */
+#define LCSR_ABC        0x00000008      /* AC Bias clock Count             */
+#define LCSR_IOL        0x00000010      /* Input FIFO Over-run Lower       */
+                                        /* panel                           */
+#define LCSR_IUL        0x00000020      /* Input FIFO Under-run Lower      */
+                                        /* panel                           */
+#define LCSR_IOU        0x00000040      /* Input FIFO Over-run Upper       */
+                                        /* panel                           */
+#define LCSR_IUU        0x00000080      /* Input FIFO Under-run Upper      */
+                                        /* panel                           */
+#define LCSR_OOL        0x00000100      /* Output FIFO Over-run Lower      */
+                                        /* panel                           */
+#define LCSR_OUL        0x00000200      /* Output FIFO Under-run Lower     */
+                                        /* panel                           */
+#define LCSR_OOU        0x00000400      /* Output FIFO Over-run Upper      */
+                                        /* panel                           */
+#define LCSR_OUU        0x00000800      /* Output FIFO Under-run Upper     */
+                                        /* panel                           */
+
+#define LCCR1_PPL       Fld (6, 4)      /* Pixels Per Line/16 - 1          */
+#define LCCR1_DisWdth(Pixel)            /*  Display Width [16..1024 pix.]  */ \
+                        (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
+#define LCCR1_HSW       Fld (6, 10)     /* Horizontal Synchronization      */
+                                        /* pulse Width - 1 [Tpix] (L_LCLK) */
+#define LCCR1_HorSnchWdth(Tpix)         /*  Horizontal Synchronization     */ \
+                                        /*  pulse Width [1..64 Tpix]       */ \
+                        (((Tpix) - 1) << FShft (LCCR1_HSW))
+#define LCCR1_ELW       Fld (8, 16)     /* End-of-Line pixel clock Wait    */
+                                        /* count - 1 [Tpix]                */
+#define LCCR1_EndLnDel(Tpix)            /*  End-of-Line Delay              */ \
+                                        /*  [1..256 Tpix]                  */ \
+                        (((Tpix) - 1) << FShft (LCCR1_ELW))
+#define LCCR1_BLW       Fld (8, 24)     /* Beginning-of-Line pixel clock   */
+                                        /* Wait count - 1 [Tpix]           */
+#define LCCR1_BegLnDel(Tpix)            /*  Beginning-of-Line Delay        */ \
+                                        /*  [1..256 Tpix]                  */ \
+                        (((Tpix) - 1) << FShft (LCCR1_BLW))
+
+#define LCCR2_LPP       Fld (10, 0)     /* Line Per Panel - 1              */
+#define LCCR2_DisHght(Line)             /*  Display Height [1..1024 lines] */ \
+                        (((Line) - 1) << FShft (LCCR2_LPP))
+#define LCCR2_VSW       Fld (6, 10)     /* Vertical Synchronization pulse  */
+                                        /* Width - 1 [Tln] (L_FCLK)        */
+#define LCCR2_VrtSnchWdth(Tln)          /*  Vertical Synchronization pulse */ \
+                                        /*  Width [1..64 Tln]              */ \
+                        (((Tln) - 1) << FShft (LCCR2_VSW))
+#define LCCR2_EFW       Fld (8, 16)     /* End-of-Frame line clock Wait    */
+                                        /* count [Tln]                     */
+#define LCCR2_EndFrmDel(Tln)            /*  End-of-Frame Delay             */ \
+                                        /*  [0..255 Tln]                   */ \
+                        ((Tln) << FShft (LCCR2_EFW))
+#define LCCR2_BFW       Fld (8, 24)     /* Beginning-of-Frame line clock   */
+                                        /* Wait count [Tln]                */
+#define LCCR2_BegFrmDel(Tln)            /*  Beginning-of-Frame Delay       */ \
+                                        /*  [0..255 Tln]                   */ \
+                        ((Tln) << FShft (LCCR2_BFW))
+
+#define LCCR3_PCD       Fld (8, 0)      /* Pixel Clock Divisor/2 - 2       */
+                                        /* [1..255] (L_PCLK)               */
+                                        /* fpix = fcpu/(2*(PCD + 2))       */
+                                        /* Tpix = 2*(PCD + 2)*Tcpu         */
+#define LCCR3_PixClkDiv(Div)            /*  Pixel Clock Divisor [6..514]   */ \
+                        (((Div) - 4)/2 << FShft (LCCR3_PCD))
+                                        /*  fpix = fcpu/(2*Floor (Div/2))  */
+                                        /*  Tpix = 2*Floor (Div/2)*Tcpu    */
+#define LCCR3_CeilPixClkDiv(Div)        /*  Ceil. of PixClkDiv [6..514]    */ \
+                        (((Div) - 3)/2 << FShft (LCCR3_PCD))
+                                        /*  fpix = fcpu/(2*Ceil (Div/2))   */
+                                        /*  Tpix = 2*Ceil (Div/2)*Tcpu     */
+#define LCCR3_ACB       Fld (8, 8)      /* AC Bias clock half period - 1   */
+                                        /* [Tln] (L_BIAS)                  */
+#define LCCR3_ACBsDiv(Div)              /*  AC Bias clock Divisor [2..512] */ \
+                        (((Div) - 2)/2 << FShft (LCCR3_ACB))
+                                        /*  fac = fln/(2*Floor (Div/2))    */
+                                        /*  Tac = 2*Floor (Div/2)*Tln      */
+#define LCCR3_CeilACBsDiv(Div)          /*  Ceil. of ACBsDiv [2..512]      */ \
+                        (((Div) - 1)/2 << FShft (LCCR3_ACB))
+                                        /*  fac = fln/(2*Ceil (Div/2))     */
+                                        /*  Tac = 2*Ceil (Div/2)*Tln       */
+#define LCCR3_API       Fld (4, 16)     /* AC bias Pin transitions per     */
+                                        /* Interrupt                       */
+#define LCCR3_ACBsCntOff                /*  AC Bias clock transition Count */ \
+                                        /*  Off                            */ \
+                        (0 << FShft (LCCR3_API))
+#define LCCR3_ACBsCnt(Trans)            /*  AC Bias clock transition Count */ \
+                                        /*  [1..15]                        */ \
+                        ((Trans) << FShft (LCCR3_API))
+#define LCCR3_VSP       0x00100000      /* Vertical Synchronization pulse  */
+                                        /* Polarity (L_FCLK)               */
+#define LCCR3_VrtSnchH  (LCCR3_VSP*0)   /*  Vertical Synchronization pulse */
+                                        /*  active High                    */
+#define LCCR3_VrtSnchL  (LCCR3_VSP*1)   /*  Vertical Synchronization pulse */
+                                        /*  active Low                     */
+#define LCCR3_HSP       0x00200000      /* Horizontal Synchronization      */
+                                        /* pulse Polarity (L_LCLK)         */
+#define LCCR3_HorSnchH  (LCCR3_HSP*0)   /*  Horizontal Synchronization     */
+                                        /*  pulse active High              */
+#define LCCR3_HorSnchL  (LCCR3_HSP*1)   /*  Horizontal Synchronization     */
+                                        /*  pulse active Low               */
+#define LCCR3_PCP       0x00400000      /* Pixel Clock Polarity (L_PCLK)   */
+#define LCCR3_PixRsEdg  (LCCR3_PCP*0)   /*  Pixel clock Rising-Edge        */
+#define LCCR3_PixFlEdg  (LCCR3_PCP*1)   /*  Pixel clock Falling-Edge       */
+#define LCCR3_OEP       0x00800000      /* Output Enable Polarity (L_BIAS, */
+                                        /* active display mode)            */
+#define LCCR3_OutEnH    (LCCR3_OEP*0)   /*  Output Enable active High      */
+#define LCCR3_OutEnL    (LCCR3_OEP*1)   /*  Output Enable active Low       */
+
+#ifndef __ASSEMBLY__
+extern unsigned int processor_id;
+#endif
+
+#define CPU_REVISION    (processor_id & 15)
+#define CPU_SA1110_A0   (0)
+#define CPU_SA1110_B0   (4)
+#define CPU_SA1110_B1   (5)
+#define CPU_SA1110_B2   (6)
+#define CPU_SA1110_B4   (8)
+
+#define CPU_SA1100_ID   (0x4401a110)
+#define CPU_SA1100_MASK (0xfffffff0)
+#define CPU_SA1110_ID   (0x6901b110)
+#define CPU_SA1110_MASK (0xfffffff0)
diff --git a/include/asm-arm/arch-sa1100/SA-1101.h b/include/asm-arm/arch-sa1100/SA-1101.h
new file mode 100644
index 000000000000..527d887f1ee3
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/SA-1101.h
@@ -0,0 +1,925 @@
+/*
+ * SA-1101.h
+ *
+ * Copyright (c) Peter Danielsson 1999
+ *
+ * Definition of constants related to the sa1101
+ * support chip for the sa1100
+ *
+ */
+
+
+/* Be sure that virtual mapping is defined right */
+#ifndef __ASM_ARCH_HARDWARE_H
+#error You must include hardware.h not SA-1101.h
+#endif
+
+#ifndef SA1101_BASE
+#error You must define SA-1101 physical base address
+#endif
+
+#ifndef LANGUAGE
+# ifdef __ASSEMBLY__
+#  define LANGUAGE Assembly
+# else
+#  define LANGUAGE C
+# endif
+#endif
+
+/*
+ * We have mapped the sa1101 depending on the value of SA1101_BASE.
+ * It then appears from 0xf4000000.
+ */
+
+#define SA1101_p2v( x )         ((x) - SA1101_BASE + 0xf4000000)
+#define SA1101_v2p( x )         ((x) - 0xf4000000  + SA1101_BASE)
+
+#ifndef SA1101_p2v
+#define SA1101_p2v(PhAdd)  (PhAdd)
+#endif
+
+#include <asm/arch/bitfield.h>
+
+#define C               0
+#define Assembly        1
+
+
+/*
+ * Memory map
+ */
+
+#define __SHMEM_CONTROL0        0x00000000
+#define __SYSTEM_CONTROL1       0x00000400
+#define __ARBITER               0x00020000
+#define __SYSTEM_CONTROL2       0x00040000
+#define __SYSTEM_CONTROL3       0x00060000
+#define __PARALLEL_PORT         0x00080000
+#define __VIDMEM_CONTROL        0x00100000
+#define __UPDATE_FIFO           0x00120000
+#define __SHMEM_CONTROL1        0x00140000
+#define __INTERRUPT_CONTROL     0x00160000
+#define __USB_CONTROL           0x00180000
+#define __TRACK_INTERFACE       0x001a0000
+#define __MOUSE_INTERFACE       0x001b0000
+#define __KEYPAD_INTERFACE      0x001c0000
+#define __PCMCIA_INTERFACE      0x001e0000
+#define __VGA_CONTROL           0x00200000
+#define __GPIO_INTERFACE        0x00300000
+
+/*
+ * Macro that calculates real address for registers in the SA-1101
+ */
+
+#define _SA1101( x )    ((x) + SA1101_BASE)
+
+/*
+ * Interface and shared memory controller registers
+ *
+ * Registers
+ *      SKCR            SA-1101 control register (read/write)
+ *      SMCR            Shared Memory Controller Register
+ *      SNPR            Snoop Register
+ */
+
+#define _SKCR           _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
+#define _SMCR           _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
+#define _SNPR           _SA1101( 0x00140400 ) /* Snoop Reg. */
+
+#if LANGUAGE == C
+#define SKCR            (*((volatile Word *) SA1101_p2v (_SKCR)))
+#define SMCR            (*((volatile Word *) SA1101_p2v (_SMCR)))
+#define SNPR            (*((volatile Word *) SA1101_p2v (_SNPR)))
+
+#define SKCR_PLLEn        0x0001          /* Enable On-Chip PLL */
+#define SKCR_BCLKEn       0x0002          /* Enables BCLK */
+#define SKCR_Sleep        0x0004          /* Sleep Mode */
+#define SKCR_IRefEn       0x0008          /* DAC Iref input enable */
+#define SKCR_VCOON        0x0010          /* VCO bias */
+#define SKCR_ScanTestEn   0x0020          /* Enables scan test */
+#define SKCR_ClockTestEn  0x0040          /* Enables clock test */
+
+#define SMCR_DCAC         Fld(2,0)        /* Number of column address bits */
+#define SMCR_DRAC         Fld(2,2)        /* Number of row address bits */
+#define SMCR_ArbiterBias  0x0008          /* favor video or USB */
+#define SMCR_TopVidMem    Fld(4,5)        /* Top 4 bits of vidmem addr. */
+
+#define SMCR_ColAdrBits( x )              /* col. addr bits 8..11 */ \
+        (( (x) - 8 ) << FShft (SMCR_DCAC))
+#define SMCR_RowAdrBits( x )              /* row addr bits 9..12 */\
+        (( (x) - 9 ) << FShft (SMCR_DRAC)
+
+#define SNPR_VFBstart     Fld(12,0)     /* Video frame buffer addr */
+#define SNPR_VFBsize      Fld(11,12)    /* Video frame buffer size */
+#define SNPR_WholeBank    (1 << 23)     /* Whole bank bit */
+#define SNPR_BankSelect   Fld(2,27)     /* Bank select */
+#define SNPR_SnoopEn      (1 << 31)     /* Enable snoop operation */
+
+#define SNPR_Set_VFBsize( x )   /* set frame buffer size (in kb) */ \
+        ( (x) << FShft (SNPR_VFBsize))
+#define SNPR_Select_Bank(x)     /* select bank 0 or 1 */  \
+        (( (x) + 1 ) << FShft (SNPR_BankSelect ))
+
+#endif /* LANGUAGE == C */
+
+/*
+ * Video Memory Controller
+ *
+ * Registers
+ *    VMCCR     Configuration register
+ *    VMCAR     VMC address register
+ *    VMCDR     VMC data register
+ *
+ */
+
+#define _VMCCR          _SA1101( 0x00100000 )   /* Configuration register */
+#define _VMCAR          _SA1101( 0x00101000 )   /* VMC address register */
+#define _VMCDR          _SA1101( 0x00101400 )   /* VMC data register */
+
+#if LANGUAGE == C
+#define VMCCR           (*((volatile Word *) SA1101_p2v (_VMCCR)))
+#define VMCAR           (*((volatile Word *) SA1101_p2v (_VMCAR)))
+#define VMCDR           (*((volatile Word *) SA1101_p2v (_VMCDR)))
+
+#define VMCCR_RefreshEn     0x0000        /* Enable memory refresh */
+#define VMCCR_Config        0x0001        /* DRAM size */
+#define VMCCR_RefPeriod     Fld(2,3)      /* Refresh period */
+#define VMCCR_StaleDataWait Fld(4,5)      /* Stale FIFO data timeout counter */
+#define VMCCR_SleepState    (1<<9)        /* State of interface pins in sleep*/
+#define VMCCR_RefTest       (1<<10)       /* refresh test */
+#define VMCCR_RefLow        Fld(6,11)     /* refresh low counter */
+#define VMCCR_RefHigh       Fld(7,17)     /* refresh high counter */
+#define VMCCR_SDTCTest      Fld(7,24)     /* stale data timeout counter */
+#define VMCCR_ForceSelfRef  (1<<31)       /* Force self refresh */
+
+#endif LANGUAGE == C
+
+
+/* Update FIFO
+ *
+ * Registers
+ *    UFCR      Update FIFO Control Register
+ *    UFSR      Update FIFO Status Register
+ *    UFLVLR    update FIFO level register
+ *    UFDR      update FIFO data register
+ */
+
+#define _UFCR   _SA1101(0x00120000)   /* Update FIFO Control Reg. */
+#define _UFSR   _SA1101(0x00120400)   /* Update FIFO Status Reg. */     
+#define _UFLVLR _SA1101(0x00120800)   /* Update FIFO level reg. */
+#define _UFDR   _SA1101(0x00120c00)   /* Update FIFO data reg. */
+
+#if LANGUAGE == C
+
+#define UFCR    (*((volatile Word *) SA1101_p2v (_UFCR)))
+#define UFSR    (*((volatile Word *) SA1101_p2v (_UFSR)))
+#define UFLVLR  (*((volatile Word *) SA1101_p2v (_UFLVLR))) 
+#define UFDR    (*((volatile Word *) SA1101_p2v (_UFDR)))
+
+
+#define UFCR_FifoThreshhold     Fld(7,0)        /* Level for FifoGTn flag */
+
+#define UFSR_FifoGTnFlag        0x01            /* FifoGTn flag */#define UFSR_FifoEmpty                0x80            /* FIFO is empty */
+
+#endif /* LANGUAGE == C */
+
+/* System Controller
+ *
+ * Registers
+ *    SKPCR     Power Control Register
+ *    SKCDR     Clock Divider Register
+ *    DACDR1    DAC1 Data register
+ *    DACDR2    DAC2 Data register
+ */
+
+#define _SKPCR          _SA1101(0x00000400)
+#define _SKCDR          _SA1101(0x00040000)
+#define _DACDR1         _SA1101(0x00060000)
+#define _DACDR2         _SA1101(0x00060400)
+
+#if LANGUAGE == C
+#define SKPCR   (*((volatile Word *) SA1101_p2v (_SKPCR)))
+#define SKCDR   (*((volatile Word *) SA1101_p2v (_SKCDR)))
+#define DACDR1  (*((volatile Word *) SA1101_p2v (_DACDR1)))
+#define DACDR2  (*((volatile Word *) SA1101_p2v (_DACDR2)))
+
+#define SKPCR_UCLKEn         0x01    /* USB Enable */
+#define SKPCR_PCLKEn         0x02    /* PS/2 Enable */
+#define SKPCR_ICLKEn         0x04    /* Interrupt Controller Enable */
+#define SKPCR_VCLKEn         0x08    /* Video Controller Enable */
+#define SKPCR_PICLKEn        0x10    /* parallel port Enable */
+#define SKPCR_DCLKEn         0x20    /* DACs Enable */
+#define SKPCR_nKPADEn        0x40    /* Multiplexer */
+
+#define SKCDR_PLLMul         Fld(7,0)   /* PLL Multiplier */
+#define SKCDR_VCLKEn         Fld(2,7)   /* Video controller clock divider */
+#define SKDCR_BCLKEn         (1<<9)     /* BCLK Divider */
+#define SKDCR_UTESTCLKEn     (1<<10)    /* Route USB clock during test mode */
+#define SKDCR_DivRValue      Fld(6,11)  /* Input clock divider for PLL */
+#define SKDCR_DivNValue      Fld(5,17)  /* Output clock divider for PLL */
+#define SKDCR_PLLRSH         Fld(3,22)  /* PLL bandwidth control */
+#define SKDCR_ChargePump     (1<<25)    /* Charge pump control */
+#define SKDCR_ClkTestMode    (1<<26)    /* Clock output test mode */
+#define SKDCR_ClkTestEn      (1<<27)    /* Test clock generator */
+#define SKDCR_ClkJitterCntl  Fld(3,28)  /* video clock jitter compensation */
+
+#define DACDR_DACCount       Fld(8,0)   /* Count value */
+#define DACDR1_DACCount      DACDR_DACCount
+#define DACDR2_DACCount      DACDR_DACCount
+
+#endif /* LANGUAGE == C */
+
+/*
+ * Parallel Port Interface
+ *
+ * Registers
+ *    IEEE_Config       IEEE mode selection and programmable attributes
+ *    IEEE_Control      Controls the states of IEEE port control outputs
+ *    IEEE_Data         Forward transfer data register
+ *    IEEE_Addr         Forward transfer address register
+ *    IEEE_Status       Port IO signal status register
+ *    IEEE_IntStatus    Port interrupts status register
+ *    IEEE_FifoLevels   Rx and Tx FIFO interrupt generation levels
+ *    IEEE_InitTime     Forward timeout counter initial value
+ *    IEEE_TimerStatus  Forward timeout counter current value
+ *    IEEE_FifoReset    Reset forward transfer FIFO
+ *    IEEE_ReloadValue  Counter reload value
+ *    IEEE_TestControl  Control testmode
+ *    IEEE_TestDataIn   Test data register
+ *    IEEE_TestDataInEn Enable test data
+ *    IEEE_TestCtrlIn   Test control signals
+ *    IEEE_TestCtrlInEn Enable test control signals
+ *    IEEE_TestDataStat Current data bus value
+ *
+ */
+
+/*
+ * The control registers are defined as offsets from a base address 
+ */
+ 
+#define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT )
+
+#define _IEEE_Config        _IEEE( 0x0000 )
+#define _IEEE_Control       _IEEE( 0x0400 )
+#define _IEEE_Data          _IEEE( 0x4000 )
+#define _IEEE_Addr          _IEEE( 0x0800 )
+#define _IEEE_Status        _IEEE( 0x0c00 )
+#define _IEEE_IntStatus     _IEEE( 0x1000 )
+#define _IEEE_FifoLevels    _IEEE( 0x1400 )
+#define _IEEE_InitTime      _IEEE( 0x1800 )
+#define _IEEE_TimerStatus   _IEEE( 0x1c00 )
+#define _IEEE_FifoReset     _IEEE( 0x2000 )
+#define _IEEE_ReloadValue   _IEEE( 0x3c00 )
+#define _IEEE_TestControl   _IEEE( 0x2400 )
+#define _IEEE_TestDataIn    _IEEE( 0x2800 )
+#define _IEEE_TestDataInEn  _IEEE( 0x2c00 )
+#define _IEEE_TestCtrlIn    _IEEE( 0x3000 )
+#define _IEEE_TestCtrlInEn  _IEEE( 0x3400 )
+#define _IEEE_TestDataStat  _IEEE( 0x3800 )
+ 
+
+#if LANGUAGE == C
+#define IEEE_Config         (*((volatile Word *) SA1101_p2v (_IEEE_Config)))
+#define IEEE_Control        (*((volatile Word *) SA1101_p2v (_IEEE_Control)))
+#define IEEE_Data           (*((volatile Word *) SA1101_p2v (_IEEE_Data)))
+#define IEEE_Addr           (*((volatile Word *) SA1101_p2v (_IEEE_Addr)))
+#define IEEE_Status         (*((volatile Word *) SA1101_p2v (_IEEE_Status)))
+#define IEEE_IntStatus      (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus)))
+#define IEEE_FifoLevels     (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels)))
+#define IEEE_InitTime       (*((volatile Word *) SA1101_p2v (_IEEE_InitTime)))
+#define IEEE_TimerStatus    (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus)))
+#define IEEE_FifoReset      (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset)))
+#define IEEE_ReloadValue    (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue)))
+#define IEEE_TestControl    (*((volatile Word *) SA1101_p2v (_IEEE_TestControl)))
+#define IEEE_TestDataIn     (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn)))
+#define IEEE_TestDataInEn   (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn)))
+#define IEEE_TestCtrlIn     (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn)))
+#define IEEE_TestCtrlInEn   (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn)))
+#define IEEE_TestDataStat   (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat)))
+
+
+#define IEEE_Config_M       Fld(3,0)     /* Mode select */
+#define IEEE_Config_D       0x04         /* FIFO access enable */
+#define IEEE_Config_B       0x08         /* 9-bit word enable */
+#define IEEE_Config_T       0x10         /* Data transfer enable */
+#define IEEE_Config_A       0x20         /* Data transfer direction */
+#define IEEE_Config_E       0x40         /* Timer enable */
+#define IEEE_Control_A      0x08         /* AutoFd output */
+#define IEEE_Control_E      0x04         /* Selectin output */
+#define IEEE_Control_T      0x02         /* Strobe output */
+#define IEEE_Control_I      0x01         /* Port init output */
+#define IEEE_Data_C         (1<<31)      /* Byte count */
+#define IEEE_Data_Db        Fld(9,16)    /* Data byte 2 */
+#define IEEE_Data_Da        Fld(9,0)     /* Data byte 1 */
+#define IEEE_Addr_A         Fld(8,0)     /* forward address transfer byte */
+#define IEEE_Status_A       0x0100       /* nAutoFd port output status */
+#define IEEE_Status_E       0x0080       /* nSelectIn port output status */
+#define IEEE_Status_T       0x0040       /* nStrobe port output status */
+#define IEEE_Status_I       0x0020       /* nInit port output status */
+#define IEEE_Status_B       0x0010       /* Busy port inout status */
+#define IEEE_Status_S       0x0008       /* Select port input status */
+#define IEEE_Status_K       0x0004       /* nAck port input status */
+#define IEEE_Status_F       0x0002       /* nFault port input status */
+#define IEEE_Status_R       0x0001       /* pError port input status */
+
+#define IEEE_IntStatus_IntReqDat         0x0100
+#define IEEE_IntStatus_IntReqEmp         0x0080
+#define IEEE_IntStatus_IntReqInt         0x0040
+#define IEEE_IntStatus_IntReqRav         0x0020
+#define IEEE_IntStatus_IntReqTim         0x0010
+#define IEEE_IntStatus_RevAddrComp       0x0008
+#define IEEE_IntStatus_RevDataComp       0x0004
+#define IEEE_IntStatus_FwdAddrComp       0x0002
+#define IEEE_IntStatus_FwdDataComp       0x0001
+#define IEEE_FifoLevels_RevFifoLevel     2
+#define IEEE_FifoLevels_FwdFifoLevel     1
+#define IEEE_InitTime_TimValInit         Fld(22,0)
+#define IEEE_TimerStatus_TimValStat      Fld(22,0)
+#define IEEE_ReloadValue_Reload          Fld(4,0)
+
+#define IEEE_TestControl_RegClk          0x04
+#define IEEE_TestControl_ClockSelect     Fld(2,1)
+#define IEEE_TestControl_TimerTestModeEn 0x01
+#define IEEE_TestCtrlIn_PError           0x10
+#define IEEE_TestCtrlIn_nFault           0x08
+#define IEEE_TestCtrlIn_nAck             0x04
+#define IEEE_TestCtrlIn_PSel             0x02
+#define IEEE_TestCtrlIn_Busy             0x01
+
+#endif /* LANGUAGE == C */
+
+/*
+ * VGA Controller
+ *
+ * Registers
+ *    VideoControl      Video Control Register
+ *    VgaTiming0        VGA Timing Register 0
+ *    VgaTiming1        VGA Timing Register 1
+ *    VgaTiming2        VGA Timing Register 2
+ *    VgaTiming3        VGA Timing Register 3
+ *    VgaBorder         VGA Border Color Register
+ *    VgaDBAR           VGADMA Base Address Register
+ *    VgaDCAR           VGADMA Channel Current Address Register
+ *    VgaStatus         VGA Status Register
+ *    VgaInterruptMask  VGA Interrupt Mask Register
+ *    VgaPalette        VGA Palette Registers
+ *    DacControl        DAC Control Register
+ *    VgaTest           VGA Controller Test Register
+ */
+
+#define _VGA( x )       _SA1101( ( x ) + __VGA_CONTROL )
+
+#define _VideoControl       _VGA( 0x0000 )
+#define _VgaTiming0         _VGA( 0x0400 )
+#define _VgaTiming1         _VGA( 0x0800 )
+#define _VgaTiming2         _VGA( 0x0c00 )
+#define _VgaTiming3         _VGA( 0x1000 )
+#define _VgaBorder          _VGA( 0x1400 )
+#define _VgaDBAR            _VGA( 0x1800 )
+#define _VgaDCAR            _VGA( 0x1c00 )
+#define _VgaStatus          _VGA( 0x2000 )
+#define _VgaInterruptMask   _VGA( 0x2400 )
+#define _VgaPalette         _VGA( 0x40000 )
+#define _DacControl         _VGA( 0x3000 )
+#define _VgaTest            _VGA( 0x2c00 )
+
+#if (LANGUAGE == C)
+#define VideoControl   (*((volatile Word *) SA1101_p2v (_VideoControl)))
+#define VgaTiming0     (*((volatile Word *) SA1101_p2v (_VgaTiming0)))
+#define VgaTiming1     (*((volatile Word *) SA1101_p2v (_VgaTiming1)))
+#define VgaTiming2     (*((volatile Word *) SA1101_p2v (_VgaTiming2)))
+#define VgaTiming3     (*((volatile Word *) SA1101_p2v (_VgaTiming3)))
+#define VgaBorder      (*((volatile Word *) SA1101_p2v (_VgaBorder)))
+#define VgaDBAR        (*((volatile Word *) SA1101_p2v (_VgaDBAR)))
+#define VgaDCAR        (*((volatile Word *) SA1101_p2v (_VgaDCAR)))
+#define VgaStatus      (*((volatile Word *) SA1101_p2v (_VgaStatus)))
+#define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))
+#define VgaPalette     (*((volatile Word *) SA1101_p2v (_VgaPalette)))
+#define DacControl     (*((volatile Word *) SA1101_p2v (_DacControl))
+#define VgaTest        (*((volatile Word *) SA1101_p2v (_VgaTest)))
+
+#define VideoControl_VgaEn    0x00000000
+#define VideoControl_BGR      0x00000001
+#define VideoControl_VCompVal Fld(2,2)
+#define VideoControl_VgaReq   Fld(4,4)
+#define VideoControl_VBurstL  Fld(4,8)
+#define VideoControl_VMode    (1<<12)
+#define VideoControl_PalRead  (1<<13)
+
+#define VgaTiming0_PPL        Fld(6,2)
+#define VgaTiming0_HSW        Fld(8,8)
+#define VgaTiming0_HFP        Fld(8,16)
+#define VgaTiming0_HBP        Fld(8,24)
+
+#define VgaTiming1_LPS        Fld(10,0)
+#define VgaTiming1_VSW        Fld(6,10)
+#define VgaTiming1_VFP        Fld(8,16)
+#define VgaTiming1_VBP        Fld(8,24)
+
+#define VgaTiming2_IVS        0x01
+#define VgaTiming2_IHS        0x02
+#define VgaTiming2_CVS        0x04
+#define VgaTiming2_CHS        0x08
+
+#define VgaTiming3_HBS        Fld(8,0)
+#define VgaTiming3_HBE        Fld(8,8)
+#define VgaTiming3_VBS        Fld(8,16)
+#define VgaTiming3_VBE        Fld(8,24)
+
+#define VgaBorder_BCOL        Fld(24,0)
+
+#define VgaStatus_VFUF        0x01
+#define VgaStatus_VNext       0x02
+#define VgaStatus_VComp       0x04
+
+#define VgaInterruptMask_VFUFMask   0x00
+#define VgaInterruptMask_VNextMask  0x01
+#define VgaInterruptMask_VCompMask  0x02
+
+#define VgaPalette_R          Fld(8,0)
+#define VgaPalette_G          Fld(8,8)
+#define VgaPalette_B          Fld(8,16)
+
+#define DacControl_DACON      0x0001
+#define DacControl_COMPON     0x0002
+#define DacControl_PEDON      0x0004
+#define DacControl_RTrim      Fld(5,4)
+#define DacControl_GTrim      Fld(5,9)
+#define DacControl_BTrim      Fld(5,14)
+
+#define VgaTest_TDAC          0x00
+#define VgaTest_Datatest      Fld(4,1)
+#define VgaTest_DACTESTDAC    0x10
+#define VgaTest_DACTESTOUT    Fld(3,5)
+
+#endif /* LANGUAGE == C */
+
+/*
+ * USB Host Interface Controller
+ *
+ * Registers
+ *    Revision
+ *    Control
+ *    CommandStatus
+ *    InterruptStatus
+ *    InterruptEnable
+ *    HCCA
+ *    PeriodCurrentED
+ *    ControlHeadED
+ *    BulkHeadED
+ *    BulkCurrentED
+ *    DoneHead
+ *    FmInterval
+ *    FmRemaining
+ *    FmNumber
+ *    PeriodicStart
+ *    LSThreshold
+ *    RhDescriptorA
+ *    RhDescriptorB
+ *    RhStatus
+ *    RhPortStatus
+ *    USBStatus
+ *    USBReset
+ *    USTAR
+ *    USWER
+ *    USRFR
+ *    USNFR
+ *    USTCSR
+ *    USSR
+ *    
+ */
+
+#define _USB( x )       _SA1101( ( x ) + __USB_CONTROL )
+
+
+#define _Revision         _USB( 0x0000 )
+#define _Control          _USB( 0x0888 )
+#define _CommandStatus    _USB( 0x0c00 )
+#define _InterruptStatus  _USB( 0x1000 )
+#define _InterruptEnable  _USB( 0x1400 )
+#define _HCCA             _USB( 0x1800 )
+#define _PeriodCurrentED  _USB( 0x1c00 )
+#define _ControlHeadED    _USB( 0x2000 )
+#define _BulkHeadED       _USB( 0x2800 )
+#define _BulkCurrentED    _USB( 0x2c00 )
+#define _DoneHead         _USB( 0x3000 )
+#define _FmInterval       _USB( 0x3400 )
+#define _FmRemaining      _USB( 0x3800 )
+#define _FmNumber         _USB( 0x3c00 )
+#define _PeriodicStart    _USB( 0x4000 )
+#define _LSThreshold      _USB( 0x4400 )
+#define _RhDescriptorA    _USB( 0x4800 )
+#define _RhDescriptorB    _USB( 0x4c00 )
+#define _RhStatus         _USB( 0x5000 )
+#define _RhPortStatus     _USB( 0x5400 )
+#define _USBStatus        _USB( 0x11800 )
+#define _USBReset         _USB( 0x11c00 )
+
+#define _USTAR            _USB( 0x10400 )
+#define _USWER            _USB( 0x10800 )
+#define _USRFR            _USB( 0x10c00 )
+#define _USNFR            _USB( 0x11000 )
+#define _USTCSR           _USB( 0x11400 )
+#define _USSR             _USB( 0x11800 )
+
+
+#if (LANGUAGE == C)
+
+#define Revision        (*((volatile Word *) SA1101_p2v (_Revision)))
+#define Control         (*((volatile Word *) SA1101_p2v (_Control)))
+#define CommandStatus   (*((volatile Word *) SA1101_p2v (_CommandStatus)))
+#define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus)))
+#define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable)))
+#define HCCA            (*((volatile Word *) SA1101_p2v (_HCCA)))
+#define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED)))
+#define ControlHeadED   (*((volatile Word *) SA1101_p2v (_ControlHeadED)))
+#define BulkHeadED      (*((volatile Word *) SA1101_p2v (_BulkHeadED)))
+#define BulkCurrentED   (*((volatile Word *) SA1101_p2v (_BulkCurrentED)))
+#define DoneHead        (*((volatile Word *) SA1101_p2v (_DoneHead)))
+#define FmInterval      (*((volatile Word *) SA1101_p2v (_FmInterval)))
+#define FmRemaining     (*((volatile Word *) SA1101_p2v (_FmRemaining)))
+#define FmNumber        (*((volatile Word *) SA1101_p2v (_FmNumber)))
+#define PeriodicStart   (*((volatile Word *) SA1101_p2v (_PeriodicStart)))
+#define LSThreshold     (*((volatile Word *) SA1101_p2v (_LSThreshold)))
+#define RhDescriptorA   (*((volatile Word *) SA1101_p2v (_RhDescriptorA)))
+#define RhDescriptorB   (*((volatile Word *) SA1101_p2v (_RhDescriptorB)))
+#define RhStatus        (*((volatile Word *) SA1101_p2v (_RhStatus)))
+#define RhPortStatus    (*((volatile Word *) SA1101_p2v (_RhPortStatus)))
+#define USBStatus       (*((volatile Word *) SA1101_p2v (_USBStatus)))
+#define USBReset        (*((volatile Word *) SA1101_p2v (_USBReset)))
+#define USTAR           (*((volatile Word *) SA1101_p2v (_USTAR)))
+#define USWER           (*((volatile Word *) SA1101_p2v (_USWER)))
+#define USRFR           (*((volatile Word *) SA1101_p2v (_USRFR)))
+#define USNFR           (*((volatile Word *) SA1101_p2v (_USNFR)))
+#define USTCSR          (*((volatile Word *) SA1101_p2v (_USTCSR)))
+#define USSR            (*((volatile Word *) SA1101_p2v (_USSR)))
+
+
+#define USBStatus_IrqHciRmtWkp       (1<<7)
+#define USBStatus_IrqHciBuffAcc      (1<<8)
+#define USBStatus_nIrqHciM           (1<<9)
+#define USBStatus_nHciMFClr          (1<<10)
+
+#define USBReset_ForceIfReset        0x01
+#define USBReset_ForceHcReset        0x02
+#define USBReset_ClkGenReset         0x04
+
+#define USTCR_RdBstCntrl             Fld(3,0)
+#define USTCR_ByteEnable             Fld(4,3)
+#define USTCR_WriteEn                (1<<7)
+#define USTCR_FifoCir                (1<<8)
+#define USTCR_TestXferSel            (1<<9)
+#define USTCR_FifoCirAtEnd           (1<<10)
+#define USTCR_nSimScaleDownClk       (1<<11)
+
+#define USSR_nAppMDEmpty             0x01
+#define USSR_nAppMDFirst             0x02
+#define USSR_nAppMDLast              0x04
+#define USSR_nAppMDFull              0x08
+#define USSR_nAppMAFull              0x10
+#define USSR_XferReq                 0x20
+#define USSR_XferEnd                 0x40
+
+#endif /* LANGUAGE == C */
+
+
+/*
+ * Interrupt Controller
+ *
+ * Registers
+ *    INTTEST0          Test register 0
+ *    INTTEST1          Test register 1
+ *    INTENABLE0        Interrupt Enable register 0
+ *    INTENABLE1        Interrupt Enable register 1
+ *    INTPOL0           Interrupt Polarity selection 0
+ *    INTPOL1           Interrupt Polarity selection 1
+ *    INTTSTSEL         Interrupt source selection
+ *    INTSTATCLR0       Interrupt Status 0
+ *    INTSTATCLR1       Interrupt Status 1
+ *    INTSET0           Interrupt Set 0
+ *    INTSET1           Interrupt Set 1
+ */
+
+#define _INT( x )       _SA1101( ( x ) + __INTERRUPT_CONTROL)
+
+#define _INTTEST0       _INT( 0x1000 )
+#define _INTTEST1       _INT( 0x1400 )
+#define _INTENABLE0     _INT( 0x2000 )
+#define _INTENABLE1     _INT( 0x2400 )
+#define _INTPOL0        _INT( 0x3000 )
+#define _INTPOL1        _INT( 0x3400 )
+#define _INTTSTSEL      _INT( 0x5000 )
+#define _INTSTATCLR0    _INT( 0x6000 )
+#define _INTSTATCLR1    _INT( 0x6400 )
+#define _INTSET0        _INT( 0x7000 )
+#define _INTSET1        _INT( 0x7400 )
+
+#if ( LANGUAGE == C )
+#define INTTEST0        (*((volatile Word *) SA1101_p2v (_INTTEST0)))
+#define INTTEST1        (*((volatile Word *) SA1101_p2v (_INTTEST1)))
+#define INTENABLE0      (*((volatile Word *) SA1101_p2v (_INTENABLE0)))
+#define INTENABLE1      (*((volatile Word *) SA1101_p2v (_INTENABLE1)))
+#define INTPOL0         (*((volatile Word *) SA1101_p2v (_INTPOL0)))
+#define INTPOL1         (*((volatile Word *) SA1101_p2v (_INTPOL1)))
+#define INTTSTSEL       (*((volatile Word *) SA1101_p2v (_INTTSTSEL)))
+#define INTSTATCLR0     (*((volatile Word *) SA1101_p2v (_INTSTATCLR0)))
+#define INTSTATCLR1     (*((volatile Word *) SA1101_p2v (_INTSTATCLR1)))
+#define INTSET0         (*((volatile Word *) SA1101_p2v (_INTSET0)))
+#define INTSET1         (*((volatile Word *) SA1101_p2v (_INTSET1)))
+
+#endif /* LANGUAGE == C */
+
+/*
+ * PS/2 Trackpad and Mouse Interfaces
+ *
+ * Registers   (prefix kbd applies to trackpad interface, mse to mouse)
+ *    KBDCR             Control Register
+ *    KBDSTAT           Status Register
+ *    KBDDATA           Transmit/Receive Data register
+ *    KBDCLKDIV         Clock Division Register
+ *    KBDPRECNT         Clock Precount Register
+ *    KBDTEST1          Test register 1
+ *    KBDTEST2          Test register 2
+ *    KBDTEST3          Test register 3
+ *    KBDTEST4          Test register 4
+ *    MSECR     
+ *    MSESTAT
+ *    MSEDATA
+ *    MSECLKDIV
+ *    MSEPRECNT
+ *    MSETEST1
+ *    MSETEST2
+ *    MSETEST3
+ *    MSETEST4
+ *     
+ */
+
+#define _KBD( x )       _SA1101( ( x ) + __TRACK_INTERFACE )
+#define _MSE( x )       _SA1101( ( x ) + __MOUSE_INTERFACE )
+
+#define _KBDCR          _KBD( 0x0000 )
+#define _KBDSTAT        _KBD( 0x0400 )
+#define _KBDDATA        _KBD( 0x0800 )
+#define _KBDCLKDIV      _KBD( 0x0c00 )
+#define _KBDPRECNT      _KBD( 0x1000 )
+#define _KBDTEST1       _KBD( 0x2000 )
+#define _KBDTEST2       _KBD( 0x2400 )
+#define _KBDTEST3       _KBD( 0x2800 )
+#define _KBDTEST4       _KBD( 0x2c00 )
+#define _MSECR          _MSE( 0x0000 )
+#define _MSESTAT        _MSE( 0x0400 )
+#define _MSEDATA        _MSE( 0x0800 )
+#define _MSECLKDIV      _MSE( 0x0c00 )
+#define _MSEPRECNT      _MSE( 0x1000 )
+#define _MSETEST1       _MSE( 0x2000 )
+#define _MSETEST2       _MSE( 0x2400 )
+#define _MSETEST3       _MSE( 0x2800 )
+#define _MSETEST4       _MSE( 0x2c00 )
+
+#if ( LANGUAGE == C )
+
+#define KBDCR       (*((volatile Word *) SA1101_p2v (_KBDCR)))
+#define KBDSTAT     (*((volatile Word *) SA1101_p2v (_KBDSTAT)))
+#define KBDDATA     (*((volatile Word *) SA1101_p2v (_KBDDATA)))
+#define KBDCLKDIV   (*((volatile Word *) SA1101_p2v (_KBDCLKDIV)))
+#define KBDPRECNT   (*((volatile Word *) SA1101_p2v (_KBDPRECNT)))
+#define KBDTEST1    (*((volatile Word *) SA1101_p2v (_KBDTEST1)))
+#define KBDTEST2    (*((volatile Word *) SA1101_p2v (_KBDTEST2)))
+#define KBDTEST3    (*((volatile Word *) SA1101_p2v (_KBDTEST3)))
+#define KBDTEST4    (*((volatile Word *) SA1101_p2v (_KBDTEST4)))
+#define MSECR       (*((volatile Word *) SA1101_p2v (_MSECR)))
+#define MSESTAT     (*((volatile Word *) SA1101_p2v (_MSESTAT)))
+#define MSEDATA     (*((volatile Word *) SA1101_p2v (_MSEDATA)))
+#define MSECLKDIV   (*((volatile Word *) SA1101_p2v (_MSECLKDIV)))
+#define MSEPRECNT   (*((volatile Word *) SA1101_p2v (_MSEPRECNT)))
+#define MSETEST1    (*((volatile Word *) SA1101_p2v (_MSETEST1)))
+#define MSETEST2    (*((volatile Word *) SA1101_p2v (_MSETEST2)))
+#define MSETEST3    (*((volatile Word *) SA1101_p2v (_MSETEST3)))
+#define MSETEST4    (*((volatile Word *) SA1101_p2v (_MSETEST4)))
+
+
+#define KBDCR_ENA                0x08
+#define KBDCR_FKD                0x02
+#define KBDCR_FKC                0x01
+
+#define KBDSTAT_TXE              0x80
+#define KBDSTAT_TXB              0x40
+#define KBDSTAT_RXF              0x20
+#define KBDSTAT_RXB              0x10
+#define KBDSTAT_ENA              0x08
+#define KBDSTAT_RXP              0x04
+#define KBDSTAT_KBD              0x02
+#define KBDSTAT_KBC              0x01
+
+#define KBDCLKDIV_DivVal         Fld(4,0)
+
+#define MSECR_ENA                0x08
+#define MSECR_FKD                0x02
+#define MSECR_FKC                0x01
+
+#define MSESTAT_TXE              0x80
+#define MSESTAT_TXB              0x40
+#define MSESTAT_RXF              0x20
+#define MSESTAT_RXB              0x10
+#define MSESTAT_ENA              0x08
+#define MSESTAT_RXP              0x04   
+#define MSESTAT_MSD              0x02
+#define MSESTAT_MSC              0x01
+
+#define MSECLKDIV_DivVal         Fld(4,0)
+
+#define KBDTEST1_CD              0x80
+#define KBDTEST1_RC1             0x40
+#define KBDTEST1_MC              0x20
+#define KBDTEST1_C               Fld(2,3)
+#define KBDTEST1_T2              0x40
+#define KBDTEST1_T1              0x20
+#define KBDTEST1_T0              0x10
+#define KBDTEST2_TICBnRES        0x08
+#define KBDTEST2_RKC             0x04
+#define KBDTEST2_RKD             0x02
+#define KBDTEST2_SEL             0x01
+#define KBDTEST3_ms_16           0x80
+#define KBDTEST3_us_64           0x40
+#define KBDTEST3_us_16           0x20
+#define KBDTEST3_DIV8            0x10
+#define KBDTEST3_DIn             0x08
+#define KBDTEST3_CIn             0x04
+#define KBDTEST3_KD              0x02
+#define KBDTEST3_KC              0x01
+#define KBDTEST4_BC12            0x80
+#define KBDTEST4_BC11            0x40
+#define KBDTEST4_TRES            0x20
+#define KBDTEST4_CLKOE           0x10
+#define KBDTEST4_CRES            0x08
+#define KBDTEST4_RXB             0x04
+#define KBDTEST4_TXB             0x02
+#define KBDTEST4_SRX             0x01
+
+#define MSETEST1_CD              0x80
+#define MSETEST1_RC1             0x40
+#define MSETEST1_MC              0x20
+#define MSETEST1_C               Fld(2,3)
+#define MSETEST1_T2              0x40
+#define MSETEST1_T1              0x20
+#define MSETEST1_T0              0x10
+#define MSETEST2_TICBnRES        0x08
+#define MSETEST2_RKC             0x04
+#define MSETEST2_RKD             0x02
+#define MSETEST2_SEL             0x01
+#define MSETEST3_ms_16           0x80
+#define MSETEST3_us_64           0x40
+#define MSETEST3_us_16           0x20
+#define MSETEST3_DIV8            0x10
+#define MSETEST3_DIn             0x08
+#define MSETEST3_CIn             0x04
+#define MSETEST3_KD              0x02
+#define MSETEST3_KC              0x01
+#define MSETEST4_BC12            0x80
+#define MSETEST4_BC11            0x40
+#define MSETEST4_TRES            0x20
+#define MSETEST4_CLKOE           0x10
+#define MSETEST4_CRES            0x08
+#define MSETEST4_RXB             0x04
+#define MSETEST4_TXB             0x02
+#define MSETEST4_SRX             0x01
+
+#endif  /* LANGUAGE == C */
+
+
+/*
+ * General-Purpose I/O Interface
+ *
+ * Registers
+ *    PADWR     Port A Data Write Register
+ *    PBDWR     Port B Data Write Register
+ *    PADRR     Port A Data Read Register
+ *    PBDRR     Port B Data Read Register
+ *    PADDR     Port A Data Direction Register
+ *    PBDDR     Port B Data Direction Register
+ *    PASSR     Port A Sleep State Register
+ *    PBSSR     Port B Sleep State Register
+ *
+ */
+
+#define _PIO( x )      _SA1101( ( x ) + __GPIO_INTERFACE )
+
+#define _PADWR         _PIO( 0x0000 )
+#define _PBDWR         _PIO( 0x0400 )
+#define _PADRR         _PIO( 0x0000 )
+#define _PBDRR         _PIO( 0x0400 )
+#define _PADDR         _PIO( 0x0800 )
+#define _PBDDR         _PIO( 0x0c00 )
+#define _PASSR         _PIO( 0x1000 )
+#define _PBSSR         _PIO( 0x1400 )
+
+
+#if ( LANGUAGE == C )
+
+
+#define PADWR       (*((volatile Word *) SA1101_p2v (_PADWR)))
+#define PBDWR       (*((volatile Word *) SA1101_p2v (_PBDWR)))
+#define PADRR       (*((volatile Word *) SA1101_p2v (_PADRR)))
+#define PBDRR       (*((volatile Word *) SA1101_p2v (_PBDRR)))
+#define PADDR       (*((volatile Word *) SA1101_p2v (_PADDR)))
+#define PBDDR       (*((volatile Word *) SA1101_p2v (_PBDDR)))
+#define PASSR       (*((volatile Word *) SA1101_p2v (_PASSR)))
+#define PBSSR       (*((volatile Word *) SA1101_p2v (_PBSSR)))
+
+#endif
+
+
+
+/*
+ * Keypad Interface
+ *
+ * Registers
+ *    PXDWR
+ *    PXDRR
+ *    PYDWR
+ *    PYDRR
+ *
+ */
+
+#define _KEYPAD( x )    _SA1101( ( x ) + __KEYPAD_INTERFACE ) 
+
+#define _PXDWR     _KEYPAD( 0x0000 )
+#define _PXDRR     _KEYPAD( 0x0000 )
+#define _PYDWR     _KEYPAD( 0x0400 )
+#define _PYDRR     _KEYPAD( 0x0400 )
+
+#if ( LANGUAGE == C )
+
+
+#define PXDWR       (*((volatile Word *) SA1101_p2v (_PXDWR)))
+#define PXDRR       (*((volatile Word *) SA1101_p2v (_PXDRR)))
+#define PYDWR       (*((volatile Word *) SA1101_p2v (_PYDWR)))
+#define PYDRR       (*((volatile Word *) SA1101_p2v (_PYDRR)))
+
+#endif
+
+
+
+/*
+ * PCMCIA Interface
+ *
+ * Registers
+ *    PCSR      Status Register
+ *    PCCR      Control Register
+ *    PCSSR     Sleep State Register
+ *
+ */
+
+#define _CARD( x )      _SA1101( ( x ) + __PCMCIA_INTERFACE )
+
+#define _PCSR      _CARD( 0x0000 )
+#define _PCCR      _CARD( 0x0400 )
+#define _PCSSR     _CARD( 0x0800 )
+
+#if ( LANGUAGE == C )
+#define PCSR    (*((volatile Word *) SA1101_p2v (_PCSR)))
+#define PCCR    (*((volatile Word *) SA1101_p2v (_PCCR)))
+#define PCSSR   (*((volatile Word *) SA1101_p2v (_PCSSR)))
+
+#define PCSR_S0_ready           0x0001
+#define PCSR_S1_ready           0x0002
+#define PCSR_S0_detected        0x0004
+#define PCSR_S1_detected        0x0008
+#define PCSR_S0_VS1             0x0010
+#define PCSR_S0_VS2             0x0020
+#define PCSR_S1_VS1             0x0040
+#define PCSR_S1_VS2             0x0080
+#define PCSR_S0_WP              0x0100
+#define PCSR_S1_WP              0x0200
+#define PCSR_S0_BVD1_nSTSCHG    0x0400
+#define PCSR_S0_BVD2_nSPKR      0x0800
+#define PCSR_S1_BVD1_nSTSCHG    0x1000
+#define PCSR_S1_BVD2_nSPKR      0x2000
+
+#define PCCR_S0_VPP0            0x0001
+#define PCCR_S0_VPP1            0x0002
+#define PCCR_S0_VCC0            0x0004
+#define PCCR_S0_VCC1            0x0008
+#define PCCR_S1_VPP0            0x0010
+#define PCCR_S1_VPP1            0x0020
+#define PCCR_S1_VCC0            0x0040
+#define PCCR_S1_VCC1            0x0080
+#define PCCR_S0_reset           0x0100
+#define PCCR_S1_reset           0x0200
+#define PCCR_S0_float           0x0400
+#define PCCR_S1_float           0x0800
+
+#define PCSSR_S0_VCC0           0x0001
+#define PCSSR_S0_VCC1           0x0002
+#define PCSSR_S0_VPP0           0x0004
+#define PCSSR_S0_VPP1           0x0008
+#define PCSSR_S0_control        0x0010
+#define PCSSR_S1_VCC0           0x0020
+#define PCSSR_S1_VCC1           0x0040
+#define PCSSR_S1_VPP0           0x0080
+#define PCSSR_S1_VPP1           0x0100
+#define PCSSR_S1_control        0x0200
+
+#endif
+
+#undef C
+#undef Assembly
diff --git a/include/asm-arm/arch-sa1100/SA-1111.h b/include/asm-arm/arch-sa1100/SA-1111.h
new file mode 100644
index 000000000000..c38f60915cb6
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/SA-1111.h
@@ -0,0 +1,5 @@
+/*
+ * Moved to new location
+ */
+#warning using old SA-1111.h - update to <asm/hardware/sa1111.h>
+#include <asm/hardware/sa1111.h>
diff --git a/include/asm-arm/arch-sa1100/assabet.h b/include/asm-arm/arch-sa1100/assabet.h
new file mode 100644
index 000000000000..1f59b368c3f6
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/assabet.h
@@ -0,0 +1,106 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/assabet.h
+ *
+ * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
+ *
+ * This file contains the hardware specific definitions for Assabet
+ * Only include this file from SA1100-specific files.
+ *
+ * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
+ *      Definitions for Neponset added.
+ */
+#ifndef __ASM_ARCH_ASSABET_H
+#define __ASM_ARCH_ASSABET_H
+
+#include <linux/config.h>
+
+/* System Configuration Register flags */
+
+#define ASSABET_SCR_SDRAM_LOW   (1<<2)  /* SDRAM size (low bit) */
+#define ASSABET_SCR_SDRAM_HIGH  (1<<3)  /* SDRAM size (high bit) */
+#define ASSABET_SCR_FLASH_LOW   (1<<4)  /* Flash size (low bit) */
+#define ASSABET_SCR_FLASH_HIGH  (1<<5)  /* Flash size (high bit) */
+#define ASSABET_SCR_GFX         (1<<8)  /* Graphics Accelerator (0 = present) */
+#define ASSABET_SCR_SA1111      (1<<9)  /* Neponset (0 = present) */
+
+#define ASSABET_SCR_INIT        -1
+
+extern unsigned long SCR_value;
+
+#ifdef CONFIG_ASSABET_NEPONSET
+#define machine_has_neponset()  ((SCR_value & ASSABET_SCR_SA1111) == 0)
+#else
+#define machine_has_neponset()  (0)
+#endif
+
+/* Board Control Register */
+
+#define ASSABET_BCR_BASE  0xf1000000
+#define ASSABET_BCR (*(volatile unsigned int *)(ASSABET_BCR_BASE))
+
+#define ASSABET_BCR_CF_PWR      (1<<0)  /* Compact Flash Power (1 = 3.3v, 0 = off) */
+#define ASSABET_BCR_CF_RST      (1<<1)  /* Compact Flash Reset (1 = power up reset) */
+#define ASSABET_BCR_GFX_RST     (1<<1)  /* Graphics Accelerator Reset (0 = hold reset) */
+#define ASSABET_BCR_CODEC_RST   (1<<2)  /* 0 = Holds UCB1300, ADI7171, and UDA1341 in reset */
+#define ASSABET_BCR_IRDA_FSEL   (1<<3)  /* IRDA Frequency select (0 = SIR, 1 = MIR/ FIR) */
+#define ASSABET_BCR_IRDA_MD0    (1<<4)  /* Range/Power select */
+#define ASSABET_BCR_IRDA_MD1    (1<<5)  /* Range/Power select */
+#define ASSABET_BCR_STEREO_LB   (1<<6)  /* Stereo Loopback */
+#define ASSABET_BCR_CF_BUS_OFF  (1<<7)  /* Compact Flash bus (0 = on, 1 = off (float)) */
+#define ASSABET_BCR_AUDIO_ON    (1<<8)  /* Audio power on */
+#define ASSABET_BCR_LIGHT_ON    (1<<9)  /* Backlight */
+#define ASSABET_BCR_LCD_12RGB   (1<<10) /* 0 = 16RGB, 1 = 12RGB */
+#define ASSABET_BCR_LCD_ON      (1<<11) /* LCD power on */
+#define ASSABET_BCR_RS232EN     (1<<12) /* RS232 transceiver enable */
+#define ASSABET_BCR_LED_RED     (1<<13) /* D9 (0 = on, 1 = off) */
+#define ASSABET_BCR_LED_GREEN   (1<<14) /* D8 (0 = on, 1 = off) */
+#define ASSABET_BCR_VIB_ON      (1<<15) /* Vibration motor (quiet alert) */
+#define ASSABET_BCR_COM_DTR     (1<<16) /* COMport Data Terminal Ready */
+#define ASSABET_BCR_COM_RTS     (1<<17) /* COMport Request To Send */
+#define ASSABET_BCR_RAD_WU      (1<<18) /* Radio wake up interrupt */
+#define ASSABET_BCR_SMB_EN      (1<<19) /* System management bus enable */
+#define ASSABET_BCR_TV_IR_DEC   (1<<20) /* TV IR Decode Enable (not implemented) */
+#define ASSABET_BCR_QMUTE       (1<<21) /* Quick Mute */
+#define ASSABET_BCR_RAD_ON      (1<<22) /* Radio Power On */
+#define ASSABET_BCR_SPK_OFF     (1<<23) /* 1 = Speaker amplifier power off */
+
+#ifdef CONFIG_SA1100_ASSABET
+extern void ASSABET_BCR_frob(unsigned int mask, unsigned int set);
+#else
+#define ASSABET_BCR_frob(x,y)   do { } while (0)
+#endif
+
+#define ASSABET_BCR_set(x)      ASSABET_BCR_frob((x), (x))
+#define ASSABET_BCR_clear(x)    ASSABET_BCR_frob((x), 0)
+
+#define ASSABET_BSR_BASE        0xf1000000
+#define ASSABET_BSR (*(volatile unsigned int*)(ASSABET_BSR_BASE))
+
+#define ASSABET_BSR_RS232_VALID (1 << 24)
+#define ASSABET_BSR_COM_DCD     (1 << 25)
+#define ASSABET_BSR_COM_CTS     (1 << 26)
+#define ASSABET_BSR_COM_DSR     (1 << 27)
+#define ASSABET_BSR_RAD_CTS     (1 << 28)
+#define ASSABET_BSR_RAD_DSR     (1 << 29)
+#define ASSABET_BSR_RAD_DCD     (1 << 30)
+#define ASSABET_BSR_RAD_RI      (1 << 31)
+
+
+/* GPIOs for which the generic definition doesn't say much */
+#define ASSABET_GPIO_RADIO_IRQ          GPIO_GPIO (14)  /* Radio interrupt request  */
+#define ASSABET_GPIO_PS_MODE_SYNC       GPIO_GPIO (16)  /* Power supply mode/sync   */
+#define ASSABET_GPIO_STEREO_64FS_CLK    GPIO_GPIO (19)  /* SSP UDA1341 clock input  */
+#define ASSABET_GPIO_CF_IRQ             GPIO_GPIO (21)  /* CF IRQ   */
+#define ASSABET_GPIO_CF_CD              GPIO_GPIO (22)  /* CF CD */
+#define ASSABET_GPIO_CF_BVD2            GPIO_GPIO (24)  /* CF BVD */
+#define ASSABET_GPIO_GFX_IRQ            GPIO_GPIO (24)  /* Graphics IRQ */
+#define ASSABET_GPIO_CF_BVD1            GPIO_GPIO (25)  /* CF BVD */
+#define ASSABET_GPIO_BATT_LOW           GPIO_GPIO (26)  /* Low battery */
+#define ASSABET_GPIO_RCLK               GPIO_GPIO (26)  /* CCLK/2  */
+
+#define ASSABET_IRQ_GPIO_CF_IRQ         IRQ_GPIO21
+#define ASSABET_IRQ_GPIO_CF_CD          IRQ_GPIO22
+#define ASSABET_IRQ_GPIO_CF_BVD2        IRQ_GPIO24
+#define ASSABET_IRQ_GPIO_CF_BVD1        IRQ_GPIO25
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/badge4.h b/include/asm-arm/arch-sa1100/badge4.h
new file mode 100644
index 000000000000..8d7a671492db
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/badge4.h
@@ -0,0 +1,75 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/badge4.h
+ *
+ *   Tim Connors <connors@hpl.hp.com>
+ *   Christopher Hoover <ch@hpl.hp.com>
+ *
+ * Copyright (C) 2002 Hewlett-Packard Company
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#error "include <asm/hardware.h> instead"
+#endif
+
+#define BADGE4_SA1111_BASE              (0x48000000)
+
+/* GPIOs on the BadgePAD 4 */
+#define BADGE4_GPIO_INT_1111            GPIO_GPIO0   /* SA-1111 IRQ */
+
+#define BADGE4_GPIO_INT_VID             GPIO_GPIO1   /* Video expansion */
+#define BADGE4_GPIO_LGP2                GPIO_GPIO2   /* GPIO_LDD8 */
+#define BADGE4_GPIO_LGP3                GPIO_GPIO3   /* GPIO_LDD9 */
+#define BADGE4_GPIO_LGP4                GPIO_GPIO4   /* GPIO_LDD10 */
+#define BADGE4_GPIO_LGP5                GPIO_GPIO5   /* GPIO_LDD11 */
+#define BADGE4_GPIO_LGP6                GPIO_GPIO6   /* GPIO_LDD12 */
+#define BADGE4_GPIO_LGP7                GPIO_GPIO7   /* GPIO_LDD13 */
+#define BADGE4_GPIO_LGP8                GPIO_GPIO8   /* GPIO_LDD14 */
+#define BADGE4_GPIO_LGP9                GPIO_GPIO9   /* GPIO_LDD15 */
+#define BADGE4_GPIO_GPA_VID             GPIO_GPIO10  /* Video expansion */
+#define BADGE4_GPIO_GPB_VID             GPIO_GPIO11  /* Video expansion */
+#define BADGE4_GPIO_GPC_VID             GPIO_GPIO12  /* Video expansion */
+
+#define BADGE4_GPIO_UART_HS1            GPIO_GPIO13
+#define BADGE4_GPIO_UART_HS2            GPIO_GPIO14
+
+#define BADGE4_GPIO_MUXSEL0             GPIO_GPIO15
+#define BADGE4_GPIO_TESTPT_J7           GPIO_GPIO16
+
+#define BADGE4_GPIO_SDSDA               GPIO_GPIO17  /* SDRAM SPD Data */
+#define BADGE4_GPIO_SDSCL               GPIO_GPIO18  /* SDRAM SPD Clock */
+#define BADGE4_GPIO_SDTYP0              GPIO_GPIO19  /* SDRAM Type Control */
+#define BADGE4_GPIO_SDTYP1              GPIO_GPIO20  /* SDRAM Type Control */
+
+#define BADGE4_GPIO_BGNT_1111           GPIO_GPIO21  /* GPIO_MBGNT */
+#define BADGE4_GPIO_BREQ_1111           GPIO_GPIO22  /* GPIO_TREQA */
+
+#define BADGE4_GPIO_TESTPT_J6           GPIO_GPIO23
+
+#define BADGE4_GPIO_PCMEN5V             GPIO_GPIO24  /* 5V power */
+
+#define BADGE4_GPIO_SA1111_NRST         GPIO_GPIO25  /* SA-1111 nRESET */
+
+#define BADGE4_GPIO_TESTPT_J5           GPIO_GPIO26
+
+#define BADGE4_GPIO_CLK_1111            GPIO_GPIO27  /* GPIO_32_768kHz */
+
+/* Interrupts on the BadgePAD 4 */
+#define BADGE4_IRQ_GPIO_SA1111          IRQ_GPIO0    /* SA-1111 interrupt */
+
+
+/* PCM5ENV Usage tracking */
+
+#define BADGE4_5V_PCMCIA_SOCK0          (1<<0)
+#define BADGE4_5V_PCMCIA_SOCK1          (1<<1)
+#define BADGE4_5V_PCMCIA_SOCK(n)        (1<<(n))
+#define BADGE4_5V_USB                   (1<<2)
+#define BADGE4_5V_INITIALLY             (1<<3)
+
+#ifndef __ASSEMBLY__
+extern void badge4_set_5V(unsigned subsystem, int on);
+#endif
diff --git a/include/asm-arm/arch-sa1100/bitfield.h b/include/asm-arm/arch-sa1100/bitfield.h
new file mode 100644
index 000000000000..f1f0e3387d9c
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/bitfield.h
@@ -0,0 +1,113 @@
+/*
+ *      FILE            bitfield.h
+ *
+ *      Version         1.1
+ *      Author          Copyright (c) Marc A. Viredaz, 1998
+ *                      DEC Western Research Laboratory, Palo Alto, CA
+ *      Date            April 1998 (April 1997)
+ *      System          Advanced RISC Machine (ARM)
+ *      Language        C or ARM Assembly
+ *      Purpose         Definition of macros to operate on bit fields.
+ */
+
+
+
+#ifndef __BITFIELD_H
+#define __BITFIELD_H
+
+#ifndef __ASSEMBLY__
+#define UData(Data)     ((unsigned long) (Data))
+#else
+#define UData(Data)     (Data)
+#endif
+
+
+/*
+ * MACRO: Fld
+ *
+ * Purpose
+ *    The macro "Fld" encodes a bit field, given its size and its shift value
+ *    with respect to bit 0.
+ *
+ * Note
+ *    A more intuitive way to encode bit fields would have been to use their
+ *    mask. However, extracting size and shift value information from a bit
+ *    field's mask is cumbersome and might break the assembler (255-character
+ *    line-size limit).
+ *
+ * Input
+ *    Size              Size of the bit field, in number of bits.
+ *    Shft              Shift value of the bit field with respect to bit 0.
+ *
+ * Output
+ *    Fld               Encoded bit field.
+ */
+
+#define Fld(Size, Shft) (((Size) << 16) + (Shft))
+
+
+/*
+ * MACROS: FSize, FShft, FMsk, FAlnMsk, F1stBit
+ *
+ * Purpose
+ *    The macros "FSize", "FShft", "FMsk", "FAlnMsk", and "F1stBit" return
+ *    the size, shift value, mask, aligned mask, and first bit of a
+ *    bit field.
+ *
+ * Input
+ *    Field             Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FSize             Size of the bit field, in number of bits.
+ *    FShft             Shift value of the bit field with respect to bit 0.
+ *    FMsk              Mask for the bit field.
+ *    FAlnMsk           Mask for the bit field, aligned on bit 0.
+ *    F1stBit           First bit of the bit field.
+ */
+
+#define FSize(Field)    ((Field) >> 16)
+#define FShft(Field)    ((Field) & 0x0000FFFF)
+#define FMsk(Field)     (((UData (1) << FSize (Field)) - 1) << FShft (Field))
+#define FAlnMsk(Field)  ((UData (1) << FSize (Field)) - 1)
+#define F1stBit(Field)  (UData (1) << FShft (Field))
+
+
+/*
+ * MACRO: FInsrt
+ *
+ * Purpose
+ *    The macro "FInsrt" inserts a value into a bit field by shifting the
+ *    former appropriately.
+ *
+ * Input
+ *    Value             Bit-field value.
+ *    Field             Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FInsrt            Bit-field value positioned appropriately.
+ */
+
+#define FInsrt(Value, Field) \
+                        (UData (Value) << FShft (Field))
+
+
+/*
+ * MACRO: FExtr
+ *
+ * Purpose
+ *    The macro "FExtr" extracts the value of a bit field by masking and
+ *    shifting it appropriately.
+ *
+ * Input
+ *    Data              Data containing the bit-field to be extracted.
+ *    Field             Encoded bit field (using the macro "Fld").
+ *
+ * Output
+ *    FExtr             Bit-field value.
+ */
+
+#define FExtr(Data, Field) \
+                        ((UData (Data) >> FShft (Field)) & FAlnMsk (Field))
+
+
+#endif /* __BITFIELD_H */
diff --git a/include/asm-arm/arch-sa1100/cerf.h b/include/asm-arm/arch-sa1100/cerf.h
new file mode 100644
index 000000000000..356d5ba88991
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/cerf.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-arm/arch-sa1100/cerf.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Apr-2003 : Removed some old PDA crud [FB]
+ */
+#ifndef _INCLUDE_CERF_H_
+#define _INCLUDE_CERF_H_
+
+#include <linux/config.h>
+
+#define CERF_ETH_IO                     0xf0000000
+#define CERF_ETH_IRQ IRQ_GPIO26
+
+#define CERF_GPIO_CF_BVD2               GPIO_GPIO (19)
+#define CERF_GPIO_CF_BVD1               GPIO_GPIO (20)
+#define CERF_GPIO_CF_RESET              GPIO_GPIO (21)
+#define CERF_GPIO_CF_IRQ                GPIO_GPIO (22)
+#define CERF_GPIO_CF_CD                 GPIO_GPIO (23)
+
+#define CERF_IRQ_GPIO_CF_BVD2           IRQ_GPIO19
+#define CERF_IRQ_GPIO_CF_BVD1           IRQ_GPIO20
+#define CERF_IRQ_GPIO_CF_IRQ            IRQ_GPIO22
+#define CERF_IRQ_GPIO_CF_CD             IRQ_GPIO23
+
+#endif // _INCLUDE_CERF_H_
diff --git a/include/asm-arm/arch-sa1100/collie.h b/include/asm-arm/arch-sa1100/collie.h
new file mode 100644
index 000000000000..d49e5ff63ca4
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/collie.h
@@ -0,0 +1,85 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/collie.h
+ *
+ * This file contains the hardware specific definitions for Assabet
+ * Only include this file from SA1100-specific files.
+ *
+ * ChangeLog:
+ *   04-06-2001 Lineo Japan, Inc.
+ *   04-16-2001 SHARP Corporation
+ *   07-07-2002 Chris Larson <clarson@digi.com>
+ *
+ */
+#ifndef __ASM_ARCH_COLLIE_H
+#define __ASM_ARCH_COLLIE_H
+
+#include <linux/config.h>
+
+#define COLLIE_SCP_CHARGE_ON    SCOOP_GPCR_PA11
+#define COLLIE_SCP_DIAG_BOOT1   SCOOP_GPCR_PA12
+#define COLLIE_SCP_DIAG_BOOT2   SCOOP_GPCR_PA13
+#define COLLIE_SCP_MUTE_L       SCOOP_GPCR_PA14
+#define COLLIE_SCP_MUTE_R       SCOOP_GPCR_PA15
+#define COLLIE_SCP_5VON         SCOOP_GPCR_PA16
+#define COLLIE_SCP_AMP_ON       SCOOP_GPCR_PA17
+#define COLLIE_SCP_VPEN         SCOOP_GPCR_PA18
+#define COLLIE_SCP_LB_VOL_CHG   SCOOP_GPCR_PA19
+
+#define COLLIE_SCOOP_IO_DIR     ( COLLIE_SCP_CHARGE_ON | COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | \
+                                COLLIE_SCP_5VON | COLLIE_SCP_AMP_ON | COLLIE_SCP_VPEN | \
+                                COLLIE_SCP_LB_VOL_CHG )
+#define COLLIE_SCOOP_IO_OUT     ( COLLIE_SCP_MUTE_L | COLLIE_SCP_MUTE_R | COLLIE_SCP_VPEN | \
+                                COLLIE_SCP_CHARGE_ON )
+
+/* GPIOs for which the generic definition doesn't say much */
+
+#define COLLIE_GPIO_ON_KEY              GPIO_GPIO (0)
+#define COLLIE_GPIO_AC_IN               GPIO_GPIO (1)
+#define COLLIE_GPIO_CF_IRQ              GPIO_GPIO (14)
+#define COLLIE_GPIO_nREMOCON_INT        GPIO_GPIO (15)
+#define COLLIE_GPIO_UCB1x00_RESET       GPIO_GPIO (16)
+#define COLLIE_GPIO_CO                  GPIO_GPIO (20)
+#define COLLIE_GPIO_MCP_CLK             GPIO_GPIO (21)
+#define COLLIE_GPIO_CF_CD               GPIO_GPIO (22)
+#define COLLIE_GPIO_UCB1x00_IRQ         GPIO_GPIO (23)
+#define COLLIE_GPIO_WAKEUP              GPIO_GPIO (24)
+#define COLLIE_GPIO_GA_INT              GPIO_GPIO (25)
+#define COLLIE_GPIO_MAIN_BAT_LOW        GPIO_GPIO (26)
+
+/* Interrupts */
+
+#define COLLIE_IRQ_GPIO_ON_KEY          IRQ_GPIO0
+#define COLLIE_IRQ_GPIO_AC_IN           IRQ_GPIO1
+#define COLLIE_IRQ_GPIO_CF_IRQ          IRQ_GPIO14
+#define COLLIE_IRQ_GPIO_nREMOCON_INT    IRQ_GPIO15
+#define COLLIE_IRQ_GPIO_CO              IRQ_GPIO20
+#define COLLIE_IRQ_GPIO_CF_CD           IRQ_GPIO22
+#define COLLIE_IRQ_GPIO_UCB1x00_IRQ     IRQ_GPIO23
+#define COLLIE_IRQ_GPIO_WAKEUP          IRQ_GPIO24
+#define COLLIE_IRQ_GPIO_GA_INT          IRQ_GPIO25
+#define COLLIE_IRQ_GPIO_MAIN_BAT_LOW    IRQ_GPIO26
+
+#define COLLIE_LCM_IRQ_GPIO_RTS         IRQ_LOCOMO_GPIO0
+#define COLLIE_LCM_IRQ_GPIO_CTS         IRQ_LOCOMO_GPIO1
+#define COLLIE_LCM_IRQ_GPIO_DSR         IRQ_LOCOMO_GPIO2
+#define COLLIE_LCM_IRQ_GPIO_DTR         IRQ_LOCOMO_GPIO3
+#define COLLIE_LCM_IRQ_GPIO_nSD_DETECT  IRQ_LOCOMO_GPIO13
+#define COLLIE_LCM_IRQ_GPIO_nSD_WP      IRQ_LOCOMO_GPIO14
+
+/* GPIO's on the TC35143AF (Toshiba Analog Frontend) */
+#define COLLIE_TC35143_GPIO_VERSION0    UCB_IO_0        /* GPIO0=Version                 */
+#define COLLIE_TC35143_GPIO_TBL_CHK     UCB_IO_1        /* GPIO1=TBL_CHK                 */
+#define COLLIE_TC35143_GPIO_VPEN_ON     UCB_IO_2        /* GPIO2=VPNE_ON                 */
+#define COLLIE_TC35143_GPIO_IR_ON       UCB_IO_3        /* GPIO3=IR_ON                   */
+#define COLLIE_TC35143_GPIO_AMP_ON      UCB_IO_4        /* GPIO4=AMP_ON                  */
+#define COLLIE_TC35143_GPIO_VERSION1    UCB_IO_5        /* GPIO5=Version                 */
+#define COLLIE_TC35143_GPIO_FS8KLPF     UCB_IO_5        /* GPIO5=fs 8k LPF               */
+#define COLLIE_TC35143_GPIO_BUZZER_BIAS UCB_IO_6        /* GPIO6=BUZZER BIAS             */
+#define COLLIE_TC35143_GPIO_MBAT_ON     UCB_IO_7        /* GPIO7=MBAT_ON                 */
+#define COLLIE_TC35143_GPIO_BBAT_ON     UCB_IO_8        /* GPIO8=BBAT_ON                 */
+#define COLLIE_TC35143_GPIO_TMP_ON      UCB_IO_9        /* GPIO9=TMP_ON                  */
+#define COLLIE_TC35143_GPIO_IN          ( UCB_IO_0 | UCB_IO_2 | UCB_IO_5 )
+#define COLLIE_TC35143_GPIO_OUT         ( UCB_IO_1 | UCB_IO_3 | UCB_IO_4 | UCB_IO_6 | \
+                                        UCB_IO_7 | UCB_IO_8 | UCB_IO_9 )
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/debug-macro.S b/include/asm-arm/arch-sa1100/debug-macro.S
new file mode 100644
index 000000000000..755fa3453862
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/debug-macro.S
@@ -0,0 +1,57 @@
+/* linux/include/asm-arm/arch-sa1100/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx, #0x80000000        @ physical base address
+                movne   \rx, #0xf8000000        @ virtual address
+
+                @ We probe for the active serial port here, coherently with
+                @ the comment in include/asm-arm/arch-sa1100/uncompress.h.
+                @ We assume r1 can be clobbered.
+
+                @ see if Ser3 is active
+                add     \rx, \rx, #0x00050000
+                ldr     r1, [\rx, #UTCR3]
+                tst     r1, #UTCR3_TXE
+
+                @ if Ser3 is inactive, then try Ser1
+                addeq   \rx, \rx, #(0x00010000 - 0x00050000)
+                ldreq   r1, [\rx, #UTCR3]
+                tsteq   r1, #UTCR3_TXE
+
+                @ if Ser1 is inactive, then try Ser2
+                addeq   \rx, \rx, #(0x00030000 - 0x00010000)
+                ldreq   r1, [\rx, #UTCR3]
+                tsteq   r1, #UTCR3_TXE
+
+                @ if all ports are inactive, then there is nothing we can do
+                moveq   pc, lr
+                .endm
+
+                .macro  senduart,rd,rx
+                str     \rd, [\rx, #UTDR]
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #UTSR1]
+                tst     \rd, #UTSR1_TNF
+                beq     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #UTSR1]
+                tst     \rd, #UTSR1_TBY
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-sa1100/dma.h b/include/asm-arm/arch-sa1100/dma.h
new file mode 100644
index 000000000000..3d60ed9f8c34
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/dma.h
@@ -0,0 +1,132 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/dma.h
+ *
+ * Generic SA1100 DMA support
+ *
+ * Copyright (C) 2000 Nicolas Pitre
+ *
+ */
+
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#include <linux/config.h>
+#include "hardware.h"
+
+
+/*
+ * This is the maximum DMA address that can be DMAd to.
+ */
+#define MAX_DMA_ADDRESS         0xffffffff
+
+
+/*
+ * The regular generic DMA interface is inappropriate for the
+ * SA1100 DMA model.  None of the SA1100 specific drivers using
+ * DMA are portable anyway so it's pointless to try to twist the
+ * regular DMA API to accommodate them.
+ */
+#define MAX_DMA_CHANNELS        0
+
+/*
+ * The SA1100 has six internal DMA channels.
+ */
+#define SA1100_DMA_CHANNELS     6
+
+/*
+ * Maximum physical DMA buffer size
+ */
+#define MAX_DMA_SIZE            0x1fff
+#define CUT_DMA_SIZE            0x1000
+
+/*
+ * All possible SA1100 devices a DMA channel can be attached to.
+ */
+typedef enum {
+        DMA_Ser0UDCWr  = DDAR_Ser0UDCWr,   /* Ser. port 0 UDC Write */
+        DMA_Ser0UDCRd  = DDAR_Ser0UDCRd,   /* Ser. port 0 UDC Read */
+        DMA_Ser1UARTWr = DDAR_Ser1UARTWr,  /* Ser. port 1 UART Write */
+        DMA_Ser1UARTRd = DDAR_Ser1UARTRd,  /* Ser. port 1 UART Read */
+        DMA_Ser1SDLCWr = DDAR_Ser1SDLCWr,  /* Ser. port 1 SDLC Write */
+        DMA_Ser1SDLCRd = DDAR_Ser1SDLCRd,  /* Ser. port 1 SDLC Read */
+        DMA_Ser2UARTWr = DDAR_Ser2UARTWr,  /* Ser. port 2 UART Write */
+        DMA_Ser2UARTRd = DDAR_Ser2UARTRd,  /* Ser. port 2 UART Read */
+        DMA_Ser2HSSPWr = DDAR_Ser2HSSPWr,  /* Ser. port 2 HSSP Write */
+        DMA_Ser2HSSPRd = DDAR_Ser2HSSPRd,  /* Ser. port 2 HSSP Read */
+        DMA_Ser3UARTWr = DDAR_Ser3UARTWr,  /* Ser. port 3 UART Write */
+        DMA_Ser3UARTRd = DDAR_Ser3UARTRd,  /* Ser. port 3 UART Read */
+        DMA_Ser4MCP0Wr = DDAR_Ser4MCP0Wr,  /* Ser. port 4 MCP 0 Write (audio) */
+        DMA_Ser4MCP0Rd = DDAR_Ser4MCP0Rd,  /* Ser. port 4 MCP 0 Read (audio) */
+        DMA_Ser4MCP1Wr = DDAR_Ser4MCP1Wr,  /* Ser. port 4 MCP 1 Write */
+        DMA_Ser4MCP1Rd = DDAR_Ser4MCP1Rd,  /* Ser. port 4 MCP 1 Read */
+        DMA_Ser4SSPWr  = DDAR_Ser4SSPWr,   /* Ser. port 4 SSP Write (16 bits) */
+        DMA_Ser4SSPRd  = DDAR_Ser4SSPRd    /* Ser. port 4 SSP Read (16 bits) */
+} dma_device_t;
+
+typedef struct {
+        volatile u_long DDAR;
+        volatile u_long SetDCSR;
+        volatile u_long ClrDCSR;
+        volatile u_long RdDCSR;
+        volatile dma_addr_t DBSA;
+        volatile u_long DBTA;
+        volatile dma_addr_t DBSB;
+        volatile u_long DBTB;
+} dma_regs_t;
+
+typedef void (*dma_callback_t)(void *data);
+
+/*
+ * DMA function prototypes
+ */
+
+extern int sa1100_request_dma( dma_device_t device, const char *device_id,
+                               dma_callback_t callback, void *data,
+                               dma_regs_t **regs );
+extern void sa1100_free_dma( dma_regs_t *regs );
+extern int sa1100_start_dma( dma_regs_t *regs, dma_addr_t dma_ptr, u_int size );
+extern dma_addr_t sa1100_get_dma_pos(dma_regs_t *regs);
+extern void sa1100_reset_dma(dma_regs_t *regs);
+
+/**
+ *      sa1100_stop_dma - stop DMA in progress
+ *      @regs: identifier for the channel to use
+ *
+ *      This stops DMA without clearing buffer pointers. Unlike
+ *      sa1100_clear_dma() this allows subsequent use of sa1100_resume_dma()
+ *      or sa1100_get_dma_pos().
+ *
+ *      The @regs identifier is provided by a successful call to
+ *      sa1100_request_dma().
+ **/
+
+#define sa1100_stop_dma(regs)   ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN)
+
+/**
+ *      sa1100_resume_dma - resume DMA on a stopped channel
+ *      @regs: identifier for the channel to use
+ *
+ *      This resumes DMA on a channel previously stopped with
+ *      sa1100_stop_dma().
+ *
+ *      The @regs identifier is provided by a successful call to
+ *      sa1100_request_dma().
+ **/
+
+#define sa1100_resume_dma(regs) ((regs)->SetDCSR = DCSR_IE|DCSR_RUN)
+
+/**
+ *      sa1100_clear_dma - clear DMA pointers
+ *      @regs: identifier for the channel to use
+ *
+ *      This clear any DMA state so the DMA engine is ready to restart
+ *      with new buffers through sa1100_start_dma(). Any buffers in flight
+ *      are discarded.
+ *
+ *      The @regs identifier is provided by a successful call to
+ *      sa1100_request_dma().
+ **/
+
+#define sa1100_clear_dma(regs)  ((regs)->ClrDCSR = DCSR_IE|DCSR_RUN|DCSR_STRTA|DCSR_STRTB)
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-sa1100/entry-macro.S b/include/asm-arm/arch-sa1100/entry-macro.S
new file mode 100644
index 000000000000..51fb50ce1169
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/entry-macro.S
@@ -0,0 +1,41 @@
+/*
+ * include/asm-arm/arch-sa1100/entry-macro.S
+ *
+ * Low-level IRQ helper macros for SA1100-based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     r4, #0xfa000000                 @ ICIP = 0xfa050000
+                add     r4, r4, #0x00050000
+                ldr     \irqstat, [r4]                  @ get irqs
+                ldr     \irqnr, [r4, #4]                @ ICMR = 0xfa050004
+                ands    \irqstat, \irqstat, \irqnr
+                mov     \irqnr, #0
+                beq     1001f
+                tst     \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tsteq   \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tsteq   \irqstat, #0xff
+                moveq   \irqstat, \irqstat, lsr #8
+                addeq   \irqnr, \irqnr, #8
+                tst     \irqstat, #0x0f
+                moveq   \irqstat, \irqstat, lsr #4
+                addeq   \irqnr, \irqnr, #4
+                tst     \irqstat, #0x03
+                moveq   \irqstat, \irqstat, lsr #2
+                addeq   \irqnr, \irqnr, #2
+                tst     \irqstat, #0x01
+                addeqs  \irqnr, \irqnr, #1
+1001:
+                .endm
+
diff --git a/include/asm-arm/arch-sa1100/h3600.h b/include/asm-arm/arch-sa1100/h3600.h
new file mode 100644
index 000000000000..1b6355971574
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/h3600.h
@@ -0,0 +1,164 @@
+/*
+ *
+ * Definitions for H3600 Handheld Computer
+ *
+ * Copyright 2000 Compaq Computer Corporation.
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Author: Jamey Hicks.
+ *
+ * History:
+ *
+ * 2001-10-??   Andrew Christian   Added support for iPAQ H3800
+ *
+ */
+
+#ifndef _INCLUDE_H3600_H_
+#define _INCLUDE_H3600_H_
+
+/* generalized support for H3xxx series Compaq Pocket PC's */
+#define machine_is_h3xxx() (machine_is_h3100() || machine_is_h3600() || machine_is_h3800())
+
+/* Physical memory regions corresponding to chip selects */
+#define H3600_EGPIO_PHYS     (SA1100_CS5_PHYS + 0x01000000)
+#define H3600_BANK_2_PHYS    SA1100_CS2_PHYS
+#define H3600_BANK_4_PHYS    SA1100_CS4_PHYS
+
+/* Virtual memory regions corresponding to chip selects 2 & 4 (used on sleeves) */
+#define H3600_EGPIO_VIRT     0xf0000000
+#define H3600_BANK_2_VIRT    0xf1000000
+#define H3600_BANK_4_VIRT    0xf3800000
+
+/*
+   Machine-independent GPIO definitions
+   --- these are common across all current iPAQ platforms
+*/
+
+#define GPIO_H3600_NPOWER_BUTTON        GPIO_GPIO (0)   /* Also known as the "off button"  */
+
+#define GPIO_H3600_PCMCIA_CD1           GPIO_GPIO (10)
+#define GPIO_H3600_PCMCIA_IRQ1          GPIO_GPIO (11)
+
+/* UDA1341 L3 Interface */
+#define GPIO_H3600_L3_DATA              GPIO_GPIO (14)
+#define GPIO_H3600_L3_MODE              GPIO_GPIO (15)
+#define GPIO_H3600_L3_CLOCK             GPIO_GPIO (16)
+
+#define GPIO_H3600_PCMCIA_CD0           GPIO_GPIO (17)
+#define GPIO_H3600_SYS_CLK              GPIO_GPIO (19)
+#define GPIO_H3600_PCMCIA_IRQ0          GPIO_GPIO (21)
+
+#define GPIO_H3600_COM_DCD              GPIO_GPIO (23)
+#define GPIO_H3600_OPT_IRQ              GPIO_GPIO (24)
+#define GPIO_H3600_COM_CTS              GPIO_GPIO (25)
+#define GPIO_H3600_COM_RTS              GPIO_GPIO (26)
+
+#define IRQ_GPIO_H3600_NPOWER_BUTTON    IRQ_GPIO0
+#define IRQ_GPIO_H3600_PCMCIA_CD1       IRQ_GPIO10
+#define IRQ_GPIO_H3600_PCMCIA_IRQ1      IRQ_GPIO11
+#define IRQ_GPIO_H3600_PCMCIA_CD0       IRQ_GPIO17
+#define IRQ_GPIO_H3600_PCMCIA_IRQ0      IRQ_GPIO21
+#define IRQ_GPIO_H3600_COM_DCD          IRQ_GPIO23
+#define IRQ_GPIO_H3600_OPT_IRQ          IRQ_GPIO24
+#define IRQ_GPIO_H3600_COM_CTS          IRQ_GPIO25
+
+
+#ifndef __ASSEMBLY__
+
+enum ipaq_egpio_type {
+        IPAQ_EGPIO_LCD_POWER,     /* Power to the LCD panel */
+        IPAQ_EGPIO_CODEC_NRESET,  /* Clear to reset the audio codec (remember to return high) */
+        IPAQ_EGPIO_AUDIO_ON,      /* Audio power */
+        IPAQ_EGPIO_QMUTE,         /* Audio muting */
+        IPAQ_EGPIO_OPT_NVRAM_ON,  /* Non-volatile RAM on extension sleeves (SPI interface) */
+        IPAQ_EGPIO_OPT_ON,        /* Power to extension sleeves */
+        IPAQ_EGPIO_CARD_RESET,    /* Reset PCMCIA cards on extension sleeve (???) */
+        IPAQ_EGPIO_OPT_RESET,     /* Reset option pack (???) */
+        IPAQ_EGPIO_IR_ON,         /* IR sensor/emitter power */
+        IPAQ_EGPIO_IR_FSEL,       /* IR speed selection 1->fast, 0->slow */
+        IPAQ_EGPIO_RS232_ON,      /* Maxim RS232 chip power */
+        IPAQ_EGPIO_VPP_ON,        /* Turn on power to flash programming */
+        IPAQ_EGPIO_LCD_ENABLE,    /* Enable/disable LCD controller */
+};
+
+struct ipaq_model_ops {
+        const char     *generic_name;
+        void          (*control)(enum ipaq_egpio_type, int);
+        unsigned long (*read)(void);
+        void          (*blank_callback)(int blank);
+        int           (*pm_callback)(int req);      /* Primary model callback */
+        int           (*pm_callback_aux)(int req);  /* Secondary callback (used by HAL modules) */
+};
+
+extern struct ipaq_model_ops ipaq_model_ops;
+
+static __inline__ const char * h3600_generic_name(void)
+{
+        return ipaq_model_ops.generic_name;
+}
+
+static __inline__ void assign_h3600_egpio(enum ipaq_egpio_type x, int level)
+{
+        if (ipaq_model_ops.control)
+                ipaq_model_ops.control(x,level);
+}
+
+static __inline__ void clr_h3600_egpio(enum ipaq_egpio_type x)
+{
+        if (ipaq_model_ops.control)
+                ipaq_model_ops.control(x,0);
+}
+
+static __inline__ void set_h3600_egpio(enum ipaq_egpio_type x)
+{
+        if (ipaq_model_ops.control)
+                ipaq_model_ops.control(x,1);
+}
+
+static __inline__ unsigned long read_h3600_egpio(void)
+{
+        if (ipaq_model_ops.read)
+                return ipaq_model_ops.read();
+        return 0;
+}
+
+static __inline__ int  h3600_register_blank_callback(void (*f)(int))
+{
+        ipaq_model_ops.blank_callback = f;
+        return 0;
+}
+
+static __inline__ void h3600_unregister_blank_callback(void (*f)(int))
+{
+        ipaq_model_ops.blank_callback = NULL;
+}
+
+
+static __inline__ int  h3600_register_pm_callback(int (*f)(int))
+{
+        ipaq_model_ops.pm_callback_aux = f;
+        return 0;
+}
+
+static __inline__ void h3600_unregister_pm_callback(int (*f)(int))
+{
+        ipaq_model_ops.pm_callback_aux = NULL;
+}
+
+static __inline__ int h3600_power_management(int req)
+{
+        if (ipaq_model_ops.pm_callback)
+                return ipaq_model_ops.pm_callback(req);
+        return 0;
+}
+
+#endif /* ASSEMBLY */
+
+#endif /* _INCLUDE_H3600_H_ */
diff --git a/include/asm-arm/arch-sa1100/h3600_gpio.h b/include/asm-arm/arch-sa1100/h3600_gpio.h
new file mode 100644
index 000000000000..62b0b7879685
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/h3600_gpio.h
@@ -0,0 +1,540 @@
+/*
+ *
+ * Definitions for H3600 Handheld Computer
+ *
+ * Copyright 2000 Compaq Computer Corporation.
+ *
+ * Use consistent with the GNU GPL is permitted,
+ * provided that this copyright notice is
+ * preserved in its entirety in all copies and derived works.
+ *
+ * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+ * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+ * FITNESS FOR ANY PARTICULAR PURPOSE.
+ *
+ * Author: Jamey Hicks.
+ *
+ * History:
+ *
+ * 2001-10-??   Andrew Christian   Added support for iPAQ H3800
+ *
+ */
+
+#ifndef _INCLUDE_H3600_GPIO_H_
+#define _INCLUDE_H3600_GPIO_H_
+
+/*
+ * GPIO lines that are common across ALL iPAQ models are in "h3600.h"
+ * This file contains machine-specific definitions
+ */
+
+#define GPIO_H3600_SUSPEND              GPIO_GPIO (0)
+/* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */
+#define GPIO_H3100_BT_ON                GPIO_GPIO (2)
+#define GPIO_H3100_GPIO3                GPIO_GPIO (3)
+#define GPIO_H3100_QMUTE                GPIO_GPIO (4)
+#define GPIO_H3100_LCD_3V_ON            GPIO_GPIO (5)
+#define GPIO_H3100_AUD_ON               GPIO_GPIO (6)
+#define GPIO_H3100_AUD_PWR_ON           GPIO_GPIO (7)
+#define GPIO_H3100_IR_ON                GPIO_GPIO (8)
+#define GPIO_H3100_IR_FSEL              GPIO_GPIO (9)
+
+/* for H3600, audio sample rate clock generator */
+#define GPIO_H3600_CLK_SET0             GPIO_GPIO (12)
+#define GPIO_H3600_CLK_SET1             GPIO_GPIO (13)
+
+#define GPIO_H3600_ACTION_BUTTON        GPIO_GPIO (18)
+#define GPIO_H3600_SOFT_RESET           GPIO_GPIO (20)   /* Also known as BATT_FAULT */
+#define GPIO_H3600_OPT_LOCK             GPIO_GPIO (22)
+#define GPIO_H3600_OPT_DET              GPIO_GPIO (27)
+
+/* H3800 specific pins */
+#define GPIO_H3800_AC_IN                GPIO_GPIO (12)
+#define GPIO_H3800_COM_DSR              GPIO_GPIO (13)
+#define GPIO_H3800_MMC_INT              GPIO_GPIO (18)
+#define GPIO_H3800_NOPT_IND             GPIO_GPIO (20)   /* Almost exactly the same as GPIO_H3600_OPT_DET */
+#define GPIO_H3800_OPT_BAT_FAULT        GPIO_GPIO (22)
+#define GPIO_H3800_CLK_OUT              GPIO_GPIO (27)
+
+/****************************************************/
+
+#define IRQ_GPIO_H3600_ACTION_BUTTON    IRQ_GPIO18
+#define IRQ_GPIO_H3600_OPT_DET          IRQ_GPIO27
+
+#define IRQ_GPIO_H3800_MMC_INT          IRQ_GPIO18
+#define IRQ_GPIO_H3800_NOPT_IND         IRQ_GPIO20 /* almost same as OPT_DET */
+
+/* H3100 / 3600 EGPIO pins */
+#define EGPIO_H3600_VPP_ON              (1 << 0)
+#define EGPIO_H3600_CARD_RESET          (1 << 1)   /* reset the attached pcmcia/compactflash card.  active high. */
+#define EGPIO_H3600_OPT_RESET           (1 << 2)   /* reset the attached option pack.  active high. */
+#define EGPIO_H3600_CODEC_NRESET        (1 << 3)   /* reset the onboard UDA1341.  active low. */
+#define EGPIO_H3600_OPT_NVRAM_ON        (1 << 4)   /* apply power to optionpack nvram, active high. */
+#define EGPIO_H3600_OPT_ON              (1 << 5)   /* full power to option pack.  active high. */
+#define EGPIO_H3600_LCD_ON              (1 << 6)   /* enable 3.3V to LCD.  active high. */
+#define EGPIO_H3600_RS232_ON            (1 << 7)   /* UART3 transceiver force on.  Active high. */
+
+/* H3600 only EGPIO pins */
+#define EGPIO_H3600_LCD_PCI             (1 << 8)   /* LCD control IC enable.  active high. */
+#define EGPIO_H3600_IR_ON               (1 << 9)   /* apply power to IR module.  active high. */
+#define EGPIO_H3600_AUD_AMP_ON          (1 << 10)  /* apply power to audio power amp.  active high. */
+#define EGPIO_H3600_AUD_PWR_ON          (1 << 11)  /* apply power to reset of audio circuit.  active high. */
+#define EGPIO_H3600_QMUTE               (1 << 12)  /* mute control for onboard UDA1341.  active high. */
+#define EGPIO_H3600_IR_FSEL             (1 << 13)  /* IR speed select: 1->fast, 0->slow */
+#define EGPIO_H3600_LCD_5V_ON           (1 << 14)  /* enable 5V to LCD. active high. */
+#define EGPIO_H3600_LVDD_ON             (1 << 15)  /* enable 9V and -6.5V to LCD. */
+
+/********************* H3800, ASIC #2 ********************/
+
+#define _H3800_ASIC2_Base            (H3600_EGPIO_VIRT)
+#define H3800_ASIC2_OFFSET(s,x,y)    \
+    (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
+#define H3800_ASIC2_NOFFSET(s,x,n,y) \
+    (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
+
+#define _H3800_ASIC2_GPIO_Base                 0x0000
+#define _H3800_ASIC2_GPIO_Direction            0x0000    /* R/W, 16 bits 1:input, 0:output */
+#define _H3800_ASIC2_GPIO_InterruptType        0x0004    /* R/W, 12 bits 1:edge, 0:level          */
+#define _H3800_ASIC2_GPIO_InterruptEdgeType    0x0008    /* R/W, 12 bits 1:rising, 0:falling */
+#define _H3800_ASIC2_GPIO_InterruptLevelType   0x000C    /* R/W, 12 bits 1:high, 0:low  */
+#define _H3800_ASIC2_GPIO_InterruptClear       0x0010    /* W,   12 bits */
+#define _H3800_ASIC2_GPIO_InterruptFlag        0x0010    /* R,   12 bits - reads int status */
+#define _H3800_ASIC2_GPIO_Data                 0x0014    /* R/W, 16 bits */
+#define _H3800_ASIC2_GPIO_BattFaultOut         0x0018    /* R/W, 16 bit - sets level on batt fault */
+#define _H3800_ASIC2_GPIO_InterruptEnable      0x001c    /* R/W, 12 bits 1:enable interrupt */
+#define _H3800_ASIC2_GPIO_Alternate            0x003c    /* R/W, 12+1 bits - set alternate functions */
+
+#define H3800_ASIC2_GPIO_Direction          H3800_ASIC2_OFFSET( u16, GPIO, Direction )
+#define H3800_ASIC2_GPIO_InterruptType      H3800_ASIC2_OFFSET( u16, GPIO, InterruptType )
+#define H3800_ASIC2_GPIO_InterruptEdgeType  H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType )
+#define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType )
+#define H3800_ASIC2_GPIO_InterruptClear     H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear )
+#define H3800_ASIC2_GPIO_InterruptFlag      H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag )
+#define H3800_ASIC2_GPIO_Data               H3800_ASIC2_OFFSET( u16, GPIO, Data )
+#define H3800_ASIC2_GPIO_BattFaultOut       H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut )
+#define H3800_ASIC2_GPIO_InterruptEnable    H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable )
+#define H3800_ASIC2_GPIO_Alternate          H3800_ASIC2_OFFSET( u16, GPIO, Alternate )
+
+#define GPIO_H3800_ASIC2_IN_Y1_N          (1 << 0)   /* Output: Touchscreen Y1 */
+#define GPIO_H3800_ASIC2_IN_X0            (1 << 1)   /* Output: Touchscreen X0 */
+#define GPIO_H3800_ASIC2_IN_Y0            (1 << 2)   /* Output: Touchscreen Y0 */
+#define GPIO_H3800_ASIC2_IN_X1_N          (1 << 3)   /* Output: Touchscreen X1 */
+#define GPIO_H3800_ASIC2_BT_RST           (1 << 4)   /* Output: Bluetooth reset */
+#define GPIO_H3800_ASIC2_PEN_IRQ          (1 << 5)   /* Input : Pen down        */
+#define GPIO_H3800_ASIC2_SD_DETECT        (1 << 6)   /* Input : SD detect */
+#define GPIO_H3800_ASIC2_EAR_IN_N         (1 << 7)   /* Input : Audio jack plug inserted */
+#define GPIO_H3800_ASIC2_OPT_PCM_RESET    (1 << 8)   /* Output: */
+#define GPIO_H3800_ASIC2_OPT_RESET        (1 << 9)   /* Output: */
+#define GPIO_H3800_ASIC2_USB_DETECT_N     (1 << 10)  /* Input : */
+#define GPIO_H3800_ASIC2_SD_CON_SLT       (1 << 11)  /* Input : */
+
+#define _H3800_ASIC2_KPIO_Base                 0x0200
+#define _H3800_ASIC2_KPIO_Direction            0x0000    /* R/W, 12 bits 1:input, 0:output */
+#define _H3800_ASIC2_KPIO_InterruptType        0x0004    /* R/W, 12 bits 1:edge, 0:level          */
+#define _H3800_ASIC2_KPIO_InterruptEdgeType    0x0008    /* R/W, 12 bits 1:rising, 0:falling */
+#define _H3800_ASIC2_KPIO_InterruptLevelType   0x000C    /* R/W, 12 bits 1:high, 0:low  */
+#define _H3800_ASIC2_KPIO_InterruptClear       0x0010    /* W,   20 bits - 8 special */
+#define _H3800_ASIC2_KPIO_InterruptFlag        0x0010    /* R,   20 bits - 8 special - reads int status */
+#define _H3800_ASIC2_KPIO_Data                 0x0014    /* R/W, 16 bits */
+#define _H3800_ASIC2_KPIO_BattFaultOut         0x0018    /* R/W, 16 bit - sets level on batt fault */
+#define _H3800_ASIC2_KPIO_InterruptEnable      0x001c    /* R/W, 20 bits - 8 special */
+#define _H3800_ASIC2_KPIO_Alternate            0x003c    /* R/W, 6 bits */
+
+#define H3800_ASIC2_KPIO_Direction          H3800_ASIC2_OFFSET( u16, KPIO, Direction )
+#define H3800_ASIC2_KPIO_InterruptType      H3800_ASIC2_OFFSET( u16, KPIO, InterruptType )
+#define H3800_ASIC2_KPIO_InterruptEdgeType  H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType )
+#define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType )
+#define H3800_ASIC2_KPIO_InterruptClear     H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear )
+#define H3800_ASIC2_KPIO_InterruptFlag      H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag )
+#define H3800_ASIC2_KPIO_Data               H3800_ASIC2_OFFSET( u16, KPIO, Data )
+#define H3800_ASIC2_KPIO_BattFaultOut       H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut )
+#define H3800_ASIC2_KPIO_InterruptEnable    H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable )
+#define H3800_ASIC2_KPIO_Alternate          H3800_ASIC2_OFFSET( u16, KPIO, Alternate )
+
+#define H3800_ASIC2_KPIO_SPI_INT        ( 1 << 16 )
+#define H3800_ASIC2_KPIO_OWM_INT        ( 1 << 17 )
+#define H3800_ASIC2_KPIO_ADC_INT        ( 1 << 18 )
+#define H3800_ASIC2_KPIO_UART_0_INT     ( 1 << 19 )
+#define H3800_ASIC2_KPIO_UART_1_INT     ( 1 << 20 )
+#define H3800_ASIC2_KPIO_TIMER_0_INT    ( 1 << 21 )
+#define H3800_ASIC2_KPIO_TIMER_1_INT    ( 1 << 22 )
+#define H3800_ASIC2_KPIO_TIMER_2_INT    ( 1 << 23 )
+
+#define KPIO_H3800_ASIC2_RECORD_BTN_N     (1 << 0)   /* Record button */
+#define KPIO_H3800_ASIC2_KEY_5W1_N        (1 << 1)   /* Keypad */
+#define KPIO_H3800_ASIC2_KEY_5W2_N        (1 << 2)   /* */
+#define KPIO_H3800_ASIC2_KEY_5W3_N        (1 << 3)   /* */
+#define KPIO_H3800_ASIC2_KEY_5W4_N        (1 << 4)   /* */
+#define KPIO_H3800_ASIC2_KEY_5W5_N        (1 << 5)   /* */
+#define KPIO_H3800_ASIC2_KEY_LEFT_N       (1 << 6)   /* */
+#define KPIO_H3800_ASIC2_KEY_RIGHT_N      (1 << 7)   /* */
+#define KPIO_H3800_ASIC2_KEY_AP1_N        (1 << 8)   /* Old "Calendar" */
+#define KPIO_H3800_ASIC2_KEY_AP2_N        (1 << 9)   /* Old "Schedule" */
+#define KPIO_H3800_ASIC2_KEY_AP3_N        (1 << 10)  /* Old "Q"        */
+#define KPIO_H3800_ASIC2_KEY_AP4_N        (1 << 11)  /* Old "Undo"     */
+
+/* Alternate KPIO functions (set by default) */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W1_N        (1 << 1)   /* Action key */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W2_N        (1 << 2)   /* J1 of keypad input */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W3_N        (1 << 3)   /* J2 of keypad input */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W4_N        (1 << 4)   /* J3 of keypad input */
+#define KPIO_ALT_H3800_ASIC2_KEY_5W5_N        (1 << 5)   /* J4 of keypad input */
+
+#define _H3800_ASIC2_SPI_Base                  0x0400
+#define _H3800_ASIC2_SPI_Control               0x0000    /* R/W 8 bits */
+#define _H3800_ASIC2_SPI_Data                  0x0004    /* R/W 8 bits */
+#define _H3800_ASIC2_SPI_ChipSelectDisabled    0x0008    /* W   8 bits */
+
+#define H3800_ASIC2_SPI_Control             H3800_ASIC2_OFFSET( u8, SPI, Control )
+#define H3800_ASIC2_SPI_Data                H3800_ASIC2_OFFSET( u8, SPI, Data )
+#define H3800_ASIC2_SPI_ChipSelectDisabled  H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled )
+
+#define _H3800_ASIC2_PWM_0_Base                0x0600
+#define _H3800_ASIC2_PWM_1_Base                0x0700
+#define _H3800_ASIC2_PWM_TimeBase              0x0000    /* R/W 6 bits */
+#define _H3800_ASIC2_PWM_PeriodTime            0x0004    /* R/W 12 bits */
+#define _H3800_ASIC2_PWM_DutyTime              0x0008    /* R/W 12 bits */
+
+#define H3800_ASIC2_PWM_0_TimeBase          H3800_ASIC2_NOFFSET(  u8, PWM, 0, TimeBase )
+#define H3800_ASIC2_PWM_0_PeriodTime        H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime )
+#define H3800_ASIC2_PWM_0_DutyTime          H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime )
+
+#define H3800_ASIC2_PWM_1_TimeBase          H3800_ASIC2_NOFFSET(  u8, PWM, 1, TimeBase )
+#define H3800_ASIC2_PWM_1_PeriodTime        H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime )
+#define H3800_ASIC2_PWM_1_DutyTime          H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime )
+
+#define H3800_ASIC2_PWM_TIMEBASE_MASK             0xf    /* Low 4 bits sets time base, max = 8 */
+#define H3800_ASIC2_PWM_TIMEBASE_ENABLE    ( 1 << 4 )    /* Enable clock */
+#define H3800_ASIC2_PWM_TIMEBASE_CLEAR     ( 1 << 5 )    /* Clear the PWM */
+
+#define _H3800_ASIC2_LED_0_Base                0x0800
+#define _H3800_ASIC2_LED_1_Base                0x0880
+#define _H3800_ASIC2_LED_2_Base                0x0900
+#define _H3800_ASIC2_LED_TimeBase              0x0000    /* R/W  7 bits */
+#define _H3800_ASIC2_LED_PeriodTime            0x0004    /* R/W 12 bits */
+#define _H3800_ASIC2_LED_DutyTime              0x0008    /* R/W 12 bits */
+#define _H3800_ASIC2_LED_AutoStopCount         0x000c    /* R/W 16 bits */
+
+#define H3800_ASIC2_LED_0_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 0, TimeBase )
+#define H3800_ASIC2_LED_0_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime )
+#define H3800_ASIC2_LED_0_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime )
+#define H3800_ASIC2_LED_0_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock )
+
+#define H3800_ASIC2_LED_1_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 1, TimeBase )
+#define H3800_ASIC2_LED_1_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime )
+#define H3800_ASIC2_LED_1_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime )
+#define H3800_ASIC2_LED_1_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock )
+
+#define H3800_ASIC2_LED_2_TimeBase          H3800_ASIC2_NOFFSET(  u8, LED, 2, TimeBase )
+#define H3800_ASIC2_LED_2_PeriodTime        H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime )
+#define H3800_ASIC2_LED_2_DutyTime          H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime )
+#define H3800_ASIC2_LED_2_AutoStopClock     H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock )
+
+#define H3800_ASIC2_LED_TIMEBASE_MASK            0x0f    /* Low 4 bits sets time base, max = 13 */
+#define H3800_ASIC2_LED_TIMEBASE_BLINK     ( 1 << 4 )    /* Enable blinking */
+#define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP  ( 1 << 5 )
+#define H3800_ASIC2_LED_TIMEBASE_ALWAYS    ( 1 << 6 )    /* Enable blink always */
+
+#define _H3800_ASIC2_UART_0_Base               0x0A00
+#define _H3800_ASIC2_UART_1_Base               0x0C00
+#define _H3800_ASIC2_UART_Receive              0x0000    /* R    8 bits */
+#define _H3800_ASIC2_UART_Transmit             0x0000    /*   W  8 bits */
+#define _H3800_ASIC2_UART_IntEnable            0x0004    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_IntVerify            0x0008    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_FIFOControl          0x000c    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_LineControl          0x0010    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_ModemStatus          0x0014    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_LineStatus           0x0018    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_ScratchPad           0x001c    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_DivisorLatchL        0x0020    /* R/W  8 bits */
+#define _H3800_ASIC2_UART_DivisorLatchH        0x0024    /* R/W  8 bits */
+
+#define H3800_ASIC2_UART_0_Receive          H3800_ASIC2_NOFFSET(  u8, UART, 0, Receive )
+#define H3800_ASIC2_UART_0_Transmit         H3800_ASIC2_NOFFSET(  u8, UART, 0, Transmit )
+#define H3800_ASIC2_UART_0_IntEnable        H3800_ASIC2_NOFFSET(  u8, UART, 0, IntEnable )
+#define H3800_ASIC2_UART_0_IntVerify        H3800_ASIC2_NOFFSET(  u8, UART, 0, IntVerify )
+#define H3800_ASIC2_UART_0_FIFOControl      H3800_ASIC2_NOFFSET(  u8, UART, 0, FIFOControl )
+#define H3800_ASIC2_UART_0_LineControl      H3800_ASIC2_NOFFSET(  u8, UART, 0, LineControl )
+#define H3800_ASIC2_UART_0_ModemStatus      H3800_ASIC2_NOFFSET(  u8, UART, 0, ModemStatus )
+#define H3800_ASIC2_UART_0_LineStatus       H3800_ASIC2_NOFFSET(  u8, UART, 0, LineStatus )
+#define H3800_ASIC2_UART_0_ScratchPad       H3800_ASIC2_NOFFSET(  u8, UART, 0, ScratchPad )
+#define H3800_ASIC2_UART_0_DivisorLatchL    H3800_ASIC2_NOFFSET(  u8, UART, 0, DivisorLatchL )
+#define H3800_ASIC2_UART_0_DivisorLatchH    H3800_ASIC2_NOFFSET(  u8, UART, 0, DivisorLatchH )
+
+#define H3800_ASIC2_UART_1_Receive          H3800_ASIC2_NOFFSET(  u8, UART, 1, Receive )
+#define H3800_ASIC2_UART_1_Transmit         H3800_ASIC2_NOFFSET(  u8, UART, 1, Transmit )
+#define H3800_ASIC2_UART_1_IntEnable        H3800_ASIC2_NOFFSET(  u8, UART, 1, IntEnable )
+#define H3800_ASIC2_UART_1_IntVerify        H3800_ASIC2_NOFFSET(  u8, UART, 1, IntVerify )
+#define H3800_ASIC2_UART_1_FIFOControl      H3800_ASIC2_NOFFSET(  u8, UART, 1, FIFOControl )
+#define H3800_ASIC2_UART_1_LineControl      H3800_ASIC2_NOFFSET(  u8, UART, 1, LineControl )
+#define H3800_ASIC2_UART_1_ModemStatus      H3800_ASIC2_NOFFSET(  u8, UART, 1, ModemStatus )
+#define H3800_ASIC2_UART_1_LineStatus       H3800_ASIC2_NOFFSET(  u8, UART, 1, LineStatus )
+#define H3800_ASIC2_UART_1_ScratchPad       H3800_ASIC2_NOFFSET(  u8, UART, 1, ScratchPad )
+#define H3800_ASIC2_UART_1_DivisorLatchL    H3800_ASIC2_NOFFSET(  u8, UART, 1, DivisorLatchL )
+#define H3800_ASIC2_UART_1_DivisorLatchH    H3800_ASIC2_NOFFSET(  u8, UART, 1, DivisorLatchH )
+
+#define _H3800_ASIC2_TIMER_Base                0x0E00
+#define _H3800_ASIC2_TIMER_Command             0x0000    /* R/W  8 bits */
+
+#define H3800_ASIC2_TIMER_Command           H3800_ASIC2_OFFSET( u8, Timer, Command )
+
+#define H3800_ASIC2_TIMER_GAT_0            ( 1 << 0 )    /* Gate enable, counter 0 */
+#define H3800_ASIC2_TIMER_GAT_1            ( 1 << 1 )    /* Gate enable, counter 1 */
+#define H3800_ASIC2_TIMER_GAT_2            ( 1 << 2 )    /* Gate enable, counter 2 */
+#define H3800_ASIC2_TIMER_CLK_0            ( 1 << 3 )    /* Clock enable, counter 0 */
+#define H3800_ASIC2_TIMER_CLK_1            ( 1 << 4 )    /* Clock enable, counter 1 */
+#define H3800_ASIC2_TIMER_CLK_2            ( 1 << 5 )    /* Clock enable, counter 2 */
+#define H3800_ASIC2_TIMER_MODE_0           ( 1 << 6 )    /* Mode 0 enable, counter 0 */
+#define H3800_ASIC2_TIMER_MODE_1           ( 1 << 7 )    /* Mode 0 enable, counter 1 */
+
+#define _H3800_ASIC2_CLOCK_Base                0x1000
+#define _H3800_ASIC2_CLOCK_Enable              0x0000    /* R/W  18 bits */
+
+#define H3800_ASIC2_CLOCK_Enable            H3800_ASIC2_OFFSET( u32, CLOCK, Enable )
+
+#define H3800_ASIC2_CLOCK_AUDIO_1              0x0001    /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */
+#define H3800_ASIC2_CLOCK_AUDIO_2              0x0002    /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */
+#define H3800_ASIC2_CLOCK_AUDIO_3              0x0004    /* Enable 5.6 MHz clock for 11 kHZ sample rate */
+#define H3800_ASIC2_CLOCK_AUDIO_4              0x0008    /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */
+#define H3800_ASIC2_CLOCK_ADC              ( 1 << 4 )    /* 1.024 MHz clock to ADC */
+#define H3800_ASIC2_CLOCK_SPI              ( 1 << 5 )    /* 4.096 MHz clock to SPI */
+#define H3800_ASIC2_CLOCK_OWM              ( 1 << 6 )    /* 4.096 MHz clock to OWM */
+#define H3800_ASIC2_CLOCK_PWM              ( 1 << 7 )    /* 2.048 MHz clock to PWM */
+#define H3800_ASIC2_CLOCK_UART_1           ( 1 << 8 )    /* 24.576 MHz clock to UART1 (turn off bit 16) */
+#define H3800_ASIC2_CLOCK_UART_0           ( 1 << 9 )    /* 24.576 MHz clock to UART0 (turn off bit 17) */
+#define H3800_ASIC2_CLOCK_SD_1             ( 1 << 10 )   /* 16.934 MHz to SD */
+#define H3800_ASIC2_CLOCK_SD_2             ( 2 << 10 )   /* 24.576 MHz to SD */
+#define H3800_ASIC2_CLOCK_SD_3             ( 3 << 10 )   /* 33.869 MHz to SD */
+#define H3800_ASIC2_CLOCK_SD_4             ( 4 << 10 )   /* 49.152 MHz to SD */
+#define H3800_ASIC2_CLOCK_EX0              ( 1 << 13 )   /* Enable 32.768 kHz crystal */
+#define H3800_ASIC2_CLOCK_EX1              ( 1 << 14 )   /* Enable 24.576 MHz crystal */
+#define H3800_ASIC2_CLOCK_EX2              ( 1 << 15 )   /* Enable 33.869 MHz crystal */
+#define H3800_ASIC2_CLOCK_SLOW_UART_1      ( 1 << 16 )   /* Enable 3.686 MHz to UART1 (turn off bit 8) */
+#define H3800_ASIC2_CLOCK_SLOW_UART_0      ( 1 << 17 )   /* Enable 3.686 MHz to UART0 (turn off bit 9) */
+
+#define _H3800_ASIC2_ADC_Base                  0x1200
+#define _H3800_ASIC2_ADC_Multiplexer           0x0000    /* R/W 4 bits - low 3 bits set channel */
+#define _H3800_ASIC2_ADC_ControlStatus         0x0004    /* R/W 8 bits */
+#define _H3800_ASIC2_ADC_Data                  0x0008    /* R   10 bits */
+
+#define H3800_ASIC2_ADC_Multiplexer       H3800_ASIC2_OFFSET(  u8, ADC, Multiplexer )
+#define H3800_ASIC2_ADC_ControlStatus     H3800_ASIC2_OFFSET(  u8, ADC, ControlStatus )
+#define H3800_ASIC2_ADC_Data              H3800_ASIC2_OFFSET( u16, ADC, Data )
+
+#define H3600_ASIC2_ADC_MUX_CHANNEL_MASK         0x07    /* Low 3 bits sets channel.  max = 4 */
+#define H3600_ASIC2_ADC_MUX_CLKEN          ( 1 << 3 )    /* Enable clock */
+
+#define H3600_ASIC2_ADC_CSR_ADPS_MASK            0x0f    /* Low 4 bits sets prescale, max = 8 */
+#define H3600_ASIC2_ADC_CSR_FREE_RUN       ( 1 << 4 )
+#define H3600_ASIC2_ADC_CSR_INT_ENABLE     ( 1 << 5 )
+#define H3600_ASIC2_ADC_CSR_START          ( 1 << 6 )    /* Set to start conversion.  Goes to 0 when done */
+#define H3600_ASIC2_ADC_CSR_ENABLE         ( 1 << 7 )    /* 1:power up ADC, 0:power down */
+
+
+#define _H3800_ASIC2_INTR_Base                 0x1600
+#define _H3800_ASIC2_INTR_MaskAndFlag          0x0000    /* R/(W) 8bits */
+#define _H3800_ASIC2_INTR_ClockPrescale        0x0004    /* R/(W) 5bits */
+#define _H3800_ASIC2_INTR_TimerSet             0x0008    /* R/(W) 8bits */
+
+#define H3800_ASIC2_INTR_MaskAndFlag      H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag )
+#define H3800_ASIC2_INTR_ClockPrescale    H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale )
+#define H3800_ASIC2_INTR_TimerSet         H3800_ASIC2_OFFSET( u8, INTR, TimerSet )
+
+#define H3800_ASIC2_INTR_GLOBAL_MASK       ( 1 << 0 )    /* Global interrupt mask */
+#define H3800_ASIC2_INTR_POWER_ON_RESET    ( 1 << 1 )    /* 01: Power on reset (bits 1 & 2 ) */
+#define H3800_ASIC2_INTR_EXTERNAL_RESET    ( 2 << 1 )    /* 10: External reset (bits 1 & 2 ) */
+#define H3800_ASIC2_INTR_MASK_UART_0       ( 1 << 4 )
+#define H3800_ASIC2_INTR_MASK_UART_1       ( 1 << 5 )
+#define H3800_ASIC2_INTR_MASK_TIMER        ( 1 << 6 )
+#define H3800_ASIC2_INTR_MASK_OWM          ( 1 << 7 )
+
+#define H3800_ASIC2_INTR_CLOCK_PRESCALE          0x0f    /* 4 bits, max 14 */
+#define H3800_ASIC2_INTR_SET               ( 1 << 4 )    /* Time base enable */
+
+
+#define _H3800_ASIC2_OWM_Base                  0x1800
+#define _H3800_ASIC2_OWM_Command               0x0000    /* R/W 4 bits command register */
+#define _H3800_ASIC2_OWM_Data                  0x0004    /* R/W 8 bits, transmit / receive buffer */
+#define _H3800_ASIC2_OWM_Interrupt             0x0008    /* R/W Command register */
+#define _H3800_ASIC2_OWM_InterruptEnable       0x000c    /* R/W Command register */
+#define _H3800_ASIC2_OWM_ClockDivisor          0x0010    /* R/W 5 bits of divisor and pre-scale */
+
+#define H3800_ASIC2_OWM_Command            H3800_ASIC2_OFFSET( u8, OWM, Command )
+#define H3800_ASIC2_OWM_Data               H3800_ASIC2_OFFSET( u8, OWM, Data )
+#define H3800_ASIC2_OWM_Interrupt          H3800_ASIC2_OFFSET( u8, OWM, Interrupt )
+#define H3800_ASIC2_OWM_InterruptEnable    H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable )
+#define H3800_ASIC2_OWM_ClockDivisor       H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor )
+
+#define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 )    /* Set to force reset on 1-wire bus */
+#define H3800_ASIC2_OWM_CMD_SRA            ( 1 << 1 )    /* Set to switch to Search ROM accelerator mode */
+#define H3800_ASIC2_OWM_CMD_DQ_OUTPUT      ( 1 << 2 )    /* Write only - forces bus low */
+#define H3800_ASIC2_OWM_CMD_DQ_INPUT       ( 1 << 3 )    /* Read only - reflects state of bus */
+
+#define H3800_ASIC2_OWM_INT_PD             ( 1 << 0 )    /* Presence detect */
+#define H3800_ASIC2_OWM_INT_PDR            ( 1 << 1 )    /* Presence detect result */
+#define H3800_ASIC2_OWM_INT_TBE            ( 1 << 2 )    /* Transmit buffer empty */
+#define H3800_ASIC2_OWM_INT_TEMT           ( 1 << 3 )    /* Transmit shift register empty */
+#define H3800_ASIC2_OWM_INT_RBF            ( 1 << 4 )    /* Receive buffer full */
+
+#define H3800_ASIC2_OWM_INTEN_EPD          ( 1 << 0 )    /* Enable receive buffer full interrupt */
+#define H3800_ASIC2_OWM_INTEN_IAS          ( 1 << 1 )    /* Enable transmit shift register empty interrupt */
+#define H3800_ASIC2_OWM_INTEN_ETBE         ( 1 << 2 )    /* Enable transmit buffer empty interrupt */
+#define H3800_ASIC2_OWM_INTEN_ETMT         ( 1 << 3 )    /* INTR active state */
+#define H3800_ASIC2_OWM_INTEN_ERBF         ( 1 << 4 )    /* Enable presence detect interrupt */
+
+#define _H3800_ASIC2_FlashCtl_Base             0x1A00
+
+/****************************************************/
+/* H3800, ASIC #1
+ * This ASIC is accesed through ASIC #2, and
+ * mapped into the 1c00 - 1f00 region
+ */
+
+#define H3800_ASIC1_OFFSET(s,x,y)   \
+     (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1))))
+
+#define _H3800_ASIC1_MMC_Base             0x1c00
+
+#define _H3800_ASIC1_MMC_StartStopClock     0x00    /* R/W 8bit                                  */
+#define _H3800_ASIC1_MMC_Status             0x02    /* R   See below, default 0x0040             */
+#define _H3800_ASIC1_MMC_ClockRate          0x04    /* R/W 8bit, low 3 bits are clock divisor    */
+#define _H3800_ASIC1_MMC_SPIRegister        0x08    /* R/W 8bit, see below                       */
+#define _H3800_ASIC1_MMC_CmdDataCont        0x0a    /* R/W 8bit, write to start MMC adapter      */
+#define _H3800_ASIC1_MMC_ResponseTimeout    0x0c    /* R/W 8bit, clocks before response timeout  */
+#define _H3800_ASIC1_MMC_ReadTimeout        0x0e    /* R/W 16bit, clocks before received data timeout */
+#define _H3800_ASIC1_MMC_BlockLength        0x10    /* R/W 10bit */
+#define _H3800_ASIC1_MMC_NumOfBlocks        0x12    /* R/W 16bit, in block mode, number of blocks  */
+#define _H3800_ASIC1_MMC_InterruptMask      0x1a    /* R/W 8bit */
+#define _H3800_ASIC1_MMC_CommandNumber      0x1c    /* R/W 6 bits */
+#define _H3800_ASIC1_MMC_ArgumentH          0x1e    /* R/W 16 bits  */
+#define _H3800_ASIC1_MMC_ArgumentL          0x20    /* R/W 16 bits */
+#define _H3800_ASIC1_MMC_ResFifo            0x22    /* R   8 x 16 bits - contains response FIFO */
+#define _H3800_ASIC1_MMC_BufferPartFull     0x28    /* R/W 8 bits */
+
+#define H3800_ASIC1_MMC_StartStopClock    H3800_ASIC1_OFFSET(  u8, MMC, StartStopClock )
+#define H3800_ASIC1_MMC_Status            H3800_ASIC1_OFFSET( u16, MMC, Status )
+#define H3800_ASIC1_MMC_ClockRate         H3800_ASIC1_OFFSET(  u8, MMC, ClockRate )
+#define H3800_ASIC1_MMC_SPIRegister       H3800_ASIC1_OFFSET(  u8, MMC, SPIRegister )
+#define H3800_ASIC1_MMC_CmdDataCont       H3800_ASIC1_OFFSET(  u8, MMC, CmdDataCont )
+#define H3800_ASIC1_MMC_ResponseTimeout   H3800_ASIC1_OFFSET(  u8, MMC, ResponseTimeout )
+#define H3800_ASIC1_MMC_ReadTimeout       H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout )
+#define H3800_ASIC1_MMC_BlockLength       H3800_ASIC1_OFFSET( u16, MMC, BlockLength )
+#define H3800_ASIC1_MMC_NumOfBlocks       H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks )
+#define H3800_ASIC1_MMC_InterruptMask     H3800_ASIC1_OFFSET(  u8, MMC, InterruptMask )
+#define H3800_ASIC1_MMC_CommandNumber     H3800_ASIC1_OFFSET(  u8, MMC, CommandNumber )
+#define H3800_ASIC1_MMC_ArgumentH         H3800_ASIC1_OFFSET( u16, MMC, ArgumentH )
+#define H3800_ASIC1_MMC_ArgumentL         H3800_ASIC1_OFFSET( u16, MMC, ArgumentL )
+#define H3800_ASIC1_MMC_ResFifo           H3800_ASIC1_OFFSET( u16, MMC, ResFifo )
+#define H3800_ASIC1_MMC_BufferPartFull    H3800_ASIC1_OFFSET(  u8, MMC, BufferPartFull )
+
+#define H3800_ASIC1_MMC_STOP_CLOCK                   (1 << 0)   /* Write to "StartStopClock" register */
+#define H3800_ASIC1_MMC_START_CLOCK                  (1 << 1)
+
+#define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT          (1 << 0)
+#define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT      (1 << 1)
+#define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR       (1 << 2)
+#define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR        (1 << 3)
+#define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR        (1 << 4)  /* SPI data token error received */
+#define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR    (1 << 5)
+#define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY            (1 << 6)
+#define H3800_ASIC1_MMC_STATUS_FIFO_FULL             (1 << 7)
+#define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE          (1 << 8)  /* MultiMediaCard clock stopped */
+#define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE    (1 << 11) /* Write operation, indicates transfer finished */
+#define H3800_ASIC1_MMC_STATUS_END_PROGRAM           (1 << 12) /* End write and read operations */
+#define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE  (1 << 13) /* End command response */
+
+#define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE           (1 << 0)  /* Enables SPI mode */
+#define H3800_ASIC1_MMC_SPI_REG_CRC_ON               (1 << 1)  /* 1:turn on CRC    */
+#define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE        (1 << 2)  /* 1:turn on SPI CS */
+#define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK      0x38      /* Bits 3,4,5 are the SPI CS relative address */
+
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE  0x00
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1           0x01
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2           0x02
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3           0x03
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE         (1 << 2)  /* This command contains a data transfer */
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE               (1 << 3)  /* This data transfer is a write */
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE         (1 << 4)  /* This data transfer is in stream mode */
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT            (1 << 5)  /* Busy signal expected after current cmd */
+#define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE          (1 << 6)  /* Enables the 80 bits for initializing card */
+
+#define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE       (1 << 0)
+#define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE             (1 << 1)
+#define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE     (1 << 2)
+#define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY             (1 << 3)
+
+#define H3800_ASIC1_MMC_BUFFER_PART_FULL                  (1 << 0)
+
+/********* GPIO **********/
+
+#define _H3800_ASIC1_GPIO_Base        0x1e00
+
+#define _H3800_ASIC1_GPIO_Mask          0x30    /* R/W 0:don't mask, 1:mask interrupt */
+#define _H3800_ASIC1_GPIO_Direction     0x32    /* R/W 0:input, 1:output              */
+#define _H3800_ASIC1_GPIO_Out           0x34    /* R/W 0:output low, 1:output high    */
+#define _H3800_ASIC1_GPIO_TriggerType   0x36    /* R/W 0:level, 1:edge                */
+#define _H3800_ASIC1_GPIO_EdgeTrigger   0x38    /* R/W 0:falling, 1:rising            */
+#define _H3800_ASIC1_GPIO_LevelTrigger  0x3A    /* R/W 0:low, 1:high level detect     */
+#define _H3800_ASIC1_GPIO_LevelStatus   0x3C    /* R/W 0:none, 1:detect               */
+#define _H3800_ASIC1_GPIO_EdgeStatus    0x3E    /* R/W 0:none, 1:detect               */
+#define _H3800_ASIC1_GPIO_State         0x40    /* R   See masks below  (default 0)         */
+#define _H3800_ASIC1_GPIO_Reset         0x42    /* R/W See masks below  (default 0x04)      */
+#define _H3800_ASIC1_GPIO_SleepMask     0x44    /* R/W 0:don't mask, 1:mask trigger in sleep mode  */
+#define _H3800_ASIC1_GPIO_SleepDir      0x46    /* R/W direction 0:input, 1:output in sleep mode    */
+#define _H3800_ASIC1_GPIO_SleepOut      0x48    /* R/W level 0:low, 1:high in sleep mode           */
+#define _H3800_ASIC1_GPIO_Status        0x4A    /* R   Pin status                                  */
+#define _H3800_ASIC1_GPIO_BattFaultDir  0x4C    /* R/W direction 0:input, 1:output in batt_fault   */
+#define _H3800_ASIC1_GPIO_BattFaultOut  0x4E    /* R/W level 0:low, 1:high in batt_fault           */
+
+#define H3800_ASIC1_GPIO_Mask         H3800_ASIC1_OFFSET( u16, GPIO, Mask )
+#define H3800_ASIC1_GPIO_Direction    H3800_ASIC1_OFFSET( u16, GPIO, Direction )
+#define H3800_ASIC1_GPIO_Out          H3800_ASIC1_OFFSET( u16, GPIO, Out )
+#define H3800_ASIC1_GPIO_TriggerType  H3800_ASIC1_OFFSET( u16, GPIO, TriggerType )
+#define H3800_ASIC1_GPIO_EdgeTrigger  H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger )
+#define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger )
+#define H3800_ASIC1_GPIO_LevelStatus  H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus )
+#define H3800_ASIC1_GPIO_EdgeStatus   H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus )
+#define H3800_ASIC1_GPIO_State        H3800_ASIC1_OFFSET(  u8, GPIO, State )
+#define H3800_ASIC1_GPIO_Reset        H3800_ASIC1_OFFSET(  u8, GPIO, Reset )
+#define H3800_ASIC1_GPIO_SleepMask    H3800_ASIC1_OFFSET( u16, GPIO, SleepMask )
+#define H3800_ASIC1_GPIO_SleepDir     H3800_ASIC1_OFFSET( u16, GPIO, SleepDir )
+#define H3800_ASIC1_GPIO_SleepOut     H3800_ASIC1_OFFSET( u16, GPIO, SleepOut )
+#define H3800_ASIC1_GPIO_Status       H3800_ASIC1_OFFSET( u16, GPIO, Status )
+#define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir )
+#define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut )
+
+#define H3800_ASIC1_GPIO_STATE_MASK            (1 << 0)
+#define H3800_ASIC1_GPIO_STATE_DIRECTION       (1 << 1)
+#define H3800_ASIC1_GPIO_STATE_OUT             (1 << 2)
+#define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE    (1 << 3)
+#define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER    (1 << 4)
+#define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER   (1 << 5)
+
+#define H3800_ASIC1_GPIO_RESET_SOFTWARE        (1 << 0)
+#define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP      (1 << 1)
+#define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON    (1 << 2)
+
+/* These are all outputs */
+#define GPIO_H3800_ASIC1_IR_ON_N          (1 << 0)   /* Apply power to the IR Module */
+#define GPIO_H3800_ASIC1_SD_PWR_ON        (1 << 1)   /* Secure Digital power on */
+#define GPIO_H3800_ASIC1_RS232_ON         (1 << 2)   /* Turn on power to the RS232 chip ? */
+#define GPIO_H3800_ASIC1_PULSE_GEN        (1 << 3)   /* Goes to speaker / earphone */
+#define GPIO_H3800_ASIC1_CH_TIMER         (1 << 4)   /* */
+#define GPIO_H3800_ASIC1_LCD_5V_ON        (1 << 5)   /* Enables LCD_5V */
+#define GPIO_H3800_ASIC1_LCD_ON           (1 << 6)   /* Enables LCD_3V */
+#define GPIO_H3800_ASIC1_LCD_PCI          (1 << 7)   /* Connects to PDWN on LCD controller */
+#define GPIO_H3800_ASIC1_VGH_ON           (1 << 8)   /* Drives VGH on the LCD (+9??) */
+#define GPIO_H3800_ASIC1_VGL_ON           (1 << 9)   /* Drivers VGL on the LCD (-6??) */
+#define GPIO_H3800_ASIC1_FL_PWR_ON        (1 << 10)  /* Frontlight power on */
+#define GPIO_H3800_ASIC1_BT_PWR_ON        (1 << 11)  /* Bluetooth power on */
+#define GPIO_H3800_ASIC1_SPK_ON           (1 << 12)  /* */
+#define GPIO_H3800_ASIC1_EAR_ON_N         (1 << 13)  /* */
+#define GPIO_H3800_ASIC1_AUD_PWR_ON       (1 << 14)  /* */
+
+/* Write enable for the flash */
+
+#define _H3800_ASIC1_FlashWP_Base         0x1F00
+#define _H3800_ASIC1_FlashWP_VPP_ON         0x00    /* R   1: write, 0: protect */
+#define H3800_ASIC1_FlashWP_VPP_ON       H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON )
+
+#endif /* _INCLUDE_H3600_GPIO_H_ */
diff --git a/include/asm-arm/arch-sa1100/hardware.h b/include/asm-arm/arch-sa1100/hardware.h
new file mode 100644
index 000000000000..10c62db34362
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/hardware.h
@@ -0,0 +1,83 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/hardware.h
+ *
+ * Copyright (C) 1998 Nicolas Pitre <nico@cam.org>
+ *
+ * This file contains the hardware definitions for SA1100 architecture
+ *
+ * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
+ *      Definitions for SA1111 added.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/config.h>
+
+/* Flushing areas */
+#define FLUSH_BASE_PHYS         0xe0000000      /* SA1100 zero bank */
+#define FLUSH_BASE              0xf5000000
+#define FLUSH_BASE_MINICACHE    0xf5800000
+#define UNCACHEABLE_ADDR        0xfa050000
+
+
+/*
+ * We requires absolute addresses i.e. (PCMCIA_IO_0_BASE + 0x3f8) for 
+ * in*()/out*() macros to be usable for all cases.
+ */
+#define PCIO_BASE               0
+
+
+/*
+ * SA1100 internal I/O mappings
+ *
+ * We have the following mapping:
+ *      phys            virt
+ *      80000000        f8000000
+ *      90000000        fa000000
+ *      a0000000        fc000000
+ *      b0000000        fe000000
+ */
+
+#define VIO_BASE        0xf8000000      /* virtual start of IO space */
+#define VIO_SHIFT       3               /* x = IO space shrink power */
+#define PIO_START       0x80000000      /* physical start of IO space */
+
+#define io_p2v( x )             \
+   ( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE )
+#define io_v2p( x )             \
+   ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START )
+
+#ifndef __ASSEMBLY__
+#include <asm/types.h>
+
+#if 0
+# define __REG(x)       (*((volatile u32 *)io_p2v(x)))
+#else
+/*
+ * This __REG() version gives the same results as the one above,  except
+ * that we are fooling gcc somehow so it generates far better and smaller
+ * assembly code for access to contigous registers.  It's a shame that gcc
+ * doesn't guess this by itself.
+ */
+typedef struct { volatile u32 offset[4096]; } __regbase;
+# define __REGP(x)      ((__regbase *)((x)&~4095))->offset[((x)&4095)>>2]
+# define __REG(x)       __REGP(io_p2v(x))
+#endif
+
+# define __PREG(x)      (io_v2p((u32)&(x)))
+
+#else
+
+# define __REG(x)       io_p2v(x)
+# define __PREG(x)      io_v2p(x)
+
+#endif
+
+#include "SA-1100.h"
+
+#ifdef CONFIG_SA1101
+#include "SA-1101.h"
+#endif
+
+#endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-sa1100/ide.h b/include/asm-arm/arch-sa1100/ide.h
new file mode 100644
index 000000000000..2153538069c7
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/ide.h
@@ -0,0 +1,76 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/ide.h
+ *
+ * Copyright (c) 1998 Hugo Fiennes & Nicolas Pitre
+ *
+ * 18-aug-2000: Cleanup by Erik Mouw (J.A.K.Mouw@its.tudelft.nl)
+ *              Get rid of the special ide_init_hwif_ports() functions
+ *              and make a generalised function that can be used by all
+ *              architectures.
+ */
+
+#include <linux/config.h>
+#include <asm/irq.h>
+#include <asm/hardware.h>
+#include <asm/mach-types.h>
+
+#error "This code is broken and needs update to match with current ide support"
+
+
+/*
+ * Set up a hw structure for a specified data port, control port and IRQ.
+ * This should follow whatever the default interface uses.
+ */
+static inline void ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
+                                       unsigned long ctrl_port, int *irq)
+{
+        unsigned long reg = data_port;
+        int i;
+        int regincr = 1;
+
+        /* The Empeg board has the first two address lines unused */
+        if (machine_is_empeg())
+                regincr = 1 << 2;
+
+        /* The LART doesn't use A0 for IDE */
+        if (machine_is_lart())
+                regincr = 1 << 1;
+
+        memset(hw, 0, sizeof(*hw));
+
+        for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
+                hw->io_ports[i] = reg;
+                reg += regincr;
+        }
+
+        hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
+
+        if (irq)
+                *irq = 0;
+}
+
+/*
+ * This registers the standard ports for this architecture with the IDE
+ * driver.
+ */
+static __inline__ void
+ide_init_default_hwifs(void)
+{
+    if (machine_is_lart()) {
+#ifdef CONFIG_SA1100_LART
+        hw_regs_t hw;
+
+        /* Enable GPIO as interrupt line */
+        GPDR &= ~LART_GPIO_IDE;
+        set_irq_type(LART_IRQ_IDE, IRQT_RISING);
+
+        /* set PCMCIA interface timing */
+        MECR = 0x00060006;
+
+        /* init the interface */
+        ide_init_hwif_ports(&hw, PCMCIA_IO_0_BASE + 0x0000, PCMCIA_IO_0_BASE + 0x1000, NULL);
+        hw.irq = LART_IRQ_IDE;
+        ide_register_hw(&hw);
+#endif
+    }
+}
diff --git a/include/asm-arm/arch-sa1100/io.h b/include/asm-arm/arch-sa1100/io.h
new file mode 100644
index 000000000000..7d969ffbd3bb
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/io.h
@@ -0,0 +1,23 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/io.h
+ *
+ * Copyright (C) 1997-1999 Russell King
+ *
+ * Modifications:
+ *  06-12-1997  RMK     Created.
+ *  07-04-1999  RMK     Major cleanup
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We don't actually have real ISA nor PCI buses, but there is so many 
+ * drivers out there that might just work if we fake them...
+ */
+#define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/irqs.h b/include/asm-arm/arch-sa1100/irqs.h
new file mode 100644
index 000000000000..eabd3be3d705
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/irqs.h
@@ -0,0 +1,198 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/irqs.h
+ *
+ * Copyright (C) 1996 Russell King
+ * Copyright (C) 1998 Deborah Wallach (updates for SA1100/Brutus).
+ * Copyright (C) 1999 Nicolas Pitre (full GPIO irq isolation)
+ *
+ * 2001/11/14   RMK     Cleaned up and standardised a lot of the IRQs.
+ */
+#include <linux/config.h>
+
+#define IRQ_GPIO0               0
+#define IRQ_GPIO1               1
+#define IRQ_GPIO2               2
+#define IRQ_GPIO3               3
+#define IRQ_GPIO4               4
+#define IRQ_GPIO5               5
+#define IRQ_GPIO6               6
+#define IRQ_GPIO7               7
+#define IRQ_GPIO8               8
+#define IRQ_GPIO9               9
+#define IRQ_GPIO10              10
+#define IRQ_GPIO11_27           11
+#define IRQ_LCD                 12      /* LCD controller           */
+#define IRQ_Ser0UDC             13      /* Ser. port 0 UDC          */
+#define IRQ_Ser1SDLC            14      /* Ser. port 1 SDLC         */
+#define IRQ_Ser1UART            15      /* Ser. port 1 UART         */
+#define IRQ_Ser2ICP             16      /* Ser. port 2 ICP          */
+#define IRQ_Ser3UART            17      /* Ser. port 3 UART         */
+#define IRQ_Ser4MCP             18      /* Ser. port 4 MCP          */
+#define IRQ_Ser4SSP             19      /* Ser. port 4 SSP          */
+#define IRQ_DMA0                20      /* DMA controller channel 0 */
+#define IRQ_DMA1                21      /* DMA controller channel 1 */
+#define IRQ_DMA2                22      /* DMA controller channel 2 */
+#define IRQ_DMA3                23      /* DMA controller channel 3 */
+#define IRQ_DMA4                24      /* DMA controller channel 4 */
+#define IRQ_DMA5                25      /* DMA controller channel 5 */
+#define IRQ_OST0                26      /* OS Timer match 0         */
+#define IRQ_OST1                27      /* OS Timer match 1         */
+#define IRQ_OST2                28      /* OS Timer match 2         */
+#define IRQ_OST3                29      /* OS Timer match 3         */
+#define IRQ_RTC1Hz              30      /* RTC 1 Hz clock           */
+#define IRQ_RTCAlrm             31      /* RTC Alarm                */
+
+#define IRQ_GPIO11              32
+#define IRQ_GPIO12              33
+#define IRQ_GPIO13              34
+#define IRQ_GPIO14              35
+#define IRQ_GPIO15              36
+#define IRQ_GPIO16              37
+#define IRQ_GPIO17              38
+#define IRQ_GPIO18              39
+#define IRQ_GPIO19              40
+#define IRQ_GPIO20              41
+#define IRQ_GPIO21              42
+#define IRQ_GPIO22              43
+#define IRQ_GPIO23              44
+#define IRQ_GPIO24              45
+#define IRQ_GPIO25              46
+#define IRQ_GPIO26              47
+#define IRQ_GPIO27              48
+
+/*
+ * The next 16 interrupts are for board specific purposes.  Since
+ * the kernel can only run on one machine at a time, we can re-use
+ * these.  If you need more, increase IRQ_BOARD_END, but keep it
+ * within sensible limits.  IRQs 49 to 64 are available.
+ */
+#define IRQ_BOARD_START         49
+#define IRQ_BOARD_END           65
+
+#define IRQ_SA1111_START        (IRQ_BOARD_END)
+#define IRQ_GPAIN0              (IRQ_BOARD_END + 0)
+#define IRQ_GPAIN1              (IRQ_BOARD_END + 1)
+#define IRQ_GPAIN2              (IRQ_BOARD_END + 2)
+#define IRQ_GPAIN3              (IRQ_BOARD_END + 3)
+#define IRQ_GPBIN0              (IRQ_BOARD_END + 4)
+#define IRQ_GPBIN1              (IRQ_BOARD_END + 5)
+#define IRQ_GPBIN2              (IRQ_BOARD_END + 6)
+#define IRQ_GPBIN3              (IRQ_BOARD_END + 7)
+#define IRQ_GPBIN4              (IRQ_BOARD_END + 8)
+#define IRQ_GPBIN5              (IRQ_BOARD_END + 9)
+#define IRQ_GPCIN0              (IRQ_BOARD_END + 10)
+#define IRQ_GPCIN1              (IRQ_BOARD_END + 11)
+#define IRQ_GPCIN2              (IRQ_BOARD_END + 12)
+#define IRQ_GPCIN3              (IRQ_BOARD_END + 13)
+#define IRQ_GPCIN4              (IRQ_BOARD_END + 14)
+#define IRQ_GPCIN5              (IRQ_BOARD_END + 15)
+#define IRQ_GPCIN6              (IRQ_BOARD_END + 16)
+#define IRQ_GPCIN7              (IRQ_BOARD_END + 17)
+#define IRQ_MSTXINT             (IRQ_BOARD_END + 18)
+#define IRQ_MSRXINT             (IRQ_BOARD_END + 19)
+#define IRQ_MSSTOPERRINT        (IRQ_BOARD_END + 20)
+#define IRQ_TPTXINT             (IRQ_BOARD_END + 21)
+#define IRQ_TPRXINT             (IRQ_BOARD_END + 22)
+#define IRQ_TPSTOPERRINT        (IRQ_BOARD_END + 23)
+#define SSPXMTINT               (IRQ_BOARD_END + 24)
+#define SSPRCVINT               (IRQ_BOARD_END + 25)
+#define SSPROR                  (IRQ_BOARD_END + 26)
+#define AUDXMTDMADONEA          (IRQ_BOARD_END + 32)
+#define AUDRCVDMADONEA          (IRQ_BOARD_END + 33)
+#define AUDXMTDMADONEB          (IRQ_BOARD_END + 34)
+#define AUDRCVDMADONEB          (IRQ_BOARD_END + 35)
+#define AUDTFSR                 (IRQ_BOARD_END + 36)
+#define AUDRFSR                 (IRQ_BOARD_END + 37)
+#define AUDTUR                  (IRQ_BOARD_END + 38)
+#define AUDROR                  (IRQ_BOARD_END + 39)
+#define AUDDTS                  (IRQ_BOARD_END + 40)
+#define AUDRDD                  (IRQ_BOARD_END + 41)
+#define AUDSTO                  (IRQ_BOARD_END + 42)
+#define IRQ_USBPWR              (IRQ_BOARD_END + 43)
+#define IRQ_HCIM                (IRQ_BOARD_END + 44)
+#define IRQ_HCIBUFFACC          (IRQ_BOARD_END + 45)
+#define IRQ_HCIRMTWKP           (IRQ_BOARD_END + 46)
+#define IRQ_NHCIMFCIR           (IRQ_BOARD_END + 47)
+#define IRQ_USB_PORT_RESUME     (IRQ_BOARD_END + 48)
+#define IRQ_S0_READY_NINT       (IRQ_BOARD_END + 49)
+#define IRQ_S1_READY_NINT       (IRQ_BOARD_END + 50)
+#define IRQ_S0_CD_VALID         (IRQ_BOARD_END + 51)
+#define IRQ_S1_CD_VALID         (IRQ_BOARD_END + 52)
+#define IRQ_S0_BVD1_STSCHG      (IRQ_BOARD_END + 53)
+#define IRQ_S1_BVD1_STSCHG      (IRQ_BOARD_END + 54)
+
+#define IRQ_LOCOMO_START        (IRQ_BOARD_END)
+#define IRQ_LOCOMO_KEY          (IRQ_BOARD_END + 0)
+#define IRQ_LOCOMO_GPIO0        (IRQ_BOARD_END + 1)
+#define IRQ_LOCOMO_GPIO1        (IRQ_BOARD_END + 2)
+#define IRQ_LOCOMO_GPIO2        (IRQ_BOARD_END + 3)
+#define IRQ_LOCOMO_GPIO3        (IRQ_BOARD_END + 4)
+#define IRQ_LOCOMO_GPIO4        (IRQ_BOARD_END + 5)
+#define IRQ_LOCOMO_GPIO5        (IRQ_BOARD_END + 6)
+#define IRQ_LOCOMO_GPIO6        (IRQ_BOARD_END + 7)
+#define IRQ_LOCOMO_GPIO7        (IRQ_BOARD_END + 8)
+#define IRQ_LOCOMO_GPIO8        (IRQ_BOARD_END + 9)
+#define IRQ_LOCOMO_GPIO9        (IRQ_BOARD_END + 10)
+#define IRQ_LOCOMO_GPIO10       (IRQ_BOARD_END + 11)
+#define IRQ_LOCOMO_GPIO11       (IRQ_BOARD_END + 12)
+#define IRQ_LOCOMO_GPIO12       (IRQ_BOARD_END + 13)
+#define IRQ_LOCOMO_GPIO13       (IRQ_BOARD_END + 14)
+#define IRQ_LOCOMO_GPIO14       (IRQ_BOARD_END + 15)
+#define IRQ_LOCOMO_GPIO15       (IRQ_BOARD_END + 16)
+#define IRQ_LOCOMO_LT           (IRQ_BOARD_END + 17)
+#define IRQ_LOCOMO_SPI_RFR      (IRQ_BOARD_END + 18)
+#define IRQ_LOCOMO_SPI_RFW      (IRQ_BOARD_END + 19)
+#define IRQ_LOCOMO_SPI_OVRN     (IRQ_BOARD_END + 20)
+#define IRQ_LOCOMO_SPI_TEND     (IRQ_BOARD_END + 21)
+
+/*
+ * Figure out the MAX IRQ number.
+ *
+ * If we have an SA1111, the max IRQ is S1_BVD1_STSCHG+1.
+ * If we have an LoCoMo, the max IRQ is IRQ_LOCOMO_SPI_TEND+1
+ * Otherwise, we have the standard IRQs only.
+ */
+#ifdef CONFIG_SA1111
+#define NR_IRQS                 (IRQ_S1_BVD1_STSCHG + 1)
+#elif defined(CONFIG_SA1100_H3800)
+#define NR_IRQS                 (IRQ_BOARD_END)
+#elif defined(CONFIG_SHARP_LOCOMO)
+#define NR_IRQS                 (IRQ_LOCOMO_SPI_TEND + 1)
+#else
+#define NR_IRQS                 (IRQ_BOARD_START)
+#endif
+
+/*
+ * Board specific IRQs.  Define them here.
+ * Do not surround them with ifdefs.
+ */
+#define IRQ_NEPONSET_SMC9196    (IRQ_BOARD_START + 0)
+#define IRQ_NEPONSET_USAR       (IRQ_BOARD_START + 1)
+#define IRQ_NEPONSET_SA1111     (IRQ_BOARD_START + 2)
+
+/* LoCoMo Interrupts (CONFIG_SHARP_LOCOMO) */
+#define IRQ_LOCOMO_KEY_BASE     (IRQ_BOARD_START + 0)
+#define IRQ_LOCOMO_GPIO_BASE    (IRQ_BOARD_START + 1)
+#define IRQ_LOCOMO_LT_BASE      (IRQ_BOARD_START + 2)
+#define IRQ_LOCOMO_SPI_BASE     (IRQ_BOARD_START + 3)
+
+/* H3800-specific IRQs (CONFIG_SA1100_H3800) */
+#define H3800_KPIO_IRQ_START    (IRQ_BOARD_START)
+#define IRQ_H3800_KEY           (IRQ_BOARD_START + 0)
+#define IRQ_H3800_SPI           (IRQ_BOARD_START + 1)
+#define IRQ_H3800_OWM           (IRQ_BOARD_START + 2)
+#define IRQ_H3800_ADC           (IRQ_BOARD_START + 3)
+#define IRQ_H3800_UART_0        (IRQ_BOARD_START + 4)
+#define IRQ_H3800_UART_1        (IRQ_BOARD_START + 5)
+#define IRQ_H3800_TIMER_0       (IRQ_BOARD_START + 6)
+#define IRQ_H3800_TIMER_1       (IRQ_BOARD_START + 7)
+#define IRQ_H3800_TIMER_2       (IRQ_BOARD_START + 8)
+#define H3800_KPIO_IRQ_COUNT    9
+
+#define H3800_GPIO_IRQ_START    (IRQ_BOARD_START + 9)
+#define IRQ_H3800_PEN           (IRQ_BOARD_START + 9)
+#define IRQ_H3800_SD_DETECT     (IRQ_BOARD_START + 10)
+#define IRQ_H3800_EAR_IN        (IRQ_BOARD_START + 11)
+#define IRQ_H3800_USB_DETECT    (IRQ_BOARD_START + 12)
+#define IRQ_H3800_SD_CON_SLT    (IRQ_BOARD_START + 13)
+#define H3800_GPIO_IRQ_COUNT    5
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
new file mode 100644
index 000000000000..1b8e8a304800
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/jornada720.h
@@ -0,0 +1,28 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/jornada720.h
+ *
+ * Created 2000/11/29 by John Ankcorn <jca@lcs.mit.edu>
+ *
+ * This file contains the hardware specific definitions for HP Jornada 720
+ *
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#error "include <asm/hardware.h> instead"
+#endif
+
+#define SA1111_BASE             (0x40000000)
+
+#define GPIO_JORNADA720_KEYBOARD        GPIO_GPIO(0)
+#define GPIO_JORNADA720_MOUSE           GPIO_GPIO(9)
+
+#define GPIO_JORNADA720_KEYBOARD_IRQ    IRQ_GPIO0
+#define GPIO_JORNADA720_MOUSE_IRQ               IRQ_GPIO9
+
+#ifndef __ASSEMBLY__
+
+void jornada720_mcu_init(void);
+void jornada_contrast(int arg_contrast);
+void jornada720_battery(void);
+int jornada720_getkey(unsigned char *data, int size);
+#endif
diff --git a/include/asm-arm/arch-sa1100/lart.h b/include/asm-arm/arch-sa1100/lart.h
new file mode 100644
index 000000000000..8a5482d908db
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/lart.h
@@ -0,0 +1,13 @@
+#ifndef _INCLUDE_LART_H
+#define _INCLUDE_LART_H
+
+#define LART_GPIO_ETH0                  GPIO_GPIO0
+#define LART_IRQ_ETH0                   IRQ_GPIO0
+
+#define LART_GPIO_IDE                   GPIO_GPIO1
+#define LART_IRQ_IDE                    IRQ_GPIO1
+
+#define LART_GPIO_UCB1200               GPIO_GPIO18
+#define LART_IRQ_UCB1200                IRQ_GPIO18
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/memory.h b/include/asm-arm/arch-sa1100/memory.h
new file mode 100644
index 000000000000..32d3d5bde34d
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/memory.h
@@ -0,0 +1,108 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/memory.h
+ *
+ * Copyright (C) 1999-2000 Nicolas Pitre <nico@cam.org>
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <linux/config.h>
+#include <asm/sizes.h>
+
+/*
+ * Physical DRAM offset is 0xc0000000 on the SA1100
+ */
+#define PHYS_OFFSET     (0xc0000000UL)
+
+#ifndef __ASSEMBLY__
+
+#ifdef CONFIG_SA1111
+static inline void
+__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
+{
+        unsigned int sz = SZ_1M >> PAGE_SHIFT;
+
+        if (node != 0)
+                sz = 0;
+
+        size[1] = size[0] - sz;
+        size[0] = sz;
+}
+
+#define arch_adjust_zones(node, size, holes) \
+        __arch_adjust_zones(node, size, holes)
+
+#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_1M - 1)
+
+#endif
+#endif
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ *
+ * On the SA1100, bus addresses are equivalent to physical addresses.
+ */
+#define __virt_to_bus(x)         __virt_to_phys(x)
+#define __bus_to_virt(x)         __phys_to_virt(x)
+
+#ifdef CONFIG_DISCONTIGMEM
+/*
+ * Because of the wide memory address space between physical RAM banks on the 
+ * SA1100, it's much convenient to use Linux's NUMA support to implement our 
+ * memory map representation.  Assuming all memory nodes have equal access 
+ * characteristics, we then have generic discontiguous memory support.
+ *
+ * Of course, all this isn't mandatory for SA1100 implementations with only
+ * one used memory bank.  For those, simply undefine CONFIG_DISCONTIGMEM.
+ *
+ * The nodes are matched with the physical memory bank addresses which are 
+ * incidentally the same as virtual addresses.
+ * 
+ *      node 0:  0xc0000000 - 0xc7ffffff
+ *      node 1:  0xc8000000 - 0xcfffffff
+ *      node 2:  0xd0000000 - 0xd7ffffff
+ *      node 3:  0xd8000000 - 0xdfffffff
+ */
+
+/*
+ * Given a kernel address, find the home node of the underlying memory.
+ */
+#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27)
+
+/*
+ * Given a page frame number, convert it to a node id.
+ */
+#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT))
+
+/*
+ * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
+ * and return the mem_map of that node.
+ */
+#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
+
+/*
+ * Given a page frame number, find the owning node of the memory
+ * and return the mem_map of that node.
+ */
+#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
+
+/*
+ * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
+ * and returns the index corresponding to the appropriate page in the
+ * node's mem_map.
+ */
+#define LOCAL_MAP_NR(addr) \
+        (((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT)
+
+#else
+
+#define PFN_TO_NID(addr)        (0)
+
+#endif
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/neponset.h b/include/asm-arm/arch-sa1100/neponset.h
new file mode 100644
index 000000000000..8051fd73a80b
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/neponset.h
@@ -0,0 +1,74 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/assabet.h
+ *
+ * Created 2000/06/05 by Nicolas Pitre <nico@cam.org>
+ *
+ * This file contains the hardware specific definitions for Assabet
+ * Only include this file from SA1100-specific files.
+ *
+ * 2000/05/23 John Dorsey <john+@cs.cmu.edu>
+ *      Definitions for Neponset added.
+ */
+#ifndef __ASM_ARCH_NEPONSET_H
+#define __ASM_ARCH_NEPONSET_H
+
+/*
+ * Neponset definitions: 
+ */
+
+#define NEPONSET_CPLD_BASE      (0x10000000)
+#define Nep_p2v( x )            ((x) - NEPONSET_CPLD_BASE + 0xf3000000)
+#define Nep_v2p( x )            ((x) - 0xf3000000 + NEPONSET_CPLD_BASE)
+
+#define _IRR                    0x10000024      /* Interrupt Reason Register */
+#define _AUD_CTL                0x100000c0      /* Audio controls (RW)       */
+#define _MDM_CTL_0              0x100000b0      /* Modem control 0 (RW)      */
+#define _MDM_CTL_1              0x100000b4      /* Modem control 1 (RW)      */
+#define _NCR_0                  0x100000a0      /* Control Register (RW)     */
+#define _KP_X_OUT               0x10000090      /* Keypad row write (RW)     */
+#define _KP_Y_IN                0x10000080      /* Keypad column read (RO)   */
+#define _SWPK                   0x10000020      /* Switch pack (RO)          */
+#define _WHOAMI                 0x10000000      /* System ID Register (RO)   */
+
+#define _LEDS                   0x10000010      /* LEDs [31:0] (WO)          */
+
+#define IRR                     (*((volatile u_char *) Nep_p2v(_IRR)))
+#define AUD_CTL                 (*((volatile u_char *) Nep_p2v(_AUD_CTL)))
+#define MDM_CTL_0               (*((volatile u_char *) Nep_p2v(_MDM_CTL_0)))
+#define MDM_CTL_1               (*((volatile u_char *) Nep_p2v(_MDM_CTL_1)))
+#define NCR_0                   (*((volatile u_char *) Nep_p2v(_NCR_0)))
+#define KP_X_OUT                (*((volatile u_char *) Nep_p2v(_KP_X_OUT)))
+#define KP_Y_IN                 (*((volatile u_char *) Nep_p2v(_KP_Y_IN)))
+#define SWPK                    (*((volatile u_char *) Nep_p2v(_SWPK)))
+#define WHOAMI                  (*((volatile u_char *) Nep_p2v(_WHOAMI)))
+
+#define LEDS                    (*((volatile Word   *) Nep_p2v(_LEDS)))
+
+#define IRR_ETHERNET            (1<<0)
+#define IRR_USAR                (1<<1)
+#define IRR_SA1111              (1<<2)
+
+#define AUD_SEL_1341            (1<<0)
+#define AUD_MUTE_1341           (1<<1)
+
+#define MDM_CTL0_RTS1           (1 << 0)
+#define MDM_CTL0_DTR1           (1 << 1)
+#define MDM_CTL0_RTS2           (1 << 2)
+#define MDM_CTL0_DTR2           (1 << 3)
+
+#define MDM_CTL1_CTS1           (1 << 0)
+#define MDM_CTL1_DSR1           (1 << 1)
+#define MDM_CTL1_DCD1           (1 << 2)
+#define MDM_CTL1_CTS2           (1 << 3)
+#define MDM_CTL1_DSR2           (1 << 4)
+#define MDM_CTL1_DCD2           (1 << 5)
+
+#define NCR_GP01_OFF            (1<<0)
+#define NCR_TP_PWR_EN           (1<<1)
+#define NCR_MS_PWR_EN           (1<<2)
+#define NCR_ENET_OSC_EN         (1<<3)
+#define NCR_SPI_KB_WK_UP        (1<<4)
+#define NCR_A0VPP               (1<<5)
+#define NCR_A1VPP               (1<<6)
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/param.h b/include/asm-arm/arch-sa1100/param.h
new file mode 100644
index 000000000000..867488909ecd
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/param.h
@@ -0,0 +1,3 @@
+/*
+ *  linux/include/asm-arm/arch-sa1100/param.h
+ */
diff --git a/include/asm-arm/arch-sa1100/shannon.h b/include/asm-arm/arch-sa1100/shannon.h
new file mode 100644
index 000000000000..ec27d6e12140
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/shannon.h
@@ -0,0 +1,43 @@
+#ifndef _INCLUDE_SHANNON_H
+#define _INCLUDE_SHANNON_H
+
+/* taken from comp.os.inferno Tue, 12 Sep 2000 09:21:50 GMT,
+ * written by <forsyth@vitanuova.com> */
+
+#define SHANNON_GPIO_SPI_FLASH          GPIO_GPIO (0)   /* Output - Driven low, enables SPI to flash */
+#define SHANNON_GPIO_SPI_DSP            GPIO_GPIO (1)   /* Output - Driven low, enables SPI to DSP */
+/* lcd lower = GPIO 2-9 */
+#define SHANNON_GPIO_SPI_OUTPUT         GPIO_GPIO (10)  /* Output - SPI output to DSP */
+#define SHANNON_GPIO_SPI_INPUT          GPIO_GPIO (11)  /* Input  - SPI input from DSP */
+#define SHANNON_GPIO_SPI_CLOCK          GPIO_GPIO (12)  /* Output - Clock for SPI */
+#define SHANNON_GPIO_SPI_FRAME          GPIO_GPIO (13)  /* Output - Frame marker - not used */
+#define SHANNON_GPIO_SPI_RTS            GPIO_GPIO (14)  /* Input  - SPI Ready to Send */
+#define SHANNON_IRQ_GPIO_SPI_RTS        IRQ_GPIO14
+#define SHANNON_GPIO_SPI_CTS            GPIO_GPIO (15)  /* Output - SPI Clear to Send */
+#define SHANNON_GPIO_IRQ_CODEC          GPIO_GPIO (16)  /* in, irq from ucb1200 */
+#define SHANNON_IRQ_GPIO_IRQ_CODEC      IRQ_GPIO16
+#define SHANNON_GPIO_DSP_RESET          GPIO_GPIO (17)  /* Output - Drive low to reset the DSP */
+#define SHANNON_GPIO_CODEC_RESET        GPIO_GPIO (18)  /* Output - Drive low to reset the UCB1x00 */
+#define SHANNON_GPIO_U3_RTS             GPIO_GPIO (19)  /* ?? */
+#define SHANNON_GPIO_U3_CTS             GPIO_GPIO (20)  /* ?? */
+#define SHANNON_GPIO_SENSE_12V          GPIO_GPIO (21)  /* Input, 12v flash unprotect detected */
+#define SHANNON_GPIO_DISP_EN            GPIO_GPIO (22)  /* out */
+/* XXX GPIO 23 unaccounted for */
+#define SHANNON_GPIO_EJECT_0            GPIO_GPIO (24)  /* in */
+#define SHANNON_IRQ_GPIO_EJECT_0        IRQ_GPIO24
+#define SHANNON_GPIO_EJECT_1            GPIO_GPIO (25)  /* in */
+#define SHANNON_IRQ_GPIO_EJECT_1        IRQ_GPIO25
+#define SHANNON_GPIO_RDY_0              GPIO_GPIO (26)  /* in */
+#define SHANNON_IRQ_GPIO_RDY_0          IRQ_GPIO26
+#define SHANNON_GPIO_RDY_1              GPIO_GPIO (27)  /* in */
+#define SHANNON_IRQ_GPIO_RDY_1          IRQ_GPIO27
+
+/* MCP UCB codec GPIO pins... */
+
+#define SHANNON_UCB_GPIO_BACKLIGHT      9
+#define SHANNON_UCB_GPIO_BRIGHT_MASK    7
+#define SHANNON_UCB_GPIO_BRIGHT         6
+#define SHANNON_UCB_GPIO_CONTRAST_MASK  0x3f
+#define SHANNON_UCB_GPIO_CONTRAST       0
+
+#endif
diff --git a/include/asm-arm/arch-sa1100/simpad.h b/include/asm-arm/arch-sa1100/simpad.h
new file mode 100644
index 000000000000..034301d23f60
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/simpad.h
@@ -0,0 +1,112 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/simpad.h
+ *
+ * based of assabet.h same as HUW_Webpanel
+ *
+ * This file contains the hardware specific definitions for SIMpad
+ *
+ * 2001/05/14 Juergen Messerer <juergen.messerer@freesurf.ch>
+ */
+
+#ifndef __ASM_ARCH_SIMPAD_H
+#define __ASM_ARCH_SIMPAD_H
+
+
+#define GPIO_UART1_RTS  GPIO_GPIO14
+#define GPIO_UART1_DTR  GPIO_GPIO7
+#define GPIO_UART1_CTS  GPIO_GPIO8
+#define GPIO_UART1_DCD  GPIO_GPIO23
+#define GPIO_UART1_DSR  GPIO_GPIO6
+
+#define GPIO_UART3_RTS  GPIO_GPIO12
+#define GPIO_UART3_DTR  GPIO_GPIO16
+#define GPIO_UART3_CTS  GPIO_GPIO13
+#define GPIO_UART3_DCD  GPIO_GPIO18
+#define GPIO_UART3_DSR  GPIO_GPIO17
+
+#define GPIO_POWER_BUTTON       GPIO_GPIO0
+#define GPIO_UCB1300_IRQ        GPIO_GPIO22     /* UCB GPIO and touchscreen */
+
+#define IRQ_UART1_CTS   IRQ_GPIO15
+#define IRQ_UART1_DCD   GPIO_GPIO23
+#define IRQ_UART1_DSR   GPIO_GPIO6
+#define IRQ_UART3_CTS   GPIO_GPIO13
+#define IRQ_UART3_DCD   GPIO_GPIO18
+#define IRQ_UART3_DSR   GPIO_GPIO17
+
+#define IRQ_GPIO_UCB1300_IRQ IRQ_GPIO22
+#define IRQ_GPIO_POWER_BUTTON IRQ_GPIO0
+
+
+/*---  PCMCIA  ---*/
+#define GPIO_CF_CD              GPIO_GPIO24
+#define GPIO_CF_IRQ             GPIO_GPIO1
+#define IRQ_GPIO_CF_IRQ         IRQ_GPIO1
+#define IRQ_GPIO_CF_CD          IRQ_GPIO24
+
+/*--- SmartCard ---*/
+#define GPIO_SMART_CARD         GPIO_GPIO10
+#define IRQ_GPIO_SMARD_CARD     IRQ_GPIO10
+
+// CS3 Latch is write only, a shadow is necessary
+
+#define CS3BUSTYPE unsigned volatile long
+#define CS3_BASE        0xf1000000
+
+#define VCC_5V_EN       0x0001 // For 5V PCMCIA
+#define VCC_3V_EN       0x0002 // FOR 3.3V PCMCIA
+#define EN1             0x0004 // This is only for EPROM's
+#define EN0             0x0008 // Both should be enable for 3.3V or 5V
+#define DISPLAY_ON      0x0010
+#define PCMCIA_BUFF_DIS 0x0020
+#define MQ_RESET        0x0040
+#define PCMCIA_RESET    0x0080
+#define DECT_POWER_ON   0x0100
+#define IRDA_SD         0x0200 // Shutdown for powersave
+#define RS232_ON        0x0400
+#define SD_MEDIAQ       0x0800 // Shutdown for powersave
+#define LED2_ON         0x1000
+#define IRDA_MODE       0x2000 // Fast/Slow IrDA mode
+#define ENABLE_5V       0x4000 // Enable 5V circuit
+#define RESET_SIMCARD   0x8000
+
+#define RS232_ENABLE    0x0440
+#define PCMCIAMASK      0x402f
+
+
+struct simpad_battery {
+        unsigned char ac_status;        /* line connected yes/no */
+        unsigned char status;           /* battery loading yes/no */
+        unsigned char percentage;       /* percentage loaded */
+        unsigned short life;            /* life till empty */
+};
+
+/* These should match the apm_bios.h definitions */
+#define SIMPAD_AC_STATUS_AC_OFFLINE      0x00
+#define SIMPAD_AC_STATUS_AC_ONLINE       0x01
+#define SIMPAD_AC_STATUS_AC_BACKUP       0x02   /* What does this mean? */
+#define SIMPAD_AC_STATUS_AC_UNKNOWN      0xff
+
+/* These bitfields are rarely "or'd" together */
+#define SIMPAD_BATT_STATUS_HIGH          0x01
+#define SIMPAD_BATT_STATUS_LOW           0x02
+#define SIMPAD_BATT_STATUS_CRITICAL      0x04
+#define SIMPAD_BATT_STATUS_CHARGING      0x08
+#define SIMPAD_BATT_STATUS_CHARGE_MAIN   0x10
+#define SIMPAD_BATT_STATUS_DEAD          0x20   /* Battery will not charge */
+#define SIMPAD_BATT_NOT_INSTALLED        0x20   /* For expansion pack batteries */
+#define SIMPAD_BATT_STATUS_FULL          0x40   /* Battery fully charged (and connected to AC) */
+#define SIMPAD_BATT_STATUS_NOBATT        0x80
+#define SIMPAD_BATT_STATUS_UNKNOWN       0xff
+
+extern int simpad_get_battery(struct simpad_battery* );
+
+#endif // __ASM_ARCH_SIMPAD_H
+
+
+
+
+
+
+
+
diff --git a/include/asm-arm/arch-sa1100/system.h b/include/asm-arm/arch-sa1100/system.h
new file mode 100644
index 000000000000..6f52118ba1a4
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/system.h
@@ -0,0 +1,22 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/system.h
+ *
+ * Copyright (c) 1999 Nicolas Pitre <nico@cam.org>
+ */
+#include <linux/config.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        if (mode == 's') {
+                /* Jump into ROM at address 0 */
+                cpu_reset(0);
+        } else {
+                /* Use on-chip reset capability */
+                RSRR = RSRR_SWR;
+        }
+}
diff --git a/include/asm-arm/arch-sa1100/timex.h b/include/asm-arm/arch-sa1100/timex.h
new file mode 100644
index 000000000000..837be9b797dd
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/timex.h
@@ -0,0 +1,12 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/timex.h
+ *
+ * SA1100 architecture timex specifications
+ *
+ * Copyright (C) 1998 
+ */
+
+/*
+ * SA1100 timer
+ */
+#define CLOCK_TICK_RATE         3686400
diff --git a/include/asm-arm/arch-sa1100/uncompress.h b/include/asm-arm/arch-sa1100/uncompress.h
new file mode 100644
index 000000000000..43453501ee66
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/uncompress.h
@@ -0,0 +1,53 @@
+/*
+ * linux/include/asm-arm/arch-brutus/uncompress.h
+ *
+ * (C) 1999 Nicolas Pitre <nico@cam.org>
+ *
+ * Reorganised to be machine independent.
+ */
+
+#include "hardware.h"
+
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ */
+
+#define UART(x)         (*(volatile unsigned long *)(serial_port + (x)))
+
+static void putstr( const char *s )
+{
+        unsigned long serial_port;
+
+        do {
+                serial_port = _Ser3UTCR0;
+                if (UART(UTCR3) & UTCR3_TXE) break;
+                serial_port = _Ser1UTCR0;
+                if (UART(UTCR3) & UTCR3_TXE) break;
+                serial_port = _Ser2UTCR0;
+                if (UART(UTCR3) & UTCR3_TXE) break;
+                return;
+        } while (0);
+
+        for (; *s; s++) {
+                /* wait for space in the UART's transmitter */
+                while (!(UART(UTSR1) & UTSR1_TNF));
+
+                /* send the character out. */
+                UART(UTDR) = *s;
+
+                /* if a LF, also do CR... */
+                if (*s == 10) {
+                        while (!(UART(UTSR1) & UTSR1_TNF));
+                        UART(UTDR) = 13;
+                }
+        }
+}
+
+/*
+ * Nothing to do for these
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-sa1100/vmalloc.h b/include/asm-arm/arch-sa1100/vmalloc.h
new file mode 100644
index 000000000000..135bc9493c06
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/vmalloc.h
@@ -0,0 +1,15 @@
+/*
+ * linux/include/asm-arm/arch-sa1100/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (0xe8000000)
diff --git a/include/asm-arm/arch-shark/debug-macro.S b/include/asm-arm/arch-shark/debug-macro.S
new file mode 100644
index 000000000000..7cb37f78825e
--- /dev/null
+++ b/include/asm-arm/arch-shark/debug-macro.S
@@ -0,0 +1,31 @@
+/* linux/include/asm-arm/arch-shark/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+                .macro  addruart,rx
+                mov     \rx, #0xe0000000
+                orr     \rx, \rx, #0x000003f8
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx]
+                .endm
+
+                .macro  busyuart,rd,rx
+                mov     \rd, #0
+1001:           add     \rd, \rd, #1
+                teq     \rd, #0x10000
+                bne     1001b
+                .endm
+
+                .macro  waituart,rd,rx
+                .endm
diff --git a/include/asm-arm/arch-shark/dma.h b/include/asm-arm/arch-shark/dma.h
new file mode 100644
index 000000000000..fc985d5e62af
--- /dev/null
+++ b/include/asm-arm/arch-shark/dma.h
@@ -0,0 +1,18 @@
+/*
+ * linux/include/asm-arm/arch-shark/dma.h
+ *
+ * by Alexander Schulz
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+/* Use only the lowest 4MB, nothing else works.
+ * The rest is not DMAable. See dev /  .properties
+ * in OpenFirmware.
+ */
+#define MAX_DMA_ADDRESS         0xC0400000
+#define MAX_DMA_CHANNELS        8
+#define DMA_ISA_CASCADE         4
+
+#endif /* _ASM_ARCH_DMA_H */
+
diff --git a/include/asm-arm/arch-shark/entry-macro.S b/include/asm-arm/arch-shark/entry-macro.S
new file mode 100644
index 000000000000..a924f27fb8d9
--- /dev/null
+++ b/include/asm-arm/arch-shark/entry-macro.S
@@ -0,0 +1,35 @@
+/*
+ * include/asm-arm/arch-shark/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Shark platform
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+                .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     r4, #0xe0000000
+
+                mov     \irqstat, #0x0C
+                strb    \irqstat, [r4, #0x20]           @outb(0x0C, 0x20) /* Poll command */
+                ldrb    \irqnr, [r4, #0x20]             @irq = inb(0x20) & 7
+                and     \irqstat, \irqnr, #0x80
+                teq     \irqstat, #0
+                beq     43f
+                and     \irqnr, \irqnr, #7
+                teq     \irqnr, #2
+                bne     44f
+43:             mov     \irqstat, #0x0C
+                strb    \irqstat, [r4, #0xa0]           @outb(0x0C, 0xA0) /* Poll command */
+                ldrb    \irqnr, [r4, #0xa0]             @irq = (inb(0xA0) & 7) + 8
+                and     \irqstat, \irqnr, #0x80
+                teq     \irqstat, #0
+                beq     44f
+                and     \irqnr, \irqnr, #7
+                add     \irqnr, \irqnr, #8
+44:             teq     \irqstat, #0
+                .endm
+
diff --git a/include/asm-arm/arch-shark/hardware.h b/include/asm-arm/arch-shark/hardware.h
new file mode 100644
index 000000000000..4d35f8c154c3
--- /dev/null
+++ b/include/asm-arm/arch-shark/hardware.h
@@ -0,0 +1,57 @@
+/*
+ * linux/include/asm-arm/arch-shark/hardware.h
+ *
+ * by Alexander Schulz
+ *
+ * derived from:
+ * linux/include/asm-arm/arch-ebsa110/hardware.h
+ * Copyright (C) 1996-1999 Russell King.
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Mapping areas
+ */
+#define IO_BASE                 0xe0000000
+
+/*
+ * RAM definitions
+ */
+#define FLUSH_BASE_PHYS         0x80000000
+
+#else
+
+#define IO_BASE                 0
+
+#endif
+
+#define IO_SIZE                 0x08000000
+#define IO_START                0x40000000
+#define ROMCARD_SIZE            0x08000000
+#define ROMCARD_START           0x10000000
+
+#define FLUSH_BASE              0xdf000000
+#define PCIO_BASE               0xe0000000
+
+
+/* defines for the Framebuffer */
+#define FB_START                0x06000000
+#define FB_SIZE                 0x01000000
+
+#define UNCACHEABLE_ADDR        0xdf010000
+
+#define SEQUOIA_LED_GREEN       (1<<6)
+#define SEQUOIA_LED_AMBER       (1<<5)
+#define SEQUOIA_LED_BACK        (1<<7)
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x6000
+#define PCIBIOS_MIN_MEM         0x50000000
+#define PCIMEM_BASE             0xe8000000
+
+#endif
+
diff --git a/include/asm-arm/arch-shark/io.h b/include/asm-arm/arch-shark/io.h
new file mode 100644
index 000000000000..1e7f26bc2e1d
--- /dev/null
+++ b/include/asm-arm/arch-shark/io.h
@@ -0,0 +1,199 @@
+/*
+ * linux/include/asm-arm/arch-shark/io.h
+ *
+ * by Alexander Schulz
+ *
+ * derived from:
+ * linux/include/asm-arm/arch-ebsa110/io.h
+ * Copyright (C) 1997,1998 Russell King
+ */
+
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/*
+ * We use two different types of addressing - PC style addresses, and ARM
+ * addresses.  PC style accesses the PC hardware with the normal PC IO
+ * addresses, eg 0x3f8 for serial#1.  ARM addresses are 0x80000000+
+ * and are translated to the start of IO.
+ */
+#define __PORT_PCIO(x)  (!((x) & 0x80000000))
+
+/*
+ * Dynamic IO functions - let the compiler
+ * optimize the expressions
+ */
+#define DECLARE_DYN_OUT(fnsuffix,instr)                                         \
+static inline void __out##fnsuffix (unsigned int value, unsigned int port)      \
+{                                                                               \
+        unsigned long temp;                                                     \
+        __asm__ __volatile__(                                                   \
+        "tst    %2, #0x80000000\n\t"                                            \
+        "mov    %0, %4\n\t"                                                     \
+        "addeq  %0, %0, %3\n\t"                                                 \
+        "str" instr "   %1, [%0, %2]    @ out" #fnsuffix                        \
+        : "=&r" (temp)                                                          \
+        : "r" (value), "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)   \
+        : "cc");                                                                \
+}
+
+#define DECLARE_DYN_IN(sz,fnsuffix,instr)                                       \
+static inline unsigned sz __in##fnsuffix (unsigned int port)            \
+{                                                                               \
+        unsigned long temp, value;                                              \
+        __asm__ __volatile__(                                                   \
+        "tst    %2, #0x80000000\n\t"                                            \
+        "mov    %0, %4\n\t"                                                     \
+        "addeq  %0, %0, %3\n\t"                                                 \
+        "ldr" instr "   %1, [%0, %2]    @ in" #fnsuffix                         \
+        : "=&r" (temp), "=r" (value)                                            \
+        : "r" (port), "Ir" (PCIO_BASE - IO_BASE), "Ir" (IO_BASE)                \
+        : "cc");                                                                \
+        return (unsigned sz)value;                                              \
+}
+
+static inline unsigned int __ioaddr (unsigned int port)                 \
+{                                                                               \
+        if (__PORT_PCIO(port))                                                  \
+                return (unsigned int)(PCIO_BASE + (port));                      \
+        else                                                                    \
+                return (unsigned int)(IO_BASE + (port));                        \
+}
+
+#define DECLARE_IO(sz,fnsuffix,instr)   \
+        DECLARE_DYN_OUT(fnsuffix,instr) \
+        DECLARE_DYN_IN(sz,fnsuffix,instr)
+
+DECLARE_IO(char,b,"b")
+DECLARE_IO(short,w,"h")
+DECLARE_IO(long,l,"")
+
+#undef DECLARE_IO
+#undef DECLARE_DYN_OUT
+#undef DECLARE_DYN_IN
+
+/*
+ * Constant address IO functions
+ *
+ * These have to be macros for the 'J' constraint to work -
+ * +/-4096 immediate operand.
+ */
+#define __outbc(value,port)                                                     \
+({                                                                              \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]            @ outbc"                        \
+                : : "r" (value), "r" (PCIO_BASE), "Jr" (port));         \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "strb   %0, [%1, %2]            @ outbc"                        \
+                : : "r" (value), "r" (IO_BASE), "r" (port));            \
+})
+
+#define __inbc(port)                                                            \
+({                                                                              \
+        unsigned char result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]            @ inbc"                         \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldrb   %0, [%1, %2]            @ inbc"                         \
+                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
+        result;                                                                 \
+})
+
+#define __outwc(value,port)                                                     \
+({                                                                              \
+        unsigned long v = value;                                                \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "strh   %0, [%1, %2]            @ outwc"                        \
+                : : "r" (v|v<<16), "r" (PCIO_BASE), "Jr" (port));       \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "strh   %0, [%1, %2]            @ outwc"                        \
+                : : "r" (v|v<<16), "r" (IO_BASE), "r" (port));          \
+})
+
+#define __inwc(port)                                                            \
+({                                                                              \
+        unsigned short result;                                                  \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldrh   %0, [%1, %2]            @ inwc"                         \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldrh   %0, [%1, %2]            @ inwc"                         \
+                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
+        result & 0xffff;                                                        \
+})
+
+#define __outlc(value,port)                                                             \
+({                                                                              \
+        unsigned long v = value;                                                \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]            @ outlc"                        \
+                : : "r" (v), "r" (PCIO_BASE), "Jr" (port));             \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "str    %0, [%1, %2]            @ outlc"                        \
+                : : "r" (v), "r" (IO_BASE), "r" (port));                        \
+})
+
+#define __inlc(port)                                                            \
+({                                                                              \
+        unsigned long result;                                                   \
+        if (__PORT_PCIO((port)))                                                \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]            @ inlc"                         \
+                : "=r" (result) : "r" (PCIO_BASE), "Jr" (port));                \
+        else                                                                    \
+                __asm__ __volatile__(                                           \
+                "ldr    %0, [%1, %2]            @ inlc"                         \
+                : "=r" (result) : "r" (IO_BASE), "r" (port));           \
+        result;                                                                 \
+})
+
+#define __ioaddrc(port)                                                         \
+({                                                                              \
+        unsigned long addr;                                                     \
+        if (__PORT_PCIO((port)))                                                \
+                addr = PCIO_BASE + (port);                              \
+        else                                                                    \
+                addr = IO_BASE + (port);                                        \
+        addr;                                                                   \
+})
+
+#define __mem_pci(addr) (addr)
+
+#define inb(p)          (__builtin_constant_p((p)) ? __inbc(p)    : __inb(p))
+#define inw(p)          (__builtin_constant_p((p)) ? __inwc(p)    : __inw(p))
+#define inl(p)          (__builtin_constant_p((p)) ? __inlc(p)    : __inl(p))
+#define outb(v,p)       (__builtin_constant_p((p)) ? __outbc(v,p) : __outb(v,p))
+#define outw(v,p)       (__builtin_constant_p((p)) ? __outwc(v,p) : __outw(v,p))
+#define outl(v,p)       (__builtin_constant_p((p)) ? __outlc(v,p) : __outl(v,p))
+
+/*
+ * Translated address IO functions
+ *
+ * IO address has already been translated to a virtual address
+ */
+#define outb_t(v,p)                                                             \
+        (*(volatile unsigned char *)(p) = (v))
+
+#define inb_t(p)                                                                \
+        (*(volatile unsigned char *)(p))
+
+#define outl_t(v,p)                                                             \
+        (*(volatile unsigned long *)(p) = (v))
+
+#define inl_t(p)                                                                \
+        (*(volatile unsigned long *)(p))
+
+#endif
diff --git a/include/asm-arm/arch-shark/irqs.h b/include/asm-arm/arch-shark/irqs.h
new file mode 100644
index 000000000000..b36cc975b290
--- /dev/null
+++ b/include/asm-arm/arch-shark/irqs.h
@@ -0,0 +1,13 @@
+/*
+ * linux/include/asm-arm/arch-shark/irqs.h
+ *
+ * by Alexander Schulz
+ */
+
+#define NR_IRQS                 16
+
+#define IRQ_ISA_KEYBOARD         1
+#define RTC_IRQ                  8
+#define I8042_KBD_IRQ            1
+#define I8042_AUX_IRQ           12
+#define IRQ_HARDDISK            14
diff --git a/include/asm-arm/arch-shark/memory.h b/include/asm-arm/arch-shark/memory.h
new file mode 100644
index 000000000000..8ff956d25463
--- /dev/null
+++ b/include/asm-arm/arch-shark/memory.h
@@ -0,0 +1,42 @@
+/*
+ * linux/include/asm-arm/arch-shark/memory.h
+ *
+ * by Alexander Schulz
+ *
+ * derived from:
+ * linux/include/asm-arm/arch-ebsa110/memory.h
+ * Copyright (c) 1996-1999 Russell King.
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#include <asm/sizes.h>
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x08000000UL)
+
+#ifndef __ASSEMBLY__
+
+static inline void __arch_adjust_zones(int node, unsigned long *zone_size, unsigned long *zhole_size) 
+{
+  if (node != 0) return;
+  /* Only the first 4 MB (=1024 Pages) are usable for DMA */
+  zone_size[1] = zone_size[0] - 1024;
+  zone_size[0] = 1024;
+  zhole_size[1] = zhole_size[0];
+  zhole_size[0] = 0;
+}
+
+#define arch_adjust_zones(node, size, holes) \
+        __arch_adjust_zones(node, size, holes)
+
+#define ISA_DMA_THRESHOLD       (PHYS_OFFSET + SZ_4M - 1)
+
+#endif
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+#endif
diff --git a/include/asm-arm/arch-shark/param.h b/include/asm-arm/arch-shark/param.h
new file mode 100644
index 000000000000..997eeb71de00
--- /dev/null
+++ b/include/asm-arm/arch-shark/param.h
@@ -0,0 +1,5 @@
+/*
+ *  linux/include/asm-arm/arch-shark/param.h
+ *
+ * by Alexander Schulz
+ */
diff --git a/include/asm-arm/arch-shark/system.h b/include/asm-arm/arch-shark/system.h
new file mode 100644
index 000000000000..f12d771ab4ce
--- /dev/null
+++ b/include/asm-arm/arch-shark/system.h
@@ -0,0 +1,28 @@
+/*
+ * linux/include/asm-arm/arch-shark/system.h
+ *
+ * by Alexander Schulz
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/io.h>
+
+static void arch_reset(char mode)
+{
+        short temp;
+        local_irq_disable();
+        /* Reset the Machine via pc[3] of the sequoia chipset */
+        outw(0x09,0x24);
+        temp=inw(0x26);
+        temp = temp | (1<<3) | (1<<10);
+        outw(0x09,0x24);
+        outw(temp,0x26);
+
+}
+
+static inline void arch_idle(void)
+{
+}
+
+#endif
diff --git a/include/asm-arm/arch-shark/timex.h b/include/asm-arm/arch-shark/timex.h
new file mode 100644
index 000000000000..0d02d255513b
--- /dev/null
+++ b/include/asm-arm/arch-shark/timex.h
@@ -0,0 +1,7 @@
+/*
+ * linux/include/asm-arm/arch-shark/timex.h
+ *
+ * by Alexander Schulz
+ */
+
+#define CLOCK_TICK_RATE 1193180
diff --git a/include/asm-arm/arch-shark/uncompress.h b/include/asm-arm/arch-shark/uncompress.h
new file mode 100644
index 000000000000..910a8e0a0ca5
--- /dev/null
+++ b/include/asm-arm/arch-shark/uncompress.h
@@ -0,0 +1,60 @@
+/*
+ * linux/include/asm-arm/arch-shark/uncompress.h
+ * by Alexander Schulz
+ *
+ * derived from:
+ * linux/include/asm-arm/arch-ebsa285/uncompress.h
+ * Copyright (C) 1996,1997,1998 Russell King
+ */
+
+#define SERIAL_BASE ((volatile unsigned char *)0x400003f8)
+
+static __inline__ void putc(char c)
+{
+        int t;
+
+        SERIAL_BASE[0] = c;
+        t=0x10000;
+        while (t--);
+}
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                putc(*s);
+                if (*s == '\n')
+                        putc('\r');
+                s++;
+        }
+}
+
+#ifdef DEBUG
+static void putn(unsigned long z)
+{
+        int i;
+        char x;
+
+        putc('0');
+        putc('x');
+        for (i=0;i<8;i++) {
+                x='0'+((z>>((7-i)*4))&0xf);
+                if (x>'9') x=x-'0'+'A'-10;
+                putc(x);
+        }
+}
+
+static void putr()
+{
+        putc('\n');
+        putc('\r');
+}
+#endif
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-shark/vmalloc.h b/include/asm-arm/arch-shark/vmalloc.h
new file mode 100644
index 000000000000..1cc20098f690
--- /dev/null
+++ b/include/asm-arm/arch-shark/vmalloc.h
@@ -0,0 +1,15 @@
+/*
+ * linux/include/asm-arm/arch-rpc/vmalloc.h
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET    (8*1024*1024)
+#define VMALLOC_START     (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_END       (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-versatile/debug-macro.S b/include/asm-arm/arch-versatile/debug-macro.S
new file mode 100644
index 000000000000..89e38ac1444e
--- /dev/null
+++ b/include/asm-arm/arch-versatile/debug-macro.S
@@ -0,0 +1,39 @@
+/* linux/include/asm-arm/arch-versatile/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ *  Copyright (C) 1994-1999 Russell King
+ *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+*/
+
+#include <asm/hardware/amba_serial.h>
+
+                .macro  addruart,rx
+                mrc     p15, 0, \rx, c1, c0
+                tst     \rx, #1                 @ MMU enabled?
+                moveq   \rx,      #0x10000000
+                movne   \rx,      #0xf1000000   @ virtual base
+                orr     \rx, \rx, #0x001F0000
+                orr     \rx, \rx, #0x00001000
+                .endm
+
+                .macro  senduart,rd,rx
+                strb    \rd, [\rx, #UART01x_DR]
+                .endm
+
+                .macro  waituart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
+                bne     1001b
+                .endm
+
+                .macro  busyuart,rd,rx
+1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
+                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
+                bne     1001b
+                .endm
diff --git a/include/asm-arm/arch-versatile/dma.h b/include/asm-arm/arch-versatile/dma.h
new file mode 100644
index 000000000000..dcc8ac26eac0
--- /dev/null
+++ b/include/asm-arm/arch-versatile/dma.h
@@ -0,0 +1,27 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/dma.h
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_DMA_H
+#define __ASM_ARCH_DMA_H
+
+#define MAX_DMA_ADDRESS         0xffffffff
+#define MAX_DMA_CHANNELS        0
+
+#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S
new file mode 100644
index 000000000000..90e4e970d253
--- /dev/null
+++ b/include/asm-arm/arch-versatile/entry-macro.S
@@ -0,0 +1,35 @@
+/*
+ * include/asm-arm/arch-versatile/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Versatile platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+                        .macro  disable_fiq
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                ldr     \base, =IO_ADDRESS(VERSATILE_VIC_BASE)
+                ldr     \irqstat, [\base, #VIC_IRQ_STATUS]      @ get masked status
+                mov     \irqnr, #0
+                teq     \irqstat, #0
+                beq     1003f
+
+1001:           tst     \irqstat, #15
+                bne     1002f
+                add     \irqnr, \irqnr, #4
+                movs    \irqstat, \irqstat, lsr #4
+                bne     1001b
+1002:           tst     \irqstat, #1
+                bne     1003f
+                add     \irqnr, \irqnr, #1
+                movs    \irqstat, \irqstat, lsr #1
+                bne     1002b
+1003:           /* EQ will be set if no irqs pending */
+
+@               clz     \irqnr, \irqstat
+@1003:          /* EQ will be set if we reach MAXIRQNUM */
+                .endm
+
diff --git a/include/asm-arm/arch-versatile/hardware.h b/include/asm-arm/arch-versatile/hardware.h
new file mode 100644
index 000000000000..d5fb4a251e7f
--- /dev/null
+++ b/include/asm-arm/arch-versatile/hardware.h
@@ -0,0 +1,45 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/hardware.h
+ *
+ *  This file contains the hardware definitions of the Versatile boards.
+ *
+ *  Copyright (C) 2003 ARM Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <asm/sizes.h>
+#include <asm/arch/platform.h>
+
+// FIXME = PCI settings need to be fixed!!!!!
+
+/*
+ * Similar to above, but for PCI addresses (memory, IO, Config and the
+ * V3 chip itself).  WARNING: this has to mirror definitions in platform.h
+ */
+#define PCI_MEMORY_VADDR       0xe8000000
+#define PCI_CONFIG_VADDR       0xec000000
+#define PCI_V3_VADDR           0xed000000
+#define PCI_IO_VADDR           0xee000000
+
+#define PCIO_BASE               PCI_IO_VADDR
+#define PCIMEM_BASE             PCI_MEMORY_VADDR
+
+/* macro to get at IO space when running virtually */
+#define IO_ADDRESS(x)           (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
+
+#endif
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h
new file mode 100644
index 000000000000..dbb7158788fc
--- /dev/null
+++ b/include/asm-arm/arch-versatile/io.h
@@ -0,0 +1,29 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/io.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+#define IO_SPACE_LIMIT 0xffff
+
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#define __mem_isa(a)            (a)
+
+#endif
diff --git a/include/asm-arm/arch-versatile/irqs.h b/include/asm-arm/arch-versatile/irqs.h
new file mode 100644
index 000000000000..745aa841b31a
--- /dev/null
+++ b/include/asm-arm/arch-versatile/irqs.h
@@ -0,0 +1,211 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/irqs.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <asm/arch/platform.h>
+
+/* 
+ *  IRQ interrupts definitions are the same the INT definitions
+ *  held within platform.h
+ */
+#define IRQ_VIC_START           0
+#define IRQ_WDOGINT             (IRQ_VIC_START + INT_WDOGINT)
+#define IRQ_SOFTINT             (IRQ_VIC_START + INT_SOFTINT)
+#define IRQ_COMMRx              (IRQ_VIC_START + INT_COMMRx)
+#define IRQ_COMMTx              (IRQ_VIC_START + INT_COMMTx)
+#define IRQ_TIMERINT0_1         (IRQ_VIC_START + INT_TIMERINT0_1)
+#define IRQ_TIMERINT2_3         (IRQ_VIC_START + INT_TIMERINT2_3)
+#define IRQ_GPIOINT0            (IRQ_VIC_START + INT_GPIOINT0)
+#define IRQ_GPIOINT1            (IRQ_VIC_START + INT_GPIOINT1)
+#define IRQ_GPIOINT2            (IRQ_VIC_START + INT_GPIOINT2)
+#define IRQ_GPIOINT3            (IRQ_VIC_START + INT_GPIOINT3)
+#define IRQ_RTCINT              (IRQ_VIC_START + INT_RTCINT)
+#define IRQ_SSPINT              (IRQ_VIC_START + INT_SSPINT)
+#define IRQ_UARTINT0            (IRQ_VIC_START + INT_UARTINT0)
+#define IRQ_UARTINT1            (IRQ_VIC_START + INT_UARTINT1)
+#define IRQ_UARTINT2            (IRQ_VIC_START + INT_UARTINT2)
+#define IRQ_SCIINT              (IRQ_VIC_START + INT_SCIINT)
+#define IRQ_CLCDINT             (IRQ_VIC_START + INT_CLCDINT)
+#define IRQ_DMAINT              (IRQ_VIC_START + INT_DMAINT)
+#define IRQ_PWRFAILINT          (IRQ_VIC_START + INT_PWRFAILINT)
+#define IRQ_MBXINT              (IRQ_VIC_START + INT_MBXINT)
+#define IRQ_GNDINT              (IRQ_VIC_START + INT_GNDINT)
+#define IRQ_VICSOURCE21         (IRQ_VIC_START + INT_VICSOURCE21)
+#define IRQ_VICSOURCE22         (IRQ_VIC_START + INT_VICSOURCE22)
+#define IRQ_VICSOURCE23         (IRQ_VIC_START + INT_VICSOURCE23)
+#define IRQ_VICSOURCE24         (IRQ_VIC_START + INT_VICSOURCE24)
+#define IRQ_VICSOURCE25         (IRQ_VIC_START + INT_VICSOURCE25)
+#define IRQ_VICSOURCE26         (IRQ_VIC_START + INT_VICSOURCE26)
+#define IRQ_VICSOURCE27         (IRQ_VIC_START + INT_VICSOURCE27)
+#define IRQ_VICSOURCE28         (IRQ_VIC_START + INT_VICSOURCE28)
+#define IRQ_VICSOURCE29         (IRQ_VIC_START + INT_VICSOURCE29)
+#define IRQ_VICSOURCE30         (IRQ_VIC_START + INT_VICSOURCE30)
+#define IRQ_VICSOURCE31         (IRQ_VIC_START + INT_VICSOURCE31)
+#define IRQ_VIC_END             (IRQ_VIC_START + 31)
+
+#define IRQMASK_WDOGINT         INTMASK_WDOGINT
+#define IRQMASK_SOFTINT         INTMASK_SOFTINT
+#define IRQMASK_COMMRx          INTMASK_COMMRx
+#define IRQMASK_COMMTx          INTMASK_COMMTx
+#define IRQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
+#define IRQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
+#define IRQMASK_GPIOINT0        INTMASK_GPIOINT0
+#define IRQMASK_GPIOINT1        INTMASK_GPIOINT1
+#define IRQMASK_GPIOINT2        INTMASK_GPIOINT2
+#define IRQMASK_GPIOINT3        INTMASK_GPIOINT3
+#define IRQMASK_RTCINT          INTMASK_RTCINT
+#define IRQMASK_SSPINT          INTMASK_SSPINT
+#define IRQMASK_UARTINT0        INTMASK_UARTINT0
+#define IRQMASK_UARTINT1        INTMASK_UARTINT1
+#define IRQMASK_UARTINT2        INTMASK_UARTINT2
+#define IRQMASK_SCIINT          INTMASK_SCIINT
+#define IRQMASK_CLCDINT         INTMASK_CLCDINT
+#define IRQMASK_DMAINT          INTMASK_DMAINT
+#define IRQMASK_PWRFAILINT      INTMASK_PWRFAILINT
+#define IRQMASK_MBXINT          INTMASK_MBXINT
+#define IRQMASK_GNDINT          INTMASK_GNDINT
+#define IRQMASK_VICSOURCE21     INTMASK_VICSOURCE21
+#define IRQMASK_VICSOURCE22     INTMASK_VICSOURCE22
+#define IRQMASK_VICSOURCE23     INTMASK_VICSOURCE23
+#define IRQMASK_VICSOURCE24     INTMASK_VICSOURCE24
+#define IRQMASK_VICSOURCE25     INTMASK_VICSOURCE25
+#define IRQMASK_VICSOURCE26     INTMASK_VICSOURCE26
+#define IRQMASK_VICSOURCE27     INTMASK_VICSOURCE27
+#define IRQMASK_VICSOURCE28     INTMASK_VICSOURCE28
+#define IRQMASK_VICSOURCE29     INTMASK_VICSOURCE29
+#define IRQMASK_VICSOURCE30     INTMASK_VICSOURCE30
+#define IRQMASK_VICSOURCE31     INTMASK_VICSOURCE31
+
+/* 
+ *  FIQ interrupts definitions are the same the INT definitions.
+ */
+#define FIQ_WDOGINT             INT_WDOGINT
+#define FIQ_SOFTINT             INT_SOFTINT
+#define FIQ_COMMRx              INT_COMMRx
+#define FIQ_COMMTx              INT_COMMTx
+#define FIQ_TIMERINT0_1         INT_TIMERINT0_1
+#define FIQ_TIMERINT2_3         INT_TIMERINT2_3
+#define FIQ_GPIOINT0            INT_GPIOINT0
+#define FIQ_GPIOINT1            INT_GPIOINT1
+#define FIQ_GPIOINT2            INT_GPIOINT2
+#define FIQ_GPIOINT3            INT_GPIOINT3
+#define FIQ_RTCINT              INT_RTCINT
+#define FIQ_SSPINT              INT_SSPINT
+#define FIQ_UARTINT0            INT_UARTINT0
+#define FIQ_UARTINT1            INT_UARTINT1
+#define FIQ_UARTINT2            INT_UARTINT2
+#define FIQ_SCIINT              INT_SCIINT
+#define FIQ_CLCDINT             INT_CLCDINT
+#define FIQ_DMAINT              INT_DMAINT
+#define FIQ_PWRFAILINT          INT_PWRFAILINT
+#define FIQ_MBXINT              INT_MBXINT
+#define FIQ_GNDINT              INT_GNDINT
+#define FIQ_VICSOURCE21         INT_VICSOURCE21
+#define FIQ_VICSOURCE22         INT_VICSOURCE22
+#define FIQ_VICSOURCE23         INT_VICSOURCE23
+#define FIQ_VICSOURCE24         INT_VICSOURCE24
+#define FIQ_VICSOURCE25         INT_VICSOURCE25
+#define FIQ_VICSOURCE26         INT_VICSOURCE26
+#define FIQ_VICSOURCE27         INT_VICSOURCE27
+#define FIQ_VICSOURCE28         INT_VICSOURCE28
+#define FIQ_VICSOURCE29         INT_VICSOURCE29
+#define FIQ_VICSOURCE30         INT_VICSOURCE30
+#define FIQ_VICSOURCE31         INT_VICSOURCE31
+
+
+#define FIQMASK_WDOGINT         INTMASK_WDOGINT
+#define FIQMASK_SOFTINT         INTMASK_SOFTINT
+#define FIQMASK_COMMRx          INTMASK_COMMRx
+#define FIQMASK_COMMTx          INTMASK_COMMTx
+#define FIQMASK_TIMERINT0_1     INTMASK_TIMERINT0_1
+#define FIQMASK_TIMERINT2_3     INTMASK_TIMERINT2_3
+#define FIQMASK_GPIOINT0        INTMASK_GPIOINT0
+#define FIQMASK_GPIOINT1        INTMASK_GPIOINT1
+#define FIQMASK_GPIOINT2        INTMASK_GPIOINT2
+#define FIQMASK_GPIOINT3        INTMASK_GPIOINT3
+#define FIQMASK_RTCINT          INTMASK_RTCINT
+#define FIQMASK_SSPINT          INTMASK_SSPINT
+#define FIQMASK_UARTINT0        INTMASK_UARTINT0
+#define FIQMASK_UARTINT1        INTMASK_UARTINT1
+#define FIQMASK_UARTINT2        INTMASK_UARTINT2
+#define FIQMASK_SCIINT          INTMASK_SCIINT
+#define FIQMASK_CLCDINT         INTMASK_CLCDINT
+#define FIQMASK_DMAINT          INTMASK_DMAINT
+#define FIQMASK_PWRFAILINT      INTMASK_PWRFAILINT
+#define FIQMASK_MBXINT          INTMASK_MBXINT
+#define FIQMASK_GNDINT          INTMASK_GNDINT
+#define FIQMASK_VICSOURCE21     INTMASK_VICSOURCE21
+#define FIQMASK_VICSOURCE22     INTMASK_VICSOURCE22
+#define FIQMASK_VICSOURCE23     INTMASK_VICSOURCE23
+#define FIQMASK_VICSOURCE24     INTMASK_VICSOURCE24
+#define FIQMASK_VICSOURCE25     INTMASK_VICSOURCE25
+#define FIQMASK_VICSOURCE26     INTMASK_VICSOURCE26
+#define FIQMASK_VICSOURCE27     INTMASK_VICSOURCE27
+#define FIQMASK_VICSOURCE28     INTMASK_VICSOURCE28
+#define FIQMASK_VICSOURCE29     INTMASK_VICSOURCE29
+#define FIQMASK_VICSOURCE30     INTMASK_VICSOURCE30
+#define FIQMASK_VICSOURCE31     INTMASK_VICSOURCE31
+
+/*
+ * Secondary interrupt controller
+ */
+#define IRQ_SIC_START           32
+#define IRQ_SIC_MMCI0B          (IRQ_SIC_START + SIC_INT_MMCI0B)
+#define IRQ_SIC_MMCI1B          (IRQ_SIC_START + SIC_INT_MMCI1B)
+#define IRQ_SIC_KMI0            (IRQ_SIC_START + SIC_INT_KMI0)
+#define IRQ_SIC_KMI1            (IRQ_SIC_START + SIC_INT_KMI1)
+#define IRQ_SIC_SCI3            (IRQ_SIC_START + SIC_INT_SCI3)
+#define IRQ_SIC_UART3           (IRQ_SIC_START + SIC_INT_UART3)
+#define IRQ_SIC_CLCD            (IRQ_SIC_START + SIC_INT_CLCD)
+#define IRQ_SIC_TOUCH           (IRQ_SIC_START + SIC_INT_TOUCH)
+#define IRQ_SIC_KEYPAD          (IRQ_SIC_START + SIC_INT_KEYPAD)
+#define IRQ_SIC_DoC             (IRQ_SIC_START + SIC_INT_DoC)
+#define IRQ_SIC_MMCI0A          (IRQ_SIC_START + SIC_INT_MMCI0A)
+#define IRQ_SIC_MMCI1A          (IRQ_SIC_START + SIC_INT_MMCI1A)
+#define IRQ_SIC_AACI            (IRQ_SIC_START + SIC_INT_AACI)
+#define IRQ_SIC_ETH             (IRQ_SIC_START + SIC_INT_ETH)
+#define IRQ_SIC_USB             (IRQ_SIC_START + SIC_INT_USB)
+#define IRQ_SIC_PCI0            (IRQ_SIC_START + SIC_INT_PCI0)
+#define IRQ_SIC_PCI1            (IRQ_SIC_START + SIC_INT_PCI1)
+#define IRQ_SIC_PCI2            (IRQ_SIC_START + SIC_INT_PCI2)
+#define IRQ_SIC_PCI3            (IRQ_SIC_START + SIC_INT_PCI3)
+#define IRQ_SIC_END             63
+
+#define SIC_IRQMASK_MMCI0B      SIC_INTMASK_MMCI0B
+#define SIC_IRQMASK_MMCI1B      SIC_INTMASK_MMCI1B
+#define SIC_IRQMASK_KMI0        SIC_INTMASK_KMI0
+#define SIC_IRQMASK_KMI1        SIC_INTMASK_KMI1
+#define SIC_IRQMASK_SCI3        SIC_INTMASK_SCI3
+#define SIC_IRQMASK_UART3       SIC_INTMASK_UART3
+#define SIC_IRQMASK_CLCD        SIC_INTMASK_CLCD
+#define SIC_IRQMASK_TOUCH       SIC_INTMASK_TOUCH
+#define SIC_IRQMASK_KEYPAD      SIC_INTMASK_KEYPAD
+#define SIC_IRQMASK_DoC         SIC_INTMASK_DoC
+#define SIC_IRQMASK_MMCI0A      SIC_INTMASK_MMCI0A
+#define SIC_IRQMASK_MMCI1A      SIC_INTMASK_MMCI1A
+#define SIC_IRQMASK_AACI        SIC_INTMASK_AACI
+#define SIC_IRQMASK_ETH         SIC_INTMASK_ETH
+#define SIC_IRQMASK_USB         SIC_INTMASK_USB
+#define SIC_IRQMASK_PCI0        SIC_INTMASK_PCI0
+#define SIC_IRQMASK_PCI1        SIC_INTMASK_PCI1
+#define SIC_IRQMASK_PCI2        SIC_INTMASK_PCI2
+#define SIC_IRQMASK_PCI3        SIC_INTMASK_PCI3
+
+#define NR_IRQS                 64
diff --git a/include/asm-arm/arch-versatile/memory.h b/include/asm-arm/arch-versatile/memory.h
new file mode 100644
index 000000000000..7b8b7cc422fa
--- /dev/null
+++ b/include/asm-arm/arch-versatile/memory.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/memory.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/*
+ * Physical DRAM offset.
+ */
+#define PHYS_OFFSET     (0x00000000UL)
+
+/*
+ * Virtual view <-> DMA view memory address translations
+ * virt_to_bus: Used to translate the virtual address to an
+ *              address suitable to be passed to set_dma_addr
+ * bus_to_virt: Used to convert an address for DMA operations
+ *              to an address that the kernel can use.
+ */
+#define __virt_to_bus(x)        ((x) - PAGE_OFFSET)
+#define __bus_to_virt(x)        ((x) + PAGE_OFFSET)
+
+#endif
diff --git a/include/asm-arm/arch-versatile/param.h b/include/asm-arm/arch-versatile/param.h
new file mode 100644
index 000000000000..34b897335f87
--- /dev/null
+++ b/include/asm-arm/arch-versatile/param.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/param.h
+ *
+ *  Copyright (C) 2002 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h
new file mode 100644
index 000000000000..2598d1f08548
--- /dev/null
+++ b/include/asm-arm/arch-versatile/platform.h
@@ -0,0 +1,510 @@
+/*
+ * linux/include/asm-arm/arch-versatile/platform.h
+ *
+ * Copyright (c) ARM Limited 2003.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef __address_h
+#define __address_h                     1
+
+/*
+ * Memory definitions
+ */
+#define VERSATILE_BOOT_ROM_LO          0x30000000               /* DoC Base (64Mb)...*/
+#define VERSATILE_BOOT_ROM_HI          0x30000000
+#define VERSATILE_BOOT_ROM_BASE        VERSATILE_BOOT_ROM_HI     /*  Normal position */
+#define VERSATILE_BOOT_ROM_SIZE        SZ_64M
+
+#define VERSATILE_SSRAM_BASE           /* VERSATILE_SSMC_BASE ? */
+#define VERSATILE_SSRAM_SIZE           SZ_2M
+
+#define VERSATILE_FLASH_BASE           0x34000000
+#define VERSATILE_FLASH_SIZE           SZ_64M
+
+/* 
+ *  SDRAM
+ */
+#define VERSATILE_SDRAM_BASE           0x00000000
+
+/* 
+ *  Logic expansion modules
+ * 
+ */
+
+
+/* ------------------------------------------------------------------------
+ *  Versatile Registers
+ * ------------------------------------------------------------------------
+ * 
+ */
+#define VERSATILE_SYS_ID_OFFSET               0x00
+#define VERSATILE_SYS_SW_OFFSET               0x04
+#define VERSATILE_SYS_LED_OFFSET              0x08
+#define VERSATILE_SYS_OSC0_OFFSET             0x0C
+
+#if defined(CONFIG_ARCH_VERSATILE_PB)
+#define VERSATILE_SYS_OSC1_OFFSET             0x10
+#define VERSATILE_SYS_OSC2_OFFSET             0x14
+#define VERSATILE_SYS_OSC3_OFFSET             0x18
+#define VERSATILE_SYS_OSC4_OFFSET             0x1C
+#elif defined(CONFIG_MACH_VERSATILE_AB)
+#define VERSATILE_SYS_OSC1_OFFSET             0x1C
+#endif
+
+#define VERSATILE_SYS_LOCK_OFFSET             0x20
+#define VERSATILE_SYS_100HZ_OFFSET            0x24
+#define VERSATILE_SYS_CFGDATA1_OFFSET         0x28
+#define VERSATILE_SYS_CFGDATA2_OFFSET         0x2C
+#define VERSATILE_SYS_FLAGS_OFFSET            0x30
+#define VERSATILE_SYS_FLAGSSET_OFFSET         0x30
+#define VERSATILE_SYS_FLAGSCLR_OFFSET         0x34
+#define VERSATILE_SYS_NVFLAGS_OFFSET          0x38
+#define VERSATILE_SYS_NVFLAGSSET_OFFSET       0x38
+#define VERSATILE_SYS_NVFLAGSCLR_OFFSET       0x3C
+#define VERSATILE_SYS_RESETCTL_OFFSET         0x40
+#define VERSATILE_SYS_PICCTL_OFFSET           0x44
+#define VERSATILE_SYS_MCI_OFFSET              0x48
+#define VERSATILE_SYS_FLASH_OFFSET            0x4C
+#define VERSATILE_SYS_CLCD_OFFSET             0x50
+#define VERSATILE_SYS_CLCDSER_OFFSET          0x54
+#define VERSATILE_SYS_BOOTCS_OFFSET           0x58
+#define VERSATILE_SYS_24MHz_OFFSET            0x5C
+#define VERSATILE_SYS_MISC_OFFSET             0x60
+#define VERSATILE_SYS_TEST_OSC0_OFFSET        0x80
+#define VERSATILE_SYS_TEST_OSC1_OFFSET        0x84
+#define VERSATILE_SYS_TEST_OSC2_OFFSET        0x88
+#define VERSATILE_SYS_TEST_OSC3_OFFSET        0x8C
+#define VERSATILE_SYS_TEST_OSC4_OFFSET        0x90
+
+#define VERSATILE_SYS_BASE                    0x10000000
+#define VERSATILE_SYS_ID                      (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET)
+#define VERSATILE_SYS_SW                      (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET)
+#define VERSATILE_SYS_LED                     (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET)
+#define VERSATILE_SYS_OSC0                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET)
+#define VERSATILE_SYS_OSC1                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET)
+
+#if defined(CONFIG_ARCH_VERSATILE_PB)
+#define VERSATILE_SYS_OSC2                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET)
+#define VERSATILE_SYS_OSC3                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET)
+#define VERSATILE_SYS_OSC4                    (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET)
+#endif
+
+#define VERSATILE_SYS_LOCK                    (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET)
+#define VERSATILE_SYS_100HZ                   (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET)
+#define VERSATILE_SYS_CFGDATA1                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET)
+#define VERSATILE_SYS_CFGDATA2                (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET)
+#define VERSATILE_SYS_FLAGS                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET)
+#define VERSATILE_SYS_FLAGSSET                (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET)
+#define VERSATILE_SYS_FLAGSCLR                (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET)
+#define VERSATILE_SYS_NVFLAGS                 (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET)
+#define VERSATILE_SYS_NVFLAGSSET              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET)
+#define VERSATILE_SYS_NVFLAGSCLR              (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET)
+#define VERSATILE_SYS_RESETCTL                (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET)
+#define VERSATILE_SYS_PICCTL                  (VERSATILE_SYS_BASE + VERSATILE_SYS_PICCTL_OFFSET)
+#define VERSATILE_SYS_MCI                     (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET)
+#define VERSATILE_SYS_FLASH                   (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET)
+#define VERSATILE_SYS_CLCD                    (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET)
+#define VERSATILE_SYS_CLCDSER                 (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET)
+#define VERSATILE_SYS_BOOTCS                  (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET)
+#define VERSATILE_SYS_24MHz                   (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET)
+#define VERSATILE_SYS_MISC                    (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET)
+#define VERSATILE_SYS_TEST_OSC0               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET)
+#define VERSATILE_SYS_TEST_OSC1               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET)
+#define VERSATILE_SYS_TEST_OSC2               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET)
+#define VERSATILE_SYS_TEST_OSC3               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET)
+#define VERSATILE_SYS_TEST_OSC4               (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET)
+
+/* 
+ * Values for VERSATILE_SYS_RESET_CTRL
+ */
+#define VERSATILE_SYS_CTRL_RESET_CONFIGCLR    0x01
+#define VERSATILE_SYS_CTRL_RESET_CONFIGINIT   0x02
+#define VERSATILE_SYS_CTRL_RESET_DLLRESET     0x03
+#define VERSATILE_SYS_CTRL_RESET_PLLRESET     0x04
+#define VERSATILE_SYS_CTRL_RESET_POR          0x05
+#define VERSATILE_SYS_CTRL_RESET_DoC          0x06
+
+#define VERSATILE_SYS_CTRL_LED         (1 << 0)
+
+
+/* ------------------------------------------------------------------------
+ *  Versatile control registers
+ * ------------------------------------------------------------------------
+ */
+
+/* 
+ * VERSATILE_IDFIELD
+ *
+ * 31:24 = manufacturer (0x41 = ARM)
+ * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus)
+ * 15:12 = FPGA (0x3 = XVC600 or XVC600E)
+ * 11:4  = build value
+ * 3:0   = revision number (0x1 = rev B (AHB))
+ */
+
+/*
+ * VERSATILE_SYS_LOCK
+ *     control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, 
+ *     SYS_CLD, SYS_BOOTCS
+ */
+#define VERSATILE_SYS_LOCK_LOCKED    (1 << 16)
+#define VERSATILE_SYS_LOCKVAL_MASK      0xFFFF          /* write 0xA05F to enable write access */
+
+/*
+ * VERSATILE_SYS_FLASH
+ */
+#define VERSATILE_FLASHPROG_FLVPPEN     (1 << 0)        /* Enable writing to flash */
+
+/*
+ * VERSATILE_INTREG
+ *     - used to acknowledge and control MMCI and UART interrupts 
+ */
+#define VERSATILE_INTREG_WPROT        0x00    /* MMC protection status (no interrupt generated) */
+#define VERSATILE_INTREG_RI0          0x01    /* Ring indicator UART0 is asserted,              */
+#define VERSATILE_INTREG_CARDIN       0x08    /* MMCI card in detect                            */
+                                                /* write 1 to acknowledge and clear               */
+#define VERSATILE_INTREG_RI1          0x02    /* Ring indicator UART1 is asserted,              */
+#define VERSATILE_INTREG_CARDINSERT   0x03    /* Signal insertion of MMC card                   */
+
+/*
+ * VERSATILE peripheral addresses
+ */
+#define VERSATILE_PCI_CORE_BASE        0x10001000       /* PCI core control */
+#define VERSATILE_I2C_BASE             0x10002000       /* I2C control */
+#define VERSATILE_SIC_BASE             0x10003000       /* Secondary interrupt controller */
+#define VERSATILE_AACI_BASE            0x10004000       /* Audio */
+#define VERSATILE_MMCI0_BASE           0x10005000       /* MMC interface */
+#define VERSATILE_KMI0_BASE            0x10006000       /* KMI interface */
+#define VERSATILE_KMI1_BASE            0x10007000       /* KMI 2nd interface */
+#define VERSATILE_CHAR_LCD_BASE        0x10008000       /* Character LCD */
+#define VERSATILE_UART3_BASE           0x10009000       /* UART 3 */
+#define VERSATILE_SCI1_BASE            0x1000A000
+#define VERSATILE_MMCI1_BASE           0x1000B000    /* MMC Interface */
+        /* 0x1000C000 - 0x1000CFFF = reserved */
+#define VERSATILE_ETH_BASE             0x10010000       /* Ethernet */
+#define VERSATILE_USB_BASE             0x10020000       /* USB */
+        /* 0x10030000 - 0x100FFFFF = reserved */
+#define VERSATILE_SMC_BASE             0x10100000       /* SMC */
+#define VERSATILE_MPMC_BASE            0x10110000       /* MPMC */
+#define VERSATILE_CLCD_BASE            0x10120000       /* CLCD */
+#define VERSATILE_DMAC_BASE            0x10130000       /* DMA controller */
+#define VERSATILE_VIC_BASE             0x10140000       /* Vectored interrupt controller */
+#define VERSATILE_PERIPH_BASE          0x10150000    /* off-chip peripherals alias from */
+                                                /* 0x10000000 - 0x100FFFFF */
+#define VERSATILE_AHBM_BASE            0x101D0000       /* AHB monitor */
+#define VERSATILE_SCTL_BASE            0x101E0000       /* System controller */
+#define VERSATILE_WATCHDOG_BASE        0x101E1000       /* Watchdog */
+#define VERSATILE_TIMER0_1_BASE        0x101E2000       /* Timer 0 and 1 */
+#define VERSATILE_TIMER2_3_BASE        0x101E3000       /* Timer 2 and 3 */
+#define VERSATILE_GPIO0_BASE           0x101E4000       /* GPIO port 0 */
+#define VERSATILE_GPIO1_BASE           0x101E5000    /* GPIO port 1 */
+#define VERSATILE_GPIO2_BASE           0x101E6000       /* GPIO port 2 */
+#define VERSATILE_GPIO3_BASE           0x101E7000       /* GPIO port 3 */
+#define VERSATILE_RTC_BASE             0x101E8000       /* Real Time Clock */
+        /* 0x101E9000 - reserved */
+#define VERSATILE_SCI_BASE             0x101F0000       /* Smart card controller */
+#define VERSATILE_UART0_BASE           0x101F1000       /* Uart 0 */
+#define VERSATILE_UART1_BASE           0x101F2000       /* Uart 1 */
+#define VERSATILE_UART2_BASE           0x101F3000       /* Uart 2 */
+#define VERSATILE_SSP_BASE             0x101F4000       /* Synchronous Serial Port */
+
+#define VERSATILE_SSMC_BASE            0x20000000       /* SSMC */
+#define VERSATILE_IB2_BASE             0x24000000       /* IB2 module */
+#define VERSATILE_MBX_BASE             0x40000000       /* MBX */
+#define VERSATILE_PCI_BASE             0x41000000       /* PCI Interface */
+#define VERSATILE_SDRAM67_BASE         0x70000000       /* SDRAM banks 6 and 7 */
+#define VERSATILE_LT_BASE              0x80000000       /* Logic Tile expansion */
+
+/*
+ * Disk on Chip
+ */
+#define VERSATILE_DOC_BASE             0x2C000000
+#define VERSATILE_DOC_SIZE             (16 << 20)
+#define VERSATILE_DOC_PAGE_SIZE        512
+#define VERSATILE_DOC_TOTAL_PAGES     (DOC_SIZE / PAGE_SIZE)
+
+#define ERASE_UNIT_PAGES    32
+#define START_PAGE          0x80
+
+/* 
+ *  LED settings, bits [7:0]
+ */
+#define VERSATILE_SYS_LED0             (1 << 0)
+#define VERSATILE_SYS_LED1             (1 << 1)
+#define VERSATILE_SYS_LED2             (1 << 2)
+#define VERSATILE_SYS_LED3             (1 << 3)
+#define VERSATILE_SYS_LED4             (1 << 4)
+#define VERSATILE_SYS_LED5             (1 << 5)
+#define VERSATILE_SYS_LED6             (1 << 6)
+#define VERSATILE_SYS_LED7             (1 << 7)
+
+#define ALL_LEDS                  0xFF
+
+#define LED_BANK                  VERSATILE_SYS_LED
+
+/* 
+ * Control registers
+ */
+#define VERSATILE_IDFIELD_OFFSET        0x0     /* Versatile build information */
+#define VERSATILE_FLASHPROG_OFFSET      0x4     /* Flash devices */
+#define VERSATILE_INTREG_OFFSET         0x8     /* Interrupt control */
+#define VERSATILE_DECODE_OFFSET         0xC     /* Fitted logic modules */
+
+
+/* ------------------------------------------------------------------------
+ *  Versatile Interrupt Controller - control registers
+ * ------------------------------------------------------------------------
+ * 
+ *  Offsets from interrupt controller base 
+ * 
+ *  System Controller interrupt controller base is
+ * 
+ *      VERSATILE_IC_BASE
+ * 
+ *  Core Module interrupt controller base is
+ * 
+ *      VERSATILE_SYS_IC 
+ * 
+ */
+#define VIC_IRQ_STATUS                  0
+#define VIC_FIQ_STATUS                  0x04
+#define VIC_IRQ_RAW_STATUS              0x08
+#define VIC_INT_SELECT                  0x0C    /* 1 = FIQ, 0 = IRQ */
+#define VIC_IRQ_ENABLE                  0x10    /* 1 = enable, 0 = disable */
+#define VIC_IRQ_ENABLE_CLEAR            0x14
+#define VIC_IRQ_SOFT                    0x18
+#define VIC_IRQ_SOFT_CLEAR              0x1C
+#define VIC_PROTECT                     0x20
+#define VIC_VECT_ADDR                   0x30
+#define VIC_DEF_VECT_ADDR               0x34
+#define VIC_VECT_ADDR0                  0x100   /* 0 to 15 */
+#define VIC_VECT_CNTL0                  0x200   /* 0 to 15 */
+#define VIC_ITCR                        0x300   /* VIC test control register */
+
+#define VIC_FIQ_RAW_STATUS              0x08
+#define VIC_FIQ_ENABLE                  0x10    /* 1 = enable, 0 = disable */
+#define VIC_FIQ_ENABLE_CLEAR            0x14
+#define VIC_FIQ_SOFT                    0x18
+#define VIC_FIQ_SOFT_CLEAR              0x1C
+
+#define SIC_IRQ_STATUS                  0
+#define SIC_IRQ_RAW_STATUS              0x04
+#define SIC_IRQ_ENABLE                  0x08
+#define SIC_IRQ_ENABLE_SET              0x08
+#define SIC_IRQ_ENABLE_CLEAR            0x0C
+#define SIC_INT_SOFT_SET                0x10
+#define SIC_INT_SOFT_CLEAR              0x14
+#define SIC_INT_PIC_ENABLE              0x20    /* read status of pass through mask */
+#define SIC_INT_PIC_ENABLES             0x20    /* set interrupt pass through bits */
+#define SIC_INT_PIC_ENABLEC             0x24    /* Clear interrupt pass through bits */
+
+#define VICVectCntl_Enable              (1 << 5)
+
+/* ------------------------------------------------------------------------
+ *  Interrupts - bit assignment (primary)
+ * ------------------------------------------------------------------------
+ */
+
+#define INT_WDOGINT                     0       /* Watchdog timer */
+#define INT_SOFTINT                     1       /* Software interrupt */
+#define INT_COMMRx                      2       /* Debug Comm Rx interrupt */
+#define INT_COMMTx                      3       /* Debug Comm Tx interrupt */
+#define INT_TIMERINT0_1                 4       /* Timer 0 and 1 */
+#define INT_TIMERINT2_3                 5       /* Timer 2 and 3 */
+#define INT_GPIOINT0                    6       /* GPIO 0 */
+#define INT_GPIOINT1                    7       /* GPIO 1 */
+#define INT_GPIOINT2                    8       /* GPIO 2 */
+#define INT_GPIOINT3                    9       /* GPIO 3 */
+#define INT_RTCINT                      10      /* Real Time Clock */
+#define INT_SSPINT                      11      /* Synchronous Serial Port */
+#define INT_UARTINT0                    12      /* UART 0 on development chip */
+#define INT_UARTINT1                    13      /* UART 1 on development chip */
+#define INT_UARTINT2                    14      /* UART 2 on development chip */
+#define INT_SCIINT                      15      /* Smart Card Interface */
+#define INT_CLCDINT                     16      /* CLCD controller */
+#define INT_DMAINT                      17      /* DMA controller */
+#define INT_PWRFAILINT                  18      /* Power failure */
+#define INT_MBXINT                      19      /* Graphics processor */
+#define INT_GNDINT                      20      /* Reserved */
+        /* External interrupt signals from logic tiles or secondary controller */
+#define INT_VICSOURCE21                 21      /* Disk on Chip */
+#define INT_VICSOURCE22                 22      /* MCI0A */
+#define INT_VICSOURCE23                 23      /* MCI1A */
+#define INT_VICSOURCE24                 24      /* AACI */
+#define INT_VICSOURCE25                 25      /* Ethernet */
+#define INT_VICSOURCE26                 26      /* USB */
+#define INT_VICSOURCE27                 27      /* PCI 0 */
+#define INT_VICSOURCE28                 28      /* PCI 1 */
+#define INT_VICSOURCE29                 29      /* PCI 2 */
+#define INT_VICSOURCE30                 30      /* PCI 3 */
+#define INT_VICSOURCE31                 31      /* SIC source */
+
+/* 
+ *  Interrupt bit positions
+ * 
+ */
+#define INTMASK_WDOGINT                 (1 << INT_WDOGINT)
+#define INTMASK_SOFTINT                 (1 << INT_SOFTINT)
+#define INTMASK_COMMRx                  (1 << INT_COMMRx)
+#define INTMASK_COMMTx                  (1 << INT_COMMTx)
+#define INTMASK_TIMERINT0_1             (1 << INT_TIMERINT0_1)
+#define INTMASK_TIMERINT2_3             (1 << INT_TIMERINT2_3)
+#define INTMASK_GPIOINT0                (1 << INT_GPIOINT0)
+#define INTMASK_GPIOINT1                (1 << INT_GPIOINT1)
+#define INTMASK_GPIOINT2                (1 << INT_GPIOINT2)
+#define INTMASK_GPIOINT3                (1 << INT_GPIOINT3)
+#define INTMASK_RTCINT                  (1 << INT_RTCINT)
+#define INTMASK_SSPINT                  (1 << INT_SSPINT)
+#define INTMASK_UARTINT0                (1 << INT_UARTINT0)
+#define INTMASK_UARTINT1                (1 << INT_UARTINT1)
+#define INTMASK_UARTINT2                (1 << INT_UARTINT2)
+#define INTMASK_SCIINT                  (1 << INT_SCIINT)
+#define INTMASK_CLCDINT                 (1 << INT_CLCDINT)
+#define INTMASK_DMAINT                  (1 << INT_DMAINT)
+#define INTMASK_PWRFAILINT              (1 << INT_PWRFAILINT)
+#define INTMASK_MBXINT                  (1 << INT_MBXINT)
+#define INTMASK_GNDINT                  (1 << INT_GNDINT)
+#define INTMASK_VICSOURCE21             (1 << INT_VICSOURCE21)
+#define INTMASK_VICSOURCE22             (1 << INT_VICSOURCE22)
+#define INTMASK_VICSOURCE23             (1 << INT_VICSOURCE23)
+#define INTMASK_VICSOURCE24             (1 << INT_VICSOURCE24)
+#define INTMASK_VICSOURCE25             (1 << INT_VICSOURCE25)
+#define INTMASK_VICSOURCE26             (1 << INT_VICSOURCE26)
+#define INTMASK_VICSOURCE27             (1 << INT_VICSOURCE27)
+#define INTMASK_VICSOURCE28             (1 << INT_VICSOURCE28)
+#define INTMASK_VICSOURCE29             (1 << INT_VICSOURCE29)
+#define INTMASK_VICSOURCE30             (1 << INT_VICSOURCE30)
+#define INTMASK_VICSOURCE31             (1 << INT_VICSOURCE31)
+
+
+#define VERSATILE_SC_VALID_INT               0x003FFFFF
+
+#define MAXIRQNUM                       31
+#define MAXFIQNUM                       31
+#define MAXSWINUM                       31
+
+/* ------------------------------------------------------------------------
+ *  Interrupts - bit assignment (secondary)
+ * ------------------------------------------------------------------------
+ */
+#define SIC_INT_MMCI0B                  1       /* Multimedia Card 0B */
+#define SIC_INT_MMCI1B                  2       /* Multimedia Card 1B */
+#define SIC_INT_KMI0                    3       /* Keyboard/Mouse port 0 */
+#define SIC_INT_KMI1                    4       /* Keyboard/Mouse port 1 */
+#define SIC_INT_SCI3                    5       /* Smart Card interface */
+#define SIC_INT_UART3                   6       /* UART 3 empty or data available */
+#define SIC_INT_CLCD                    7       /* Character LCD */
+#define SIC_INT_TOUCH                   8       /* Touchscreen */
+#define SIC_INT_KEYPAD                  9       /* Key pressed on display keypad */
+        /* 10:20 - reserved */
+#define SIC_INT_DoC                     21      /* Disk on Chip memory controller */
+#define SIC_INT_MMCI0A                  22      /* MMC 0A */
+#define SIC_INT_MMCI1A                  23      /* MMC 1A */
+#define SIC_INT_AACI                    24      /* Audio Codec */
+#define SIC_INT_ETH                     25      /* Ethernet controller */
+#define SIC_INT_USB                     26      /* USB controller */
+#define SIC_INT_PCI0                    27
+#define SIC_INT_PCI1                    28
+#define SIC_INT_PCI2                    29
+#define SIC_INT_PCI3                    30
+
+
+#define SIC_INTMASK_MMCI0B              (1 << SIC_INT_MMCI0B)
+#define SIC_INTMASK_MMCI1B              (1 << SIC_INT_MMCI1B)
+#define SIC_INTMASK_KMI0                (1 << SIC_INT_KMI0)
+#define SIC_INTMASK_KMI1                (1 << SIC_INT_KMI1)
+#define SIC_INTMASK_SCI3                (1 << SIC_INT_SCI3)
+#define SIC_INTMASK_UART3               (1 << SIC_INT_UART3)
+#define SIC_INTMASK_CLCD                (1 << SIC_INT_CLCD)
+#define SIC_INTMASK_TOUCH               (1 << SIC_INT_TOUCH)
+#define SIC_INTMASK_KEYPAD              (1 << SIC_INT_KEYPAD)
+#define SIC_INTMASK_DoC                 (1 << SIC_INT_DoC)
+#define SIC_INTMASK_MMCI0A              (1 << SIC_INT_MMCI0A)
+#define SIC_INTMASK_MMCI1A              (1 << SIC_INT_MMCI1A)
+#define SIC_INTMASK_AACI                (1 << SIC_INT_AACI)
+#define SIC_INTMASK_ETH                 (1 << SIC_INT_ETH)
+#define SIC_INTMASK_USB                 (1 << SIC_INT_USB)
+#define SIC_INTMASK_PCI0                (1 << SIC_INT_PCI0)
+#define SIC_INTMASK_PCI1                (1 << SIC_INT_PCI1)
+#define SIC_INTMASK_PCI2                (1 << SIC_INT_PCI2)
+#define SIC_INTMASK_PCI3                (1 << SIC_INT_PCI3)
+/* 
+ *  Application Flash
+ * 
+ */
+#define FLASH_BASE                      VERSATILE_FLASH_BASE
+#define FLASH_SIZE                      VERSATILE_FLASH_SIZE
+#define FLASH_END                       (FLASH_BASE + FLASH_SIZE - 1)
+#define FLASH_BLOCK_SIZE                SZ_128K
+
+/* 
+ *  Boot Flash
+ * 
+ */
+#define EPROM_BASE                      VERSATILE_BOOT_ROM_HI
+#define EPROM_SIZE                      VERSATILE_BOOT_ROM_SIZE
+#define EPROM_END                       (EPROM_BASE + EPROM_SIZE - 1)
+
+/* 
+ *  Clean base - dummy
+ * 
+ */
+#define CLEAN_BASE                      EPROM_BASE
+
+/*
+ * System controller bit assignment
+ */
+#define VERSATILE_REFCLK        0
+#define VERSATILE_TIMCLK        1
+
+#define VERSATILE_TIMER1_EnSel  15
+#define VERSATILE_TIMER2_EnSel  17
+#define VERSATILE_TIMER3_EnSel  19
+#define VERSATILE_TIMER4_EnSel  21
+
+
+#define MAX_TIMER                       2
+#define MAX_PERIOD                      699050
+#define TICKS_PER_uSEC                  1
+
+/* 
+ *  These are useconds NOT ticks.  
+ * 
+ */
+#define mSEC_1                          1000
+#define mSEC_5                          (mSEC_1 * 5)
+#define mSEC_10                         (mSEC_1 * 10)
+#define mSEC_25                         (mSEC_1 * 25)
+#define SEC_1                           (mSEC_1 * 1000)
+
+#define VERSATILE_CSR_BASE             0x10000000
+#define VERSATILE_CSR_SIZE             0x10000000
+
+#ifdef CONFIG_MACH_VERSATILE_AB
+/*
+ * IB2 Versatile/AB expansion board definitions
+ */
+#define VERSATILE_IB2_CAMERA_BANK       0x24000000
+#define VERSATILE_IB2_KBD_DATAREG       0x25000000
+#define VERSATILE_IB2_IER               0x26000000      /* for VICINTSOURCE27 */
+#define VERSATILE_IB2_CTRL              0x27000000
+#define VERSATILE_IB2_STAT              0x27000004
+#endif
+
+#endif
+
+/*      END */
diff --git a/include/asm-arm/arch-versatile/system.h b/include/asm-arm/arch-versatile/system.h
new file mode 100644
index 000000000000..8889a189739f
--- /dev/null
+++ b/include/asm-arm/arch-versatile/system.h
@@ -0,0 +1,51 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/system.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+#include <asm/arch/platform.h>
+
+static inline void arch_idle(void)
+{
+        /*
+         * This should do all the clock switching
+         * and wait for interrupt tricks
+         */
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        unsigned int hdr_ctrl = (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_RESETCTL_OFFSET);
+        unsigned int val;
+
+        /*
+         * To reset, we hit the on-board reset register
+         * in the system FPGA
+         */
+        val = __raw_readl(hdr_ctrl);
+        val |= VERSATILE_SYS_CTRL_RESET_CONFIGCLR;
+        __raw_writel(val, hdr_ctrl);
+}
+
+#endif
diff --git a/include/asm-arm/arch-versatile/timex.h b/include/asm-arm/arch-versatile/timex.h
new file mode 100644
index 000000000000..38fd04fc9141
--- /dev/null
+++ b/include/asm-arm/arch-versatile/timex.h
@@ -0,0 +1,23 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/timex.h
+ *
+ *  Versatile architecture timex specifications
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#define CLOCK_TICK_RATE         (50000000 / 16)
diff --git a/include/asm-arm/arch-versatile/uncompress.h b/include/asm-arm/arch-versatile/uncompress.h
new file mode 100644
index 000000000000..2f57499c7b92
--- /dev/null
+++ b/include/asm-arm/arch-versatile/uncompress.h
@@ -0,0 +1,52 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/uncompress.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#define AMBA_UART_DR    (*(volatile unsigned char *)0x101F1000)
+#define AMBA_UART_LCRH  (*(volatile unsigned char *)0x101F102C)
+#define AMBA_UART_CR    (*(volatile unsigned char *)0x101F1030)
+#define AMBA_UART_FR    (*(volatile unsigned char *)0x101F1018)
+
+/*
+ * This does not append a newline
+ */
+static void putstr(const char *s)
+{
+        while (*s) {
+                while (AMBA_UART_FR & (1 << 5))
+                        barrier();
+
+                AMBA_UART_DR = *s;
+
+                if (*s == '\n') {
+                        while (AMBA_UART_FR & (1 << 5))
+                                barrier();
+
+                        AMBA_UART_DR = '\r';
+                }
+                s++;
+        }
+        while (AMBA_UART_FR & (1 << 3))
+                barrier();
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-versatile/vmalloc.h b/include/asm-arm/arch-versatile/vmalloc.h
new file mode 100644
index 000000000000..adfb34829bfc
--- /dev/null
+++ b/include/asm-arm/arch-versatile/vmalloc.h
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/arch-versatile/vmalloc.h
+ *
+ *  Copyright (C) 2003 ARM Limited
+ *  Copyright (C) 2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 8MB value just means that there will be a 8MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ */
+#define VMALLOC_OFFSET          (8*1024*1024)
+#define VMALLOC_START           (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
+#define VMALLOC_VMADDR(x)       ((unsigned long)(x))
+#define VMALLOC_END             (PAGE_OFFSET + 0x18000000)
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
new file mode 100644
index 000000000000..69a28f96bee2
--- /dev/null
+++ b/include/asm-arm/assembler.h
@@ -0,0 +1,117 @@
+/*
+ *  linux/include/asm-arm/assembler.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains arm architecture specific defines
+ *  for the different processors.
+ *
+ *  Do not include any C declarations in this file - it is included by
+ *  assembler source.
+ */
+#ifndef __ASSEMBLY__
+#error "Only include this from assembly code"
+#endif
+
+#include <asm/ptrace.h>
+
+/*
+ * Endian independent macros for shifting bytes within registers.
+ */
+#ifndef __ARMEB__
+#define pull            lsr
+#define push            lsl
+#define get_byte_0      lsl #0
+#define get_byte_1      lsr #8
+#define get_byte_2      lsr #16
+#define get_byte_3      lsr #24
+#define put_byte_0      lsl #0
+#define put_byte_1      lsl #8
+#define put_byte_2      lsl #16
+#define put_byte_3      lsl #24
+#else
+#define pull            lsl
+#define push            lsr
+#define get_byte_0      lsr #24
+#define get_byte_1      lsr #16
+#define get_byte_2      lsr #8
+#define get_byte_3      lsl #0
+#define put_byte_0      lsl #24
+#define put_byte_1      lsl #16
+#define put_byte_2      lsl #8
+#define put_byte_3      lsl #0
+#endif
+
+/*
+ * Data preload for architectures that support it
+ */
+#if __LINUX_ARM_ARCH__ >= 5
+#define PLD(code...)    code
+#else
+#define PLD(code...)
+#endif
+
+#define MODE_USR        USR_MODE
+#define MODE_FIQ        FIQ_MODE
+#define MODE_IRQ        IRQ_MODE
+#define MODE_SVC        SVC_MODE
+
+#define DEFAULT_FIQ     MODE_FIQ
+
+/*
+ * LOADREGS - ldm with PC in register list (eg, ldmfd sp!, {pc})
+ */
+#ifdef __STDC__
+#define LOADREGS(cond, base, reglist...)\
+        ldm##cond       base,reglist
+#else
+#define LOADREGS(cond, base, reglist...)\
+        ldm/**/cond     base,reglist
+#endif
+
+/*
+ * Build a return instruction for this processor type.
+ */
+#define RETINSTR(instr, regs...)\
+        instr   regs
+
+/*
+ * Save the current IRQ state and disable IRQs.  Note that this macro
+ * assumes FIQs are enabled, and that the processor is in SVC mode.
+ */
+        .macro  save_and_disable_irqs, oldcpsr, temp
+        mrs     \oldcpsr, cpsr
+        mov     \temp, #PSR_I_BIT | MODE_SVC
+        msr     cpsr_c, \temp
+        .endm
+
+/*
+ * Restore interrupt state previously stored in a register.  We don't
+ * guarantee that this will preserve the flags.
+ */
+        .macro  restore_irqs, oldcpsr
+        msr     cpsr_c, \oldcpsr
+        .endm
+
+/*
+ * These two are used to save LR/restore PC over a user-based access.
+ * The old 26-bit architecture requires that we do.  On 32-bit
+ * architecture, we can safely ignore this requirement.
+ */
+        .macro  save_lr
+        .endm
+
+        .macro  restore_pc
+        mov     pc, lr
+        .endm
+
+#define USER(x...)                              \
+9999:   x;                                      \
+        .section __ex_table,"a";                \
+        .align  3;                              \
+        .long   9999b,9001f;                    \
+        .previous
diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
new file mode 100644
index 000000000000..2885972b0855
--- /dev/null
+++ b/include/asm-arm/atomic.h
@@ -0,0 +1,165 @@
+/*
+ *  linux/include/asm-arm/atomic.h
+ *
+ *  Copyright (C) 1996 Russell King.
+ *  Copyright (C) 2002 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_ATOMIC_H
+#define __ASM_ARM_ATOMIC_H
+
+#include <linux/config.h>
+
+typedef struct { volatile int counter; } atomic_t;
+
+#define ATOMIC_INIT(i)  { (i) }
+
+#ifdef __KERNEL__
+
+#define atomic_read(v)  ((v)->counter)
+
+#if __LINUX_ARM_ARCH__ >= 6
+
+/*
+ * ARMv6 UP and SMP safe atomic ops.  We use load exclusive and
+ * store exclusive to ensure that these are atomic.  We may loop
+ * to ensure that the update happens.  Writing to 'v->counter'
+ * without using the following operations WILL break the atomic
+ * nature of these ops.
+ */
+static inline void atomic_set(atomic_t *v, int i)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__("@ atomic_set\n"
+"1:     ldrex   %0, [%1]\n"
+"       strex   %0, %2, [%1]\n"
+"       teq     %0, #0\n"
+"       bne     1b"
+        : "=&r" (tmp)
+        : "r" (&v->counter), "r" (i)
+        : "cc");
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        unsigned long tmp;
+        int result;
+
+        __asm__ __volatile__("@ atomic_add_return\n"
+"1:     ldrex   %0, [%2]\n"
+"       add     %0, %0, %3\n"
+"       strex   %1, %0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "Ir" (i)
+        : "cc");
+
+        return result;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        unsigned long tmp;
+        int result;
+
+        __asm__ __volatile__("@ atomic_sub_return\n"
+"1:     ldrex   %0, [%2]\n"
+"       sub     %0, %0, %3\n"
+"       strex   %1, %0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (result), "=&r" (tmp)
+        : "r" (&v->counter), "Ir" (i)
+        : "cc");
+
+        return result;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+        unsigned long tmp, tmp2;
+
+        __asm__ __volatile__("@ atomic_clear_mask\n"
+"1:     ldrex   %0, %2\n"
+"       bic     %0, %0, %3\n"
+"       strex   %1, %0, %2\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (tmp), "=&r" (tmp2)
+        : "r" (addr), "Ir" (mask)
+        : "cc");
+}
+
+#else /* ARM_ARCH_6 */
+
+#include <asm/system.h>
+
+#ifdef CONFIG_SMP
+#error SMP not supported on pre-ARMv6 CPUs
+#endif
+
+#define atomic_set(v,i) (((v)->counter) = (i))
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+        unsigned long flags;
+        int val;
+
+        local_irq_save(flags);
+        val = v->counter;
+        v->counter = val += i;
+        local_irq_restore(flags);
+
+        return val;
+}
+
+static inline int atomic_sub_return(int i, atomic_t *v)
+{
+        unsigned long flags;
+        int val;
+
+        local_irq_save(flags);
+        val = v->counter;
+        v->counter = val -= i;
+        local_irq_restore(flags);
+
+        return val;
+}
+
+static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+{
+        unsigned long flags;
+
+        local_irq_save(flags);
+        *addr &= ~mask;
+        local_irq_restore(flags);
+}
+
+#endif /* __LINUX_ARM_ARCH__ */
+
+#define atomic_add(i, v)        (void) atomic_add_return(i, v)
+#define atomic_inc(v)           (void) atomic_add_return(1, v)
+#define atomic_sub(i, v)        (void) atomic_sub_return(i, v)
+#define atomic_dec(v)           (void) atomic_sub_return(1, v)
+
+#define atomic_inc_and_test(v)  (atomic_add_return(1, v) == 0)
+#define atomic_dec_and_test(v)  (atomic_sub_return(1, v) == 0)
+#define atomic_inc_return(v)    (atomic_add_return(1, v))
+#define atomic_dec_return(v)    (atomic_sub_return(1, v))
+#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
+
+#define atomic_add_negative(i,v) (atomic_add_return(i, v) < 0)
+
+/* Atomic operations are already serializing on ARM */
+#define smp_mb__before_atomic_dec()     barrier()
+#define smp_mb__after_atomic_dec()      barrier()
+#define smp_mb__before_atomic_inc()     barrier()
+#define smp_mb__after_atomic_inc()      barrier()
+
+#endif
+#endif
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
new file mode 100644
index 000000000000..4edd4dc40c5b
--- /dev/null
+++ b/include/asm-arm/bitops.h
@@ -0,0 +1,416 @@
+/*
+ * Copyright 1995, Russell King.
+ * Various bits and pieces copyrights include:
+ *  Linus Torvalds (test_bit).
+ * Big endian support: Copyright 2001, Nicolas Pitre
+ *  reworked by rmk.
+ *
+ * bit 0 is the LSB of an "unsigned long" quantity.
+ *
+ * Please note that the code in this file should never be included
+ * from user space.  Many of these are not implemented in assembler
+ * since they would be too costly.  Also, they require privileged
+ * instructions (which are not available from user mode) to ensure
+ * that they are atomic.
+ */
+
+#ifndef __ASM_ARM_BITOPS_H
+#define __ASM_ARM_BITOPS_H
+
+#ifdef __KERNEL__
+
+#include <asm/system.h>
+
+#define smp_mb__before_clear_bit()      do { } while (0)
+#define smp_mb__after_clear_bit()       do { } while (0)
+
+/*
+ * These functions are the basis of our bit ops.
+ *
+ * First, the atomic bitops. These use native endian.
+ */
+static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
+{
+        unsigned long flags;
+        unsigned long mask = 1UL << (bit & 31);
+
+        p += bit >> 5;
+
+        local_irq_save(flags);
+        *p |= mask;
+        local_irq_restore(flags);
+}
+
+static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
+{
+        unsigned long flags;
+        unsigned long mask = 1UL << (bit & 31);
+
+        p += bit >> 5;
+
+        local_irq_save(flags);
+        *p &= ~mask;
+        local_irq_restore(flags);
+}
+
+static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
+{
+        unsigned long flags;
+        unsigned long mask = 1UL << (bit & 31);
+
+        p += bit >> 5;
+
+        local_irq_save(flags);
+        *p ^= mask;
+        local_irq_restore(flags);
+}
+
+static inline int
+____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
+{
+        unsigned long flags;
+        unsigned int res;
+        unsigned long mask = 1UL << (bit & 31);
+
+        p += bit >> 5;
+
+        local_irq_save(flags);
+        res = *p;
+        *p = res | mask;
+        local_irq_restore(flags);
+
+        return res & mask;
+}
+
+static inline int
+____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
+{
+        unsigned long flags;
+        unsigned int res;
+        unsigned long mask = 1UL << (bit & 31);
+
+        p += bit >> 5;
+
+        local_irq_save(flags);
+        res = *p;
+        *p = res & ~mask;
+        local_irq_restore(flags);
+
+        return res & mask;
+}
+
+static inline int
+____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
+{
+        unsigned long flags;
+        unsigned int res;
+        unsigned long mask = 1UL << (bit & 31);
+
+        p += bit >> 5;
+
+        local_irq_save(flags);
+        res = *p;
+        *p = res ^ mask;
+        local_irq_restore(flags);
+
+        return res & mask;
+}
+
+/*
+ * Now the non-atomic variants.  We let the compiler handle all
+ * optimisations for these.  These are all _native_ endian.
+ */
+static inline void __set_bit(int nr, volatile unsigned long *p)
+{
+        p[nr >> 5] |= (1UL << (nr & 31));
+}
+
+static inline void __clear_bit(int nr, volatile unsigned long *p)
+{
+        p[nr >> 5] &= ~(1UL << (nr & 31));
+}
+
+static inline void __change_bit(int nr, volatile unsigned long *p)
+{
+        p[nr >> 5] ^= (1UL << (nr & 31));
+}
+
+static inline int __test_and_set_bit(int nr, volatile unsigned long *p)
+{
+        unsigned long oldval, mask = 1UL << (nr & 31);
+
+        p += nr >> 5;
+
+        oldval = *p;
+        *p = oldval | mask;
+        return oldval & mask;
+}
+
+static inline int __test_and_clear_bit(int nr, volatile unsigned long *p)
+{
+        unsigned long oldval, mask = 1UL << (nr & 31);
+
+        p += nr >> 5;
+
+        oldval = *p;
+        *p = oldval & ~mask;
+        return oldval & mask;
+}
+
+static inline int __test_and_change_bit(int nr, volatile unsigned long *p)
+{
+        unsigned long oldval, mask = 1UL << (nr & 31);
+
+        p += nr >> 5;
+
+        oldval = *p;
+        *p = oldval ^ mask;
+        return oldval & mask;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static inline int __test_bit(int nr, const volatile unsigned long * p)
+{
+        return (p[nr >> 5] >> (nr & 31)) & 1UL;
+}
+
+/*
+ *  A note about Endian-ness.
+ *  -------------------------
+ *
+ * When the ARM is put into big endian mode via CR15, the processor
+ * merely swaps the order of bytes within words, thus:
+ *
+ *          ------------ physical data bus bits -----------
+ *          D31 ... D24  D23 ... D16  D15 ... D8  D7 ... D0
+ * little     byte 3       byte 2       byte 1      byte 0
+ * big        byte 0       byte 1       byte 2      byte 3
+ *
+ * This means that reading a 32-bit word at address 0 returns the same
+ * value irrespective of the endian mode bit.
+ *
+ * Peripheral devices should be connected with the data bus reversed in
+ * "Big Endian" mode.  ARM Application Note 61 is applicable, and is
+ * available from http://www.arm.com/.
+ *
+ * The following assumes that the data bus connectivity for big endian
+ * mode has been followed.
+ *
+ * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
+ */
+
+/*
+ * Little endian assembly bitops.  nr = 0 -> byte 0 bit 0.
+ */
+extern void _set_bit_le(int nr, volatile unsigned long * p);
+extern void _clear_bit_le(int nr, volatile unsigned long * p);
+extern void _change_bit_le(int nr, volatile unsigned long * p);
+extern int _test_and_set_bit_le(int nr, volatile unsigned long * p);
+extern int _test_and_clear_bit_le(int nr, volatile unsigned long * p);
+extern int _test_and_change_bit_le(int nr, volatile unsigned long * p);
+extern int _find_first_zero_bit_le(const void * p, unsigned size);
+extern int _find_next_zero_bit_le(const void * p, int size, int offset);
+extern int _find_first_bit_le(const unsigned long *p, unsigned size);
+extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
+
+/*
+ * Big endian assembly bitops.  nr = 0 -> byte 3 bit 0.
+ */
+extern void _set_bit_be(int nr, volatile unsigned long * p);
+extern void _clear_bit_be(int nr, volatile unsigned long * p);
+extern void _change_bit_be(int nr, volatile unsigned long * p);
+extern int _test_and_set_bit_be(int nr, volatile unsigned long * p);
+extern int _test_and_clear_bit_be(int nr, volatile unsigned long * p);
+extern int _test_and_change_bit_be(int nr, volatile unsigned long * p);
+extern int _find_first_zero_bit_be(const void * p, unsigned size);
+extern int _find_next_zero_bit_be(const void * p, int size, int offset);
+extern int _find_first_bit_be(const unsigned long *p, unsigned size);
+extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
+
+/*
+ * The __* form of bitops are non-atomic and may be reordered.
+ */
+#define ATOMIC_BITOP_LE(name,nr,p)              \
+        (__builtin_constant_p(nr) ?             \
+         ____atomic_##name(nr, p) :             \
+         _##name##_le(nr,p))
+
+#define ATOMIC_BITOP_BE(name,nr,p)              \
+        (__builtin_constant_p(nr) ?             \
+         ____atomic_##name(nr, p) :             \
+         _##name##_be(nr,p))
+
+#define NONATOMIC_BITOP(name,nr,p)              \
+        (____nonatomic_##name(nr, p))
+
+#ifndef __ARMEB__
+/*
+ * These are the little endian, atomic definitions.
+ */
+#define set_bit(nr,p)                   ATOMIC_BITOP_LE(set_bit,nr,p)
+#define clear_bit(nr,p)                 ATOMIC_BITOP_LE(clear_bit,nr,p)
+#define change_bit(nr,p)                ATOMIC_BITOP_LE(change_bit,nr,p)
+#define test_and_set_bit(nr,p)          ATOMIC_BITOP_LE(test_and_set_bit,nr,p)
+#define test_and_clear_bit(nr,p)        ATOMIC_BITOP_LE(test_and_clear_bit,nr,p)
+#define test_and_change_bit(nr,p)       ATOMIC_BITOP_LE(test_and_change_bit,nr,p)
+#define test_bit(nr,p)                  __test_bit(nr,p)
+#define find_first_zero_bit(p,sz)       _find_first_zero_bit_le(p,sz)
+#define find_next_zero_bit(p,sz,off)    _find_next_zero_bit_le(p,sz,off)
+#define find_first_bit(p,sz)            _find_first_bit_le(p,sz)
+#define find_next_bit(p,sz,off)         _find_next_bit_le(p,sz,off)
+
+#define WORD_BITOFF_TO_LE(x)            ((x))
+
+#else
+
+/*
+ * These are the big endian, atomic definitions.
+ */
+#define set_bit(nr,p)                   ATOMIC_BITOP_BE(set_bit,nr,p)
+#define clear_bit(nr,p)                 ATOMIC_BITOP_BE(clear_bit,nr,p)
+#define change_bit(nr,p)                ATOMIC_BITOP_BE(change_bit,nr,p)
+#define test_and_set_bit(nr,p)          ATOMIC_BITOP_BE(test_and_set_bit,nr,p)
+#define test_and_clear_bit(nr,p)        ATOMIC_BITOP_BE(test_and_clear_bit,nr,p)
+#define test_and_change_bit(nr,p)       ATOMIC_BITOP_BE(test_and_change_bit,nr,p)
+#define test_bit(nr,p)                  __test_bit(nr,p)
+#define find_first_zero_bit(p,sz)       _find_first_zero_bit_be(p,sz)
+#define find_next_zero_bit(p,sz,off)    _find_next_zero_bit_be(p,sz,off)
+#define find_first_bit(p,sz)            _find_first_bit_be(p,sz)
+#define find_next_bit(p,sz,off)         _find_next_bit_be(p,sz,off)
+
+#define WORD_BITOFF_TO_LE(x)            ((x) ^ 0x18)
+
+#endif
+
+#if __LINUX_ARM_ARCH__ < 5
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long ffz(unsigned long word)
+{
+        int k;
+
+        word = ~word;
+        k = 31;
+        if (word & 0x0000ffff) { k -= 16; word <<= 16; }
+        if (word & 0x00ff0000) { k -= 8;  word <<= 8;  }
+        if (word & 0x0f000000) { k -= 4;  word <<= 4;  }
+        if (word & 0x30000000) { k -= 2;  word <<= 2;  }
+        if (word & 0x40000000) { k -= 1; }
+        return k;
+}
+
+/*
+ * ffz = Find First Zero in word. Undefined if no zero exists,
+ * so code should check against ~0UL first..
+ */
+static inline unsigned long __ffs(unsigned long word)
+{
+        int k;
+
+        k = 31;
+        if (word & 0x0000ffff) { k -= 16; word <<= 16; }
+        if (word & 0x00ff0000) { k -= 8;  word <<= 8;  }
+        if (word & 0x0f000000) { k -= 4;  word <<= 4;  }
+        if (word & 0x30000000) { k -= 2;  word <<= 2;  }
+        if (word & 0x40000000) { k -= 1; }
+        return k;
+}
+
+/*
+ * fls: find last bit set.
+ */
+
+#define fls(x) generic_fls(x)
+
+/*
+ * ffs: find first bit set. This is defined the same way as
+ * the libc and compiler builtin ffs routines, therefore
+ * differs in spirit from the above ffz (man ffs).
+ */
+
+#define ffs(x) generic_ffs(x)
+
+#else
+
+/*
+ * On ARMv5 and above those functions can be implemented around
+ * the clz instruction for much better code efficiency.
+ */
+
+static __inline__ int generic_fls(int x);
+#define fls(x) \
+        ( __builtin_constant_p(x) ? generic_fls(x) : \
+          ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
+#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
+#define __ffs(x) (ffs(x) - 1)
+#define ffz(x) __ffs( ~(x) )
+
+#endif
+
+/*
+ * Find first bit set in a 168-bit bitmap, where the first
+ * 128 bits are unlikely to be set.
+ */
+static inline int sched_find_first_bit(const unsigned long *b)
+{
+        unsigned long v;
+        unsigned int off;
+
+        for (off = 0; v = b[off], off < 4; off++) {
+                if (unlikely(v))
+                        break;
+        }
+        return __ffs(v) + off * 32;
+}
+
+/*
+ * hweightN: returns the hamming weight (i.e. the number
+ * of bits set) of a N-bit word
+ */
+
+#define hweight32(x) generic_hweight32(x)
+#define hweight16(x) generic_hweight16(x)
+#define hweight8(x) generic_hweight8(x)
+
+/*
+ * Ext2 is defined to use little-endian byte ordering.
+ * These do not need to be atomic.
+ */
+#define ext2_set_bit(nr,p)                      \
+                __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define ext2_set_bit_atomic(lock,nr,p)          \
+                test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define ext2_clear_bit(nr,p)                    \
+                __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define ext2_clear_bit_atomic(lock,nr,p)        \
+                test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define ext2_test_bit(nr,p)                     \
+                __test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define ext2_find_first_zero_bit(p,sz)          \
+                _find_first_zero_bit_le(p,sz)
+#define ext2_find_next_zero_bit(p,sz,off)       \
+                _find_next_zero_bit_le(p,sz,off)
+
+/*
+ * Minix is defined to use little-endian byte ordering.
+ * These do not need to be atomic.
+ */
+#define minix_set_bit(nr,p)                     \
+                __set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define minix_test_bit(nr,p)                    \
+                __test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define minix_test_and_set_bit(nr,p)            \
+                __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define minix_test_and_clear_bit(nr,p)          \
+                __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
+#define minix_find_first_zero_bit(p,sz)         \
+                _find_first_zero_bit_le(p,sz)
+
+#endif /* __KERNEL__ */
+
+#endif /* _ARM_BITOPS_H */
diff --git a/include/asm-arm/bug.h b/include/asm-arm/bug.h
new file mode 100644
index 000000000000..5e91b90a8181
--- /dev/null
+++ b/include/asm-arm/bug.h
@@ -0,0 +1,22 @@
+#ifndef _ASMARM_BUG_H
+#define _ASMARM_BUG_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_DEBUG_BUGVERBOSE
+extern volatile void __bug(const char *file, int line, void *data);
+
+/* give file/line information */
+#define BUG()           __bug(__FILE__, __LINE__, NULL)
+
+#else
+
+/* this just causes an oops */
+#define BUG()           (*(int *)0 = 0)
+
+#endif
+
+#define HAVE_ARCH_BUG
+#include <asm-generic/bug.h>
+
+#endif
diff --git a/include/asm-arm/bugs.h b/include/asm-arm/bugs.h
new file mode 100644
index 000000000000..4c80ec519d45
--- /dev/null
+++ b/include/asm-arm/bugs.h
@@ -0,0 +1,17 @@
+/*
+ *  linux/include/asm-arm/bugs.h
+ *
+ *  Copyright (C) 1995-2003 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_BUGS_H
+#define __ASM_BUGS_H
+
+extern void check_writebuffer_bugs(void);
+
+#define check_bugs() check_writebuffer_bugs()
+
+#endif
diff --git a/include/asm-arm/byteorder.h b/include/asm-arm/byteorder.h
new file mode 100644
index 000000000000..d648a1915c33
--- /dev/null
+++ b/include/asm-arm/byteorder.h
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/byteorder.h
+ *
+ * ARM Endian-ness.  In little endian mode, the data bus is connected such
+ * that byte accesses appear as:
+ *  0 = d0...d7, 1 = d8...d15, 2 = d16...d23, 3 = d24...d31
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ *
+ * When in big endian mode, byte accesses appear as:
+ *  0 = d24...d31, 1 = d16...d23, 2 = d8...d15, 3 = d0...d7
+ * and word accesses (data or instruction) appear as:
+ *  d0...d31
+ */
+#ifndef __ASM_ARM_BYTEORDER_H
+#define __ASM_ARM_BYTEORDER_H
+
+
+#include <asm/types.h>
+
+#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#ifdef __ARMEB__
+#include <linux/byteorder/big_endian.h>
+#else
+#include <linux/byteorder/little_endian.h>
+#endif
+
+#endif
+
diff --git a/include/asm-arm/cache.h b/include/asm-arm/cache.h
new file mode 100644
index 000000000000..8d161f7c87ff
--- /dev/null
+++ b/include/asm-arm/cache.h
@@ -0,0 +1,15 @@
+/*
+ *  linux/include/asm-arm/cache.h
+ */
+#ifndef __ASMARM_CACHE_H
+#define __ASMARM_CACHE_H
+
+#define L1_CACHE_SHIFT          5
+#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
+
+/*
+ * largest L1 which this arch supports
+ */
+#define L1_CACHE_SHIFT_MAX      5
+
+#endif
diff --git a/include/asm-arm/cacheflush.h b/include/asm-arm/cacheflush.h
new file mode 100644
index 000000000000..09ffeed507c2
--- /dev/null
+++ b/include/asm-arm/cacheflush.h
@@ -0,0 +1,387 @@
+/*
+ *  linux/include/asm-arm/cacheflush.h
+ *
+ *  Copyright (C) 1999-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASMARM_CACHEFLUSH_H
+#define _ASMARM_CACHEFLUSH_H
+
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+
+#include <asm/mman.h>
+#include <asm/glue.h>
+
+/*
+ *      Cache Model
+ *      ===========
+ */
+#undef _CACHE
+#undef MULTI_CACHE
+
+#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE v3
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM720T)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE v4
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
+    defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020)
+# define MULTI_CACHE 1
+#endif
+
+#if defined(CONFIG_CPU_ARM926T)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE arm926
+# endif
+#endif
+
+#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE v4wb
+# endif
+#endif
+
+#if defined(CONFIG_CPU_XSCALE)
+# ifdef _CACHE
+#  define MULTI_CACHE 1
+# else
+#  define _CACHE xscale
+# endif
+#endif
+
+#if defined(CONFIG_CPU_V6)
+//# ifdef _CACHE
+#  define MULTI_CACHE 1
+//# else
+//#  define _CACHE v6
+//# endif
+#endif
+
+#if !defined(_CACHE) && !defined(MULTI_CACHE)
+#error Unknown cache maintainence model
+#endif
+
+/*
+ * This flag is used to indicate that the page pointed to by a pte
+ * is dirty and requires cleaning before returning it to the user.
+ */
+#define PG_dcache_dirty PG_arch_1
+
+/*
+ *      MM Cache Management
+ *      ===================
+ *
+ *      The arch/arm/mm/cache-*.S and arch/arm/mm/proc-*.S files
+ *      implement these methods.
+ *
+ *      Start addresses are inclusive and end addresses are exclusive;
+ *      start addresses should be rounded down, end addresses up.
+ *
+ *      See Documentation/cachetlb.txt for more information.
+ *      Please note that the implementation of these, and the required
+ *      effects are cache-type (VIVT/VIPT/PIPT) specific.
+ *
+ *      flush_cache_kern_all()
+ *
+ *              Unconditionally clean and invalidate the entire cache.
+ *
+ *      flush_cache_user_mm(mm)
+ *
+ *              Clean and invalidate all user space cache entries
+ *              before a change of page tables.
+ *
+ *      flush_cache_user_range(start, end, flags)
+ *
+ *              Clean and invalidate a range of cache entries in the
+ *              specified address space before a change of page tables.
+ *              - start - user start address (inclusive, page aligned)
+ *              - end   - user end address   (exclusive, page aligned)
+ *              - flags - vma->vm_flags field
+ *
+ *      coherent_kern_range(start, end)
+ *
+ *              Ensure coherency between the Icache and the Dcache in the
+ *              region described by start, end.  If you have non-snooping
+ *              Harvard caches, you need to implement this function.
+ *              - start  - virtual start address
+ *              - end    - virtual end address
+ *
+ *      DMA Cache Coherency
+ *      ===================
+ *
+ *      dma_inv_range(start, end)
+ *
+ *              Invalidate (discard) the specified virtual address range.
+ *              May not write back any entries.  If 'start' or 'end'
+ *              are not cache line aligned, those lines must be written
+ *              back.
+ *              - start  - virtual start address
+ *              - end    - virtual end address
+ *
+ *      dma_clean_range(start, end)
+ *
+ *              Clean (write back) the specified virtual address range.
+ *              - start  - virtual start address
+ *              - end    - virtual end address
+ *
+ *      dma_flush_range(start, end)
+ *
+ *              Clean and invalidate the specified virtual address range.
+ *              - start  - virtual start address
+ *              - end    - virtual end address
+ */
+
+struct cpu_cache_fns {
+        void (*flush_kern_all)(void);
+        void (*flush_user_all)(void);
+        void (*flush_user_range)(unsigned long, unsigned long, unsigned int);
+
+        void (*coherent_kern_range)(unsigned long, unsigned long);
+        void (*coherent_user_range)(unsigned long, unsigned long);
+        void (*flush_kern_dcache_page)(void *);
+
+        void (*dma_inv_range)(unsigned long, unsigned long);
+        void (*dma_clean_range)(unsigned long, unsigned long);
+        void (*dma_flush_range)(unsigned long, unsigned long);
+};
+
+/*
+ * Select the calling method
+ */
+#ifdef MULTI_CACHE
+
+extern struct cpu_cache_fns cpu_cache;
+
+#define __cpuc_flush_kern_all           cpu_cache.flush_kern_all
+#define __cpuc_flush_user_all           cpu_cache.flush_user_all
+#define __cpuc_flush_user_range         cpu_cache.flush_user_range
+#define __cpuc_coherent_kern_range      cpu_cache.coherent_kern_range
+#define __cpuc_coherent_user_range      cpu_cache.coherent_user_range
+#define __cpuc_flush_dcache_page        cpu_cache.flush_kern_dcache_page
+
+/*
+ * These are private to the dma-mapping API.  Do not use directly.
+ * Their sole purpose is to ensure that data held in the cache
+ * is visible to DMA, or data written by DMA to system memory is
+ * visible to the CPU.
+ */
+#define dmac_inv_range                  cpu_cache.dma_inv_range
+#define dmac_clean_range                cpu_cache.dma_clean_range
+#define dmac_flush_range                cpu_cache.dma_flush_range
+
+#else
+
+#define __cpuc_flush_kern_all           __glue(_CACHE,_flush_kern_cache_all)
+#define __cpuc_flush_user_all           __glue(_CACHE,_flush_user_cache_all)
+#define __cpuc_flush_user_range         __glue(_CACHE,_flush_user_cache_range)
+#define __cpuc_coherent_kern_range      __glue(_CACHE,_coherent_kern_range)
+#define __cpuc_coherent_user_range      __glue(_CACHE,_coherent_user_range)
+#define __cpuc_flush_dcache_page        __glue(_CACHE,_flush_kern_dcache_page)
+
+extern void __cpuc_flush_kern_all(void);
+extern void __cpuc_flush_user_all(void);
+extern void __cpuc_flush_user_range(unsigned long, unsigned long, unsigned int);
+extern void __cpuc_coherent_kern_range(unsigned long, unsigned long);
+extern void __cpuc_coherent_user_range(unsigned long, unsigned long);
+extern void __cpuc_flush_dcache_page(void *);
+
+/*
+ * These are private to the dma-mapping API.  Do not use directly.
+ * Their sole purpose is to ensure that data held in the cache
+ * is visible to DMA, or data written by DMA to system memory is
+ * visible to the CPU.
+ */
+#define dmac_inv_range                  __glue(_CACHE,_dma_inv_range)
+#define dmac_clean_range                __glue(_CACHE,_dma_clean_range)
+#define dmac_flush_range                __glue(_CACHE,_dma_flush_range)
+
+extern void dmac_inv_range(unsigned long, unsigned long);
+extern void dmac_clean_range(unsigned long, unsigned long);
+extern void dmac_flush_range(unsigned long, unsigned long);
+
+#endif
+
+/*
+ * flush_cache_vmap() is used when creating mappings (eg, via vmap,
+ * vmalloc, ioremap etc) in kernel space for pages.  Since the
+ * direct-mappings of these pages may contain cached data, we need
+ * to do a full cache flush to ensure that writebacks don't corrupt
+ * data placed into these pages via the new mappings.
+ */
+#define flush_cache_vmap(start, end)            flush_cache_all()
+#define flush_cache_vunmap(start, end)          flush_cache_all()
+
+/*
+ * Copy user data from/to a page which is mapped into a different
+ * processes address space.  Really, we want to allow our "user
+ * space" model to handle this.
+ */
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+        do {                                                    \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));\
+                memcpy(dst, src, len);                          \
+                flush_dcache_page(page);                        \
+        } while (0)
+
+#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
+        do {                                                    \
+                flush_cache_page(vma, vaddr, page_to_pfn(page));\
+                memcpy(dst, src, len);                          \
+        } while (0)
+
+/*
+ * Convert calls to our calling convention.
+ */
+#define flush_cache_all()               __cpuc_flush_kern_all()
+
+static inline void flush_cache_mm(struct mm_struct *mm)
+{
+        if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask))
+                __cpuc_flush_user_all();
+}
+
+static inline void
+flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
+{
+        if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask))
+                __cpuc_flush_user_range(start & PAGE_MASK, PAGE_ALIGN(end),
+                                        vma->vm_flags);
+}
+
+static inline void
+flush_cache_page(struct vm_area_struct *vma, unsigned long user_addr, unsigned long pfn)
+{
+        if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
+                unsigned long addr = user_addr & PAGE_MASK;
+                __cpuc_flush_user_range(addr, addr + PAGE_SIZE, vma->vm_flags);
+        }
+}
+
+/*
+ * flush_cache_user_range is used when we want to ensure that the
+ * Harvard caches are synchronised for the user space address range.
+ * This is used for the ARM private sys_cacheflush system call.
+ */
+#define flush_cache_user_range(vma,start,end) \
+        __cpuc_coherent_user_range((start) & PAGE_MASK, PAGE_ALIGN(end))
+
+/*
+ * Perform necessary cache operations to ensure that data previously
+ * stored within this range of addresses can be executed by the CPU.
+ */
+#define flush_icache_range(s,e)         __cpuc_coherent_kern_range(s,e)
+
+/*
+ * Perform necessary cache operations to ensure that the TLB will
+ * see data written in the specified area.
+ */
+#define clean_dcache_area(start,size)   cpu_dcache_clean_area(start, size)
+
+/*
+ * flush_dcache_page is used when the kernel has written to the page
+ * cache page at virtual address page->virtual.
+ *
+ * If this page isn't mapped (ie, page_mapping == NULL), or it might
+ * have userspace mappings, then we _must_ always clean + invalidate
+ * the dcache entries associated with the kernel mapping.
+ *
+ * Otherwise we can defer the operation, and clean the cache when we are
+ * about to change to user space.  This is the same method as used on SPARC64.
+ * See update_mmu_cache for the user space part.
+ */
+extern void flush_dcache_page(struct page *);
+
+#define flush_dcache_mmap_lock(mapping) \
+        write_lock_irq(&(mapping)->tree_lock)
+#define flush_dcache_mmap_unlock(mapping) \
+        write_unlock_irq(&(mapping)->tree_lock)
+
+#define flush_icache_user_range(vma,page,addr,len) \
+        flush_dcache_page(page)
+
+/*
+ * We don't appear to need to do anything here.  In fact, if we did, we'd
+ * duplicate cache flushing elsewhere performed by flush_dcache_page().
+ */
+#define flush_icache_page(vma,page)     do { } while (0)
+
+#define __cacheid_present(val)          (val != read_cpuid(CPUID_ID))
+#define __cacheid_vivt(val)             ((val & (15 << 25)) != (14 << 25))
+#define __cacheid_vipt(val)             ((val & (15 << 25)) == (14 << 25))
+#define __cacheid_vipt_nonaliasing(val) ((val & (15 << 25 | 1 << 23)) == (14 << 25))
+#define __cacheid_vipt_aliasing(val)    ((val & (15 << 25 | 1 << 23)) == (14 << 25 | 1 << 23))
+
+#if defined(CONFIG_CPU_CACHE_VIVT) && !defined(CONFIG_CPU_CACHE_VIPT)
+
+#define cache_is_vivt()                 1
+#define cache_is_vipt()                 0
+#define cache_is_vipt_nonaliasing()     0
+#define cache_is_vipt_aliasing()        0
+
+#elif defined(CONFIG_CPU_CACHE_VIPT)
+
+#define cache_is_vivt()                 0
+#define cache_is_vipt()                 1
+#define cache_is_vipt_nonaliasing()                                     \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_vipt_nonaliasing(__val);                      \
+        })
+
+#define cache_is_vipt_aliasing()                                        \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_vipt_aliasing(__val);                         \
+        })
+
+#else
+
+#define cache_is_vivt()                                                 \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                (!__cacheid_present(__val)) || __cacheid_vivt(__val);   \
+        })
+                
+#define cache_is_vipt()                                                 \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_present(__val) && __cacheid_vipt(__val);      \
+        })
+
+#define cache_is_vipt_nonaliasing()                                     \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_present(__val) &&                             \
+                 __cacheid_vipt_nonaliasing(__val);                     \
+        })
+
+#define cache_is_vipt_aliasing()                                        \
+        ({                                                              \
+                unsigned int __val = read_cpuid(CPUID_CACHETYPE);       \
+                __cacheid_present(__val) &&                             \
+                 __cacheid_vipt_aliasing(__val);                        \
+        })
+
+#endif
+
+#endif
diff --git a/include/asm-arm/checksum.h b/include/asm-arm/checksum.h
new file mode 100644
index 000000000000..d4256d5f3a7c
--- /dev/null
+++ b/include/asm-arm/checksum.h
@@ -0,0 +1,160 @@
+/*
+ *  linux/include/asm-arm/checksum.h
+ *
+ * IP checksum routines
+ *
+ * Copyright (C) Original authors of ../asm-i386/checksum.h
+ * Copyright (C) 1996-1999 Russell King
+ */
+#ifndef __ASM_ARM_CHECKSUM_H
+#define __ASM_ARM_CHECKSUM_H
+
+#include <linux/in6.h>
+
+/*
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum);
+
+/*
+ * the same as csum_partial, but copies from src while it
+ * checksums, and handles user-space pointer exceptions correctly, when needed.
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+unsigned int
+csum_partial_copy_nocheck(const char *src, char *dst, int len, int sum);
+
+unsigned int
+csum_partial_copy_from_user(const char __user *src, char *dst, int len, int sum, int *err_ptr);
+
+/*
+ * This is the old (and unsafe) way of doing checksums, a warning message will
+ * be printed if it is used and an exception occurs.
+ *
+ * this functions should go away after some time.
+ */
+#define csum_partial_copy(src,dst,len,sum)      csum_partial_copy_nocheck(src,dst,len,sum)
+
+/*
+ *      This is a version of ip_compute_csum() optimized for IP headers,
+ *      which always checksum on 4 octet boundaries.
+ */
+static inline unsigned short
+ip_fast_csum(unsigned char * iph, unsigned int ihl)
+{
+        unsigned int sum, tmp1;
+
+        __asm__ __volatile__(
+        "ldr    %0, [%1], #4            @ ip_fast_csum          \n\
+        ldr     %3, [%1], #4                                    \n\
+        sub     %2, %2, #5                                      \n\
+        adds    %0, %0, %3                                      \n\
+        ldr     %3, [%1], #4                                    \n\
+        adcs    %0, %0, %3                                      \n\
+        ldr     %3, [%1], #4                                    \n\
+1:      adcs    %0, %0, %3                                      \n\
+        ldr     %3, [%1], #4                                    \n\
+        tst     %2, #15                 @ do this carefully     \n\
+        subne   %2, %2, #1              @ without destroying    \n\
+        bne     1b                      @ the carry flag        \n\
+        adcs    %0, %0, %3                                      \n\
+        adc     %0, %0, #0                                      \n\
+        adds    %0, %0, %0, lsl #16                             \n\
+        addcs   %0, %0, #0x10000                                \n\
+        mvn     %0, %0                                          \n\
+        mov     %0, %0, lsr #16"
+        : "=r" (sum), "=r" (iph), "=r" (ihl), "=r" (tmp1)
+        : "1" (iph), "2" (ihl)
+        : "cc");
+        return sum;
+}
+
+/*
+ *      Fold a partial checksum without adding pseudo headers
+ */
+static inline unsigned int
+csum_fold(unsigned int sum)
+{
+        __asm__(
+        "adds   %0, %1, %1, lsl #16     @ csum_fold             \n\
+        addcs   %0, %0, #0x10000"
+        : "=r" (sum)
+        : "r" (sum)
+        : "cc");
+        return (~sum) >> 16;
+}
+
+static inline unsigned int
+csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len,
+                   unsigned int proto, unsigned int sum)
+{
+        __asm__(
+        "adds   %0, %1, %2              @ csum_tcpudp_nofold    \n\
+        adcs    %0, %0, %3                                      \n\
+        adcs    %0, %0, %4                                      \n\
+        adcs    %0, %0, %5                                      \n\
+        adc     %0, %0, #0"
+        : "=&r"(sum)
+        : "r" (sum), "r" (daddr), "r" (saddr), "r" (ntohs(len)), "Ir" (ntohs(proto))
+        : "cc");
+        return sum;
+}       
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+static inline unsigned short int
+csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len,
+                  unsigned int proto, unsigned int sum)
+{
+        __asm__(
+        "adds   %0, %1, %2              @ csum_tcpudp_magic     \n\
+        adcs    %0, %0, %3                                      \n\
+        adcs    %0, %0, %4                                      \n\
+        adcs    %0, %0, %5                                      \n\
+        adc     %0, %0, #0                                      \n\
+        adds    %0, %0, %0, lsl #16                             \n\
+        addcs   %0, %0, #0x10000                                \n\
+        mvn     %0, %0"
+        : "=&r"(sum)
+        : "r" (sum), "r" (daddr), "r" (saddr), "r" (ntohs(len)), "Ir" (ntohs(proto))
+        : "cc");
+        return sum >> 16;
+}
+
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+static inline unsigned short
+ip_compute_csum(unsigned char * buff, int len)
+{
+        return csum_fold(csum_partial(buff, len, 0));
+}
+
+#define _HAVE_ARCH_IPV6_CSUM
+extern unsigned long
+__csum_ipv6_magic(struct in6_addr *saddr, struct in6_addr *daddr, __u32 len,
+                __u32 proto, unsigned int sum);
+
+static inline unsigned short int
+csum_ipv6_magic(struct in6_addr *saddr, struct in6_addr *daddr, __u32 len,
+                unsigned short proto, unsigned int sum)
+{
+        return csum_fold(__csum_ipv6_magic(saddr, daddr, htonl(len),
+                                           htonl(proto), sum));
+}
+#endif
diff --git a/include/asm-arm/cpu-multi32.h b/include/asm-arm/cpu-multi32.h
new file mode 100644
index 000000000000..ff48022e4720
--- /dev/null
+++ b/include/asm-arm/cpu-multi32.h
@@ -0,0 +1,64 @@
+/*
+ *  linux/include/asm-arm/cpu-multi32.h
+ *
+ *  Copyright (C) 2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm/page.h>
+
+struct mm_struct;
+
+/*
+ * Don't change this structure - ASM code
+ * relies on it.
+ */
+extern struct processor {
+        /* MISC
+         * get data abort address/flags
+         */
+        void (*_data_abort)(unsigned long pc);
+        /*
+         * Set up any processor specifics
+         */
+        void (*_proc_init)(void);
+        /*
+         * Disable any processor specifics
+         */
+        void (*_proc_fin)(void);
+        /*
+         * Special stuff for a reset
+         */
+        volatile void (*reset)(unsigned long addr);
+        /*
+         * Idle the processor
+         */
+        int (*_do_idle)(void);
+        /*
+         * Processor architecture specific
+         */
+        /*
+         * clean a virtual address range from the
+         * D-cache without flushing the cache.
+         */
+        void (*dcache_clean_area)(void *addr, int size);
+
+        /*
+         * Set the page table
+         */
+        void (*switch_mm)(unsigned long pgd_phys, struct mm_struct *mm);
+        /*
+         * Set a PTE
+         */
+        void (*set_pte)(pte_t *ptep, pte_t pte);
+} processor;
+
+#define cpu_proc_init()                 processor._proc_init()
+#define cpu_proc_fin()                  processor._proc_fin()
+#define cpu_reset(addr)                 processor.reset(addr)
+#define cpu_do_idle()                   processor._do_idle()
+#define cpu_dcache_clean_area(addr,sz)  processor.dcache_clean_area(addr,sz)
+#define cpu_set_pte(ptep, pte)          processor.set_pte(ptep, pte)
+#define cpu_do_switch_mm(pgd,mm)        processor.switch_mm(pgd,mm)
diff --git a/include/asm-arm/cpu-single.h b/include/asm-arm/cpu-single.h
new file mode 100644
index 000000000000..b5ec5d54665d
--- /dev/null
+++ b/include/asm-arm/cpu-single.h
@@ -0,0 +1,44 @@
+/*
+ *  linux/include/asm-arm/cpu-single.h
+ *
+ *  Copyright (C) 2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*
+ * Single CPU
+ */
+#ifdef __STDC__
+#define __catify_fn(name,x)     name##x
+#else
+#define __catify_fn(name,x)     name/**/x
+#endif
+#define __cpu_fn(name,x)        __catify_fn(name,x)
+
+/*
+ * If we are supporting multiple CPUs, then we must use a table of
+ * function pointers for this lot.  Otherwise, we can optimise the
+ * table away.
+ */
+#define cpu_proc_init                   __cpu_fn(CPU_NAME,_proc_init)
+#define cpu_proc_fin                    __cpu_fn(CPU_NAME,_proc_fin)
+#define cpu_reset                       __cpu_fn(CPU_NAME,_reset)
+#define cpu_do_idle                     __cpu_fn(CPU_NAME,_do_idle)
+#define cpu_dcache_clean_area           __cpu_fn(CPU_NAME,_dcache_clean_area)
+#define cpu_do_switch_mm                __cpu_fn(CPU_NAME,_switch_mm)
+#define cpu_set_pte                     __cpu_fn(CPU_NAME,_set_pte)
+
+#include <asm/page.h>
+
+struct mm_struct;
+
+/* declare all the functions as extern */
+extern void cpu_proc_init(void);
+extern void cpu_proc_fin(void);
+extern int cpu_do_idle(void);
+extern void cpu_dcache_clean_area(void *, int);
+extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
+extern void cpu_set_pte(pte_t *ptep, pte_t pte);
+extern volatile void cpu_reset(unsigned long addr);
diff --git a/include/asm-arm/cpu.h b/include/asm-arm/cpu.h
new file mode 100644
index 000000000000..fcbdd40cb667
--- /dev/null
+++ b/include/asm-arm/cpu.h
@@ -0,0 +1,25 @@
+/*
+ *  linux/include/asm-arm/cpu.h
+ *
+ *  Copyright (C) 2004-2005 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_CPU_H
+#define __ASM_ARM_CPU_H
+
+#include <linux/config.h>
+#include <linux/percpu.h>
+
+struct cpuinfo_arm {
+        struct cpu      cpu;
+#ifdef CONFIG_SMP
+        unsigned int    loops_per_jiffy;
+#endif
+};
+
+DECLARE_PER_CPU(struct cpuinfo_arm, cpu_data);
+
+#endif
diff --git a/include/asm-arm/cputime.h b/include/asm-arm/cputime.h
new file mode 100644
index 000000000000..3a8002a5fec7
--- /dev/null
+++ b/include/asm-arm/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __ARM_CPUTIME_H
+#define __ARM_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif /* __ARM_CPUTIME_H */
diff --git a/include/asm-arm/current.h b/include/asm-arm/current.h
new file mode 100644
index 000000000000..75d21e2a3ff7
--- /dev/null
+++ b/include/asm-arm/current.h
@@ -0,0 +1,15 @@
+#ifndef _ASMARM_CURRENT_H
+#define _ASMARM_CURRENT_H
+
+#include <linux/thread_info.h>
+
+static inline struct task_struct *get_current(void) __attribute_const__;
+
+static inline struct task_struct *get_current(void)
+{
+        return current_thread_info()->task;
+}
+
+#define current (get_current())
+
+#endif /* _ASMARM_CURRENT_H */
diff --git a/include/asm-arm/delay.h b/include/asm-arm/delay.h
new file mode 100644
index 000000000000..1704360e9699
--- /dev/null
+++ b/include/asm-arm/delay.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 1995-2004 Russell King
+ *
+ * Delay routines, using a pre-computed "loops_per_second" value.
+ */
+#ifndef __ASM_ARM_DELAY_H
+#define __ASM_ARM_DELAY_H
+
+extern void __delay(int loops);
+
+/*
+ * This function intentionally does not exist; if you see references to
+ * it, it means that you're calling udelay() with an out of range value.
+ *
+ * With currently imposed limits, this means that we support a max delay
+ * of 2000us and 671 bogomips
+ */
+extern void __bad_udelay(void);
+
+/*
+ * division by multiplication: you don't have to worry about
+ * loss of precision.
+ *
+ * Use only for very small delays ( < 1 msec).  Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays.  This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+extern void __udelay(unsigned long usecs);
+extern void __const_udelay(unsigned long);
+
+#define MAX_UDELAY_MS 2
+
+#define udelay(n)                                               \
+        (__builtin_constant_p(n) ?                              \
+          ((n) > (MAX_UDELAY_MS * 1000) ? __bad_udelay() :      \
+                        __const_udelay((n) * 0x68dbul)) :       \
+          __udelay(n))
+
+#endif /* defined(_ARM_DELAY_H) */
+
diff --git a/include/asm-arm/div64.h b/include/asm-arm/div64.h
new file mode 100644
index 000000000000..3682616804ca
--- /dev/null
+++ b/include/asm-arm/div64.h
@@ -0,0 +1,48 @@
+#ifndef __ASM_ARM_DIV64
+#define __ASM_ARM_DIV64
+
+#include <asm/system.h>
+
+/*
+ * The semantics of do_div() are:
+ *
+ * uint32_t do_div(uint64_t *n, uint32_t base)
+ * {
+ *      uint32_t remainder = *n % base;
+ *      *n = *n / base;
+ *      return remainder;
+ * }
+ *
+ * In other words, a 64-bit dividend with a 32-bit divisor producing
+ * a 64-bit result and a 32-bit remainder.  To accomplish this optimally
+ * we call a special __do_div64 helper with completely non standard
+ * calling convention for arguments and results (beware).
+ */
+
+#ifdef __ARMEB__
+#define __xh "r0"
+#define __xl "r1"
+#else
+#define __xl "r0"
+#define __xh "r1"
+#endif
+
+#define do_div(n,base)                                          \
+({                                                              \
+        register unsigned int __base      asm("r4") = base;     \
+        register unsigned long long __n   asm("r0") = n;        \
+        register unsigned long long __res asm("r2");            \
+        register unsigned int __rem       asm(__xh);            \
+        asm(    __asmeq("%0", __xh)                             \
+                __asmeq("%1", "r2")                             \
+                __asmeq("%2", "r0")                             \
+                __asmeq("%3", "r4")                             \
+                "bl     __do_div64"                             \
+                : "=r" (__rem), "=r" (__res)                    \
+                : "r" (__n), "r" (__base)                       \
+                : "ip", "lr", "cc");                            \
+        n = __res;                                              \
+        __rem;                                                  \
+})
+
+#endif
diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h
new file mode 100644
index 000000000000..925d016dd4b5
--- /dev/null
+++ b/include/asm-arm/dma-mapping.h
@@ -0,0 +1,426 @@
+#ifndef ASMARM_DMA_MAPPING_H
+#define ASMARM_DMA_MAPPING_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+#include <linux/mm.h> /* need struct page */
+
+#include <asm/scatterlist.h>
+
+/*
+ * DMA-consistent mapping functions.  These allocate/free a region of
+ * uncached, unwrite-buffered mapped memory space for use with DMA
+ * devices.  This is the "generic" version.  The PCI specific version
+ * is in pci.h
+ */
+extern void consistent_sync(void *kaddr, size_t size, int rw);
+
+/*
+ * Return whether the given device DMA address mask can be supported
+ * properly.  For example, if your device can only drive the low 24-bits
+ * during bus mastering, then you would pass 0x00ffffff as the mask
+ * to this function.
+ */
+static inline int dma_supported(struct device *dev, u64 mask)
+{
+        return dev->dma_mask && *dev->dma_mask != 0;
+}
+
+static inline int dma_set_mask(struct device *dev, u64 dma_mask)
+{
+        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
+                return -EIO;
+
+        *dev->dma_mask = dma_mask;
+
+        return 0;
+}
+
+static inline int dma_get_cache_alignment(void)
+{
+        return 32;
+}
+
+static inline int dma_is_consistent(dma_addr_t handle)
+{
+        return 0;
+}
+
+/*
+ * DMA errors are defined by all-bits-set in the DMA address.
+ */
+static inline int dma_mapping_error(dma_addr_t dma_addr)
+{
+        return dma_addr == ~0;
+}
+
+/**
+ * dma_alloc_coherent - allocate consistent memory for DMA
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @size: required memory size
+ * @handle: bus-specific DMA address
+ *
+ * Allocate some uncached, unbuffered memory for a device for
+ * performing DMA.  This function allocates pages, and will
+ * return the CPU-viewed address, and sets @handle to be the
+ * device-viewed address.
+ */
+extern void *
+dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
+
+/**
+ * dma_free_coherent - free memory allocated by dma_alloc_coherent
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @size: size of memory originally requested in dma_alloc_coherent
+ * @cpu_addr: CPU-view address returned from dma_alloc_coherent
+ * @handle: device-view address returned from dma_alloc_coherent
+ *
+ * Free (and unmap) a DMA buffer previously allocated by
+ * dma_alloc_coherent().
+ *
+ * References to memory and mappings associated with cpu_addr/handle
+ * during and after this call executing are illegal.
+ */
+extern void
+dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
+                  dma_addr_t handle);
+
+/**
+ * dma_mmap_coherent - map a coherent DMA allocation into user space
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @vma: vm_area_struct describing requested user mapping
+ * @cpu_addr: kernel CPU-view address returned from dma_alloc_coherent
+ * @handle: device-view address returned from dma_alloc_coherent
+ * @size: size of memory originally requested in dma_alloc_coherent
+ *
+ * Map a coherent DMA buffer previously allocated by dma_alloc_coherent
+ * into user space.  The coherent DMA buffer must not be freed by the
+ * driver until the user space mapping has been released.
+ */
+int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma,
+                      void *cpu_addr, dma_addr_t handle, size_t size);
+
+
+/**
+ * dma_alloc_writecombine - allocate writecombining memory for DMA
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @size: required memory size
+ * @handle: bus-specific DMA address
+ *
+ * Allocate some uncached, buffered memory for a device for
+ * performing DMA.  This function allocates pages, and will
+ * return the CPU-viewed address, and sets @handle to be the
+ * device-viewed address.
+ */
+extern void *
+dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, int gfp);
+
+#define dma_free_writecombine(dev,size,cpu_addr,handle) \
+        dma_free_coherent(dev,size,cpu_addr,handle)
+
+int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma,
+                          void *cpu_addr, dma_addr_t handle, size_t size);
+
+
+/**
+ * dma_map_single - map a single buffer for streaming DMA
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @cpu_addr: CPU direct mapped address of buffer
+ * @size: size of buffer to map
+ * @dir: DMA transfer direction
+ *
+ * Ensure that any data held in the cache is appropriately discarded
+ * or written back.
+ *
+ * The device owns this memory once this call has completed.  The CPU
+ * can regain ownership by calling dma_unmap_single() or
+ * dma_sync_single_for_cpu().
+ */
+#ifndef CONFIG_DMABOUNCE
+static inline dma_addr_t
+dma_map_single(struct device *dev, void *cpu_addr, size_t size,
+               enum dma_data_direction dir)
+{
+        consistent_sync(cpu_addr, size, dir);
+        return virt_to_dma(dev, (unsigned long)cpu_addr);
+}
+#else
+extern dma_addr_t dma_map_single(struct device *,void *, size_t, enum dma_data_direction);
+#endif
+
+/**
+ * dma_map_page - map a portion of a page for streaming DMA
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @page: page that buffer resides in
+ * @offset: offset into page for start of buffer
+ * @size: size of buffer to map
+ * @dir: DMA transfer direction
+ *
+ * Ensure that any data held in the cache is appropriately discarded
+ * or written back.
+ *
+ * The device owns this memory once this call has completed.  The CPU
+ * can regain ownership by calling dma_unmap_page() or
+ * dma_sync_single_for_cpu().
+ */
+static inline dma_addr_t
+dma_map_page(struct device *dev, struct page *page,
+             unsigned long offset, size_t size,
+             enum dma_data_direction dir)
+{
+        return dma_map_single(dev, page_address(page) + offset, size, (int)dir);
+}
+
+/**
+ * dma_unmap_single - unmap a single buffer previously mapped
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @handle: DMA address of buffer
+ * @size: size of buffer to map
+ * @dir: DMA transfer direction
+ *
+ * Unmap a single streaming mode DMA translation.  The handle and size
+ * must match what was provided in the previous dma_map_single() call.
+ * All other usages are undefined.
+ *
+ * After this call, reads by the CPU to the buffer are guaranteed to see
+ * whatever the device wrote there.
+ */
+#ifndef CONFIG_DMABOUNCE
+static inline void
+dma_unmap_single(struct device *dev, dma_addr_t handle, size_t size,
+                 enum dma_data_direction dir)
+{
+        /* nothing to do */
+}
+#else
+extern void dma_unmap_single(struct device *, dma_addr_t, size_t, enum dma_data_direction);
+#endif
+
+/**
+ * dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @handle: DMA address of buffer
+ * @size: size of buffer to map
+ * @dir: DMA transfer direction
+ *
+ * Unmap a single streaming mode DMA translation.  The handle and size
+ * must match what was provided in the previous dma_map_single() call.
+ * All other usages are undefined.
+ *
+ * After this call, reads by the CPU to the buffer are guaranteed to see
+ * whatever the device wrote there.
+ */
+static inline void
+dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
+               enum dma_data_direction dir)
+{
+        dma_unmap_single(dev, handle, size, (int)dir);
+}
+
+/**
+ * dma_map_sg - map a set of SG buffers for streaming mode DMA
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @sg: list of buffers
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
+ *
+ * Map a set of buffers described by scatterlist in streaming
+ * mode for DMA.  This is the scatter-gather version of the
+ * above dma_map_single interface.  Here the scatter gather list
+ * elements are each tagged with the appropriate dma address
+ * and length.  They are obtained via sg_dma_{address,length}(SG).
+ *
+ * NOTE: An implementation may be able to use a smaller number of
+ *       DMA address/length pairs than there are SG table elements.
+ *       (for example via virtual mapping capabilities)
+ *       The routine returns the number of addr/length pairs actually
+ *       used, at most nents.
+ *
+ * Device ownership issues as mentioned above for dma_map_single are
+ * the same here.
+ */
+#ifndef CONFIG_DMABOUNCE
+static inline int
+dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+           enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nents; i++, sg++) {
+                char *virt;
+
+                sg->dma_address = page_to_dma(dev, sg->page) + sg->offset;
+                virt = page_address(sg->page) + sg->offset;
+                consistent_sync(virt, sg->length, dir);
+        }
+
+        return nents;
+}
+#else
+extern int dma_map_sg(struct device *, struct scatterlist *, int, enum dma_data_direction);
+#endif
+
+/**
+ * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @sg: list of buffers
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
+ *
+ * Unmap a set of streaming mode DMA translations.
+ * Again, CPU read rules concerning calls here are the same as for
+ * dma_unmap_single() above.
+ */
+#ifndef CONFIG_DMABOUNCE
+static inline void
+dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
+             enum dma_data_direction dir)
+{
+
+        /* nothing to do */
+}
+#else
+extern void dma_unmap_sg(struct device *, struct scatterlist *, int, enum dma_data_direction);
+#endif
+
+
+/**
+ * dma_sync_single_for_cpu
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @handle: DMA address of buffer
+ * @size: size of buffer to map
+ * @dir: DMA transfer direction
+ *
+ * Make physical memory consistent for a single streaming mode DMA
+ * translation after a transfer.
+ *
+ * If you perform a dma_map_single() but wish to interrogate the
+ * buffer using the cpu, yet do not wish to teardown the PCI dma
+ * mapping, you must call this function before doing so.  At the
+ * next point you give the PCI dma address back to the card, you
+ * must first the perform a dma_sync_for_device, and then the
+ * device again owns the buffer.
+ */
+#ifndef CONFIG_DMABOUNCE
+static inline void
+dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size,
+                        enum dma_data_direction dir)
+{
+        consistent_sync((void *)dma_to_virt(dev, handle), size, dir);
+}
+
+static inline void
+dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size,
+                           enum dma_data_direction dir)
+{
+        consistent_sync((void *)dma_to_virt(dev, handle), size, dir);
+}
+#else
+extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction);
+extern void dma_sync_single_for_device(struct device*, dma_addr_t, size_t, enum dma_data_direction);
+#endif
+
+
+/**
+ * dma_sync_sg_for_cpu
+ * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
+ * @sg: list of buffers
+ * @nents: number of buffers to map
+ * @dir: DMA transfer direction
+ *
+ * Make physical memory consistent for a set of streaming
+ * mode DMA translations after a transfer.
+ *
+ * The same as dma_sync_single_for_* but for a scatter-gather list,
+ * same rules and usage.
+ */
+#ifndef CONFIG_DMABOUNCE
+static inline void
+dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
+                    enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nents; i++, sg++) {
+                char *virt = page_address(sg->page) + sg->offset;
+                consistent_sync(virt, sg->length, dir);
+        }
+}
+
+static inline void
+dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
+                       enum dma_data_direction dir)
+{
+        int i;
+
+        for (i = 0; i < nents; i++, sg++) {
+                char *virt = page_address(sg->page) + sg->offset;
+                consistent_sync(virt, sg->length, dir);
+        }
+}
+#else
+extern void dma_sync_sg_for_cpu(struct device*, struct scatterlist*, int, enum dma_data_direction);
+extern void dma_sync_sg_for_device(struct device*, struct scatterlist*, int, enum dma_data_direction);
+#endif
+
+#ifdef CONFIG_DMABOUNCE
+/*
+ * For SA-1111, IXP425, and ADI systems  the dma-mapping functions are "magic"
+ * and utilize bounce buffers as needed to work around limited DMA windows.
+ *
+ * On the SA-1111, a bug limits DMA to only certain regions of RAM.
+ * On the IXP425, the PCI inbound window is 64MB (256MB total RAM)
+ * On some ADI engineering sytems, PCI inbound window is 32MB (12MB total RAM)
+ *
+ * The following are helper functions used by the dmabounce subystem
+ *
+ */
+
+/**
+ * dmabounce_register_dev
+ *
+ * @dev: valid struct device pointer
+ * @small_buf_size: size of buffers to use with small buffer pool
+ * @large_buf_size: size of buffers to use with large buffer pool (can be 0)
+ *
+ * This function should be called by low-level platform code to register
+ * a device as requireing DMA buffer bouncing. The function will allocate
+ * appropriate DMA pools for the device.
+ *
+ */
+extern int dmabounce_register_dev(struct device *, unsigned long, unsigned long);
+
+/**
+ * dmabounce_unregister_dev
+ *
+ * @dev: valid struct device pointer
+ *
+ * This function should be called by low-level platform code when device
+ * that was previously registered with dmabounce_register_dev is removed
+ * from the system.
+ *
+ */
+extern void dmabounce_unregister_dev(struct device *);
+
+/**
+ * dma_needs_bounce
+ *
+ * @dev: valid struct device pointer
+ * @dma_handle: dma_handle of unbounced buffer
+ * @size: size of region being mapped
+ *
+ * Platforms that utilize the dmabounce mechanism must implement
+ * this function.
+ *
+ * The dmabounce routines call this function whenever a dma-mapping
+ * is requested to determine whether a given buffer needs to be bounced
+ * or not. The function must return 0 if the the buffer is OK for
+ * DMA access and 1 if the buffer needs to be bounced.
+ *
+ */
+extern int dma_needs_bounce(struct device*, dma_addr_t, size_t);
+#endif /* CONFIG_DMABOUNCE */
+
+#endif /* __KERNEL__ */
+#endif
diff --git a/include/asm-arm/dma.h b/include/asm-arm/dma.h
new file mode 100644
index 000000000000..ef41df43a584
--- /dev/null
+++ b/include/asm-arm/dma.h
@@ -0,0 +1,135 @@
+#ifndef __ASM_ARM_DMA_H
+#define __ASM_ARM_DMA_H
+
+typedef unsigned int dmach_t;
+
+#include <linux/config.h>
+#include <linux/spinlock.h>
+#include <asm/system.h>
+#include <asm/scatterlist.h>
+#include <asm/arch/dma.h>
+
+/*
+ * DMA modes
+ */
+typedef unsigned int dmamode_t;
+
+#define DMA_MODE_MASK   3
+
+#define DMA_MODE_READ    0
+#define DMA_MODE_WRITE   1
+#define DMA_MODE_CASCADE 2
+#define DMA_AUTOINIT     4
+
+extern spinlock_t  dma_spin_lock;
+
+static inline unsigned long claim_dma_lock(void)
+{
+        unsigned long flags;
+        spin_lock_irqsave(&dma_spin_lock, flags);
+        return flags;
+}
+
+static inline void release_dma_lock(unsigned long flags)
+{
+        spin_unlock_irqrestore(&dma_spin_lock, flags);
+}
+
+/* Clear the 'DMA Pointer Flip Flop'.
+ * Write 0 for LSB/MSB, 1 for MSB/LSB access.
+ */
+#define clear_dma_ff(channel)
+
+/* Set only the page register bits of the transfer address.
+ *
+ * NOTE: This is an architecture specific function, and should
+ *       be hidden from the drivers
+ */
+extern void set_dma_page(dmach_t channel, char pagenr);
+
+/* Request a DMA channel
+ *
+ * Some architectures may need to do allocate an interrupt
+ */
+extern int  request_dma(dmach_t channel, const char * device_id);
+
+/* Free a DMA channel
+ *
+ * Some architectures may need to do free an interrupt
+ */
+extern void free_dma(dmach_t channel);
+
+/* Enable DMA for this channel
+ *
+ * On some architectures, this may have other side effects like
+ * enabling an interrupt and setting the DMA registers.
+ */
+extern void enable_dma(dmach_t channel);
+
+/* Disable DMA for this channel
+ *
+ * On some architectures, this may have other side effects like
+ * disabling an interrupt or whatever.
+ */
+extern void disable_dma(dmach_t channel);
+
+/* Test whether the specified channel has an active DMA transfer
+ */
+extern int dma_channel_active(dmach_t channel);
+
+/* Set the DMA scatter gather list for this channel
+ *
+ * This should not be called if a DMA channel is enabled,
+ * especially since some DMA architectures don't update the
+ * DMA address immediately, but defer it to the enable_dma().
+ */
+extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg);
+
+/* Set the DMA address for this channel
+ *
+ * This should not be called if a DMA channel is enabled,
+ * especially since some DMA architectures don't update the
+ * DMA address immediately, but defer it to the enable_dma().
+ */
+extern void set_dma_addr(dmach_t channel, unsigned long physaddr);
+
+/* Set the DMA byte count for this channel
+ *
+ * This should not be called if a DMA channel is enabled,
+ * especially since some DMA architectures don't update the
+ * DMA count immediately, but defer it to the enable_dma().
+ */
+extern void set_dma_count(dmach_t channel, unsigned long count);
+
+/* Set the transfer direction for this channel
+ *
+ * This should not be called if a DMA channel is enabled,
+ * especially since some DMA architectures don't update the
+ * DMA transfer direction immediately, but defer it to the
+ * enable_dma().
+ */
+extern void set_dma_mode(dmach_t channel, dmamode_t mode);
+
+/* Set the transfer speed for this channel
+ */
+extern void set_dma_speed(dmach_t channel, int cycle_ns);
+
+/* Get DMA residue count. After a DMA transfer, this
+ * should return zero. Reading this while a DMA transfer is
+ * still in progress will return unpredictable results.
+ * If called before the channel has been used, it may return 1.
+ * Otherwise, it returns the number of _bytes_ left to transfer.
+ */
+extern int  get_dma_residue(dmach_t channel);
+
+#ifndef NO_DMA
+#define NO_DMA  255
+#endif
+
+#ifdef CONFIG_PCI
+extern int isa_dma_bridge_buggy;
+#else
+#define isa_dma_bridge_buggy    (0)
+#endif
+
+#endif /* _ARM_DMA_H */
diff --git a/include/asm-arm/domain.h b/include/asm-arm/domain.h
new file mode 100644
index 000000000000..da1d960387d9
--- /dev/null
+++ b/include/asm-arm/domain.h
@@ -0,0 +1,52 @@
+/*
+ *  linux/include/asm-arm/domain.h
+ *
+ *  Copyright (C) 1999 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROC_DOMAIN_H
+#define __ASM_PROC_DOMAIN_H
+
+/*
+ * Domain numbers
+ *
+ *  DOMAIN_IO     - domain 2 includes all IO only
+ *  DOMAIN_USER   - domain 1 includes all user memory only
+ *  DOMAIN_KERNEL - domain 0 includes all kernel memory only
+ */
+#define DOMAIN_KERNEL   0
+#define DOMAIN_TABLE    0
+#define DOMAIN_USER     1
+#define DOMAIN_IO       2
+
+/*
+ * Domain types
+ */
+#define DOMAIN_NOACCESS 0
+#define DOMAIN_CLIENT   1
+#define DOMAIN_MANAGER  3
+
+#define domain_val(dom,type)    ((type) << (2*(dom)))
+
+#ifndef __ASSEMBLY__
+#define set_domain(x)                                   \
+        do {                                            \
+        __asm__ __volatile__(                           \
+        "mcr    p15, 0, %0, c3, c0      @ set domain"   \
+          : : "r" (x));                                 \
+        } while (0)
+
+#define modify_domain(dom,type)                                 \
+        do {                                                    \
+        struct thread_info *thread = current_thread_info();     \
+        unsigned int domain = thread->cpu_domain;               \
+        domain &= ~domain_val(dom, DOMAIN_MANAGER);             \
+        thread->cpu_domain = domain | domain_val(dom, type);    \
+        set_domain(thread->cpu_domain);                         \
+        } while (0)
+
+#endif
+#endif /* !__ASSEMBLY__ */
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
new file mode 100644
index 000000000000..a0ae2b954d29
--- /dev/null
+++ b/include/asm-arm/ecard.h
@@ -0,0 +1,298 @@
+/*
+ * linux/include/asm-arm/ecard.h
+ *
+ * definitions for expansion cards
+ *
+ * This is a new system as from Linux 1.2.3
+ *
+ * Changelog:
+ *  11-12-1996  RMK     Further minor improvements
+ *  12-09-1997  RMK     Added interrupt enable/disable for card level
+ *
+ * Reference: Acorns Risc OS 3 Programmers Reference Manuals.
+ */
+
+#ifndef __ASM_ECARD_H
+#define __ASM_ECARD_H
+
+/*
+ * Currently understood cards (but not necessarily
+ * supported):
+ *                        Manufacturer  Product ID
+ */
+#define MANU_ACORN              0x0000
+#define PROD_ACORN_SCSI                 0x0002
+#define PROD_ACORN_ETHER1               0x0003
+#define PROD_ACORN_MFM                  0x000b
+
+#define MANU_ANT2               0x0011
+#define PROD_ANT_ETHER3                 0x00a4
+
+#define MANU_ATOMWIDE           0x0017
+#define PROD_ATOMWIDE_3PSERIAL          0x0090
+
+#define MANU_IRLAM_INSTRUMENTS  0x001f
+#define MANU_IRLAM_INSTRUMENTS_ETHERN   0x5678
+
+#define MANU_OAK                0x0021
+#define PROD_OAK_SCSI                   0x0058
+
+#define MANU_MORLEY             0x002b
+#define PROD_MORLEY_SCSI_UNCACHED       0x0067
+
+#define MANU_CUMANA             0x003a
+#define PROD_CUMANA_SCSI_2              0x003a
+#define PROD_CUMANA_SCSI_1              0x00a0
+
+#define MANU_ICS                0x003c
+#define PROD_ICS_IDE                    0x00ae
+
+#define MANU_ICS2               0x003d
+#define PROD_ICS2_IDE                   0x00ae
+
+#define MANU_SERPORT            0x003f
+#define PROD_SERPORT_DSPORT             0x00b9
+
+#define MANU_ARXE               0x0041
+#define PROD_ARXE_SCSI                  0x00be
+
+#define MANU_I3                 0x0046
+#define PROD_I3_ETHERLAN500             0x00d4
+#define PROD_I3_ETHERLAN600             0x00ec
+#define PROD_I3_ETHERLAN600A            0x011e
+
+#define MANU_ANT                0x0053
+#define PROD_ANT_ETHERM                 0x00d8
+#define PROD_ANT_ETHERB                 0x00e4
+
+#define MANU_ALSYSTEMS          0x005b
+#define PROD_ALSYS_SCSIATAPI            0x0107
+
+#define MANU_MCS                0x0063
+#define PROD_MCS_CONNECT32              0x0125
+
+#define MANU_EESOX              0x0064
+#define PROD_EESOX_SCSI2                0x008c
+
+#define MANU_YELLOWSTONE        0x0096
+#define PROD_YELLOWSTONE_RAPIDE32       0x0120
+
+#ifdef ECARD_C
+#define CONST
+#else
+#define CONST const
+#endif
+
+#define MAX_ECARDS      9
+
+typedef enum {                          /* Cards address space          */
+        ECARD_IOC,
+        ECARD_MEMC,
+        ECARD_EASI
+} card_type_t;
+
+typedef enum {                          /* Speed for ECARD_IOC space    */
+        ECARD_SLOW       = 0,
+        ECARD_MEDIUM     = 1,
+        ECARD_FAST       = 2,
+        ECARD_SYNC       = 3
+} card_speed_t;
+
+struct ecard_id {                       /* Card ID structure            */
+        unsigned short  manufacturer;
+        unsigned short  product;
+        void            *data;
+};
+
+struct in_ecid {                        /* Packed card ID information   */
+        unsigned short  product;        /* Product code                 */
+        unsigned short  manufacturer;   /* Manufacturer code            */
+        unsigned char   id:4;           /* Simple ID                    */
+        unsigned char   cd:1;           /* Chunk dir present            */
+        unsigned char   is:1;           /* Interrupt status pointers    */
+        unsigned char   w:2;            /* Width                        */
+        unsigned char   country;        /* Country                      */
+        unsigned char   irqmask;        /* IRQ mask                     */
+        unsigned char   fiqmask;        /* FIQ mask                     */
+        unsigned long   irqoff;         /* IRQ offset                   */
+        unsigned long   fiqoff;         /* FIQ offset                   */
+};
+
+typedef struct expansion_card ecard_t;
+typedef unsigned long *loader_t;
+
+typedef struct {                        /* Card handler routines        */
+        void (*irqenable)(ecard_t *ec, int irqnr);
+        void (*irqdisable)(ecard_t *ec, int irqnr);
+        int  (*irqpending)(ecard_t *ec);
+        void (*fiqenable)(ecard_t *ec, int fiqnr);
+        void (*fiqdisable)(ecard_t *ec, int fiqnr);
+        int  (*fiqpending)(ecard_t *ec);
+} expansioncard_ops_t;
+
+#define ECARD_NUM_RESOURCES     (6)
+
+#define ECARD_RES_IOCSLOW       (0)
+#define ECARD_RES_IOCMEDIUM     (1)
+#define ECARD_RES_IOCFAST       (2)
+#define ECARD_RES_IOCSYNC       (3)
+#define ECARD_RES_MEMC          (4)
+#define ECARD_RES_EASI          (5)
+
+#define ecard_resource_start(ec,nr)     ((ec)->resource[nr].start)
+#define ecard_resource_end(ec,nr)       ((ec)->resource[nr].end)
+#define ecard_resource_len(ec,nr)       ((ec)->resource[nr].end - \
+                                         (ec)->resource[nr].start + 1)
+#define ecard_resource_flags(ec,nr)     ((ec)->resource[nr].flags)
+
+/*
+ * This contains all the info needed on an expansion card
+ */
+struct expansion_card {
+        struct expansion_card  *next;
+
+        struct device           dev;
+        struct resource         resource[ECARD_NUM_RESOURCES];
+
+        /* Public data */
+        void __iomem            *irqaddr;       /* address of IRQ register      */
+        void __iomem            *fiqaddr;       /* address of FIQ register      */
+        unsigned char           irqmask;        /* IRQ mask                     */
+        unsigned char           fiqmask;        /* FIQ mask                     */
+        unsigned char           claimed;        /* Card claimed?                */
+
+        void                    *irq_data;      /* Data for use for IRQ by card */
+        void                    *fiq_data;      /* Data for use for FIQ by card */
+        const expansioncard_ops_t *ops;         /* Enable/Disable Ops for card  */
+
+        CONST unsigned int      slot_no;        /* Slot number                  */
+        CONST unsigned int      dma;            /* DMA number (for request_dma) */
+        CONST unsigned int      irq;            /* IRQ number (for request_irq) */
+        CONST unsigned int      fiq;            /* FIQ number (for request_irq) */
+        CONST card_type_t       type;           /* Type of card                 */
+        CONST struct in_ecid    cid;            /* Card Identification          */
+
+        /* Private internal data */
+        const char              *card_desc;     /* Card description             */
+        CONST unsigned int      podaddr;        /* Base Linux address for card  */
+        CONST loader_t          loader;         /* loader program */
+        u64                     dma_mask;
+};
+
+struct in_chunk_dir {
+        unsigned int start_offset;
+        union {
+                unsigned char string[256];
+                unsigned char data[1];
+        } d;
+};
+
+/*
+ * ecard_claim: claim an expansion card entry
+ */
+#define ecard_claim(ec) ((ec)->claimed = 1)
+
+/*
+ * ecard_release: release an expansion card entry
+ */
+#define ecard_release(ec) ((ec)->claimed = 0)
+
+/*
+ * Read a chunk from an expansion card
+ * cd : where to put read data
+ * ec : expansion card info struct
+ * id : id number to find
+ * num: (n+1)'th id to find.
+ */
+extern int ecard_readchunk (struct in_chunk_dir *cd, struct expansion_card *ec, int id, int num);
+
+/*
+ * Obtain the address of a card.  This returns the "old style" address
+ * and should no longer be used.
+ */
+static inline unsigned int __deprecated
+ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
+{
+        extern unsigned int __ecard_address(struct expansion_card *,
+                                            card_type_t, card_speed_t);
+        return __ecard_address(ec, type, speed);
+}
+
+/*
+ * Request and release ecard resources
+ */
+extern int ecard_request_resources(struct expansion_card *ec);
+extern void ecard_release_resources(struct expansion_card *ec);
+
+#ifdef ECARD_C
+/* Definitions internal to ecard.c - for it's use only!!
+ *
+ * External expansion card header as read from the card
+ */
+struct ex_ecid {
+        unsigned char   r_irq:1;
+        unsigned char   r_zero:1;
+        unsigned char   r_fiq:1;
+        unsigned char   r_id:4;
+        unsigned char   r_a:1;
+
+        unsigned char   r_cd:1;
+        unsigned char   r_is:1;
+        unsigned char   r_w:2;
+        unsigned char   r_r1:4;
+
+        unsigned char   r_r2:8;
+
+        unsigned char   r_prod[2];
+
+        unsigned char   r_manu[2];
+
+        unsigned char   r_country;
+
+        unsigned char   r_fiqmask;
+        unsigned char   r_fiqoff[3];
+
+        unsigned char   r_irqmask;
+        unsigned char   r_irqoff[3];
+};
+
+/*
+ * Chunk directory entry as read from the card
+ */
+struct ex_chunk_dir {
+        unsigned char r_id;
+        unsigned char r_len[3];
+        unsigned long r_start;
+        union {
+                char string[256];
+                char data[1];
+        } d;
+#define c_id(x)         ((x)->r_id)
+#define c_len(x)        ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
+#define c_start(x)      ((x)->r_start)
+};
+
+#endif
+
+extern struct bus_type ecard_bus_type;
+
+#define ECARD_DEV(_d)   container_of((_d), struct expansion_card, dev)
+
+struct ecard_driver {
+        int                     (*probe)(struct expansion_card *, const struct ecard_id *id);
+        void                    (*remove)(struct expansion_card *);
+        void                    (*shutdown)(struct expansion_card *);
+        const struct ecard_id   *id_table;
+        unsigned int            id;
+        struct device_driver    drv;
+};
+
+#define ECARD_DRV(_d)   container_of((_d), struct ecard_driver, drv)
+
+#define ecard_set_drvdata(ec,data)      dev_set_drvdata(&(ec)->dev, (data))
+#define ecard_get_drvdata(ec)           dev_get_drvdata(&(ec)->dev)
+
+int ecard_register_driver(struct ecard_driver *);
+void ecard_remove_driver(struct ecard_driver *);
+
+#endif
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
new file mode 100644
index 000000000000..cbceacbe5afa
--- /dev/null
+++ b/include/asm-arm/elf.h
@@ -0,0 +1,133 @@
+#ifndef __ASMARM_ELF_H
+#define __ASMARM_ELF_H
+
+#include <linux/config.h>
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+#include <asm/user.h>
+#include <asm/procinfo.h>
+
+typedef unsigned long elf_greg_t;
+typedef unsigned long elf_freg_t[3];
+
+#define EM_ARM  40
+#define EF_ARM_APCS26 0x08
+#define EF_ARM_SOFT_FLOAT 0x200
+#define EF_ARM_EABI_MASK 0xFF000000
+
+#define R_ARM_NONE      0
+#define R_ARM_PC24      1
+#define R_ARM_ABS32     2
+
+#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_fp elf_fpregset_t;
+
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && (ELF_PROC_OK((x))) )
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS32
+#ifdef __ARMEB__
+#define ELF_DATA        ELFDATA2MSB;
+#else
+#define ELF_DATA        ELFDATA2LSB;
+#endif
+#define ELF_ARCH        EM_ARM
+
+#define USE_ELF_CORE_DUMP
+#define ELF_EXEC_PAGESIZE       4096
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
+
+/* When the program starts, a1 contains a pointer to a function to be 
+   registered with atexit, as per the SVR4 ABI.  A value of 0 means we 
+   have no such handler.  */
+#define ELF_PLAT_INIT(_r, load_addr)    (_r)->ARM_r0 = 0
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports. */
+
+#define ELF_HWCAP       (elf_hwcap)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo. */
+
+/* For now we just provide a fairly general string that describes the
+   processor family.  This could be made more specific later if someone
+   implemented optimisations that require it.  26-bit CPUs give you
+   "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
+   supported).  32-bit CPUs give you "v3[lb]" for anything based on an
+   ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
+   core.  */
+
+#define ELF_PLATFORM_SIZE 8
+extern char elf_platform[];
+#define ELF_PLATFORM    (elf_platform)
+
+#ifdef __KERNEL__
+
+/*
+ * 32-bit code is always OK.  Some cpus can do 26-bit, some can't.
+ */
+#define ELF_PROC_OK(x)  (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
+
+#define ELF_THUMB_OK(x) \
+        (( (elf_hwcap & HWCAP_THUMB) && ((x)->e_entry & 1) == 1) || \
+         ((x)->e_entry & 3) == 0)
+
+#define ELF_26BIT_OK(x) \
+        (( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \
+          ((x)->e_flags & EF_ARM_APCS26) == 0)
+
+#ifndef CONFIG_IWMMXT
+
+/* Old NetWinder binaries were compiled in such a way that the iBCS
+   heuristic always trips on them.  Until these binaries become uncommon
+   enough not to care, don't trust the `ibcs' flag here.  In any case
+   there is no other ELF system currently supported by iBCS.
+   @@ Could print a warning message to encourage users to upgrade.  */
+#define SET_PERSONALITY(ex,ibcs2) \
+        set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT))
+
+#else
+
+/*
+ * All iWMMXt capable CPUs don't support 26-bit mode.  Yet they can run
+ * legacy binaries which used to contain FPA11 floating point instructions
+ * that have always been emulated by the kernel.  PFA11 and iWMMXt overlap
+ * on coprocessor 1 space though.  We therefore must decide if given task
+ * is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked
+ * at all times for the prefetch exception handler to catch FPA11 opcodes
+ * and emulate them.  The best indication to discriminate those two cases
+ * is the SOFT_FLOAT flag in the ELF header.
+ */
+
+#define SET_PERSONALITY(ex,ibcs2) \
+do { \
+        set_personality(PER_LINUX_32BIT); \
+        if (((ex).e_flags & EF_ARM_EABI_MASK) || \
+            ((ex).e_flags & EF_ARM_SOFT_FLOAT)) \
+                set_thread_flag(TIF_USING_IWMMXT); \
+} while (0)
+
+#endif
+
+#endif
+
+#endif
diff --git a/include/asm-arm/errno.h b/include/asm-arm/errno.h
new file mode 100644
index 000000000000..6e60f0612bb6
--- /dev/null
+++ b/include/asm-arm/errno.h
@@ -0,0 +1,6 @@
+#ifndef _ARM_ERRNO_H
+#define _ARM_ERRNO_H
+
+#include <asm-generic/errno.h>
+
+#endif
diff --git a/include/asm-arm/fcntl.h b/include/asm-arm/fcntl.h
new file mode 100644
index 000000000000..485b6bdf4d7a
--- /dev/null
+++ b/include/asm-arm/fcntl.h
@@ -0,0 +1,87 @@
+#ifndef _ARM_FCNTL_H
+#define _ARM_FCNTL_H
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+   located on an ext2 file system */
+#define O_ACCMODE          0003
+#define O_RDONLY             00
+#define O_WRONLY             01
+#define O_RDWR               02
+#define O_CREAT            0100 /* not fcntl */
+#define O_EXCL             0200 /* not fcntl */
+#define O_NOCTTY           0400 /* not fcntl */
+#define O_TRUNC           01000 /* not fcntl */
+#define O_APPEND          02000
+#define O_NONBLOCK        04000
+#define O_NDELAY        O_NONBLOCK
+#define O_SYNC           010000
+#define FASYNC           020000 /* fcntl, for BSD compatibility */
+#define O_DIRECTORY      040000 /* must be a directory */
+#define O_NOFOLLOW      0100000 /* don't follow links */
+#define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
+#define O_LARGEFILE     0400000
+#define O_NOATIME       01000000
+
+#define F_DUPFD         0       /* dup */
+#define F_GETFD         1       /* get close_on_exec */
+#define F_SETFD         2       /* set/clear close_on_exec */
+#define F_GETFL         3       /* get file->f_flags */
+#define F_SETFL         4       /* set file->f_flags */
+#define F_GETLK         5
+#define F_SETLK         6
+#define F_SETLKW        7
+
+#define F_SETOWN        8       /*  for sockets. */
+#define F_GETOWN        9       /*  for sockets. */
+#define F_SETSIG        10      /*  for sockets. */
+#define F_GETSIG        11      /*  for sockets. */
+
+#define F_GETLK64       12      /*  using 'struct flock64' */
+#define F_SETLK64       13
+#define F_SETLKW64      14
+
+/* for F_[GET|SET]FL */
+#define FD_CLOEXEC      1       /* actually anything with low bit set goes */
+
+/* for posix fcntl() and lockf() */
+#define F_RDLCK         0
+#define F_WRLCK         1
+#define F_UNLCK         2
+
+/* for old implementation of bsd flock () */
+#define F_EXLCK         4       /* or 3 */
+#define F_SHLCK         8       /* or 4 */
+
+/* for leases */
+#define F_INPROGRESS    16
+
+/* operations for bsd flock(), also used by the kernel implementation */
+#define LOCK_SH         1       /* shared lock */
+#define LOCK_EX         2       /* exclusive lock */
+#define LOCK_NB         4       /* or'd with one of the above to prevent
+                                   blocking */
+#define LOCK_UN         8       /* remove lock */
+
+#define LOCK_MAND       32      /* This is a mandatory flock */
+#define LOCK_READ       64      /* ... Which allows concurrent read operations */
+#define LOCK_WRITE      128     /* ... Which allows concurrent write operations */
+#define LOCK_RW         192     /* ... Which allows concurrent read & write ops */
+
+struct flock {
+        short l_type;
+        short l_whence;
+        off_t l_start;
+        off_t l_len;
+        pid_t l_pid;
+};
+
+struct flock64 {
+        short  l_type;
+        short  l_whence;
+        loff_t l_start;
+        loff_t l_len;
+        pid_t  l_pid;
+};
+
+#define F_LINUX_SPECIFIC_BASE   1024
+#endif
diff --git a/include/asm-arm/fiq.h b/include/asm-arm/fiq.h
new file mode 100644
index 000000000000..a3bad09e825c
--- /dev/null
+++ b/include/asm-arm/fiq.h
@@ -0,0 +1,37 @@
+/*
+ *  linux/include/asm-arm/fiq.h
+ *
+ * Support for FIQ on ARM architectures.
+ * Written by Philip Blundell <philb@gnu.org>, 1998
+ * Re-written by Russell King
+ */
+
+#ifndef __ASM_FIQ_H
+#define __ASM_FIQ_H
+
+#include <asm/ptrace.h>
+
+struct fiq_handler {
+        struct fiq_handler *next;
+        /* Name
+         */
+        const char *name;
+        /* Called to ask driver to relinquish/
+         * reacquire FIQ
+         * return zero to accept, or -<errno>
+         */
+        int (*fiq_op)(void *, int relinquish);
+        /* data for the relinquish/reacquire functions
+         */
+        void *dev_id;
+};
+
+extern int claim_fiq(struct fiq_handler *f);
+extern void release_fiq(struct fiq_handler *f);
+extern void set_fiq_handler(void *start, unsigned int length);
+extern void set_fiq_regs(struct pt_regs *regs);
+extern void get_fiq_regs(struct pt_regs *regs);
+extern void enable_fiq(int fiq);
+extern void disable_fiq(int fiq);
+
+#endif
diff --git a/include/asm-arm/floppy.h b/include/asm-arm/floppy.h
new file mode 100644
index 000000000000..6ea657c886b9
--- /dev/null
+++ b/include/asm-arm/floppy.h
@@ -0,0 +1,144 @@
+/*
+ *  linux/include/asm-arm/floppy.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note that we don't touch FLOPPY_DMA nor FLOPPY_IRQ here
+ */
+#ifndef __ASM_ARM_FLOPPY_H
+#define __ASM_ARM_FLOPPY_H
+#if 0
+#include <asm/arch/floppy.h>
+#endif
+
+#define fd_outb(val,port)                       \
+        do {                                    \
+                if ((port) == FD_DOR)           \
+                        fd_setdor((val));       \
+                else                            \
+                        outb((val),(port));     \
+        } while(0)
+
+#define fd_inb(port)            inb((port))
+#define fd_request_irq()        request_irq(IRQ_FLOPPYDISK,floppy_interrupt,\
+                                        SA_INTERRUPT|SA_SAMPLE_RANDOM,"floppy",NULL)
+#define fd_free_irq()           free_irq(IRQ_FLOPPYDISK,NULL)
+#define fd_disable_irq()        disable_irq(IRQ_FLOPPYDISK)
+#define fd_enable_irq()         enable_irq(IRQ_FLOPPYDISK)
+
+#define fd_request_dma()        request_dma(DMA_FLOPPY,"floppy")
+#define fd_free_dma()           free_dma(DMA_FLOPPY)
+#define fd_disable_dma()        disable_dma(DMA_FLOPPY)
+#define fd_enable_dma()         enable_dma(DMA_FLOPPY)
+#define fd_clear_dma_ff()       clear_dma_ff(DMA_FLOPPY)
+#define fd_set_dma_mode(mode)   set_dma_mode(DMA_FLOPPY, (mode))
+#define fd_set_dma_addr(addr)   set_dma_addr(DMA_FLOPPY, virt_to_bus((addr)))
+#define fd_set_dma_count(len)   set_dma_count(DMA_FLOPPY, (len))
+#define fd_cacheflush(addr,sz)
+
+/* need to clean up dma.h */
+#define DMA_FLOPPYDISK          DMA_FLOPPY
+
+/* Floppy_selects is the list of DOR's to select drive fd
+ *
+ * On initialisation, the floppy list is scanned, and the drives allocated
+ * in the order that they are found.  This is done by seeking the drive
+ * to a non-zero track, and then restoring it to track 0.  If an error occurs,
+ * then there is no floppy drive present.       [to be put back in again]
+ */
+static unsigned char floppy_selects[2][4] =
+{
+        { 0x10, 0x21, 0x23, 0x33 },
+        { 0x10, 0x21, 0x23, 0x33 }
+};
+
+#define fd_setdor(dor)                                                          \
+do {                                                                            \
+        int new_dor = (dor);                                                    \
+        if (new_dor & 0xf0)                                                     \
+                new_dor = (new_dor & 0x0c) | floppy_selects[fdc][new_dor & 3];  \
+        else                                                                    \
+                new_dor &= 0x0c;                                                \
+        outb(new_dor, FD_DOR);                                                  \
+} while (0)
+
+/*
+ * Someday, we'll automatically detect which drives are present...
+ */
+static inline void fd_scandrives (void)
+{
+#if 0
+        int floppy, drive_count;
+
+        fd_disable_irq();
+        raw_cmd = &default_raw_cmd;
+        raw_cmd->flags = FD_RAW_SPIN | FD_RAW_NEED_SEEK;
+        raw_cmd->track = 0;
+        raw_cmd->rate = ?;
+        drive_count = 0;
+        for (floppy = 0; floppy < 4; floppy ++) {
+                current_drive = drive_count;
+                /*
+                 * Turn on floppy motor
+                 */
+                if (start_motor(redo_fd_request))
+                        continue;
+                /*
+                 * Set up FDC
+                 */
+                fdc_specify();
+                /*
+                 * Tell FDC to recalibrate
+                 */
+                output_byte(FD_RECALIBRATE);
+                LAST_OUT(UNIT(floppy));
+                /* wait for command to complete */
+                if (!successful) {
+                        int i;
+                        for (i = drive_count; i < 3; i--)
+                                floppy_selects[fdc][i] = floppy_selects[fdc][i + 1];
+                        floppy_selects[fdc][3] = 0;
+                        floppy -= 1;
+                } else
+                        drive_count++;
+        }
+#else
+        floppy_selects[0][0] = 0x10;
+        floppy_selects[0][1] = 0x21;
+        floppy_selects[0][2] = 0x23;
+        floppy_selects[0][3] = 0x33;
+#endif
+}
+
+#define FDC1 (0x3f0)
+
+#define FLOPPY0_TYPE 4
+#define FLOPPY1_TYPE 4
+
+#define N_FDC 1
+#define N_DRIVE 4
+
+#define FLOPPY_MOTOR_MASK 0xf0
+
+#define CROSS_64KB(a,s) (0)
+
+/*
+ * This allows people to reverse the order of
+ * fd0 and fd1, in case their hardware is
+ * strangely connected (as some RiscPCs
+ * and A5000s seem to be).
+ */
+static void driveswap(int *ints, int dummy, int dummy2)
+{
+        floppy_selects[0][0] ^= floppy_selects[0][1];
+        floppy_selects[0][1] ^= floppy_selects[0][0];
+        floppy_selects[0][0] ^= floppy_selects[0][1];
+}
+
+#define EXTRA_FLOPPY_PARAMS ,{ "driveswap", &driveswap, NULL, 0, 0 }
+        
+#endif
diff --git a/include/asm-arm/fpstate.h b/include/asm-arm/fpstate.h
new file mode 100644
index 000000000000..f7430e3aa55d
--- /dev/null
+++ b/include/asm-arm/fpstate.h
@@ -0,0 +1,74 @@
+/*
+ *  linux/include/asm-arm/fpstate.h
+ *
+ *  Copyright (C) 1995 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_FPSTATE_H
+#define __ASM_ARM_FPSTATE_H
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+
+/*
+ * VFP storage area has:
+ *  - FPEXC, FPSCR, FPINST and FPINST2.
+ *  - 16 double precision data registers
+ *  - an implementation-dependant word of state for FLDMX/FSTMX
+ * 
+ *  FPEXC will always be non-zero once the VFP has been used in this process.
+ */
+
+struct vfp_hard_struct {
+        __u64 fpregs[16];
+        __u32 fpmx_state;
+        __u32 fpexc;
+        __u32 fpscr;
+        /*
+         * VFP implementation specific state
+         */
+        __u32 fpinst;
+        __u32 fpinst2;
+};
+
+union vfp_state {
+        struct vfp_hard_struct  hard;
+};
+
+extern void vfp_flush_thread(union vfp_state *);
+extern void vfp_release_thread(union vfp_state *);
+
+#define FP_HARD_SIZE 35
+
+struct fp_hard_struct {
+        unsigned int save[FP_HARD_SIZE];                /* as yet undefined */
+};
+
+#define FP_SOFT_SIZE 35
+
+struct fp_soft_struct {
+        unsigned int save[FP_SOFT_SIZE];                /* undefined information */
+};
+
+struct iwmmxt_struct {
+        unsigned int save[0x98/sizeof(int) + 1];
+};
+
+union fp_state {
+        struct fp_hard_struct   hard;
+        struct fp_soft_struct   soft;
+#ifdef CONFIG_IWMMXT
+        struct iwmmxt_struct    iwmmxt;
+#endif
+};
+
+#define FP_SIZE (sizeof(union fp_state) / sizeof(int))
+
+#endif
+
+#endif
diff --git a/include/asm-arm/glue.h b/include/asm-arm/glue.h
new file mode 100644
index 000000000000..223e0d6c41be
--- /dev/null
+++ b/include/asm-arm/glue.h
@@ -0,0 +1,114 @@
+/*
+ *  linux/include/asm-arm/glue.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *  Copyright (C) 2000-2002 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file provides the glue to stick the processor-specific bits
+ *  into the kernel in an efficient manner.  The idea is to use branches
+ *  when we're only targetting one class of TLB, or indirect calls
+ *  when we're targetting multiple classes of TLBs.
+ */
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+#ifdef __STDC__
+#define ____glue(name,fn)       name##fn
+#else
+#define ____glue(name,fn)       name/**/fn
+#endif
+#define __glue(name,fn)         ____glue(name,fn)
+
+
+
+/*
+ *      Data Abort Model
+ *      ================
+ *
+ *      We have the following to choose from:
+ *        arm6          - ARM6 style
+ *        arm7          - ARM7 style
+ *        v4_early      - ARMv4 without Thumb early abort handler
+ *        v4t_late      - ARMv4 with Thumb late abort handler
+ *        v4t_early     - ARMv4 with Thumb early abort handler
+ *        v5tej_early   - ARMv5 with Thumb and Java early abort handler
+ *        xscale        - ARMv5 with Thumb with Xscale extensions
+ *        v6_early      - ARMv6 generic early abort handler
+ */
+#undef CPU_ABORT_HANDLER
+#undef MULTI_ABORT
+
+#if defined(CONFIG_CPU_ARM610)
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER cpu_arm6_data_abort
+# endif
+#endif
+
+#if defined(CONFIG_CPU_ARM710)
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER cpu_arm7_data_abort
+# endif
+#endif
+
+#ifdef CONFIG_CPU_ABRT_LV4T
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v4t_late_abort
+# endif
+#endif
+
+#ifdef CONFIG_CPU_ABRT_EV4
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v4_early_abort
+# endif
+#endif
+
+#ifdef CONFIG_CPU_ABRT_EV4T
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v4t_early_abort
+# endif
+#endif
+
+#ifdef CONFIG_CPU_ABRT_EV5TJ
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v5tj_early_abort
+# endif
+#endif
+
+#ifdef CONFIG_CPU_ABRT_EV5T
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v5t_early_abort
+# endif
+#endif
+
+#ifdef CONFIG_CPU_ABRT_EV6
+# ifdef CPU_ABORT_HANDLER
+#  define MULTI_ABORT 1
+# else
+#  define CPU_ABORT_HANDLER v6_early_abort
+# endif
+#endif
+
+#ifndef CPU_ABORT_HANDLER
+#error Unknown data abort handler type
+#endif
+
+#endif
diff --git a/include/asm-arm/hardirq.h b/include/asm-arm/hardirq.h
new file mode 100644
index 000000000000..e5ccb6b8ff83
--- /dev/null
+++ b/include/asm-arm/hardirq.h
@@ -0,0 +1,32 @@
+#ifndef __ASM_HARDIRQ_H
+#define __ASM_HARDIRQ_H
+
+#include <linux/config.h>
+#include <linux/cache.h>
+#include <linux/threads.h>
+#include <asm/irq.h>
+
+typedef struct {
+        unsigned int __softirq_pending;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+#if NR_IRQS > 256
+#define HARDIRQ_BITS    9
+#else
+#define HARDIRQ_BITS    8
+#endif
+
+/*
+ * The hardirq mask has to be large enough to have space
+ * for potentially all IRQ sources in the system nesting
+ * on a single CPU:
+ */
+#if (1 << HARDIRQ_BITS) < NR_IRQS
+# error HARDIRQ_BITS is too low!
+#endif
+
+#define __ARCH_IRQ_EXIT_IRQS_DISABLED   1
+
+#endif /* __ASM_HARDIRQ_H */
diff --git a/include/asm-arm/hardware.h b/include/asm-arm/hardware.h
new file mode 100644
index 000000000000..1fd1a5b6504b
--- /dev/null
+++ b/include/asm-arm/hardware.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/hardware.h
+ *
+ *  Copyright (C) 1996 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Common hardware definitions
+ */
+
+#ifndef __ASM_HARDWARE_H
+#define __ASM_HARDWARE_H
+
+#include <asm/arch/hardware.h>
+
+#endif
diff --git a/include/asm-arm/hardware/amba.h b/include/asm-arm/hardware/amba.h
new file mode 100644
index 000000000000..51e6e54b2aa1
--- /dev/null
+++ b/include/asm-arm/hardware/amba.h
@@ -0,0 +1,55 @@
+/*
+ *  linux/include/asm-arm/hardware/amba.h
+ *
+ *  Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_AMBA_H
+#define ASMARM_AMBA_H
+
+#define AMBA_NR_IRQS    2
+
+struct amba_device {
+        struct device           dev;
+        struct resource         res;
+        u64                     dma_mask;
+        unsigned int            periphid;
+        unsigned int            irq[AMBA_NR_IRQS];
+};
+
+struct amba_id {
+        unsigned int            id;
+        unsigned int            mask;
+        void                    *data;
+};
+
+struct amba_driver {
+        struct device_driver    drv;
+        int                     (*probe)(struct amba_device *, void *);
+        int                     (*remove)(struct amba_device *);
+        void                    (*shutdown)(struct amba_device *);
+        int                     (*suspend)(struct amba_device *, pm_message_t);
+        int                     (*resume)(struct amba_device *);
+        struct amba_id          *id_table;
+};
+
+#define amba_get_drvdata(d)     dev_get_drvdata(&d->dev)
+#define amba_set_drvdata(d,p)   dev_set_drvdata(&d->dev, p)
+
+int amba_driver_register(struct amba_driver *);
+void amba_driver_unregister(struct amba_driver *);
+int amba_device_register(struct amba_device *, struct resource *);
+void amba_device_unregister(struct amba_device *);
+struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int);
+int amba_request_regions(struct amba_device *, const char *);
+void amba_release_regions(struct amba_device *);
+
+#define amba_config(d)  (((d)->periphid >> 24) & 0xff)
+#define amba_rev(d)     (((d)->periphid >> 20) & 0x0f)
+#define amba_manf(d)    (((d)->periphid >> 12) & 0xff)
+#define amba_part(d)    ((d)->periphid & 0xfff)
+
+#endif
diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h
new file mode 100644
index 000000000000..2149be7c7023
--- /dev/null
+++ b/include/asm-arm/hardware/amba_clcd.h
@@ -0,0 +1,264 @@
+/*
+ * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
+ *
+ * David A Rusling
+ *
+ * Copyright (C) 2001 ARM Limited
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+#include <linux/config.h>
+#include <linux/fb.h>
+
+/*
+ * CLCD Controller Internal Register addresses
+ */
+#define CLCD_TIM0               0x00000000
+#define CLCD_TIM1               0x00000004
+#define CLCD_TIM2               0x00000008
+#define CLCD_TIM3               0x0000000c
+#define CLCD_UBAS               0x00000010
+#define CLCD_LBAS               0x00000014
+
+#ifndef CONFIG_ARCH_VERSATILE
+#define CLCD_IENB               0x00000018
+#define CLCD_CNTL               0x0000001c
+#else
+/*
+ * Someone rearranged these two registers on the Versatile
+ * platform...
+ */
+#define CLCD_IENB               0x0000001c
+#define CLCD_CNTL               0x00000018
+#endif
+
+#define CLCD_STAT               0x00000020
+#define CLCD_INTR               0x00000024
+#define CLCD_UCUR               0x00000028
+#define CLCD_LCUR               0x0000002C
+#define CLCD_PALL               0x00000200
+#define CLCD_PALETTE            0x00000200
+
+#define TIM2_CLKSEL             (1 << 5)
+#define TIM2_IVS                (1 << 11)
+#define TIM2_IHS                (1 << 12)
+#define TIM2_IPC                (1 << 13)
+#define TIM2_IOE                (1 << 14)
+#define TIM2_BCD                (1 << 26)
+
+#define CNTL_LCDEN              (1 << 0)
+#define CNTL_LCDBPP1            (0 << 1)
+#define CNTL_LCDBPP2            (1 << 1)
+#define CNTL_LCDBPP4            (2 << 1)
+#define CNTL_LCDBPP8            (3 << 1)
+#define CNTL_LCDBPP16           (4 << 1)
+#define CNTL_LCDBPP24           (5 << 1)
+#define CNTL_LCDBW              (1 << 4)
+#define CNTL_LCDTFT             (1 << 5)
+#define CNTL_LCDMONO8           (1 << 6)
+#define CNTL_LCDDUAL            (1 << 7)
+#define CNTL_BGR                (1 << 8)
+#define CNTL_BEBO               (1 << 9)
+#define CNTL_BEPO               (1 << 10)
+#define CNTL_LCDPWR             (1 << 11)
+#define CNTL_LCDVCOMP(x)        ((x) << 12)
+#define CNTL_LDMAFIFOTIME       (1 << 15)
+#define CNTL_WATERMARK          (1 << 16)
+
+struct clcd_panel {
+        struct fb_videomode     mode;
+        signed short            width;  /* width in mm */
+        signed short            height; /* height in mm */
+        u32                     tim2;
+        u32                     tim3;
+        u32                     cntl;
+        unsigned int            bpp:8,
+                                fixedtimings:1,
+                                grayscale:1;
+        unsigned int            connector;
+};
+
+struct clcd_regs {
+        u32                     tim0;
+        u32                     tim1;
+        u32                     tim2;
+        u32                     tim3;
+        u32                     cntl;
+        unsigned long           pixclock;
+};
+
+struct clcd_fb;
+
+/*
+ * the board-type specific routines
+ */
+struct clcd_board {
+        const char *name;
+
+        /*
+         * Optional.  Check whether the var structure is acceptable
+         * for this display.
+         */
+        int     (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
+
+        /*
+         * Compulsary.  Decode fb->fb.var into regs->*.  In the case of
+         * fixed timing, set regs->* to the register values required.
+         */
+        void    (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
+
+        /*
+         * Optional.  Disable any extra display hardware.
+         */
+        void    (*disable)(struct clcd_fb *);
+
+        /*
+         * Optional.  Enable any extra display hardware.
+         */
+        void    (*enable)(struct clcd_fb *);
+
+        /*
+         * Setup platform specific parts of CLCD driver
+         */
+        int     (*setup)(struct clcd_fb *);
+
+        /*
+         * mmap the framebuffer memory
+         */
+        int     (*mmap)(struct clcd_fb *, struct vm_area_struct *);
+
+        /*
+         * Remove platform specific parts of CLCD driver
+         */
+        void    (*remove)(struct clcd_fb *);
+};
+
+struct amba_device;
+struct clk;
+
+/* this data structure describes each frame buffer device we find */
+struct clcd_fb {
+        struct fb_info          fb;
+        struct amba_device      *dev;
+        struct clk              *clk;
+        struct clcd_panel       *panel;
+        struct clcd_board       *board;
+        void                    *board_data;
+        void __iomem            *regs;
+        u32                     clcd_cntl;
+        u32                     cmap[16];
+};
+
+static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
+{
+        u32 val;
+
+        /*
+         * Program the CLCD controller registers and start the CLCD
+         */
+        val = ((fb->fb.var.xres / 16) - 1) << 2;
+        val |= (fb->fb.var.hsync_len - 1) << 8;
+        val |= (fb->fb.var.right_margin - 1) << 16;
+        val |= (fb->fb.var.left_margin - 1) << 24;
+        regs->tim0 = val;
+
+        val = fb->fb.var.yres - 1;
+        val |= (fb->fb.var.vsync_len - 1) << 10;
+        val |= fb->fb.var.lower_margin << 16;
+        val |= fb->fb.var.upper_margin << 24;
+        regs->tim1 = val;
+
+        val = fb->panel->tim2;
+        val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT  ? 0 : TIM2_IHS;
+        val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
+
+        if (fb->panel->cntl & CNTL_LCDTFT)
+                val |= (fb->fb.var.xres_virtual - 1) << 16;
+        else if (fb->panel->cntl & CNTL_LCDBW)
+                printk("what value for CPL for stnmono panels?");
+        else
+                val |= ((fb->fb.var.xres_virtual * 8 / 3) - 1) << 16;
+        regs->tim2 = val;
+
+        regs->tim3 = fb->panel->tim3;
+
+        val = fb->panel->cntl;
+        if (fb->fb.var.grayscale)
+                val |= CNTL_LCDBW;
+
+        switch (fb->fb.var.bits_per_pixel) {
+        case 1:
+                val |= CNTL_LCDBPP1;
+                break;
+        case 2:
+                val |= CNTL_LCDBPP2;
+                break;
+        case 4:
+                val |= CNTL_LCDBPP4;
+                break;
+        case 8:
+                val |= CNTL_LCDBPP8;
+                break;
+        case 16:
+                val |= CNTL_LCDBPP16;
+                break;
+        case 24:
+                val |= CNTL_LCDBPP24;
+                break;
+        }
+
+        regs->cntl = val;
+        regs->pixclock = fb->fb.var.pixclock;
+}
+
+static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
+{
+        var->xres_virtual = var->xres = (var->xres + 7) & ~7;
+        var->yres_virtual = var->yres;
+
+#define CHECK(e,l,h) (var->e < l || var->e > h)
+        if (CHECK(right_margin, (5+1), 256) ||  /* back porch */
+            CHECK(left_margin, (5+1), 256) ||   /* front porch */
+            CHECK(hsync_len, (5+1), 256) ||
+            var->xres > 4096 ||
+            var->lower_margin > 255 ||          /* back porch */
+            var->upper_margin > 255 ||          /* front porch */
+            var->vsync_len > 32 ||
+            var->yres > 1024)
+                return -EINVAL;
+#undef CHECK
+
+        /* single panel mode: PCD = max(PCD, 1) */
+        /* dual panel mode: PCD = max(PCD, 5) */
+
+        /*
+         * You can't change the grayscale setting, and
+         * we can only do non-interlaced video.
+         */
+        if (var->grayscale != fb->fb.var.grayscale ||
+            (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
+                return -EINVAL;
+
+#define CHECK(e) (var->e != fb->fb.var.e)
+        if (fb->panel->fixedtimings &&
+            (CHECK(xres)                ||
+             CHECK(yres)                ||
+             CHECK(bits_per_pixel)      ||
+             CHECK(pixclock)            ||
+             CHECK(left_margin)         ||
+             CHECK(right_margin)        ||
+             CHECK(upper_margin)        ||
+             CHECK(lower_margin)        ||
+             CHECK(hsync_len)           ||
+             CHECK(vsync_len)           ||
+             CHECK(sync)))
+                return -EINVAL;
+#undef CHECK
+
+        var->nonstd = 0;
+        var->accel_flags = 0;
+
+        return 0;
+}
diff --git a/include/asm-arm/hardware/amba_kmi.h b/include/asm-arm/hardware/amba_kmi.h
new file mode 100644
index 000000000000..a39e5be751b3
--- /dev/null
+++ b/include/asm-arm/hardware/amba_kmi.h
@@ -0,0 +1,92 @@
+/*
+ *  linux/include/asm-arm/hardware/amba_kmi.h
+ *
+ *  Internal header file for AMBA KMI ports
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ *
+ *
+ * ---------------------------------------------------------------------------
+ *  From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
+ *  Reference Manual - ARM DDI 0143B - see http://www.arm.com/
+ * ---------------------------------------------------------------------------
+ */
+#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
+#define ASM_ARM_HARDWARE_AMBA_KMI_H
+
+/*
+ * KMI control register:
+ *  KMICR_TYPE       0 = PS2/AT mode, 1 = No line control bit mode
+ *  KMICR_RXINTREN   1 = enable RX interrupts
+ *  KMICR_TXINTREN   1 = enable TX interrupts
+ *  KMICR_EN         1 = enable KMI
+ *  KMICR_FD         1 = force KMI data low
+ *  KMICR_FC         1 = force KMI clock low
+ */
+#define KMICR           (KMI_BASE + 0x00)
+#define KMICR_TYPE              (1 << 5)
+#define KMICR_RXINTREN          (1 << 4)
+#define KMICR_TXINTREN          (1 << 3)
+#define KMICR_EN                (1 << 2)
+#define KMICR_FD                (1 << 1)
+#define KMICR_FC                (1 << 0)
+
+/*
+ * KMI status register:
+ *  KMISTAT_TXEMPTY  1 = transmitter register empty
+ *  KMISTAT_TXBUSY   1 = currently sending data
+ *  KMISTAT_RXFULL   1 = receiver register ready to be read
+ *  KMISTAT_RXBUSY   1 = currently receiving data
+ *  KMISTAT_RXPARITY parity of last databyte received
+ *  KMISTAT_IC       current level of KMI clock input
+ *  KMISTAT_ID       current level of KMI data input
+ */
+#define KMISTAT         (KMI_BASE + 0x04)
+#define KMISTAT_TXEMPTY         (1 << 6)
+#define KMISTAT_TXBUSY          (1 << 5)
+#define KMISTAT_RXFULL          (1 << 4)
+#define KMISTAT_RXBUSY          (1 << 3)
+#define KMISTAT_RXPARITY        (1 << 2)
+#define KMISTAT_IC              (1 << 1)
+#define KMISTAT_ID              (1 << 0)
+
+/*
+ * KMI data register
+ */
+#define KMIDATA         (KMI_BASE + 0x08)
+
+/*
+ * KMI clock divisor: to generate 8MHz internal clock
+ *  div = (ref / 8MHz) - 1; 0 <= div <= 15
+ */
+#define KMICLKDIV       (KMI_BASE + 0x0c)
+
+/*
+ * KMI interrupt register:
+ *  KMIIR_TXINTR     1 = transmit interrupt asserted
+ *  KMIIR_RXINTR     1 = receive interrupt asserted
+ */
+#define KMIIR           (KMI_BASE + 0x10)
+#define KMIIR_TXINTR            (1 << 1)
+#define KMIIR_RXINTR            (1 << 0)
+
+/*
+ * The size of the KMI primecell
+ */
+#define KMI_SIZE        (0x100)
+
+#endif
diff --git a/include/asm-arm/hardware/amba_serial.h b/include/asm-arm/hardware/amba_serial.h
new file mode 100644
index 000000000000..71770aa6389f
--- /dev/null
+++ b/include/asm-arm/hardware/amba_serial.h
@@ -0,0 +1,156 @@
+/*
+ *  linux/include/asm-arm/hardware/serial_amba.h
+ *
+ *  Internal header file for AMBA serial ports
+ *
+ *  Copyright (C) ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
+#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
+
+/* -------------------------------------------------------------------------------
+ *  From AMBA UART (PL010) Block Specification
+ * -------------------------------------------------------------------------------
+ *  UART Register Offsets.
+ */
+#define UART01x_DR              0x00    /* Data read or written from the interface. */
+#define UART01x_RSR             0x04    /* Receive status register (Read). */
+#define UART01x_ECR             0x04    /* Error clear register (Write). */
+#define UART010_LCRH            0x08    /* Line control register, high byte. */
+#define UART010_LCRM            0x0C    /* Line control register, middle byte. */
+#define UART010_LCRL            0x10    /* Line control register, low byte. */
+#define UART010_CR              0x14    /* Control register. */
+#define UART01x_FR              0x18    /* Flag register (Read only). */
+#define UART010_IIR             0x1C    /* Interrupt indentification register (Read). */
+#define UART010_ICR             0x1C    /* Interrupt clear register (Write). */
+#define UART01x_ILPR            0x20    /* IrDA low power counter register. */
+#define UART011_IBRD            0x24    /* Integer baud rate divisor register. */
+#define UART011_FBRD            0x28    /* Fractional baud rate divisor register. */
+#define UART011_LCRH            0x2c    /* Line control register. */
+#define UART011_CR              0x30    /* Control register. */
+#define UART011_IFLS            0x34    /* Interrupt fifo level select. */
+#define UART011_IMSC            0x38    /* Interrupt mask. */
+#define UART011_RIS             0x3c    /* Raw interrupt status. */
+#define UART011_MIS             0x40    /* Masked interrupt status. */
+#define UART011_ICR             0x44    /* Interrupt clear register. */
+#define UART011_DMACR           0x48    /* DMA control register. */
+
+#define UART01x_RSR_OE          0x08
+#define UART01x_RSR_BE          0x04
+#define UART01x_RSR_PE          0x02
+#define UART01x_RSR_FE          0x01
+
+#define UART011_FR_RI           0x100
+#define UART011_FR_TXFE         0x080
+#define UART011_FR_RXFF         0x040
+#define UART01x_FR_TXFF         0x020
+#define UART01x_FR_RXFE         0x010
+#define UART01x_FR_BUSY         0x008
+#define UART01x_FR_DCD          0x004
+#define UART01x_FR_DSR          0x002
+#define UART01x_FR_CTS          0x001
+#define UART01x_FR_TMSK         (UART01x_FR_TXFF + UART01x_FR_BUSY)
+
+#define UART011_CR_CTSEN        0x8000  /* CTS hardware flow control */
+#define UART011_CR_RTSEN        0x4000  /* RTS hardware flow control */
+#define UART011_CR_OUT2         0x2000  /* OUT2 */
+#define UART011_CR_OUT1         0x1000  /* OUT1 */
+#define UART011_CR_RTS          0x0800  /* RTS */
+#define UART011_CR_DTR          0x0400  /* DTR */
+#define UART011_CR_RXE          0x0200  /* receive enable */
+#define UART011_CR_TXE          0x0100  /* transmit enable */
+#define UART011_CR_LBE          0x0080  /* loopback enable */
+#define UART010_CR_RTIE         0x0040
+#define UART010_CR_TIE          0x0020
+#define UART010_CR_RIE          0x0010
+#define UART010_CR_MSIE         0x0008
+#define UART01x_CR_IIRLP        0x0004  /* SIR low power mode */
+#define UART01x_CR_SIREN        0x0002  /* SIR enable */
+#define UART01x_CR_UARTEN       0x0001  /* UART enable */
+ 
+#define UART011_LCRH_SPS        0x80
+#define UART01x_LCRH_WLEN_8     0x60
+#define UART01x_LCRH_WLEN_7     0x40
+#define UART01x_LCRH_WLEN_6     0x20
+#define UART01x_LCRH_WLEN_5     0x00
+#define UART01x_LCRH_FEN        0x10
+#define UART01x_LCRH_STP2       0x08
+#define UART01x_LCRH_EPS        0x04
+#define UART01x_LCRH_PEN        0x02
+#define UART01x_LCRH_BRK        0x01
+
+#define UART010_IIR_RTIS        0x08
+#define UART010_IIR_TIS         0x04
+#define UART010_IIR_RIS         0x02
+#define UART010_IIR_MIS         0x01
+
+#define UART011_IFLS_RX1_8      (0 << 3)
+#define UART011_IFLS_RX2_8      (1 << 3)
+#define UART011_IFLS_RX4_8      (2 << 3)
+#define UART011_IFLS_RX6_8      (3 << 3)
+#define UART011_IFLS_RX7_8      (4 << 3)
+#define UART011_IFLS_TX1_8      (0 << 0)
+#define UART011_IFLS_TX2_8      (1 << 0)
+#define UART011_IFLS_TX4_8      (2 << 0)
+#define UART011_IFLS_TX6_8      (3 << 0)
+#define UART011_IFLS_TX7_8      (4 << 0)
+
+#define UART011_OEIM            (1 << 10)       /* overrun error interrupt mask */
+#define UART011_BEIM            (1 << 9)        /* break error interrupt mask */
+#define UART011_PEIM            (1 << 8)        /* parity error interrupt mask */
+#define UART011_FEIM            (1 << 7)        /* framing error interrupt mask */
+#define UART011_RTIM            (1 << 6)        /* receive timeout interrupt mask */
+#define UART011_TXIM            (1 << 5)        /* transmit interrupt mask */
+#define UART011_RXIM            (1 << 4)        /* receive interrupt mask */
+#define UART011_DSRMIM          (1 << 3)        /* DSR interrupt mask */
+#define UART011_DCDMIM          (1 << 2)        /* DCD interrupt mask */
+#define UART011_CTSMIM          (1 << 1)        /* CTS interrupt mask */
+#define UART011_RIMIM           (1 << 0)        /* RI interrupt mask */
+
+#define UART011_OEIS            (1 << 10)       /* overrun error interrupt status */
+#define UART011_BEIS            (1 << 9)        /* break error interrupt status */
+#define UART011_PEIS            (1 << 8)        /* parity error interrupt status */
+#define UART011_FEIS            (1 << 7)        /* framing error interrupt status */
+#define UART011_RTIS            (1 << 6)        /* receive timeout interrupt status */
+#define UART011_TXIS            (1 << 5)        /* transmit interrupt status */
+#define UART011_RXIS            (1 << 4)        /* receive interrupt status */
+#define UART011_DSRMIS          (1 << 3)        /* DSR interrupt status */
+#define UART011_DCDMIS          (1 << 2)        /* DCD interrupt status */
+#define UART011_CTSMIS          (1 << 1)        /* CTS interrupt status */
+#define UART011_RIMIS           (1 << 0)        /* RI interrupt status */
+
+#define UART011_OEIC            (1 << 10)       /* overrun error interrupt clear */
+#define UART011_BEIC            (1 << 9)        /* break error interrupt clear */
+#define UART011_PEIC            (1 << 8)        /* parity error interrupt clear */
+#define UART011_FEIC            (1 << 7)        /* framing error interrupt clear */
+#define UART011_RTIC            (1 << 6)        /* receive timeout interrupt clear */
+#define UART011_TXIC            (1 << 5)        /* transmit interrupt clear */
+#define UART011_RXIC            (1 << 4)        /* receive interrupt clear */
+#define UART011_DSRMIC          (1 << 3)        /* DSR interrupt clear */
+#define UART011_DCDMIC          (1 << 2)        /* DCD interrupt clear */
+#define UART011_CTSMIC          (1 << 1)        /* CTS interrupt clear */
+#define UART011_RIMIC           (1 << 0)        /* RI interrupt clear */
+
+#define UART011_DMAONERR        (1 << 2)        /* disable dma on error */
+#define UART011_TXDMAE          (1 << 1)        /* enable transmit dma */
+#define UART011_RXDMAE          (1 << 0)        /* enable receive dma */
+
+#define UART01x_RSR_ANY         (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
+#define UART01x_FR_MODEM_ANY    (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
+
+#endif
diff --git a/include/asm-arm/hardware/clock.h b/include/asm-arm/hardware/clock.h
new file mode 100644
index 000000000000..4983449ff2c7
--- /dev/null
+++ b/include/asm-arm/hardware/clock.h
@@ -0,0 +1,121 @@
+/*
+ *  linux/include/asm-arm/hardware/clock.h
+ *
+ *  Copyright (C) 2004 ARM Limited.
+ *  Written by Deep Blue Solutions Limited.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_CLOCK_H
+#define ASMARM_CLOCK_H
+
+struct device;
+
+/*
+ * The base API.
+ */
+
+
+/*
+ * struct clk - an machine class defined object / cookie.
+ */
+struct clk;
+
+/**
+ * clk_get - lookup and obtain a reference to a clock producer.
+ * @dev: device for clock "consumer"
+ * @id: device ID
+ *
+ * Returns a struct clk corresponding to the clock producer, or
+ * valid IS_ERR() condition containing errno.
+ */
+struct clk *clk_get(struct device *dev, const char *id);
+
+/**
+ * clk_enable - inform the system when the clock source should be running.
+ * @clk: clock source
+ *
+ * If the clock can not be enabled/disabled, this should return success.
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_enable(struct clk *clk);
+
+/**
+ * clk_disable - inform the system when the clock source is no longer required.
+ * @clk: clock source
+ */
+void clk_disable(struct clk *clk);
+
+/**
+ * clk_use - increment the use count
+ * @clk: clock source
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_use(struct clk *clk);
+
+/**
+ * clk_unuse - decrement the use count
+ * @clk: clock source
+ */
+void clk_unuse(struct clk *clk);
+
+/**
+ * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
+ *                This is only valid once the clock source has been enabled.
+ * @clk: clock source
+ */
+unsigned long clk_get_rate(struct clk *clk);
+
+/**
+ * clk_put      - "free" the clock source
+ * @clk: clock source
+ */
+void clk_put(struct clk *clk);
+
+
+/*
+ * The remaining APIs are optional for machine class support.
+ */
+
+
+/**
+ * clk_round_rate - adjust a rate to the exact rate a clock can provide
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ *
+ * Returns rounded clock rate in Hz, or negative errno.
+ */
+long clk_round_rate(struct clk *clk, unsigned long rate);
+ 
+/**
+ * clk_set_rate - set the clock rate for a clock source
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate(struct clk *clk, unsigned long rate);
+ 
+/**
+ * clk_set_parent - set the parent clock source for this clock
+ * @clk: clock source
+ * @parent: parent clock source
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_parent(struct clk *clk, struct clk *parent);
+
+/**
+ * clk_get_parent - get the parent clock source for this clock
+ * @clk: clock source
+ *
+ * Returns struct clk corresponding to parent clock source, or
+ * valid IS_ERR() condition containing errno.
+ */
+struct clk *clk_get_parent(struct clk *clk);
+
+#endif
diff --git a/include/asm-arm/hardware/clps7111.h b/include/asm-arm/hardware/clps7111.h
new file mode 100644
index 000000000000..8d3228dc1778
--- /dev/null
+++ b/include/asm-arm/hardware/clps7111.h
@@ -0,0 +1,184 @@
+/*
+ *  linux/include/asm-arm/hardware/clps7111.h
+ *
+ *  This file contains the hardware definitions of the CLPS7111 internal
+ *  registers.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_HARDWARE_CLPS7111_H
+#define __ASM_HARDWARE_CLPS7111_H
+
+#define CLPS7111_PHYS_BASE      (0x80000000)
+
+#ifndef __ASSEMBLY__
+#define clps_readb(off)         __raw_readb(CLPS7111_BASE + (off))
+#define clps_readw(off)         __raw_readw(CLPS7111_BASE + (off))
+#define clps_readl(off)         __raw_readl(CLPS7111_BASE + (off))
+#define clps_writeb(val,off)    __raw_writeb(val, CLPS7111_BASE + (off))
+#define clps_writew(val,off)    __raw_writew(val, CLPS7111_BASE + (off))
+#define clps_writel(val,off)    __raw_writel(val, CLPS7111_BASE + (off))
+#endif
+
+#define PADR            (0x0000)
+#define PBDR            (0x0001)
+#define PDDR            (0x0003)
+#define PADDR           (0x0040)
+#define PBDDR           (0x0041)
+#define PDDDR           (0x0043)
+#define PEDR            (0x0080)
+#define PEDDR           (0x00c0)
+#define SYSCON1         (0x0100)
+#define SYSFLG1         (0x0140)
+#define MEMCFG1         (0x0180)
+#define MEMCFG2         (0x01c0)
+#define DRFPR           (0x0200)
+#define INTSR1          (0x0240)
+#define INTMR1          (0x0280)
+#define LCDCON          (0x02c0)
+#define TC1D            (0x0300)
+#define TC2D            (0x0340)
+#define RTCDR           (0x0380)
+#define RTCMR           (0x03c0)
+#define PMPCON          (0x0400)
+#define CODR            (0x0440)
+#define UARTDR1         (0x0480)
+#define UBRLCR1         (0x04c0)
+#define SYNCIO          (0x0500)
+#define PALLSW          (0x0540)
+#define PALMSW          (0x0580)
+#define STFCLR          (0x05c0)
+#define BLEOI           (0x0600)
+#define MCEOI           (0x0640)
+#define TEOI            (0x0680)
+#define TC1EOI          (0x06c0)
+#define TC2EOI          (0x0700)
+#define RTCEOI          (0x0740)
+#define UMSEOI          (0x0780)
+#define COEOI           (0x07c0)
+#define HALT            (0x0800)
+#define STDBY           (0x0840)
+
+#define FBADDR          (0x1000)
+#define SYSCON2         (0x1100)
+#define SYSFLG2         (0x1140)
+#define INTSR2          (0x1240)
+#define INTMR2          (0x1280)
+#define UARTDR2         (0x1480)
+#define UBRLCR2         (0x14c0)
+#define SS2DR           (0x1500)
+#define SRXEOF          (0x1600)
+#define SS2POP          (0x16c0)
+#define KBDEOI          (0x1700)
+
+/* common bits: SYSCON1 / SYSCON2 */
+#define SYSCON_UARTEN           (1 << 8)
+
+#define SYSCON1_KBDSCAN(x)      ((x) & 15)
+#define SYSCON1_KBDSCANMASK     (15)
+#define SYSCON1_TC1M            (1 << 4)
+#define SYSCON1_TC1S            (1 << 5)
+#define SYSCON1_TC2M            (1 << 6)
+#define SYSCON1_TC2S            (1 << 7)
+#define SYSCON1_UART1EN         SYSCON_UARTEN
+#define SYSCON1_BZTOG           (1 << 9)
+#define SYSCON1_BZMOD           (1 << 10)
+#define SYSCON1_DBGEN           (1 << 11)
+#define SYSCON1_LCDEN           (1 << 12)
+#define SYSCON1_CDENTX          (1 << 13)
+#define SYSCON1_CDENRX          (1 << 14)
+#define SYSCON1_SIREN           (1 << 15)
+#define SYSCON1_ADCKSEL(x)      (((x) & 3) << 16)
+#define SYSCON1_ADCKSEL_MASK    (3 << 16)
+#define SYSCON1_EXCKEN          (1 << 18)
+#define SYSCON1_WAKEDIS         (1 << 19)
+#define SYSCON1_IRTXM           (1 << 20)
+
+/* common bits: SYSFLG1 / SYSFLG2 */
+#define SYSFLG_UBUSY            (1 << 11)
+#define SYSFLG_URXFE            (1 << 22)
+#define SYSFLG_UTXFF            (1 << 23)
+
+#define SYSFLG1_MCDR            (1 << 0)
+#define SYSFLG1_DCDET           (1 << 1)
+#define SYSFLG1_WUDR            (1 << 2)
+#define SYSFLG1_WUON            (1 << 3)
+#define SYSFLG1_CTS             (1 << 8)
+#define SYSFLG1_DSR             (1 << 9)
+#define SYSFLG1_DCD             (1 << 10)
+#define SYSFLG1_UBUSY           SYSFLG_UBUSY
+#define SYSFLG1_NBFLG           (1 << 12)
+#define SYSFLG1_RSTFLG          (1 << 13)
+#define SYSFLG1_PFFLG           (1 << 14)
+#define SYSFLG1_CLDFLG          (1 << 15)
+#define SYSFLG1_URXFE           SYSFLG_URXFE
+#define SYSFLG1_UTXFF           SYSFLG_UTXFF
+#define SYSFLG1_CRXFE           (1 << 24)
+#define SYSFLG1_CTXFF           (1 << 25)
+#define SYSFLG1_SSIBUSY         (1 << 26)
+#define SYSFLG1_ID              (1 << 29)
+
+#define SYSFLG2_SSRXOF          (1 << 0)
+#define SYSFLG2_RESVAL          (1 << 1)
+#define SYSFLG2_RESFRM          (1 << 2)
+#define SYSFLG2_SS2RXFE         (1 << 3)
+#define SYSFLG2_SS2TXFF         (1 << 4)
+#define SYSFLG2_SS2TXUF         (1 << 5)
+#define SYSFLG2_CKMODE          (1 << 6)
+#define SYSFLG2_UBUSY           SYSFLG_UBUSY
+#define SYSFLG2_URXFE           SYSFLG_URXFE
+#define SYSFLG2_UTXFF           SYSFLG_UTXFF
+
+#define LCDCON_GSEN             (1 << 30)
+#define LCDCON_GSMD             (1 << 31)
+
+#define SYSCON2_SERSEL          (1 << 0)
+#define SYSCON2_KBD6            (1 << 1)
+#define SYSCON2_DRAMZ           (1 << 2)
+#define SYSCON2_KBWEN           (1 << 3)
+#define SYSCON2_SS2TXEN         (1 << 4)
+#define SYSCON2_PCCARD1         (1 << 5)
+#define SYSCON2_PCCARD2         (1 << 6)
+#define SYSCON2_SS2RXEN         (1 << 7)
+#define SYSCON2_UART2EN         SYSCON_UARTEN
+#define SYSCON2_SS2MAEN         (1 << 9)
+#define SYSCON2_OSTB            (1 << 12)
+#define SYSCON2_CLKENSL         (1 << 13)
+#define SYSCON2_BUZFREQ         (1 << 14)
+
+/* common bits: UARTDR1 / UARTDR2 */
+#define UARTDR_FRMERR           (1 << 8)
+#define UARTDR_PARERR           (1 << 9)
+#define UARTDR_OVERR            (1 << 10)
+
+/* common bits: UBRLCR1 / UBRLCR2 */
+#define UBRLCR_BAUD_MASK        ((1 << 12) - 1)
+#define UBRLCR_BREAK            (1 << 12)
+#define UBRLCR_PRTEN            (1 << 13)
+#define UBRLCR_EVENPRT          (1 << 14)
+#define UBRLCR_XSTOP            (1 << 15)
+#define UBRLCR_FIFOEN           (1 << 16)
+#define UBRLCR_WRDLEN5          (0 << 17)
+#define UBRLCR_WRDLEN6          (1 << 17)
+#define UBRLCR_WRDLEN7          (2 << 17)
+#define UBRLCR_WRDLEN8          (3 << 17)
+#define UBRLCR_WRDLEN_MASK      (3 << 17)
+
+#define SYNCIO_SMCKEN           (1 << 13)
+#define SYNCIO_TXFRMEN          (1 << 14)
+
+#endif /* __ASM_HARDWARE_CLPS7111_H */
diff --git a/include/asm-arm/hardware/cs89712.h b/include/asm-arm/hardware/cs89712.h
new file mode 100644
index 000000000000..ad99a3e1b802
--- /dev/null
+++ b/include/asm-arm/hardware/cs89712.h
@@ -0,0 +1,49 @@
+/*
+ *  linux/include/asm-arm/hardware/cs89712.h
+ *
+ *  This file contains the hardware definitions of the CS89712
+ *  additional internal registers.
+ *
+ *  Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
+ *                      
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_HARDWARE_CS89712_H
+#define __ASM_HARDWARE_CS89712_H
+
+/*
+*       CS89712 additional registers
+*/
+                                  
+#define PCDR                    0x0002  /* Port C Data register ---------------------------- */
+#define PCDDR                   0x0042  /* Port C Data Direction register ------------------ */
+#define SDCONF                  0x2300  /* SDRAM Configuration register ---------------------*/
+#define SDRFPR                  0x2340  /* SDRAM Refresh period register --------------------*/
+
+#define SDCONF_ACTIVE           (1 << 10)
+#define SDCONF_CLKCTL           (1 << 9)
+#define SDCONF_WIDTH_4          (0 << 7)
+#define SDCONF_WIDTH_8          (1 << 7)
+#define SDCONF_WIDTH_16         (2 << 7)
+#define SDCONF_WIDTH_32         (3 << 7)
+#define SDCONF_SIZE_16          (0 << 5)
+#define SDCONF_SIZE_64          (1 << 5)
+#define SDCONF_SIZE_128         (2 << 5)
+#define SDCONF_SIZE_256         (3 << 5)
+#define SDCONF_CASLAT_2         (2)
+#define SDCONF_CASLAT_3         (3)
+
+#endif /* __ASM_HARDWARE_CS89712_H */
diff --git a/include/asm-arm/hardware/dec21285.h b/include/asm-arm/hardware/dec21285.h
new file mode 100644
index 000000000000..9049f0ddaecf
--- /dev/null
+++ b/include/asm-arm/hardware/dec21285.h
@@ -0,0 +1,148 @@
+/*
+ *  linux/include/asm-arm/hardware/dec21285.h
+ *
+ *  Copyright (C) 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  DC21285 registers
+ */
+#define DC21285_PCI_IACK                0x79000000
+#define DC21285_ARMCSR_BASE             0x42000000
+#define DC21285_PCI_TYPE_0_CONFIG       0x7b000000
+#define DC21285_PCI_TYPE_1_CONFIG       0x7a000000
+#define DC21285_OUTBOUND_WRITE_FLUSH    0x78000000
+#define DC21285_FLASH                   0x41000000
+#define DC21285_PCI_IO                  0x7c000000
+#define DC21285_PCI_MEM                 0x80000000
+
+#include <linux/config.h>
+#ifndef __ASSEMBLY__
+#include <asm/arch/hardware.h>
+#define DC21285_IO(x)           ((volatile unsigned long *)(ARMCSR_BASE+(x)))
+#else
+#define DC21285_IO(x)           (x)
+#endif
+
+#define CSR_PCICMD              DC21285_IO(0x0004)
+#define CSR_CLASSREV            DC21285_IO(0x0008)
+#define CSR_PCICACHELINESIZE    DC21285_IO(0x000c)
+#define CSR_PCICSRBASE          DC21285_IO(0x0010)
+#define CSR_PCICSRIOBASE        DC21285_IO(0x0014)
+#define CSR_PCISDRAMBASE        DC21285_IO(0x0018)
+#define CSR_PCIROMBASE          DC21285_IO(0x0030)
+#define CSR_MBOX0               DC21285_IO(0x0050)
+#define CSR_MBOX1               DC21285_IO(0x0054)
+#define CSR_MBOX2               DC21285_IO(0x0058)
+#define CSR_MBOX3               DC21285_IO(0x005c)
+#define CSR_DOORBELL            DC21285_IO(0x0060)
+#define CSR_DOORBELL_SETUP      DC21285_IO(0x0064)
+#define CSR_ROMWRITEREG         DC21285_IO(0x0068)
+#define CSR_CSRBASEMASK         DC21285_IO(0x00f8)
+#define CSR_CSRBASEOFFSET       DC21285_IO(0x00fc)
+#define CSR_SDRAMBASEMASK       DC21285_IO(0x0100)
+#define CSR_SDRAMBASEOFFSET     DC21285_IO(0x0104)
+#define CSR_ROMBASEMASK         DC21285_IO(0x0108)
+#define CSR_SDRAMTIMING         DC21285_IO(0x010c)
+#define CSR_SDRAMADDRSIZE0      DC21285_IO(0x0110)
+#define CSR_SDRAMADDRSIZE1      DC21285_IO(0x0114)
+#define CSR_SDRAMADDRSIZE2      DC21285_IO(0x0118)
+#define CSR_SDRAMADDRSIZE3      DC21285_IO(0x011c)
+#define CSR_I2O_INFREEHEAD      DC21285_IO(0x0120)
+#define CSR_I2O_INPOSTTAIL      DC21285_IO(0x0124)
+#define CSR_I2O_OUTPOSTHEAD     DC21285_IO(0x0128)
+#define CSR_I2O_OUTFREETAIL     DC21285_IO(0x012c)
+#define CSR_I2O_INFREECOUNT     DC21285_IO(0x0130)
+#define CSR_I2O_OUTPOSTCOUNT    DC21285_IO(0x0134)
+#define CSR_I2O_INPOSTCOUNT     DC21285_IO(0x0138)
+#define CSR_SA110_CNTL          DC21285_IO(0x013c)
+#define SA110_CNTL_INITCMPLETE          (1 << 0)
+#define SA110_CNTL_ASSERTSERR           (1 << 1)
+#define SA110_CNTL_RXSERR               (1 << 3)
+#define SA110_CNTL_SA110DRAMPARITY      (1 << 4)
+#define SA110_CNTL_PCISDRAMPARITY       (1 << 5)
+#define SA110_CNTL_DMASDRAMPARITY       (1 << 6)
+#define SA110_CNTL_DISCARDTIMER         (1 << 8)
+#define SA110_CNTL_PCINRESET            (1 << 9)
+#define SA110_CNTL_I2O_256              (0 << 10)
+#define SA110_CNTL_I20_512              (1 << 10)
+#define SA110_CNTL_I2O_1024             (2 << 10)
+#define SA110_CNTL_I2O_2048             (3 << 10)
+#define SA110_CNTL_I2O_4096             (4 << 10)
+#define SA110_CNTL_I2O_8192             (5 << 10)
+#define SA110_CNTL_I2O_16384            (6 << 10)
+#define SA110_CNTL_I2O_32768            (7 << 10)
+#define SA110_CNTL_WATCHDOG             (1 << 13)
+#define SA110_CNTL_ROMWIDTH_UNDEF       (0 << 14)
+#define SA110_CNTL_ROMWIDTH_16          (1 << 14)
+#define SA110_CNTL_ROMWIDTH_32          (2 << 14)
+#define SA110_CNTL_ROMWIDTH_8           (3 << 14)
+#define SA110_CNTL_ROMACCESSTIME(x)     ((x)<<16)
+#define SA110_CNTL_ROMBURSTTIME(x)      ((x)<<20)
+#define SA110_CNTL_ROMTRISTATETIME(x)   ((x)<<24)
+#define SA110_CNTL_XCSDIR(x)            ((x)<<28)
+#define SA110_CNTL_PCICFN               (1 << 31)
+
+/*
+ * footbridge_cfn_mode() is used when we want
+ * to check whether we are the central function
+ */
+#define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)
+#if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN)
+#define footbridge_cfn_mode() __footbridge_cfn_mode()
+#elif defined(CONFIG_FOOTBRIDGE_HOST)
+#define footbridge_cfn_mode() (1)
+#else
+#define footbridge_cfn_mode() (0)
+#endif
+
+#define CSR_PCIADDR_EXTN        DC21285_IO(0x0140)
+#define CSR_PREFETCHMEMRANGE    DC21285_IO(0x0144)
+#define CSR_XBUS_CYCLE          DC21285_IO(0x0148)
+#define CSR_XBUS_IOSTROBE       DC21285_IO(0x014c)
+#define CSR_DOORBELL_PCI        DC21285_IO(0x0150)
+#define CSR_DOORBELL_SA110      DC21285_IO(0x0154)
+#define CSR_UARTDR              DC21285_IO(0x0160)
+#define CSR_RXSTAT              DC21285_IO(0x0164)
+#define CSR_H_UBRLCR            DC21285_IO(0x0168)
+#define CSR_M_UBRLCR            DC21285_IO(0x016c)
+#define CSR_L_UBRLCR            DC21285_IO(0x0170)
+#define CSR_UARTCON             DC21285_IO(0x0174)
+#define CSR_UARTFLG             DC21285_IO(0x0178)
+#define CSR_IRQ_STATUS          DC21285_IO(0x0180)
+#define CSR_IRQ_RAWSTATUS       DC21285_IO(0x0184)
+#define CSR_IRQ_ENABLE          DC21285_IO(0x0188)
+#define CSR_IRQ_DISABLE         DC21285_IO(0x018c)
+#define CSR_IRQ_SOFT            DC21285_IO(0x0190)
+#define CSR_FIQ_STATUS          DC21285_IO(0x0280)
+#define CSR_FIQ_RAWSTATUS       DC21285_IO(0x0284)
+#define CSR_FIQ_ENABLE          DC21285_IO(0x0288)
+#define CSR_FIQ_DISABLE         DC21285_IO(0x028c)
+#define CSR_FIQ_SOFT            DC21285_IO(0x0290)
+#define CSR_TIMER1_LOAD         DC21285_IO(0x0300)
+#define CSR_TIMER1_VALUE        DC21285_IO(0x0304)
+#define CSR_TIMER1_CNTL         DC21285_IO(0x0308)
+#define CSR_TIMER1_CLR          DC21285_IO(0x030c)
+#define CSR_TIMER2_LOAD         DC21285_IO(0x0320)
+#define CSR_TIMER2_VALUE        DC21285_IO(0x0324)
+#define CSR_TIMER2_CNTL         DC21285_IO(0x0328)
+#define CSR_TIMER2_CLR          DC21285_IO(0x032c)
+#define CSR_TIMER3_LOAD         DC21285_IO(0x0340)
+#define CSR_TIMER3_VALUE        DC21285_IO(0x0344)
+#define CSR_TIMER3_CNTL         DC21285_IO(0x0348)
+#define CSR_TIMER3_CLR          DC21285_IO(0x034c)
+#define CSR_TIMER4_LOAD         DC21285_IO(0x0360)
+#define CSR_TIMER4_VALUE        DC21285_IO(0x0364)
+#define CSR_TIMER4_CNTL         DC21285_IO(0x0368)
+#define CSR_TIMER4_CLR          DC21285_IO(0x036c)
+
+#define TIMER_CNTL_ENABLE       (1 << 7)
+#define TIMER_CNTL_AUTORELOAD   (1 << 6)
+#define TIMER_CNTL_DIV1         (0)
+#define TIMER_CNTL_DIV16        (1 << 2)
+#define TIMER_CNTL_DIV256       (2 << 2)
+#define TIMER_CNTL_CNTEXT       (3 << 2)
+
+
diff --git a/include/asm-arm/hardware/entry-macro-iomd.S b/include/asm-arm/hardware/entry-macro-iomd.S
new file mode 100644
index 000000000000..30c7b92c2416
--- /dev/null
+++ b/include/asm-arm/hardware/entry-macro-iomd.S
@@ -0,0 +1,145 @@
+/*
+ * arch/arm/commond/entry-macro-iomd.S
+ *
+ * Low-level IRQ helper macros for IOC/IOMD based platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/* IOC / IOMD based hardware */
+#include <asm/hardware/iomd.h>
+
+                .equ    ioc_base_high, IOC_BASE & 0xff000000
+                .equ    ioc_base_low, IOC_BASE & 0x00ff0000
+                .macro  disable_fiq
+                mov     r12, #ioc_base_high
+                .if     ioc_base_low
+                orr     r12, r12, #ioc_base_low
+                .endif
+                strb    r12, [r12, #0x38]       @ Disable FIQ register
+                .endm
+
+                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+                mov     r4, #ioc_base_high              @ point at IOC
+                .if     ioc_base_low
+                orr     r4, r4, #ioc_base_low
+                .endif
+                ldrb    \irqstat, [r4, #IOMD_IRQREQB]   @ get high priority first
+                ldr     \base, =irq_prio_h
+                teq     \irqstat, #0
+#ifdef IOMD_BASE
+                ldreqb  \irqstat, [r4, #IOMD_DMAREQ]    @ get dma
+                addeq   \base, \base, #256              @ irq_prio_h table size
+                teqeq   \irqstat, #0
+                bne     2406f
+#endif
+                ldreqb  \irqstat, [r4, #IOMD_IRQREQA]   @ get low priority
+                addeq   \base, \base, #256              @ irq_prio_d table size
+                teqeq   \irqstat, #0
+#ifdef IOMD_IRQREQC
+                ldreqb  \irqstat, [r4, #IOMD_IRQREQC]
+                addeq   \base, \base, #256              @ irq_prio_l table size
+                teqeq   \irqstat, #0
+#endif
+#ifdef IOMD_IRQREQD
+                ldreqb  \irqstat, [r4, #IOMD_IRQREQD]
+                addeq   \base, \base, #256              @ irq_prio_lc table size
+                teqeq   \irqstat, #0
+#endif
+2406:           ldrneb  \irqnr, [\base, \irqstat]       @ get IRQ number
+                .endm
+
+/*
+ * Interrupt table (incorporates priority).  Please note that we
+ * rely on the order of these tables (see above code).
+ */
+                .align  5
+irq_prio_h:     .byte    0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
+                .byte   13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
+#ifdef IOMD_BASE
+irq_prio_d:     .byte    0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+                .byte   21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
+#endif
+irq_prio_l:     .byte    0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
+                .byte    4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
+                .byte    5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
+                .byte    5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
+                .byte    6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
+                .byte    6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
+                .byte    5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
+                .byte    5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
+                .byte    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
+                .byte    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
+                .byte    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
+                .byte    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
+                .byte    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
+                .byte    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
+                .byte    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
+                .byte    7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
+#ifdef IOMD_IRQREQC
+irq_prio_lc:    .byte   24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
+                .byte   28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
+                .byte   29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
+                .byte   29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
+                .byte   30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
+                .byte   30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
+                .byte   29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
+                .byte   29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
+                .byte   31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
+                .byte   31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
+                .byte   31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
+                .byte   31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
+                .byte   31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
+                .byte   31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
+                .byte   31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
+                .byte   31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
+#endif
+#ifdef IOMD_IRQREQD
+irq_prio_ld:    .byte   40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
+                .byte   44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
+                .byte   45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
+                .byte   45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
+                .byte   46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
+                .byte   46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
+                .byte   45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
+                .byte   45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
+                .byte   47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
+                .byte   47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
+                .byte   47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
+                .byte   47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
+                .byte   47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
+                .byte   47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
+                .byte   47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
+                .byte   47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
+#endif
+
diff --git a/include/asm-arm/hardware/ep7211.h b/include/asm-arm/hardware/ep7211.h
new file mode 100644
index 000000000000..017aa68f612d
--- /dev/null
+++ b/include/asm-arm/hardware/ep7211.h
@@ -0,0 +1,40 @@
+/*
+ *  linux/include/asm-arm/hardware/ep7211.h
+ *
+ *  This file contains the hardware definitions of the EP7211 internal
+ *  registers.
+ *
+ *  Copyright (C) 2001 Blue Mug, Inc.  All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_HARDWARE_EP7211_H
+#define __ASM_HARDWARE_EP7211_H
+
+#include <asm/hardware/clps7111.h>
+
+/*
+ * define EP7211_BASE to be the base address of the region
+ * you want to access.
+ */
+
+#define EP7211_PHYS_BASE        (0x80000000)
+
+/*
+ * XXX miket@bluemug.com: need to introduce EP7211 registers (those not
+ * present in 7212) here.
+ */
+
+#endif /* __ASM_HARDWARE_EP7211_H */
diff --git a/include/asm-arm/hardware/ep7212.h b/include/asm-arm/hardware/ep7212.h
new file mode 100644
index 000000000000..0e952e747073
--- /dev/null
+++ b/include/asm-arm/hardware/ep7212.h
@@ -0,0 +1,83 @@
+/*
+ *  linux/include/asm-arm/hardware/ep7212.h
+ *
+ *  This file contains the hardware definitions of the EP7212 internal
+ *  registers.
+ *
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_HARDWARE_EP7212_H
+#define __ASM_HARDWARE_EP7212_H
+
+/*
+ * define EP7212_BASE to be the base address of the region
+ * you want to access.
+ */
+
+#define EP7212_PHYS_BASE        (0x80000000)
+
+#ifndef __ASSEMBLY__
+#define ep_readl(off)           __raw_readl(EP7212_BASE + (off))
+#define ep_writel(val,off)      __raw_writel(val, EP7212_BASE + (off))
+#endif
+
+/*
+ * These registers are specific to the EP7212 only
+ */
+#define DAIR                    0x2000
+#define DAIR0                   0x2040
+#define DAIDR1                  0x2080
+#define DAIDR2                  0x20c0
+#define DAISR                   0x2100
+#define SYSCON3                 0x2200
+#define INTSR3                  0x2240
+#define INTMR3                  0x2280
+#define LEDFLSH                 0x22c0
+
+#define DAIR_DAIEN              (1 << 16)
+#define DAIR_ECS                (1 << 17)
+#define DAIR_LCTM               (1 << 19)
+#define DAIR_LCRM               (1 << 20)
+#define DAIR_RCTM               (1 << 21)
+#define DAIR_RCRM               (1 << 22)
+#define DAIR_LBM                (1 << 23)
+
+#define DAIDR2_FIFOEN           (1 << 15)
+#define DAIDR2_FIFOLEFT         (0x0d << 16)
+#define DAIDR2_FIFORIGHT        (0x11 << 16)
+
+#define DAISR_RCTS              (1 << 0)
+#define DAISR_RCRS              (1 << 1)
+#define DAISR_LCTS              (1 << 2)
+#define DAISR_LCRS              (1 << 3)
+#define DAISR_RCTU              (1 << 4)
+#define DAISR_RCRO              (1 << 5)
+#define DAISR_LCTU              (1 << 6)
+#define DAISR_LCRO              (1 << 7)
+#define DAISR_RCNF              (1 << 8)
+#define DAISR_RCNE              (1 << 9)
+#define DAISR_LCNF              (1 << 10)
+#define DAISR_LCNE              (1 << 11)
+#define DAISR_FIFO              (1 << 12)
+
+#define SYSCON3_ADCCON          (1 << 0)
+#define SYSCON3_DAISEL          (1 << 3)
+#define SYSCON3_ADCCKNSEN       (1 << 4)
+#define SYSCON3_FASTWAKE        (1 << 8)
+#define SYSCON3_DAIEN           (1 << 9)
+
+#endif /* __ASM_HARDWARE_EP7212_H */
diff --git a/include/asm-arm/hardware/icst307.h b/include/asm-arm/hardware/icst307.h
new file mode 100644
index 000000000000..ff8618a441c0
--- /dev/null
+++ b/include/asm-arm/hardware/icst307.h
@@ -0,0 +1,38 @@
+/*
+ *  linux/include/asm-arm/hardware/icst307.h
+ *
+ *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Support functions for calculating clocks/divisors for the ICS307
+ *  clock generators.  See http://www.icst.com/ for more information
+ *  on these devices.
+ *
+ *  This file is similar to the icst525.h file
+ */
+#ifndef ASMARM_HARDWARE_ICST307_H
+#define ASMARM_HARDWARE_ICST307_H
+
+struct icst307_params {
+        unsigned long   ref;
+        unsigned long   vco_max;        /* inclusive */
+        unsigned short  vd_min;         /* inclusive */
+        unsigned short  vd_max;         /* inclusive */
+        unsigned char   rd_min;         /* inclusive */
+        unsigned char   rd_max;         /* inclusive */
+};
+
+struct icst307_vco {
+        unsigned short  v;
+        unsigned char   r;
+        unsigned char   s;
+};
+
+unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco);
+struct icst307_vco icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq);
+struct icst307_vco icst307_ps_to_vco(const struct icst307_params *p, unsigned long period);
+
+#endif
diff --git a/include/asm-arm/hardware/icst525.h b/include/asm-arm/hardware/icst525.h
new file mode 100644
index 000000000000..edd5a5704406
--- /dev/null
+++ b/include/asm-arm/hardware/icst525.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/hardware/icst525.h
+ *
+ *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Support functions for calculating clocks/divisors for the ICST525
+ *  clock generators.  See http://www.icst.com/ for more information
+ *  on these devices.
+ */
+#ifndef ASMARM_HARDWARE_ICST525_H
+#define ASMARM_HARDWARE_ICST525_H
+
+struct icst525_params {
+        unsigned long   ref;
+        unsigned long   vco_max;        /* inclusive */
+        unsigned short  vd_min;         /* inclusive */
+        unsigned short  vd_max;         /* inclusive */
+        unsigned char   rd_min;         /* inclusive */
+        unsigned char   rd_max;         /* inclusive */
+};
+
+struct icst525_vco {
+        unsigned short  v;
+        unsigned char   r;
+        unsigned char   s;
+};
+
+unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco);
+struct icst525_vco icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq);
+struct icst525_vco icst525_ps_to_vco(const struct icst525_params *p, unsigned long period);
+
+#endif
diff --git a/include/asm-arm/hardware/ioc.h b/include/asm-arm/hardware/ioc.h
new file mode 100644
index 000000000000..b3b46ef65943
--- /dev/null
+++ b/include/asm-arm/hardware/ioc.h
@@ -0,0 +1,72 @@
+/*
+ *  linux/include/asm-arm/hardware/ioc.h
+ *
+ *  Copyright (C) Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Use these macros to read/write the IOC.  All it does is perform the actual
+ *  read/write.
+ */
+#ifndef __ASMARM_HARDWARE_IOC_H
+#define __ASMARM_HARDWARE_IOC_H
+
+#ifndef __ASSEMBLY__
+
+/*
+ * We use __raw_base variants here so that we give the compiler the
+ * chance to keep IOC_BASE in a register.
+ */
+#define ioc_readb(off)          __raw_readb(IOC_BASE + (off))
+#define ioc_writeb(val,off)     __raw_writeb(val, IOC_BASE + (off))
+
+#endif
+
+#define IOC_CONTROL     (0x00)
+#define IOC_KARTTX      (0x04)
+#define IOC_KARTRX      (0x04)
+
+#define IOC_IRQSTATA    (0x10)
+#define IOC_IRQREQA     (0x14)
+#define IOC_IRQCLRA     (0x14)
+#define IOC_IRQMASKA    (0x18)
+
+#define IOC_IRQSTATB    (0x20)
+#define IOC_IRQREQB     (0x24)
+#define IOC_IRQMASKB    (0x28)
+
+#define IOC_FIQSTAT     (0x30)
+#define IOC_FIQREQ      (0x34)
+#define IOC_FIQMASK     (0x38)
+
+#define IOC_T0CNTL      (0x40)
+#define IOC_T0LTCHL     (0x40)
+#define IOC_T0CNTH      (0x44)
+#define IOC_T0LTCHH     (0x44)
+#define IOC_T0GO        (0x48)
+#define IOC_T0LATCH     (0x4c)
+
+#define IOC_T1CNTL      (0x50)
+#define IOC_T1LTCHL     (0x50)
+#define IOC_T1CNTH      (0x54)
+#define IOC_T1LTCHH     (0x54)
+#define IOC_T1GO        (0x58)
+#define IOC_T1LATCH     (0x5c)
+
+#define IOC_T2CNTL      (0x60)
+#define IOC_T2LTCHL     (0x60)
+#define IOC_T2CNTH      (0x64)
+#define IOC_T2LTCHH     (0x64)
+#define IOC_T2GO        (0x68)
+#define IOC_T2LATCH     (0x6c)
+
+#define IOC_T3CNTL      (0x70)
+#define IOC_T3LTCHL     (0x70)
+#define IOC_T3CNTH      (0x74)
+#define IOC_T3LTCHH     (0x74)
+#define IOC_T3GO        (0x78)
+#define IOC_T3LATCH     (0x7c)
+
+#endif
diff --git a/include/asm-arm/hardware/iomd.h b/include/asm-arm/hardware/iomd.h
new file mode 100644
index 000000000000..82fa2c279a18
--- /dev/null
+++ b/include/asm-arm/hardware/iomd.h
@@ -0,0 +1,227 @@
+/*
+ *  linux/include/asm-arm/hardware/iomd.h
+ *
+ *  Copyright (C) 1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This file contains information out the IOMD ASIC used in the
+ *  Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
+ */
+#ifndef __ASMARM_HARDWARE_IOMD_H
+#define __ASMARM_HARDWARE_IOMD_H
+
+#include <linux/config.h>
+
+#ifndef __ASSEMBLY__
+
+/*
+ * We use __raw_base variants here so that we give the compiler the
+ * chance to keep IOC_BASE in a register.
+ */
+#define iomd_readb(off)         __raw_readb(IOMD_BASE + (off))
+#define iomd_readl(off)         __raw_readl(IOMD_BASE + (off))
+#define iomd_writeb(val,off)    __raw_writeb(val, IOMD_BASE + (off))
+#define iomd_writel(val,off)    __raw_writel(val, IOMD_BASE + (off))
+
+#endif
+
+#define IOMD_CONTROL    (0x000)
+#define IOMD_KARTTX     (0x004)
+#define IOMD_KARTRX     (0x004)
+#define IOMD_KCTRL      (0x008)
+
+#ifdef CONFIG_ARCH_CLPS7500
+#define IOMD_IOLINES    (0x00C)
+#endif
+
+#define IOMD_IRQSTATA   (0x010)
+#define IOMD_IRQREQA    (0x014)
+#define IOMD_IRQCLRA    (0x014)
+#define IOMD_IRQMASKA   (0x018)
+
+#ifdef CONFIG_ARCH_CLPS7500
+#define IOMD_SUSMODE    (0x01C)
+#endif
+
+#define IOMD_IRQSTATB   (0x020)
+#define IOMD_IRQREQB    (0x024)
+#define IOMD_IRQMASKB   (0x028)
+
+#define IOMD_FIQSTAT    (0x030)
+#define IOMD_FIQREQ     (0x034)
+#define IOMD_FIQMASK    (0x038)
+
+#ifdef CONFIG_ARCH_CLPS7500
+#define IOMD_CLKCTL     (0x03C)
+#endif
+
+#define IOMD_T0CNTL     (0x040)
+#define IOMD_T0LTCHL    (0x040)
+#define IOMD_T0CNTH     (0x044)
+#define IOMD_T0LTCHH    (0x044)
+#define IOMD_T0GO       (0x048)
+#define IOMD_T0LATCH    (0x04c)
+
+#define IOMD_T1CNTL     (0x050)
+#define IOMD_T1LTCHL    (0x050)
+#define IOMD_T1CNTH     (0x054)
+#define IOMD_T1LTCHH    (0x054)
+#define IOMD_T1GO       (0x058)
+#define IOMD_T1LATCH    (0x05c)
+
+#ifdef CONFIG_ARCH_CLPS7500
+#define IOMD_IRQSTATC   (0x060)
+#define IOMD_IRQREQC    (0x064)
+#define IOMD_IRQMASKC   (0x068)
+
+#define IOMD_VIDMUX     (0x06c)
+
+#define IOMD_IRQSTATD   (0x070)
+#define IOMD_IRQREQD    (0x074)
+#define IOMD_IRQMASKD   (0x078)
+#endif
+
+#define IOMD_ROMCR0     (0x080)
+#define IOMD_ROMCR1     (0x084)
+#ifdef CONFIG_ARCH_RPC
+#define IOMD_DRAMCR     (0x088)
+#endif
+#define IOMD_REFCR      (0x08C)
+
+#define IOMD_FSIZE      (0x090)
+#define IOMD_ID0        (0x094)
+#define IOMD_ID1        (0x098)
+#define IOMD_VERSION    (0x09C)
+
+#ifdef CONFIG_ARCH_RPC
+#define IOMD_MOUSEX     (0x0A0)
+#define IOMD_MOUSEY     (0x0A4)
+#endif
+
+#ifdef CONFIG_ARCH_CLPS7500
+#define IOMD_MSEDAT     (0x0A8)
+#define IOMD_MSECTL     (0x0Ac)
+#endif
+
+#ifdef CONFIG_ARCH_RPC
+#define IOMD_DMATCR     (0x0C0)
+#endif
+#define IOMD_IOTCR      (0x0C4)
+#define IOMD_ECTCR      (0x0C8)
+#ifdef CONFIG_ARCH_RPC
+#define IOMD_DMAEXT     (0x0CC)
+#endif
+#ifdef CONFIG_ARCH_CLPS7500
+#define IOMD_ASTCR      (0x0CC)
+#define IOMD_DRAMCR     (0x0D0)
+#define IOMD_SELFREF    (0x0D4)
+#define IOMD_ATODICR    (0x0E0)
+#define IOMD_ATODSR     (0x0E4)
+#define IOMD_ATODCC     (0x0E8)
+#define IOMD_ATODCNT1   (0x0EC)
+#define IOMD_ATODCNT2   (0x0F0)
+#define IOMD_ATODCNT3   (0x0F4)
+#define IOMD_ATODCNT4   (0x0F8)
+#endif
+
+#ifdef CONFIG_ARCH_RPC
+#define DMA_EXT_IO0     1
+#define DMA_EXT_IO1     2
+#define DMA_EXT_IO2     4
+#define DMA_EXT_IO3     8
+
+#define IOMD_IO0CURA    (0x100)
+#define IOMD_IO0ENDA    (0x104)
+#define IOMD_IO0CURB    (0x108)
+#define IOMD_IO0ENDB    (0x10C)
+#define IOMD_IO0CR      (0x110)
+#define IOMD_IO0ST      (0x114)
+
+#define IOMD_IO1CURA    (0x120)
+#define IOMD_IO1ENDA    (0x124)
+#define IOMD_IO1CURB    (0x128)
+#define IOMD_IO1ENDB    (0x12C)
+#define IOMD_IO1CR      (0x130)
+#define IOMD_IO1ST      (0x134)
+
+#define IOMD_IO2CURA    (0x140)
+#define IOMD_IO2ENDA    (0x144)
+#define IOMD_IO2CURB    (0x148)
+#define IOMD_IO2ENDB    (0x14C)
+#define IOMD_IO2CR      (0x150)
+#define IOMD_IO2ST      (0x154)
+
+#define IOMD_IO3CURA    (0x160)
+#define IOMD_IO3ENDA    (0x164)
+#define IOMD_IO3CURB    (0x168)
+#define IOMD_IO3ENDB    (0x16C)
+#define IOMD_IO3CR      (0x170)
+#define IOMD_IO3ST      (0x174)
+#endif
+
+#define IOMD_SD0CURA    (0x180)
+#define IOMD_SD0ENDA    (0x184)
+#define IOMD_SD0CURB    (0x188)
+#define IOMD_SD0ENDB    (0x18C)
+#define IOMD_SD0CR      (0x190)
+#define IOMD_SD0ST      (0x194)
+
+#ifdef CONFIG_ARCH_RPC
+#define IOMD_SD1CURA    (0x1A0)
+#define IOMD_SD1ENDA    (0x1A4)
+#define IOMD_SD1CURB    (0x1A8)
+#define IOMD_SD1ENDB    (0x1AC)
+#define IOMD_SD1CR      (0x1B0)
+#define IOMD_SD1ST      (0x1B4)
+#endif
+
+#define IOMD_CURSCUR    (0x1C0)
+#define IOMD_CURSINIT   (0x1C4)
+
+#define IOMD_VIDCUR     (0x1D0)
+#define IOMD_VIDEND     (0x1D4)
+#define IOMD_VIDSTART   (0x1D8)
+#define IOMD_VIDINIT    (0x1DC)
+#define IOMD_VIDCR      (0x1E0)
+
+#define IOMD_DMASTAT    (0x1F0)
+#define IOMD_DMAREQ     (0x1F4)
+#define IOMD_DMAMASK    (0x1F8)
+
+#define DMA_END_S       (1 << 31)
+#define DMA_END_L       (1 << 30)
+
+#define DMA_CR_C        0x80
+#define DMA_CR_D        0x40
+#define DMA_CR_E        0x20
+
+#define DMA_ST_OFL      4
+#define DMA_ST_INT      2
+#define DMA_ST_AB       1
+
+/*
+ * DMA (MEMC) compatibility
+ */
+#define HALF_SAM        vram_half_sam
+#define VDMA_ALIGNMENT  (HALF_SAM * 2)
+#define VDMA_XFERSIZE   (HALF_SAM)
+#define VDMA_INIT       IOMD_VIDINIT
+#define VDMA_START      IOMD_VIDSTART
+#define VDMA_END        IOMD_VIDEND
+
+#ifndef __ASSEMBLY__
+extern unsigned int vram_half_sam;
+#define video_set_dma(start,end,offset)                         \
+do {                                                            \
+        outl (SCREEN_START + start, VDMA_START);                \
+        outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END);    \
+        if (offset >= end - VDMA_XFERSIZE)                      \
+                offset |= 0x40000000;                           \
+        outl (SCREEN_START + offset, VDMA_INIT);                \
+} while (0)
+#endif
+
+#endif
diff --git a/include/asm-arm/hardware/linkup-l1110.h b/include/asm-arm/hardware/linkup-l1110.h
new file mode 100644
index 000000000000..7ec91168a576
--- /dev/null
+++ b/include/asm-arm/hardware/linkup-l1110.h
@@ -0,0 +1,48 @@
+/*
+*
+* Definitions for H3600 Handheld Computer
+*
+* Copyright 2001 Compaq Computer Corporation.
+*
+* Use consistent with the GNU GPL is permitted,
+* provided that this copyright notice is
+* preserved in its entirety in all copies and derived works.
+*
+* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
+* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
+* FITNESS FOR ANY PARTICULAR PURPOSE.
+*
+* Author: Jamey Hicks.
+*
+*/
+
+/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */
+
+/* PC Card Status Register */
+#define LINKUP_PRS_S1   (1 << 0) /* voltage control bits S1-S4 */
+#define LINKUP_PRS_S2   (1 << 1)
+#define LINKUP_PRS_S3   (1 << 2)
+#define LINKUP_PRS_S4   (1 << 3)
+#define LINKUP_PRS_BVD1 (1 << 4)
+#define LINKUP_PRS_BVD2 (1 << 5)
+#define LINKUP_PRS_VS1  (1 << 6)
+#define LINKUP_PRS_VS2  (1 << 7)
+#define LINKUP_PRS_RDY  (1 << 8)
+#define LINKUP_PRS_CD1  (1 << 9)
+#define LINKUP_PRS_CD2  (1 << 10)
+
+/* PC Card Command Register */
+#define LINKUP_PRC_S1   (1 << 0)
+#define LINKUP_PRC_S2   (1 << 1)
+#define LINKUP_PRC_S3   (1 << 2)
+#define LINKUP_PRC_S4   (1 << 3)
+#define LINKUP_PRC_RESET (1 << 4)
+#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */
+#define LINKUP_PRC_CFE  (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */
+#define LINKUP_PRC_SOE  (1 << 7) /* signal output driver enable */
+#define LINKUP_PRC_SSP  (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */
+#define LINKUP_PRC_MBZ  (1 << 15) /* must be zero */
+
+struct linkup_l1110 {
+        volatile short prc;
+};
diff --git a/include/asm-arm/hardware/locomo.h b/include/asm-arm/hardware/locomo.h
new file mode 100644
index 000000000000..5f10048ec54e
--- /dev/null
+++ b/include/asm-arm/hardware/locomo.h
@@ -0,0 +1,206 @@
+/*
+ * linux/include/asm-arm/hardware/locomo.h
+ *
+ * This file contains the definitions for the LoCoMo G/A Chip
+ *
+ * (C) Copyright 2004 John Lenz
+ *
+ * May be copied or modified under the terms of the GNU General Public
+ * License.  See linux/COPYING for more information.
+ *
+ * Based on sa1111.h
+ */
+#ifndef _ASM_ARCH_LOCOMO
+#define _ASM_ARCH_LOCOMO
+
+#define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); })
+#define locomo_readl(addr)      (*(volatile u16 *)(addr))
+
+/* LOCOMO version */
+#define LOCOMO_VER      0x00
+
+/* Pin status */
+#define LOCOMO_ST       0x04
+
+/* Pin status */
+#define LOCOMO_C32K     0x08
+
+/* Interrupt controller */
+#define LOCOMO_ICR      0x0C
+
+/* MCS decoder for boot selecting */
+#define LOCOMO_MCSX0    0x10
+#define LOCOMO_MCSX1    0x14
+#define LOCOMO_MCSX2    0x18
+#define LOCOMO_MCSX3    0x1c
+
+/* Touch panel controller */
+#define LOCOMO_ASD      0x20            /* AD start delay */
+#define LOCOMO_HSD      0x28            /* HSYS delay */
+#define LOCOMO_HSC      0x2c            /* HSYS period */
+#define LOCOMO_TADC     0x30            /* tablet ADC clock */
+
+
+/* Long time timer */
+#define LOCOMO_LTC      0xd8            /* LTC interrupt setting */
+#define LOCOMO_LTINT    0xdc            /* LTC interrupt */
+
+/* DAC control signal for LCD (COMADJ ) */
+#define LOCOMO_DAC              0xe0
+/* DAC control */
+#define LOCOMO_DAC_SCLOEB       0x08    /* SCL pin output data       */
+#define LOCOMO_DAC_TEST         0x04    /* Test bit                  */
+#define LOCOMO_DAC_SDA          0x02    /* SDA pin level (read-only) */
+#define LOCOMO_DAC_SDAOEB       0x01    /* SDA pin output data       */
+
+/* SPI interface */
+#define LOCOMO_SPIMD    0x60            /* SPI mode setting */
+#define LOCOMO_SPICT    0x64            /* SPI mode control */
+#define LOCOMO_SPIST    0x68            /* SPI status */
+#define LOCOMO_SPIIS    0x70            /* SPI interrupt status */
+#define LOCOMO_SPIWE    0x74            /* SPI interrupt status write enable */
+#define LOCOMO_SPIIE    0x78            /* SPI interrupt enable */
+#define LOCOMO_SPIIR    0x7c            /* SPI interrupt request */
+#define LOCOMO_SPITD    0x80            /* SPI transfer data write */
+#define LOCOMO_SPIRD    0x84            /* SPI receive data read */
+#define LOCOMO_SPITS    0x88            /* SPI transfer data shift */
+#define LOCOMO_SPIRS    0x8C            /* SPI receive data shift */
+#define LOCOMO_SPI_TEND (1 << 3)        /* Transfer end bit */
+#define LOCOMO_SPI_OVRN (1 << 2)        /* Over Run bit */
+#define LOCOMO_SPI_RFW  (1 << 1)        /* write buffer bit */
+#define LOCOMO_SPI_RFR  (1)             /* read buffer bit */
+
+/* GPIO */
+#define LOCOMO_GPD              0x90    /* GPIO direction */
+#define LOCOMO_GPE              0x94    /* GPIO input enable */
+#define LOCOMO_GPL              0x98    /* GPIO level */
+#define LOCOMO_GPO              0x9c    /* GPIO out data setteing */
+#define LOCOMO_GRIE             0xa0    /* GPIO rise detection */
+#define LOCOMO_GFIE             0xa4    /* GPIO fall detection */
+#define LOCOMO_GIS              0xa8    /* GPIO edge detection status */
+#define LOCOMO_GWE              0xac    /* GPIO status write enable */
+#define LOCOMO_GIE              0xb0    /* GPIO interrupt enable */
+#define LOCOMO_GIR              0xb4    /* GPIO interrupt request */
+#define LOCOMO_GPIO(Nb)         (0x01 << (Nb))
+#define LOCOMO_GPIO_RTS         LOCOMO_GPIO(0)
+#define LOCOMO_GPIO_CTS         LOCOMO_GPIO(1)
+#define LOCOMO_GPIO_DSR         LOCOMO_GPIO(2)
+#define LOCOMO_GPIO_DTR         LOCOMO_GPIO(3)
+#define LOCOMO_GPIO_LCD_VSHA_ON LOCOMO_GPIO(4)
+#define LOCOMO_GPIO_LCD_VSHD_ON LOCOMO_GPIO(5)
+#define LOCOMO_GPIO_LCD_VEE_ON  LOCOMO_GPIO(6)
+#define LOCOMO_GPIO_LCD_MOD     LOCOMO_GPIO(7)
+#define LOCOMO_GPIO_DAC_ON      LOCOMO_GPIO(8)
+#define LOCOMO_GPIO_FL_VR       LOCOMO_GPIO(9)
+#define LOCOMO_GPIO_DAC_SDATA   LOCOMO_GPIO(10)
+#define LOCOMO_GPIO_DAC_SCK     LOCOMO_GPIO(11)
+#define LOCOMO_GPIO_DAC_SLOAD   LOCOMO_GPIO(12)
+
+/* Start the definitions of the devices.  Each device has an initial
+ * base address and a series of offsets from that base address. */
+
+/* Keyboard controller */
+#define LOCOMO_KEYBOARD         0x40
+#define LOCOMO_KIB              0x00    /* KIB level */
+#define LOCOMO_KSC              0x04    /* KSTRB control */
+#define LOCOMO_KCMD             0x08    /* KSTRB command */
+#define LOCOMO_KIC              0x0c    /* Key interrupt */
+
+/* Front light adjustment controller */
+#define LOCOMO_FRONTLIGHT       0xc8
+#define LOCOMO_ALS              0x00    /* Adjust light cycle */
+#define LOCOMO_ALD              0x04    /* Adjust light duty */
+
+/* Backlight controller: TFT signal */
+#define LOCOMO_BACKLIGHT        0x38
+#define LOCOMO_TC               0x00            /* TFT control signal */
+#define LOCOMO_CPSD             0x04            /* CPS delay */
+
+/* Audio controller */
+#define LOCOMO_AUDIO            0x54
+#define LOCOMO_ACC              0x00    /* Audio clock */
+#define LOCOMO_PAIF             0x7C    /* PCM audio interface */
+/* Audio clock */
+#define LOCOMO_ACC_XON          0x80
+#define LOCOMO_ACC_XEN          0x40
+#define LOCOMO_ACC_XSEL0        0x00
+#define LOCOMO_ACC_XSEL1        0x20
+#define LOCOMO_ACC_MCLKEN       0x10
+#define LOCOMO_ACC_64FSEN       0x08
+#define LOCOMO_ACC_CLKSEL000    0x00    /* mclk  2 */
+#define LOCOMO_ACC_CLKSEL001    0x01    /* mclk  3 */
+#define LOCOMO_ACC_CLKSEL010    0x02    /* mclk  4 */
+#define LOCOMO_ACC_CLKSEL011    0x03    /* mclk  6 */
+#define LOCOMO_ACC_CLKSEL100    0x04    /* mclk  8 */
+#define LOCOMO_ACC_CLKSEL101    0x05    /* mclk 12 */
+/* PCM audio interface */
+#define LOCOMO_PAIF_SCINV       0x20
+#define LOCOMO_PAIF_SCEN        0x10
+#define LOCOMO_PAIF_LRCRST      0x08
+#define LOCOMO_PAIF_LRCEVE      0x04
+#define LOCOMO_PAIF_LRCINV      0x02
+#define LOCOMO_PAIF_LRCEN       0x01
+
+/* LED controller */
+#define LOCOMO_LED              0xe8
+#define LOCOMO_LPT0             0x00
+#define LOCOMO_LPT1             0x04
+/* LED control */
+#define LOCOMO_LPT_TOFH         0x80
+#define LOCOMO_LPT_TOFL         0x08
+#define LOCOMO_LPT_TOH(TOH)     ((TOH & 0x7) << 4)
+#define LOCOMO_LPT_TOL(TOL)     ((TOL & 0x7))
+
+extern struct bus_type locomo_bus_type;
+
+#define LOCOMO_DEVID_KEYBOARD   0
+#define LOCOMO_DEVID_FRONTLIGHT 1
+#define LOCOMO_DEVID_BACKLIGHT  2
+#define LOCOMO_DEVID_AUDIO      3
+#define LOCOMO_DEVID_LED        4
+#define LOCOMO_DEVID_UART       5
+
+struct locomo_dev {
+        struct device   dev;
+        unsigned int    devid;
+        unsigned int    irq[1];
+
+        void            *mapbase;
+        unsigned long   length;
+
+        u64             dma_mask;
+};
+
+#define LOCOMO_DEV(_d)  container_of((_d), struct locomo_dev, dev)
+
+#define locomo_get_drvdata(d)   dev_get_drvdata(&(d)->dev)
+#define locomo_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
+
+struct locomo_driver {
+        struct device_driver    drv;
+        unsigned int            devid;
+        int (*probe)(struct locomo_dev *);
+        int (*remove)(struct locomo_dev *);
+        int (*suspend)(struct locomo_dev *, pm_message_t);
+        int (*resume)(struct locomo_dev *);
+};
+
+#define LOCOMO_DRV(_d)  container_of((_d), struct locomo_driver, drv)
+
+#define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name)
+
+void locomo_lcd_power(struct locomo_dev *, int, unsigned int);
+
+int locomo_driver_register(struct locomo_driver *);
+void locomo_driver_unregister(struct locomo_driver *);
+
+/* GPIO control functions */
+void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned int dir);
+unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits);
+unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits);
+void locomo_gpio_write(struct locomo_dev *ldev, unsigned int bits, unsigned int set);
+
+/* M62332 control function */
+void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
+
+#endif
diff --git a/include/asm-arm/hardware/memc.h b/include/asm-arm/hardware/memc.h
new file mode 100644
index 000000000000..8aef5aa0e01b
--- /dev/null
+++ b/include/asm-arm/hardware/memc.h
@@ -0,0 +1,26 @@
+/*
+ *  linux/include/asm-arm/hardware/memc.h
+ *
+ *  Copyright (C) Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#define VDMA_ALIGNMENT  PAGE_SIZE
+#define VDMA_XFERSIZE   16
+#define VDMA_INIT       0
+#define VDMA_START      1
+#define VDMA_END        2
+
+#ifndef __ASSEMBLY__
+extern void memc_write(unsigned int reg, unsigned long val);
+
+#define video_set_dma(start,end,offset)                         \
+do {                                                            \
+        memc_write (VDMA_START, (start >> 2));                  \
+        memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2);      \
+        memc_write (VDMA_INIT, (offset >> 2));                  \
+} while (0)
+
+#endif
diff --git a/include/asm-arm/hardware/pci_v3.h b/include/asm-arm/hardware/pci_v3.h
new file mode 100644
index 000000000000..4d497bdb9a97
--- /dev/null
+++ b/include/asm-arm/hardware/pci_v3.h
@@ -0,0 +1,186 @@
+/*
+ *  linux/include/asm-arm/hardware/pci_v3.h
+ *
+ *  Internal header file PCI V3 chip
+ *
+ *  Copyright (C) ARM Limited
+ *  Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef ASM_ARM_HARDWARE_PCI_V3_H
+#define ASM_ARM_HARDWARE_PCI_V3_H
+
+/* -------------------------------------------------------------------------------
+ *  V3 Local Bus to PCI Bridge definitions
+ * -------------------------------------------------------------------------------
+ *  Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
+ *  All V3 register names are prefaced by V3_ to avoid clashing with any other
+ *  PCI definitions.  Their names match the user's manual.
+ * 
+ *  I'm assuming that I20 is disabled.
+ * 
+ */
+#define V3_PCI_VENDOR                   0x00000000
+#define V3_PCI_DEVICE                   0x00000002
+#define V3_PCI_CMD                      0x00000004
+#define V3_PCI_STAT                     0x00000006
+#define V3_PCI_CC_REV                   0x00000008
+#define V3_PCI_HDR_CFG                  0x0000000C
+#define V3_PCI_IO_BASE                  0x00000010
+#define V3_PCI_BASE0                    0x00000014
+#define V3_PCI_BASE1                    0x00000018
+#define V3_PCI_SUB_VENDOR               0x0000002C
+#define V3_PCI_SUB_ID                   0x0000002E
+#define V3_PCI_ROM                      0x00000030
+#define V3_PCI_BPARAM                   0x0000003C
+#define V3_PCI_MAP0                     0x00000040
+#define V3_PCI_MAP1                     0x00000044
+#define V3_PCI_INT_STAT                 0x00000048
+#define V3_PCI_INT_CFG                  0x0000004C 
+#define V3_LB_BASE0                     0x00000054
+#define V3_LB_BASE1                     0x00000058
+#define V3_LB_MAP0                      0x0000005E
+#define V3_LB_MAP1                      0x00000062
+#define V3_LB_BASE2                     0x00000064
+#define V3_LB_MAP2                      0x00000066
+#define V3_LB_SIZE                      0x00000068
+#define V3_LB_IO_BASE                   0x0000006E
+#define V3_FIFO_CFG                     0x00000070
+#define V3_FIFO_PRIORITY                0x00000072
+#define V3_FIFO_STAT                    0x00000074
+#define V3_LB_ISTAT                     0x00000076
+#define V3_LB_IMASK                     0x00000077
+#define V3_SYSTEM                       0x00000078
+#define V3_LB_CFG                       0x0000007A
+#define V3_PCI_CFG                      0x0000007C
+#define V3_DMA_PCI_ADR0                 0x00000080
+#define V3_DMA_PCI_ADR1                 0x00000090
+#define V3_DMA_LOCAL_ADR0               0x00000084
+#define V3_DMA_LOCAL_ADR1               0x00000094
+#define V3_DMA_LENGTH0                  0x00000088
+#define V3_DMA_LENGTH1                  0x00000098
+#define V3_DMA_CSR0                     0x0000008B
+#define V3_DMA_CSR1                     0x0000009B
+#define V3_DMA_CTLB_ADR0                0x0000008C
+#define V3_DMA_CTLB_ADR1                0x0000009C
+#define V3_DMA_DELAY                    0x000000E0
+#define V3_MAIL_DATA                    0x000000C0
+#define V3_PCI_MAIL_IEWR                0x000000D0
+#define V3_PCI_MAIL_IERD                0x000000D2
+#define V3_LB_MAIL_IEWR                 0x000000D4
+#define V3_LB_MAIL_IERD                 0x000000D6
+#define V3_MAIL_WR_STAT                 0x000000D8
+#define V3_MAIL_RD_STAT                 0x000000DA
+#define V3_QBA_MAP                      0x000000DC
+
+/*  PCI COMMAND REGISTER bits
+ */
+#define V3_COMMAND_M_FBB_EN             (1 << 9)
+#define V3_COMMAND_M_SERR_EN            (1 << 8)
+#define V3_COMMAND_M_PAR_EN             (1 << 6)
+#define V3_COMMAND_M_MASTER_EN          (1 << 2)
+#define V3_COMMAND_M_MEM_EN             (1 << 1)
+#define V3_COMMAND_M_IO_EN              (1 << 0)
+
+/*  SYSTEM REGISTER bits
+ */
+#define V3_SYSTEM_M_RST_OUT             (1 << 15)
+#define V3_SYSTEM_M_LOCK                (1 << 14)
+
+/*  PCI_CFG bits
+ */
+#define V3_PCI_CFG_M_I2O_EN             (1 << 15)
+#define V3_PCI_CFG_M_IO_REG_DIS         (1 << 14)
+#define V3_PCI_CFG_M_IO_DIS             (1 << 13)
+#define V3_PCI_CFG_M_EN3V               (1 << 12)
+#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
+#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
+#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)
+
+/*  PCI_BASE register bits (PCI -> Local Bus)
+ */
+#define V3_PCI_BASE_M_ADR_BASE          0xFFF00000
+#define V3_PCI_BASE_M_ADR_BASEL         0x000FFF00
+#define V3_PCI_BASE_M_PREFETCH          (1 << 3)
+#define V3_PCI_BASE_M_TYPE              (3 << 1)
+#define V3_PCI_BASE_M_IO                (1 << 0)
+
+/*  PCI MAP register bits (PCI -> Local bus)
+ */
+#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
+#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
+#define V3_PCI_MAP_M_ROM_SIZE           (3 << 10)
+#define V3_PCI_MAP_M_SWAP               (3 << 8)
+#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
+#define V3_PCI_MAP_M_REG_EN             (1 << 1)
+#define V3_PCI_MAP_M_ENABLE             (1 << 0)
+
+/*
+ *  LB_BASE0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_BASE_ADR_BASE             0xfff00000
+#define V3_LB_BASE_SWAP                 (3 << 8)
+#define V3_LB_BASE_ADR_SIZE             (15 << 4)
+#define V3_LB_BASE_PREFETCH             (1 << 3)
+#define V3_LB_BASE_ENABLE               (1 << 0)
+
+#define V3_LB_BASE_ADR_SIZE_1MB         (0 << 4)
+#define V3_LB_BASE_ADR_SIZE_2MB         (1 << 4)
+#define V3_LB_BASE_ADR_SIZE_4MB         (2 << 4)
+#define V3_LB_BASE_ADR_SIZE_8MB         (3 << 4)
+#define V3_LB_BASE_ADR_SIZE_16MB        (4 << 4)
+#define V3_LB_BASE_ADR_SIZE_32MB        (5 << 4)
+#define V3_LB_BASE_ADR_SIZE_64MB        (6 << 4)
+#define V3_LB_BASE_ADR_SIZE_128MB       (7 << 4)
+#define V3_LB_BASE_ADR_SIZE_256MB       (8 << 4)
+#define V3_LB_BASE_ADR_SIZE_512MB       (9 << 4)
+#define V3_LB_BASE_ADR_SIZE_1GB         (10 << 4)
+#define V3_LB_BASE_ADR_SIZE_2GB         (11 << 4)
+
+#define v3_addr_to_lb_base(a)   ((a) & V3_LB_BASE_ADR_BASE)
+
+/*
+ *  LB_MAP0,1 register bits (Local bus -> PCI)
+ */
+#define V3_LB_MAP_MAP_ADR               0xfff0
+#define V3_LB_MAP_TYPE                  (7 << 1)
+#define V3_LB_MAP_AD_LOW_EN             (1 << 0)
+
+#define V3_LB_MAP_TYPE_IACK             (0 << 1)
+#define V3_LB_MAP_TYPE_IO               (1 << 1)
+#define V3_LB_MAP_TYPE_MEM              (3 << 1)
+#define V3_LB_MAP_TYPE_CONFIG           (5 << 1)
+#define V3_LB_MAP_TYPE_MEM_MULTIPLE     (6 << 1)
+
+#define v3_addr_to_lb_map(a)    (((a) >> 16) & V3_LB_MAP_MAP_ADR)
+
+/*
+ *  LB_BASE2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_BASE2_ADR_BASE            0xff00
+#define V3_LB_BASE2_SWAP                (3 << 6)
+#define V3_LB_BASE2_ENABLE              (1 << 0)
+
+#define v3_addr_to_lb_base2(a)  (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
+
+/*
+ *  LB_MAP2 register bits (Local bus -> PCI IO)
+ */
+#define V3_LB_MAP2_MAP_ADR              0xff00
+
+#define v3_addr_to_lb_map2(a)   (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
+
+#endif
diff --git a/include/asm-arm/hardware/sa1111.h b/include/asm-arm/hardware/sa1111.h
new file mode 100644
index 000000000000..319aea064c36
--- /dev/null
+++ b/include/asm-arm/hardware/sa1111.h
@@ -0,0 +1,602 @@
+/*
+ * linux/include/asm-arm/hardware/SA-1111.h
+ *
+ * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
+ *
+ * This file contains definitions for the SA-1111 Companion Chip.
+ * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
+ *
+ * Macro that calculates real address for registers in the SA-1111
+ */
+
+#ifndef _ASM_ARCH_SA1111
+#define _ASM_ARCH_SA1111
+
+#include <asm/arch/bitfield.h>
+
+/*
+ * The SA1111 is always located at virtual 0xf4000000, and is always
+ * "native" endian.
+ */
+
+#define SA1111_VBASE            0xf4000000
+
+/* Don't use these! */
+#define SA1111_p2v( x )         ((x) - SA1111_BASE + SA1111_VBASE)
+#define SA1111_v2p( x )         ((x) - SA1111_VBASE + SA1111_BASE)
+
+#ifndef __ASSEMBLY__
+#define _SA1111(x)      ((x) + sa1111->resource.start)
+#endif
+
+/*
+ * 26 bits of the SA-1110 address bus are available to the SA-1111.
+ * Use these when feeding target addresses to the DMA engines.
+ */
+
+#define SA1111_ADDR_WIDTH       (26)
+#define SA1111_ADDR_MASK        ((1<<SA1111_ADDR_WIDTH)-1)
+#define SA1111_DMA_ADDR(x)      ((x)&SA1111_ADDR_MASK)
+
+/*
+ * Don't ask the (SAC) DMA engines to move less than this amount.
+ */
+
+#define SA1111_SAC_DMA_MIN_XFER (0x800)
+
+/*
+ * SA1111 register definitions.
+ */
+#define __CCREG(x)      __REGP(SA1111_VBASE + (x))
+
+#define sa1111_writel(val,addr) __raw_writel(val, addr)
+#define sa1111_readl(addr)      __raw_readl(addr)
+
+/*
+ * System Bus Interface (SBI)
+ *
+ * Registers
+ *    SKCR      Control Register
+ *    SMCR      Shared Memory Controller Register
+ *    SKID      ID Register
+ */
+#define SA1111_SKCR     0x0000
+#define SA1111_SMCR     0x0004
+#define SA1111_SKID     0x0008
+
+#define SKCR_PLL_BYPASS (1<<0)
+#define SKCR_RCLKEN     (1<<1)
+#define SKCR_SLEEP      (1<<2)
+#define SKCR_DOZE       (1<<3)
+#define SKCR_VCO_OFF    (1<<4)
+#define SKCR_SCANTSTEN  (1<<5)
+#define SKCR_CLKTSTEN   (1<<6)
+#define SKCR_RDYEN      (1<<7)
+#define SKCR_SELAC      (1<<8)
+#define SKCR_OPPC       (1<<9)
+#define SKCR_PLLTSTEN   (1<<10)
+#define SKCR_USBIOTSTEN (1<<11)
+/*
+ * Don't believe the specs!  Take them, throw them outside.  Leave them
+ * there for a week.  Spit on them.  Walk on them.  Stamp on them.
+ * Pour gasoline over them and finally burn them.  Now think about coding.
+ *  - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
+ *  - The Feb 2001 errata (278260-010) says that the previous errata
+ *    (278260-009) is wrong, and its bit actually 12, fixed in spec
+ *    278242-003.
+ *  - The SA1111 manual (278242) says bit 12, but 0 to enable.
+ *  - Reality is bit 13, 1 to enable.
+ *      -- rmk
+ */
+#define SKCR_OE_EN      (1<<13)
+
+#define SMCR_DTIM       (1<<0)
+#define SMCR_MBGE       (1<<1)
+#define SMCR_DRAC_0     (1<<2)
+#define SMCR_DRAC_1     (1<<3)
+#define SMCR_DRAC_2     (1<<4)
+#define SMCR_DRAC       Fld(3, 2)
+#define SMCR_CLAT       (1<<5)
+
+#define SKID_SIREV_MASK (0x000000f0)
+#define SKID_MTREV_MASK (0x0000000f)
+#define SKID_ID_MASK    (0xffffff00)
+#define SKID_SA1111_ID  (0x690cc200)
+
+/*
+ * System Controller
+ *
+ * Registers
+ *    SKPCR     Power Control Register
+ *    SKCDR     Clock Divider Register
+ *    SKAUD     Audio Clock Divider Register
+ *    SKPMC     PS/2 Mouse Clock Divider Register
+ *    SKPTC     PS/2 Track Pad Clock Divider Register
+ *    SKPEN0    PWM0 Enable Register
+ *    SKPWM0    PWM0 Clock Register
+ *    SKPEN1    PWM1 Enable Register
+ *    SKPWM1    PWM1 Clock Register
+ */
+#define SA1111_SKPCR    0x0200
+#define SA1111_SKCDR    0x0204
+#define SA1111_SKAUD    0x0208
+#define SA1111_SKPMC    0x020c
+#define SA1111_SKPTC    0x0210
+#define SA1111_SKPEN0   0x0214
+#define SA1111_SKPWM0   0x0218
+#define SA1111_SKPEN1   0x021c
+#define SA1111_SKPWM1   0x0220
+
+#define SKPCR_UCLKEN    (1<<0)
+#define SKPCR_ACCLKEN   (1<<1)
+#define SKPCR_I2SCLKEN  (1<<2)
+#define SKPCR_L3CLKEN   (1<<3)
+#define SKPCR_SCLKEN    (1<<4)
+#define SKPCR_PMCLKEN   (1<<5)
+#define SKPCR_PTCLKEN   (1<<6)
+#define SKPCR_DCLKEN    (1<<7)
+#define SKPCR_PWMCLKEN  (1<<8)
+
+/*
+ * USB Host controller
+ */
+#define SA1111_USB              0x0400
+
+/*
+ * Offsets from SA1111_USB_BASE
+ */
+#define SA1111_USB_STATUS       0x0118
+#define SA1111_USB_RESET        0x011c
+#define SA1111_USB_IRQTEST      0x0120
+
+#define USB_RESET_FORCEIFRESET  (1 << 0)
+#define USB_RESET_FORCEHCRESET  (1 << 1)
+#define USB_RESET_CLKGENRESET   (1 << 2)
+#define USB_RESET_SIMSCALEDOWN  (1 << 3)
+#define USB_RESET_USBINTTEST    (1 << 4)
+#define USB_RESET_SLEEPSTBYEN   (1 << 5)
+#define USB_RESET_PWRSENSELOW   (1 << 6)
+#define USB_RESET_PWRCTRLLOW    (1 << 7)
+
+#define USB_STATUS_IRQHCIRMTWKUP  (1 <<  7)
+#define USB_STATUS_IRQHCIBUFFACC  (1 <<  8)
+#define USB_STATUS_NIRQHCIM       (1 <<  9)
+#define USB_STATUS_NHCIMFCLR      (1 << 10)
+#define USB_STATUS_USBPWRSENSE    (1 << 11)
+
+/*
+ * Serial Audio Controller
+ *
+ * Registers
+ *    SACR0             Serial Audio Common Control Register
+ *    SACR1             Serial Audio Alternate Mode (I2C/MSB) Control Register
+ *    SACR2             Serial Audio AC-link Control Register
+ *    SASR0             Serial Audio I2S/MSB Interface & FIFO Status Register
+ *    SASR1             Serial Audio AC-link Interface & FIFO Status Register
+ *    SASCR             Serial Audio Status Clear Register
+ *    L3_CAR            L3 Control Bus Address Register
+ *    L3_CDR            L3 Control Bus Data Register
+ *    ACCAR             AC-link Command Address Register
+ *    ACCDR             AC-link Command Data Register
+ *    ACSAR             AC-link Status Address Register
+ *    ACSDR             AC-link Status Data Register
+ *    SADTCS            Serial Audio DMA Transmit Control/Status Register
+ *    SADTSA            Serial Audio DMA Transmit Buffer Start Address A
+ *    SADTCA            Serial Audio DMA Transmit Buffer Count Register A
+ *    SADTSB            Serial Audio DMA Transmit Buffer Start Address B
+ *    SADTCB            Serial Audio DMA Transmit Buffer Count Register B
+ *    SADRCS            Serial Audio DMA Receive Control/Status Register
+ *    SADRSA            Serial Audio DMA Receive Buffer Start Address A
+ *    SADRCA            Serial Audio DMA Receive Buffer Count Register A
+ *    SADRSB            Serial Audio DMA Receive Buffer Start Address B
+ *    SADRCB            Serial Audio DMA Receive Buffer Count Register B
+ *    SAITR             Serial Audio Interrupt Test Register
+ *    SADR              Serial Audio Data Register (16 x 32-bit)
+ */
+
+#define _SACR0          _SA1111( 0x0600 )
+#define _SACR1          _SA1111( 0x0604 )
+#define _SACR2          _SA1111( 0x0608 )
+#define _SASR0          _SA1111( 0x060c )
+#define _SASR1          _SA1111( 0x0610 )
+#define _SASCR          _SA1111( 0x0618 )
+#define _L3_CAR         _SA1111( 0x061c )
+#define _L3_CDR         _SA1111( 0x0620 )
+#define _ACCAR          _SA1111( 0x0624 )
+#define _ACCDR          _SA1111( 0x0628 )
+#define _ACSAR          _SA1111( 0x062c )
+#define _ACSDR          _SA1111( 0x0630 )
+#define _SADTCS         _SA1111( 0x0634 )
+#define _SADTSA         _SA1111( 0x0638 )
+#define _SADTCA         _SA1111( 0x063c )
+#define _SADTSB         _SA1111( 0x0640 )
+#define _SADTCB         _SA1111( 0x0644 )
+#define _SADRCS         _SA1111( 0x0648 )
+#define _SADRSA         _SA1111( 0x064c )
+#define _SADRCA         _SA1111( 0x0650 )
+#define _SADRSB         _SA1111( 0x0654 )
+#define _SADRCB         _SA1111( 0x0658 )
+#define _SAITR          _SA1111( 0x065c )
+#define _SADR           _SA1111( 0x0680 )
+
+#define SACR0           __CCREG(0x0600)
+#define SACR1           __CCREG(0x0604)
+#define SACR2           __CCREG(0x0608)
+#define SASR0           __CCREG(0x060c)
+#define SASR1           __CCREG(0x0610)
+#define SASCR           __CCREG(0x0618)
+#define L3_CAR          __CCREG(0x061c)
+#define L3_CDR          __CCREG(0x0620)
+#define ACCAR           __CCREG(0x0624)
+#define ACCDR           __CCREG(0x0628)
+#define ACSAR           __CCREG(0x062c)
+#define ACSDR           __CCREG(0x0630)
+#define SADTCS          __CCREG(0x0634)
+#define SADTSA          __CCREG(0x0638)
+#define SADTCA          __CCREG(0x063c)
+#define SADTSB          __CCREG(0x0640)
+#define SADTCB          __CCREG(0x0644)
+#define SADRCS          __CCREG(0x0648)
+#define SADRSA          __CCREG(0x064c)
+#define SADRCA          __CCREG(0x0650)
+#define SADRSB          __CCREG(0x0654)
+#define SADRCB          __CCREG(0x0658)
+#define SAITR           __CCREG(0x065c)
+#define SADR            __CCREG(0x0680)
+
+#define SACR0_ENB       (1<<0)
+#define SACR0_BCKD      (1<<2)
+#define SACR0_RST       (1<<3)
+
+#define SACR1_AMSL      (1<<0)
+#define SACR1_L3EN      (1<<1)
+#define SACR1_L3MB      (1<<2)
+#define SACR1_DREC      (1<<3)
+#define SACR1_DRPL      (1<<4)
+#define SACR1_ENLBF     (1<<5)
+
+#define SACR2_TS3V      (1<<0)
+#define SACR2_TS4V      (1<<1)
+#define SACR2_WKUP      (1<<2)
+#define SACR2_DREC      (1<<3)
+#define SACR2_DRPL      (1<<4)
+#define SACR2_ENLBF     (1<<5)
+#define SACR2_RESET     (1<<6)
+
+#define SASR0_TNF       (1<<0)
+#define SASR0_RNE       (1<<1)
+#define SASR0_BSY       (1<<2)
+#define SASR0_TFS       (1<<3)
+#define SASR0_RFS       (1<<4)
+#define SASR0_TUR       (1<<5)
+#define SASR0_ROR       (1<<6)
+#define SASR0_L3WD      (1<<16)
+#define SASR0_L3RD      (1<<17)
+
+#define SASR1_TNF       (1<<0)
+#define SASR1_RNE       (1<<1)
+#define SASR1_BSY       (1<<2)
+#define SASR1_TFS       (1<<3)
+#define SASR1_RFS       (1<<4)
+#define SASR1_TUR       (1<<5)
+#define SASR1_ROR       (1<<6)
+#define SASR1_CADT      (1<<16)
+#define SASR1_SADR      (1<<17)
+#define SASR1_RSTO      (1<<18)
+#define SASR1_CLPM      (1<<19)
+#define SASR1_CRDY      (1<<20)
+#define SASR1_RS3V      (1<<21)
+#define SASR1_RS4V      (1<<22)
+
+#define SASCR_TUR       (1<<5)
+#define SASCR_ROR       (1<<6)
+#define SASCR_DTS       (1<<16)
+#define SASCR_RDD       (1<<17)
+#define SASCR_STO       (1<<18)
+
+#define SADTCS_TDEN     (1<<0)
+#define SADTCS_TDIE     (1<<1)
+#define SADTCS_TDBDA    (1<<3)
+#define SADTCS_TDSTA    (1<<4)
+#define SADTCS_TDBDB    (1<<5)
+#define SADTCS_TDSTB    (1<<6)
+#define SADTCS_TBIU     (1<<7)
+
+#define SADRCS_RDEN     (1<<0)
+#define SADRCS_RDIE     (1<<1)
+#define SADRCS_RDBDA    (1<<3)
+#define SADRCS_RDSTA    (1<<4)
+#define SADRCS_RDBDB    (1<<5)
+#define SADRCS_RDSTB    (1<<6)
+#define SADRCS_RBIU     (1<<7)
+
+#define SAD_CS_DEN      (1<<0)
+#define SAD_CS_DIE      (1<<1)  /* Not functional on metal 1 */
+#define SAD_CS_DBDA     (1<<3)  /* Not functional on metal 1 */
+#define SAD_CS_DSTA     (1<<4)
+#define SAD_CS_DBDB     (1<<5)  /* Not functional on metal 1 */
+#define SAD_CS_DSTB     (1<<6)
+#define SAD_CS_BIU      (1<<7)  /* Not functional on metal 1 */
+
+#define SAITR_TFS       (1<<0)
+#define SAITR_RFS       (1<<1)
+#define SAITR_TUR       (1<<2)
+#define SAITR_ROR       (1<<3)
+#define SAITR_CADT      (1<<4)
+#define SAITR_SADR      (1<<5)
+#define SAITR_RSTO      (1<<6)
+#define SAITR_TDBDA     (1<<8)
+#define SAITR_TDBDB     (1<<9)
+#define SAITR_RDBDA     (1<<10)
+#define SAITR_RDBDB     (1<<11)
+
+/*
+ * General-Purpose I/O Interface
+ *
+ * Registers
+ *    PA_DDR            GPIO Block A Data Direction
+ *    PA_DRR/PA_DWR     GPIO Block A Data Value Register (read/write)
+ *    PA_SDR            GPIO Block A Sleep Direction
+ *    PA_SSR            GPIO Block A Sleep State
+ *    PB_DDR            GPIO Block B Data Direction
+ *    PB_DRR/PB_DWR     GPIO Block B Data Value Register (read/write)
+ *    PB_SDR            GPIO Block B Sleep Direction
+ *    PB_SSR            GPIO Block B Sleep State
+ *    PC_DDR            GPIO Block C Data Direction
+ *    PC_DRR/PC_DWR     GPIO Block C Data Value Register (read/write)
+ *    PC_SDR            GPIO Block C Sleep Direction
+ *    PC_SSR            GPIO Block C Sleep State
+ */
+
+#define _PA_DDR         _SA1111( 0x1000 )
+#define _PA_DRR         _SA1111( 0x1004 )
+#define _PA_DWR         _SA1111( 0x1004 )
+#define _PA_SDR         _SA1111( 0x1008 )
+#define _PA_SSR         _SA1111( 0x100c )
+#define _PB_DDR         _SA1111( 0x1010 )
+#define _PB_DRR         _SA1111( 0x1014 )
+#define _PB_DWR         _SA1111( 0x1014 )
+#define _PB_SDR         _SA1111( 0x1018 )
+#define _PB_SSR         _SA1111( 0x101c )
+#define _PC_DDR         _SA1111( 0x1020 )
+#define _PC_DRR         _SA1111( 0x1024 )
+#define _PC_DWR         _SA1111( 0x1024 )
+#define _PC_SDR         _SA1111( 0x1028 )
+#define _PC_SSR         _SA1111( 0x102c )
+
+#define SA1111_GPIO     0x1000
+
+#define SA1111_GPIO_PADDR       (0x000)
+#define SA1111_GPIO_PADRR       (0x004)
+#define SA1111_GPIO_PADWR       (0x004)
+#define SA1111_GPIO_PASDR       (0x008)
+#define SA1111_GPIO_PASSR       (0x00c)
+#define SA1111_GPIO_PBDDR       (0x010)
+#define SA1111_GPIO_PBDRR       (0x014)
+#define SA1111_GPIO_PBDWR       (0x014)
+#define SA1111_GPIO_PBSDR       (0x018)
+#define SA1111_GPIO_PBSSR       (0x01c)
+#define SA1111_GPIO_PCDDR       (0x020)
+#define SA1111_GPIO_PCDRR       (0x024)
+#define SA1111_GPIO_PCDWR       (0x024)
+#define SA1111_GPIO_PCSDR       (0x028)
+#define SA1111_GPIO_PCSSR       (0x02c)
+
+#define GPIO_A0         (1 << 0)
+#define GPIO_A1         (1 << 1)
+#define GPIO_A2         (1 << 2)
+#define GPIO_A3         (1 << 3)
+
+#define GPIO_B0         (1 << 8)
+#define GPIO_B1         (1 << 9)
+#define GPIO_B2         (1 << 10)
+#define GPIO_B3         (1 << 11)
+#define GPIO_B4         (1 << 12)
+#define GPIO_B5         (1 << 13)
+#define GPIO_B6         (1 << 14)
+#define GPIO_B7         (1 << 15)
+
+#define GPIO_C0         (1 << 16)
+#define GPIO_C1         (1 << 17)
+#define GPIO_C2         (1 << 18)
+#define GPIO_C3         (1 << 19)
+#define GPIO_C4         (1 << 20)
+#define GPIO_C5         (1 << 21)
+#define GPIO_C6         (1 << 22)
+#define GPIO_C7         (1 << 23)
+
+/*
+ * Interrupt Controller
+ *
+ * Registers
+ *    INTTEST0          Test register 0
+ *    INTTEST1          Test register 1
+ *    INTEN0            Interrupt Enable register 0
+ *    INTEN1            Interrupt Enable register 1
+ *    INTPOL0           Interrupt Polarity selection 0
+ *    INTPOL1           Interrupt Polarity selection 1
+ *    INTTSTSEL         Interrupt source selection
+ *    INTSTATCLR0       Interrupt Status/Clear 0
+ *    INTSTATCLR1       Interrupt Status/Clear 1
+ *    INTSET0           Interrupt source set 0
+ *    INTSET1           Interrupt source set 1
+ *    WAKE_EN0          Wake-up source enable 0
+ *    WAKE_EN1          Wake-up source enable 1
+ *    WAKE_POL0         Wake-up polarity selection 0
+ *    WAKE_POL1         Wake-up polarity selection 1
+ */
+#define SA1111_INTC             0x1600
+
+/*
+ * These are offsets from the above base.
+ */
+#define SA1111_INTTEST0         0x0000
+#define SA1111_INTTEST1         0x0004
+#define SA1111_INTEN0           0x0008
+#define SA1111_INTEN1           0x000c
+#define SA1111_INTPOL0          0x0010
+#define SA1111_INTPOL1          0x0014
+#define SA1111_INTTSTSEL        0x0018
+#define SA1111_INTSTATCLR0      0x001c
+#define SA1111_INTSTATCLR1      0x0020
+#define SA1111_INTSET0          0x0024
+#define SA1111_INTSET1          0x0028
+#define SA1111_WAKEEN0          0x002c
+#define SA1111_WAKEEN1          0x0030
+#define SA1111_WAKEPOL0         0x0034
+#define SA1111_WAKEPOL1         0x0038
+
+/*
+ * PS/2 Trackpad and Mouse Interfaces
+ *
+ * Registers
+ *    PS2CR             Control Register
+ *    PS2STAT           Status Register
+ *    PS2DATA           Transmit/Receive Data register
+ *    PS2CLKDIV         Clock Division Register
+ *    PS2PRECNT         Clock Precount Register
+ *    PS2TEST1          Test register 1
+ *    PS2TEST2          Test register 2
+ *    PS2TEST3          Test register 3
+ *    PS2TEST4          Test register 4
+ */
+
+#define SA1111_KBD              0x0a00
+#define SA1111_MSE              0x0c00
+
+/*
+ * These are offsets from the above bases.
+ */
+#define SA1111_PS2CR            0x0000
+#define SA1111_PS2STAT          0x0004
+#define SA1111_PS2DATA          0x0008
+#define SA1111_PS2CLKDIV        0x000c
+#define SA1111_PS2PRECNT        0x0010
+
+#define PS2CR_ENA               0x08
+#define PS2CR_FKD               0x02
+#define PS2CR_FKC               0x01
+
+#define PS2STAT_STP             0x0100
+#define PS2STAT_TXE             0x0080
+#define PS2STAT_TXB             0x0040
+#define PS2STAT_RXF             0x0020
+#define PS2STAT_RXB             0x0010
+#define PS2STAT_ENA             0x0008
+#define PS2STAT_RXP             0x0004
+#define PS2STAT_KBD             0x0002
+#define PS2STAT_KBC             0x0001
+
+/*
+ * PCMCIA Interface
+ *
+ * Registers
+ *    PCSR      Status Register
+ *    PCCR      Control Register
+ *    PCSSR     Sleep State Register
+ */
+
+#define SA1111_PCMCIA   0x1600
+
+/*
+ * These are offsets from the above base.
+ */
+#define SA1111_PCCR     0x0000
+#define SA1111_PCSSR    0x0004
+#define SA1111_PCSR     0x0008
+
+#define PCSR_S0_READY   (1<<0)
+#define PCSR_S1_READY   (1<<1)
+#define PCSR_S0_DETECT  (1<<2)
+#define PCSR_S1_DETECT  (1<<3)
+#define PCSR_S0_VS1     (1<<4)
+#define PCSR_S0_VS2     (1<<5)
+#define PCSR_S1_VS1     (1<<6)
+#define PCSR_S1_VS2     (1<<7)
+#define PCSR_S0_WP      (1<<8)
+#define PCSR_S1_WP      (1<<9)
+#define PCSR_S0_BVD1    (1<<10)
+#define PCSR_S0_BVD2    (1<<11)
+#define PCSR_S1_BVD1    (1<<12)
+#define PCSR_S1_BVD2    (1<<13)
+
+#define PCCR_S0_RST     (1<<0)
+#define PCCR_S1_RST     (1<<1)
+#define PCCR_S0_FLT     (1<<2)
+#define PCCR_S1_FLT     (1<<3)
+#define PCCR_S0_PWAITEN (1<<4)
+#define PCCR_S1_PWAITEN (1<<5)
+#define PCCR_S0_PSE     (1<<6)
+#define PCCR_S1_PSE     (1<<7)
+
+#define PCSSR_S0_SLEEP  (1<<0)
+#define PCSSR_S1_SLEEP  (1<<1)
+
+
+
+
+extern struct bus_type sa1111_bus_type;
+
+#define SA1111_DEVID_SBI        0
+#define SA1111_DEVID_SK         1
+#define SA1111_DEVID_USB        2
+#define SA1111_DEVID_SAC        3
+#define SA1111_DEVID_SSP        4
+#define SA1111_DEVID_PS2        5
+#define SA1111_DEVID_GPIO       6
+#define SA1111_DEVID_INT        7
+#define SA1111_DEVID_PCMCIA     8
+
+struct sa1111_dev {
+        struct device   dev;
+        unsigned int    devid;
+        struct resource res;
+        void __iomem    *mapbase;
+        unsigned int    skpcr_mask;
+        unsigned int    irq[6];
+        u64             dma_mask;
+};
+
+#define SA1111_DEV(_d)  container_of((_d), struct sa1111_dev, dev)
+
+#define sa1111_get_drvdata(d)   dev_get_drvdata(&(d)->dev)
+#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
+
+struct sa1111_driver {
+        struct device_driver    drv;
+        unsigned int            devid;
+        int (*probe)(struct sa1111_dev *);
+        int (*remove)(struct sa1111_dev *);
+        int (*suspend)(struct sa1111_dev *, pm_message_t);
+        int (*resume)(struct sa1111_dev *);
+};
+
+#define SA1111_DRV(_d)  container_of((_d), struct sa1111_driver, drv)
+
+#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
+
+/*
+ * These frob the SKPCR register.
+ */
+void sa1111_enable_device(struct sa1111_dev *);
+void sa1111_disable_device(struct sa1111_dev *);
+
+unsigned int sa1111_pll_clock(struct sa1111_dev *);
+
+#define SA1111_AUDIO_ACLINK     0
+#define SA1111_AUDIO_I2S        1
+
+void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
+int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
+int sa1111_get_audio_rate(struct sa1111_dev *sadev);
+
+int sa1111_check_dma_bug(dma_addr_t addr);
+
+int sa1111_driver_register(struct sa1111_driver *);
+void sa1111_driver_unregister(struct sa1111_driver *);
+
+void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir);
+void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
+void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
+
+#endif  /* _ASM_ARCH_SA1111 */
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
new file mode 100644
index 000000000000..7ea771ff6144
--- /dev/null
+++ b/include/asm-arm/hardware/scoop.h
@@ -0,0 +1,47 @@
+/*
+ *  Definitions for the SCOOP interface found on various Sharp PDAs
+ *
+ *  Copyright (c) 2004 Richard Purdie
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ */
+
+#define SCOOP_MCR  0x00
+#define SCOOP_CDR  0x04
+#define SCOOP_CSR  0x08
+#define SCOOP_CPR  0x0C
+#define SCOOP_CCR  0x10
+#define SCOOP_IRR  0x14
+#define SCOOP_IRM  0x14
+#define SCOOP_IMR  0x18
+#define SCOOP_ISR  0x1C
+#define SCOOP_GPCR 0x20
+#define SCOOP_GPWR 0x24
+#define SCOOP_GPRR 0x28
+
+#define SCOOP_GPCR_PA22 ( 1 << 12 )
+#define SCOOP_GPCR_PA21 ( 1 << 11 )
+#define SCOOP_GPCR_PA20 ( 1 << 10 )
+#define SCOOP_GPCR_PA19 ( 1 << 9 )
+#define SCOOP_GPCR_PA18 ( 1 << 8 )
+#define SCOOP_GPCR_PA17 ( 1 << 7 )
+#define SCOOP_GPCR_PA16 ( 1 << 6 )
+#define SCOOP_GPCR_PA15 ( 1 << 5 )
+#define SCOOP_GPCR_PA14 ( 1 << 4 )
+#define SCOOP_GPCR_PA13 ( 1 << 3 )
+#define SCOOP_GPCR_PA12 ( 1 << 2 )
+#define SCOOP_GPCR_PA11 ( 1 << 1 )
+
+struct scoop_config {
+        unsigned short io_out;
+        unsigned short io_dir;
+};
+
+void reset_scoop(struct device *dev);
+unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
+unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
+void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
diff --git a/include/asm-arm/hardware/ssp.h b/include/asm-arm/hardware/ssp.h
new file mode 100644
index 000000000000..28aa11b769cd
--- /dev/null
+++ b/include/asm-arm/hardware/ssp.h
@@ -0,0 +1,28 @@
+/*
+ *  ssp.h
+ *
+ *  Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef SSP_H
+#define SSP_H
+
+struct ssp_state {
+        unsigned int    cr0;
+        unsigned int    cr1;
+};
+
+int ssp_write_word(u16 data);
+int ssp_read_word(void);
+void ssp_flush(void);
+void ssp_enable(void);
+void ssp_disable(void);
+void ssp_save_state(struct ssp_state *ssp);
+void ssp_restore_state(struct ssp_state *ssp);
+int ssp_init(void);
+void ssp_exit(void);
+
+#endif
diff --git a/include/asm-arm/hdreg.h b/include/asm-arm/hdreg.h
new file mode 100644
index 000000000000..7f7fd1af0af3
--- /dev/null
+++ b/include/asm-arm/hdreg.h
@@ -0,0 +1 @@
+#include <asm-generic/hdreg.h>
diff --git a/include/asm-arm/ide.h b/include/asm-arm/ide.h
new file mode 100644
index 000000000000..2114acb3d237
--- /dev/null
+++ b/include/asm-arm/ide.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/ide.h
+ *
+ *  Copyright (C) 1994-1996  Linus Torvalds & authors
+ */
+
+/*
+ *  This file contains the i386 architecture specific IDE code.
+ */
+
+#ifndef __ASMARM_IDE_H
+#define __ASMARM_IDE_H
+
+#ifdef __KERNEL__
+
+#ifndef MAX_HWIFS
+#define MAX_HWIFS       4
+#endif
+
+#if !defined(CONFIG_ARCH_L7200)
+# define IDE_ARCH_OBSOLETE_INIT
+# ifdef CONFIG_ARCH_CLPS7500
+#  define ide_default_io_ctl(base)      ((base) + 0x206) /* obsolete */
+# else
+#  define ide_default_io_ctl(base)      (0)
+# endif
+#endif /* !ARCH_L7200 */
+
+#define __ide_mm_insw(port,addr,len)    readsw(port,addr,len)
+#define __ide_mm_insl(port,addr,len)    readsl(port,addr,len)
+#define __ide_mm_outsw(port,addr,len)   writesw(port,addr,len)
+#define __ide_mm_outsl(port,addr,len)   writesl(port,addr,len)
+
+#endif /* __KERNEL__ */
+
+#endif /* __ASMARM_IDE_H */
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
new file mode 100644
index 000000000000..69bc7a3e8160
--- /dev/null
+++ b/include/asm-arm/io.h
@@ -0,0 +1,286 @@
+/*
+ *  linux/include/asm-arm/io.h
+ *
+ *  Copyright (C) 1996-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Modifications:
+ *  16-Sep-1996 RMK     Inlined the inx/outx functions & optimised for both
+ *                      constant addresses and variable addresses.
+ *  04-Dec-1997 RMK     Moved a lot of this stuff to the new architecture
+ *                      specific IO header files.
+ *  27-Mar-1999 PJB     Second parameter of memcpy_toio is const..
+ *  04-Apr-1999 PJB     Added check_signature.
+ *  12-Dec-1999 RMK     More cleanups
+ *  18-Jun-2000 RMK     Removed virt_to_* and friends definitions
+ *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
+ */
+#ifndef __ASM_ARM_IO_H
+#define __ASM_ARM_IO_H
+
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+#include <asm/byteorder.h>
+#include <asm/memory.h>
+#include <asm/arch/hardware.h>
+
+/*
+ * ISA I/O bus memory addresses are 1:1 with the physical address.
+ */
+#define isa_virt_to_bus virt_to_phys
+#define isa_page_to_bus page_to_phys
+#define isa_bus_to_virt phys_to_virt
+
+/*
+ * Generic IO read/write.  These perform native-endian accesses.  Note
+ * that some architectures will want to re-define __raw_{read,write}w.
+ */
+extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
+extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
+extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
+
+extern void __raw_readsb(void __iomem *addr, void *data, int bytelen);
+extern void __raw_readsw(void __iomem *addr, void *data, int wordlen);
+extern void __raw_readsl(void __iomem *addr, void *data, int longlen);
+
+#define __raw_writeb(v,a)       (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v))
+#define __raw_writew(v,a)       (__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
+#define __raw_writel(v,a)       (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v))
+
+#define __raw_readb(a)          (__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
+#define __raw_readw(a)          (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
+#define __raw_readl(a)          (__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))
+
+/*
+ * Bad read/write accesses...
+ */
+extern void __readwrite_bug(const char *fn);
+
+/*
+ * Now, pick up the machine-defined IO definitions
+ */
+#include <asm/arch/io.h>
+
+#ifdef __io_pci
+#warning machine class uses buggy __io_pci
+#endif
+#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
+    defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
+#warning machine class uses old __arch_putw or __arch_getw
+#endif
+
+/*
+ *  IO port access primitives
+ *  -------------------------
+ *
+ * The ARM doesn't have special IO access instructions; all IO is memory
+ * mapped.  Note that these are defined to perform little endian accesses
+ * only.  Their primary purpose is to access PCI and ISA peripherals.
+ *
+ * Note that for a big endian machine, this implies that the following
+ * big endian mode connectivity is in place, as described by numerious
+ * ARM documents:
+ *
+ *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
+ *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
+ *
+ * The machine specific io.h include defines __io to translate an "IO"
+ * address to a memory address.
+ *
+ * Note that we prevent GCC re-ordering or caching values in expressions
+ * by introducing sequence points into the in*() definitions.  Note that
+ * __raw_* do not guarantee this behaviour.
+ *
+ * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
+ */
+#ifdef __io
+#define outb(v,p)               __raw_writeb(v,__io(p))
+#define outw(v,p)               __raw_writew(cpu_to_le16(v),__io(p))
+#define outl(v,p)               __raw_writel(cpu_to_le32(v),__io(p))
+
+#define inb(p)  ({ unsigned int __v = __raw_readb(__io(p)); __v; })
+#define inw(p)  ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
+#define inl(p)  ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
+
+#define outsb(p,d,l)            __raw_writesb(__io(p),d,l)
+#define outsw(p,d,l)            __raw_writesw(__io(p),d,l)
+#define outsl(p,d,l)            __raw_writesl(__io(p),d,l)
+
+#define insb(p,d,l)             __raw_readsb(__io(p),d,l)
+#define insw(p,d,l)             __raw_readsw(__io(p),d,l)
+#define insl(p,d,l)             __raw_readsl(__io(p),d,l)
+#endif
+
+#define outb_p(val,port)        outb((val),(port))
+#define outw_p(val,port)        outw((val),(port))
+#define outl_p(val,port)        outl((val),(port))
+#define inb_p(port)             inb((port))
+#define inw_p(port)             inw((port))
+#define inl_p(port)             inl((port))
+
+#define outsb_p(port,from,len)  outsb(port,from,len)
+#define outsw_p(port,from,len)  outsw(port,from,len)
+#define outsl_p(port,from,len)  outsl(port,from,len)
+#define insb_p(port,to,len)     insb(port,to,len)
+#define insw_p(port,to,len)     insw(port,to,len)
+#define insl_p(port,to,len)     insl(port,to,len)
+
+/*
+ * String version of IO memory access ops:
+ */
+extern void _memcpy_fromio(void *, void __iomem *, size_t);
+extern void _memcpy_toio(void __iomem *, const void *, size_t);
+extern void _memset_io(void __iomem *, int, size_t);
+
+#define mmiowb()
+
+/*
+ *  Memory access primitives
+ *  ------------------------
+ *
+ * These perform PCI memory accesses via an ioremap region.  They don't
+ * take an address as such, but a cookie.
+ *
+ * Again, this are defined to perform little endian accesses.  See the
+ * IO port primitives for more information.
+ */
+#ifdef __mem_pci
+#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
+#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
+#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
+#define readb_relaxed(addr) readb(addr)
+#define readw_relaxed(addr) readw(addr)
+#define readl_relaxed(addr) readl(addr)
+
+#define readsb(p,d,l)           __raw_readsb(__mem_pci(p),d,l)
+#define readsw(p,d,l)           __raw_readsw(__mem_pci(p),d,l)
+#define readsl(p,d,l)           __raw_readsl(__mem_pci(p),d,l)
+
+#define writeb(v,c)             __raw_writeb(v,__mem_pci(c))
+#define writew(v,c)             __raw_writew(cpu_to_le16(v),__mem_pci(c))
+#define writel(v,c)             __raw_writel(cpu_to_le32(v),__mem_pci(c))
+
+#define writesb(p,d,l)          __raw_writesb(__mem_pci(p),d,l)
+#define writesw(p,d,l)          __raw_writesw(__mem_pci(p),d,l)
+#define writesl(p,d,l)          __raw_writesl(__mem_pci(p),d,l)
+
+#define memset_io(c,v,l)        _memset_io(__mem_pci(c),(v),(l))
+#define memcpy_fromio(a,c,l)    _memcpy_fromio((a),__mem_pci(c),(l))
+#define memcpy_toio(c,a,l)      _memcpy_toio(__mem_pci(c),(a),(l))
+
+#define eth_io_copy_and_sum(s,c,l,b) \
+                                eth_copy_and_sum((s),__mem_pci(c),(l),(b))
+
+static inline int
+check_signature(void __iomem *io_addr, const unsigned char *signature,
+                int length)
+{
+        int retval = 0;
+        do {
+                if (readb(io_addr) != *signature)
+                        goto out;
+                io_addr++;
+                signature++;
+                length--;
+        } while (length);
+        retval = 1;
+out:
+        return retval;
+}
+
+#elif !defined(readb)
+
+#define readb(c)                        (__readwrite_bug("readb"),0)
+#define readw(c)                        (__readwrite_bug("readw"),0)
+#define readl(c)                        (__readwrite_bug("readl"),0)
+#define writeb(v,c)                     __readwrite_bug("writeb")
+#define writew(v,c)                     __readwrite_bug("writew")
+#define writel(v,c)                     __readwrite_bug("writel")
+
+#define eth_io_copy_and_sum(s,c,l,b)    __readwrite_bug("eth_io_copy_and_sum")
+
+#define check_signature(io,sig,len)     (0)
+
+#endif  /* __mem_pci */
+
+/*
+ * If this architecture has ISA IO, then define the isa_read/isa_write
+ * macros.
+ */
+#ifdef __mem_isa
+
+#define isa_readb(addr)                 __raw_readb(__mem_isa(addr))
+#define isa_readw(addr)                 __raw_readw(__mem_isa(addr))
+#define isa_readl(addr)                 __raw_readl(__mem_isa(addr))
+#define isa_writeb(val,addr)            __raw_writeb(val,__mem_isa(addr))
+#define isa_writew(val,addr)            __raw_writew(val,__mem_isa(addr))
+#define isa_writel(val,addr)            __raw_writel(val,__mem_isa(addr))
+#define isa_memset_io(a,b,c)            _memset_io(__mem_isa(a),(b),(c))
+#define isa_memcpy_fromio(a,b,c)        _memcpy_fromio((a),__mem_isa(b),(c))
+#define isa_memcpy_toio(a,b,c)          _memcpy_toio(__mem_isa((a)),(b),(c))
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+                                eth_copy_and_sum((a),__mem_isa(b),(c),(d))
+
+#else   /* __mem_isa */
+
+#define isa_readb(addr)                 (__readwrite_bug("isa_readb"),0)
+#define isa_readw(addr)                 (__readwrite_bug("isa_readw"),0)
+#define isa_readl(addr)                 (__readwrite_bug("isa_readl"),0)
+#define isa_writeb(val,addr)            __readwrite_bug("isa_writeb")
+#define isa_writew(val,addr)            __readwrite_bug("isa_writew")
+#define isa_writel(val,addr)            __readwrite_bug("isa_writel")
+#define isa_memset_io(a,b,c)            __readwrite_bug("isa_memset_io")
+#define isa_memcpy_fromio(a,b,c)        __readwrite_bug("isa_memcpy_fromio")
+#define isa_memcpy_toio(a,b,c)          __readwrite_bug("isa_memcpy_toio")
+
+#define isa_eth_io_copy_and_sum(a,b,c,d) \
+                                __readwrite_bug("isa_eth_io_copy_and_sum")
+
+#endif  /* __mem_isa */
+
+/*
+ * ioremap and friends.
+ *
+ * ioremap takes a PCI memory address, as specified in
+ * Documentation/IO-mapping.txt.
+ */
+extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
+extern void __iounmap(void __iomem *addr);
+
+#ifndef __arch_ioremap
+#define ioremap(cookie,size)            __ioremap(cookie,size,0,1)
+#define ioremap_nocache(cookie,size)    __ioremap(cookie,size,0,1)
+#define ioremap_cached(cookie,size)     __ioremap(cookie,size,L_PTE_CACHEABLE,1)
+#define iounmap(cookie)                 __iounmap(cookie)
+#else
+#define ioremap(cookie,size)            __arch_ioremap((cookie),(size),0,1)
+#define ioremap_nocache(cookie,size)    __arch_ioremap((cookie),(size),0,1)
+#define ioremap_cached(cookie,size)     __arch_ioremap((cookie),(size),L_PTE_CACHEABLE,1)
+#define iounmap(cookie)                 __arch_iounmap(cookie)
+#endif
+
+/*
+ * can the hardware map this into one segment or not, given no other
+ * constraints.
+ */
+#define BIOVEC_MERGEABLE(vec1, vec2)    \
+        ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif  /* __KERNEL__ */
+#endif  /* __ASM_ARM_IO_H */
diff --git a/include/asm-arm/ioctl.h b/include/asm-arm/ioctl.h
new file mode 100644
index 000000000000..2cbb7d0e9dc6
--- /dev/null
+++ b/include/asm-arm/ioctl.h
@@ -0,0 +1,74 @@
+/*
+ * linux/ioctl.h for Linux by H.H. Bergman.
+ */
+
+#ifndef _ASMARM_IOCTL_H
+#define _ASMARM_IOCTL_H
+
+/* ioctl command encoding: 32 bits total, command in lower 16 bits,
+ * size of the parameter structure in the lower 14 bits of the
+ * upper 16 bits.
+ * Encoding the size of the parameter structure in the ioctl request
+ * is useful for catching programs compiled with old versions
+ * and to avoid overwriting user space outside the user buffer area.
+ * The highest 2 bits are reserved for indicating the ``access mode''.
+ * NOTE: This limits the max parameter size to 16kB -1 !
+ */
+
+/*
+ * The following is for compatibility across the various Linux
+ * platforms.  The i386 ioctl numbering scheme doesn't really enforce
+ * a type field.  De facto, however, the top 8 bits of the lower 16
+ * bits are indeed used as a type field, so we might just as well make
+ * this explicit here.  Please be sure to use the decoding macros
+ * below from now on.
+ */
+#define _IOC_NRBITS     8
+#define _IOC_TYPEBITS   8
+#define _IOC_SIZEBITS   14
+#define _IOC_DIRBITS    2
+
+#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
+#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
+#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
+#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
+
+#define _IOC_NRSHIFT    0
+#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
+#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
+#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
+
+/*
+ * Direction bits.
+ */
+#define _IOC_NONE       0U
+#define _IOC_WRITE      1U
+#define _IOC_READ       2U
+
+#define _IOC(dir,type,nr,size) \
+        (((dir)  << _IOC_DIRSHIFT) | \
+         ((type) << _IOC_TYPESHIFT) | \
+         ((nr)   << _IOC_NRSHIFT) | \
+         ((size) << _IOC_SIZESHIFT))
+
+/* used to create numbers */
+#define _IO(type,nr)            _IOC(_IOC_NONE,(type),(nr),0)
+#define _IOR(type,nr,size)      _IOC(_IOC_READ,(type),(nr),sizeof(size))
+#define _IOW(type,nr,size)      _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
+#define _IOWR(type,nr,size)     _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
+
+/* used to decode ioctl numbers.. */
+#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
+#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
+#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
+#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
+
+/* ...and for the drivers/sound files... */
+
+#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
+#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
+#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
+#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
+#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
+
+#endif /* _ASMARM_IOCTL_H */
diff --git a/include/asm-arm/ioctls.h b/include/asm-arm/ioctls.h
new file mode 100644
index 000000000000..bb9a7aa10c12
--- /dev/null
+++ b/include/asm-arm/ioctls.h
@@ -0,0 +1,80 @@
+#ifndef __ASM_ARM_IOCTLS_H
+#define __ASM_ARM_IOCTLS_H
+
+#include <asm/ioctl.h>
+
+/* 0x54 is just a magic number to make these relatively unique ('T') */
+
+#define TCGETS          0x5401
+#define TCSETS          0x5402
+#define TCSETSW         0x5403
+#define TCSETSF         0x5404
+#define TCGETA          0x5405
+#define TCSETA          0x5406
+#define TCSETAW         0x5407
+#define TCSETAF         0x5408
+#define TCSBRK          0x5409
+#define TCXONC          0x540A
+#define TCFLSH          0x540B
+#define TIOCEXCL        0x540C
+#define TIOCNXCL        0x540D
+#define TIOCSCTTY       0x540E
+#define TIOCGPGRP       0x540F
+#define TIOCSPGRP       0x5410
+#define TIOCOUTQ        0x5411
+#define TIOCSTI         0x5412
+#define TIOCGWINSZ      0x5413
+#define TIOCSWINSZ      0x5414
+#define TIOCMGET        0x5415
+#define TIOCMBIS        0x5416
+#define TIOCMBIC        0x5417
+#define TIOCMSET        0x5418
+#define TIOCGSOFTCAR    0x5419
+#define TIOCSSOFTCAR    0x541A
+#define FIONREAD        0x541B
+#define TIOCINQ         FIONREAD
+#define TIOCLINUX       0x541C
+#define TIOCCONS        0x541D
+#define TIOCGSERIAL     0x541E
+#define TIOCSSERIAL     0x541F
+#define TIOCPKT         0x5420
+#define FIONBIO         0x5421
+#define TIOCNOTTY       0x5422
+#define TIOCSETD        0x5423
+#define TIOCGETD        0x5424
+#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
+
+#define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
+#define FIOCLEX         0x5451
+#define FIOASYNC        0x5452
+#define TIOCSERCONFIG   0x5453
+#define TIOCSERGWILD    0x5454
+#define TIOCSERSWILD    0x5455
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458 /* For debugging only */
+#define TIOCSERGETLSR   0x5459 /* Get line status register */
+#define TIOCSERGETMULTI 0x545A /* Get multiport config  */
+#define TIOCSERSETMULTI 0x545B /* Set multiport config */
+
+#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+#define FIOQSIZE        0x545E
+
+/* Used for packet mode */
+#define TIOCPKT_DATA             0
+#define TIOCPKT_FLUSHREAD        1
+#define TIOCPKT_FLUSHWRITE       2
+#define TIOCPKT_STOP             4
+#define TIOCPKT_START            8
+#define TIOCPKT_NOSTOP          16
+#define TIOCPKT_DOSTOP          32
+
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+#endif
diff --git a/include/asm-arm/ipc.h b/include/asm-arm/ipc.h
new file mode 100644
index 000000000000..a46e3d9c2a3f
--- /dev/null
+++ b/include/asm-arm/ipc.h
@@ -0,0 +1 @@
+#include <asm-generic/ipc.h>
diff --git a/include/asm-arm/ipcbuf.h b/include/asm-arm/ipcbuf.h
new file mode 100644
index 000000000000..97683975f7df
--- /dev/null
+++ b/include/asm-arm/ipcbuf.h
@@ -0,0 +1,29 @@
+#ifndef __ASMARM_IPCBUF_H
+#define __ASMARM_IPCBUF_H
+
+/*
+ * The ipc64_perm structure for arm architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct ipc64_perm
+{
+        __kernel_key_t          key;
+        __kernel_uid32_t        uid;
+        __kernel_gid32_t        gid;
+        __kernel_uid32_t        cuid;
+        __kernel_gid32_t        cgid;
+        __kernel_mode_t         mode;
+        unsigned short          __pad1;
+        unsigned short          seq;
+        unsigned short          __pad2;
+        unsigned long           __unused1;
+        unsigned long           __unused2;
+};
+
+#endif /* __ASMARM_IPCBUF_H */
diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h
new file mode 100644
index 000000000000..f97912fbb10f
--- /dev/null
+++ b/include/asm-arm/irq.h
@@ -0,0 +1,51 @@
+#ifndef __ASM_ARM_IRQ_H
+#define __ASM_ARM_IRQ_H
+
+#include <asm/arch/irqs.h>
+
+#ifndef irq_canonicalize
+#define irq_canonicalize(i)     (i)
+#endif
+
+#ifndef NR_IRQS
+#define NR_IRQS 128
+#endif
+
+/*
+ * Use this value to indicate lack of interrupt
+ * capability
+ */
+#ifndef NO_IRQ
+#define NO_IRQ  ((unsigned int)(-1))
+#endif
+
+struct irqaction;
+
+extern void disable_irq_nosync(unsigned int);
+extern void disable_irq(unsigned int);
+extern void enable_irq(unsigned int);
+
+#define __IRQT_FALEDGE  (1 << 0)
+#define __IRQT_RISEDGE  (1 << 1)
+#define __IRQT_LOWLVL   (1 << 2)
+#define __IRQT_HIGHLVL  (1 << 3)
+
+#define IRQT_NOEDGE     (0)
+#define IRQT_RISING     (__IRQT_RISEDGE)
+#define IRQT_FALLING    (__IRQT_FALEDGE)
+#define IRQT_BOTHEDGE   (__IRQT_RISEDGE|__IRQT_FALEDGE)
+#define IRQT_LOW        (__IRQT_LOWLVL)
+#define IRQT_HIGH       (__IRQT_HIGHLVL)
+#define IRQT_PROBE      (1 << 4)
+
+int set_irq_type(unsigned int irq, unsigned int type);
+void disable_irq_wake(unsigned int irq);
+void enable_irq_wake(unsigned int irq);
+int setup_irq(unsigned int, struct irqaction *);
+
+struct irqaction;
+struct pt_regs;
+int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
+
+#endif
+
diff --git a/include/asm-arm/kmap_types.h b/include/asm-arm/kmap_types.h
new file mode 100644
index 000000000000..45def13ee17a
--- /dev/null
+++ b/include/asm-arm/kmap_types.h
@@ -0,0 +1,24 @@
+#ifndef __ARM_KMAP_TYPES_H
+#define __ARM_KMAP_TYPES_H
+
+/*
+ * This is the "bare minimum".  AIO seems to require this.
+ */
+enum km_type {
+        KM_BOUNCE_READ,
+        KM_SKB_SUNRPC_DATA,
+        KM_SKB_DATA_SOFTIRQ,
+        KM_USER0,
+        KM_USER1,
+        KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
+        KM_IRQ0,
+        KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
+        KM_TYPE_NR
+};
+
+#endif
diff --git a/include/asm-arm/leds.h b/include/asm-arm/leds.h
new file mode 100644
index 000000000000..88ce4124f854
--- /dev/null
+++ b/include/asm-arm/leds.h
@@ -0,0 +1,51 @@
+/*
+ *  linux/include/asm-arm/leds.h
+ *
+ *  Copyright (C) 1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Event-driven interface for LEDs on machines
+ *  Added led_start and led_stop- Alex Holden, 28th Dec 1998.
+ */
+#ifndef ASM_ARM_LEDS_H
+#define ASM_ARM_LEDS_H
+
+#include <linux/config.h>
+
+typedef enum {
+        led_idle_start,
+        led_idle_end,
+        led_timer,
+        led_start,
+        led_stop,
+        led_claim,              /* override idle & timer leds */
+        led_release,            /* restore idle & timer leds */
+        led_start_timer_mode,
+        led_stop_timer_mode,
+        led_green_on,
+        led_green_off,
+        led_amber_on,
+        led_amber_off,
+        led_red_on,
+        led_red_off,
+        led_blue_on,
+        led_blue_off,
+        /*
+         * I want this between led_timer and led_start, but
+         * someone has decided to export this to user space
+         */
+        led_halted
+} led_event_t;
+
+/* Use this routine to handle LEDs */
+
+#ifdef CONFIG_LEDS
+extern void (*leds_event)(led_event_t);
+#else
+#define leds_event(e)
+#endif
+
+#endif
diff --git a/include/asm-arm/limits.h b/include/asm-arm/limits.h
new file mode 100644
index 000000000000..08d8c6600804
--- /dev/null
+++ b/include/asm-arm/limits.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_PIPE_H
+#define __ASM_PIPE_H
+
+#ifndef PAGE_SIZE
+#include <asm/page.h>
+#endif
+
+#define PIPE_BUF        PAGE_SIZE
+
+#endif
+
diff --git a/include/asm-arm/linkage.h b/include/asm-arm/linkage.h
new file mode 100644
index 000000000000..dbe4b4e31a5b
--- /dev/null
+++ b/include/asm-arm/linkage.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .align 0
+#define __ALIGN_STR ".align 0"
+
+#endif
diff --git a/include/asm-arm/local.h b/include/asm-arm/local.h
new file mode 100644
index 000000000000..c11c530f74d0
--- /dev/null
+++ b/include/asm-arm/local.h
@@ -0,0 +1 @@
+#include <asm-generic/local.h>
diff --git a/include/asm-arm/locks.h b/include/asm-arm/locks.h
new file mode 100644
index 000000000000..c26298f3891f
--- /dev/null
+++ b/include/asm-arm/locks.h
@@ -0,0 +1,262 @@
+/*
+ *  linux/include/asm-arm/locks.h
+ *
+ *  Copyright (C) 2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Interrupt safe locking assembler. 
+ */
+#ifndef __ASM_PROC_LOCKS_H
+#define __ASM_PROC_LOCKS_H
+
+#if __LINUX_ARM_ARCH__ >= 6
+
+#define __down_op(ptr,fail)                     \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ down_op\n"                           \
+"1:     ldrex   lr, [%0]\n"                     \
+"       sub     lr, lr, %1\n"                   \
+"       strex   ip, lr, [%0]\n"                 \
+"       teq     ip, #0\n"                       \
+"       bne     1b\n"                           \
+"       teq     lr, #0\n"                       \
+"       movmi   ip, %0\n"                       \
+"       blmi    " #fail                         \
+        :                                       \
+        : "r" (ptr), "I" (1)                    \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+#define __down_op_ret(ptr,fail)                 \
+        ({                                      \
+                unsigned int ret;               \
+        __asm__ __volatile__(                   \
+        "@ down_op_ret\n"                       \
+"1:     ldrex   lr, [%1]\n"                     \
+"       sub     lr, lr, %2\n"                   \
+"       strex   ip, lr, [%1]\n"                 \
+"       teq     ip, #0\n"                       \
+"       bne     1b\n"                           \
+"       teq     lr, #0\n"                       \
+"       movmi   ip, %1\n"                       \
+"       movpl   ip, #0\n"                       \
+"       blmi    " #fail "\n"                    \
+"       mov     %0, ip"                         \
+        : "=&r" (ret)                           \
+        : "r" (ptr), "I" (1)                    \
+        : "ip", "lr", "cc", "memory");          \
+        ret;                                    \
+        })
+
+#define __up_op(ptr,wake)                       \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ up_op\n"                             \
+"1:     ldrex   lr, [%0]\n"                     \
+"       add     lr, lr, %1\n"                   \
+"       strex   ip, lr, [%0]\n"                 \
+"       teq     ip, #0\n"                       \
+"       bne     1b\n"                           \
+"       teq     lr, #0\n"                       \
+"       movle   ip, %0\n"                       \
+"       blle    " #wake                         \
+        :                                       \
+        : "r" (ptr), "I" (1)                    \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+/*
+ * The value 0x01000000 supports up to 128 processors and
+ * lots of processes.  BIAS must be chosen such that sub'ing
+ * BIAS once per CPU will result in the long remaining
+ * negative.
+ */
+#define RW_LOCK_BIAS      0x01000000
+#define RW_LOCK_BIAS_STR "0x01000000"
+
+#define __down_op_write(ptr,fail)               \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ down_op_write\n"                     \
+"1:     ldrex   lr, [%0]\n"                     \
+"       sub     lr, lr, %1\n"                   \
+"       strex   ip, lr, [%0]\n"                 \
+"       teq     ip, #0\n"                       \
+"       bne     1b\n"                           \
+"       teq     lr, #0\n"                       \
+"       movne   ip, %0\n"                       \
+"       blne    " #fail                         \
+        :                                       \
+        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+#define __up_op_write(ptr,wake)                 \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ up_op_read\n"                        \
+"1:     ldrex   lr, [%0]\n"                     \
+"       add     lr, lr, %1\n"                   \
+"       strex   ip, lr, [%0]\n"                 \
+"       teq     ip, #0\n"                       \
+"       bne     1b\n"                           \
+"       movcs   ip, %0\n"                       \
+"       blcs    " #wake                         \
+        :                                       \
+        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+#define __down_op_read(ptr,fail)                \
+        __down_op(ptr, fail)
+
+#define __up_op_read(ptr,wake)                  \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ up_op_read\n"                        \
+"1:     ldrex   lr, [%0]\n"                     \
+"       add     lr, lr, %1\n"                   \
+"       strex   ip, lr, [%0]\n"                 \
+"       teq     ip, #0\n"                       \
+"       bne     1b\n"                           \
+"       teq     lr, #0\n"                       \
+"       moveq   ip, %0\n"                       \
+"       bleq    " #wake                         \
+        :                                       \
+        : "r" (ptr), "I" (1)                    \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+#else
+
+#define __down_op(ptr,fail)                     \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ down_op\n"                           \
+"       mrs     ip, cpsr\n"                     \
+"       orr     lr, ip, #128\n"                 \
+"       msr     cpsr_c, lr\n"                   \
+"       ldr     lr, [%0]\n"                     \
+"       subs    lr, lr, %1\n"                   \
+"       str     lr, [%0]\n"                     \
+"       msr     cpsr_c, ip\n"                   \
+"       movmi   ip, %0\n"                       \
+"       blmi    " #fail                         \
+        :                                       \
+        : "r" (ptr), "I" (1)                    \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+#define __down_op_ret(ptr,fail)                 \
+        ({                                      \
+                unsigned int ret;               \
+        __asm__ __volatile__(                   \
+        "@ down_op_ret\n"                       \
+"       mrs     ip, cpsr\n"                     \
+"       orr     lr, ip, #128\n"                 \
+"       msr     cpsr_c, lr\n"                   \
+"       ldr     lr, [%1]\n"                     \
+"       subs    lr, lr, %2\n"                   \
+"       str     lr, [%1]\n"                     \
+"       msr     cpsr_c, ip\n"                   \
+"       movmi   ip, %1\n"                       \
+"       movpl   ip, #0\n"                       \
+"       blmi    " #fail "\n"                    \
+"       mov     %0, ip"                         \
+        : "=&r" (ret)                           \
+        : "r" (ptr), "I" (1)                    \
+        : "ip", "lr", "cc", "memory");          \
+        ret;                                    \
+        })
+
+#define __up_op(ptr,wake)                       \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ up_op\n"                             \
+"       mrs     ip, cpsr\n"                     \
+"       orr     lr, ip, #128\n"                 \
+"       msr     cpsr_c, lr\n"                   \
+"       ldr     lr, [%0]\n"                     \
+"       adds    lr, lr, %1\n"                   \
+"       str     lr, [%0]\n"                     \
+"       msr     cpsr_c, ip\n"                   \
+"       movle   ip, %0\n"                       \
+"       blle    " #wake                         \
+        :                                       \
+        : "r" (ptr), "I" (1)                    \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+/*
+ * The value 0x01000000 supports up to 128 processors and
+ * lots of processes.  BIAS must be chosen such that sub'ing
+ * BIAS once per CPU will result in the long remaining
+ * negative.
+ */
+#define RW_LOCK_BIAS      0x01000000
+#define RW_LOCK_BIAS_STR "0x01000000"
+
+#define __down_op_write(ptr,fail)               \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ down_op_write\n"                     \
+"       mrs     ip, cpsr\n"                     \
+"       orr     lr, ip, #128\n"                 \
+"       msr     cpsr_c, lr\n"                   \
+"       ldr     lr, [%0]\n"                     \
+"       subs    lr, lr, %1\n"                   \
+"       str     lr, [%0]\n"                     \
+"       msr     cpsr_c, ip\n"                   \
+"       movne   ip, %0\n"                       \
+"       blne    " #fail                         \
+        :                                       \
+        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+#define __up_op_write(ptr,wake)                 \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ up_op_read\n"                        \
+"       mrs     ip, cpsr\n"                     \
+"       orr     lr, ip, #128\n"                 \
+"       msr     cpsr_c, lr\n"                   \
+"       ldr     lr, [%0]\n"                     \
+"       adds    lr, lr, %1\n"                   \
+"       str     lr, [%0]\n"                     \
+"       msr     cpsr_c, ip\n"                   \
+"       movcs   ip, %0\n"                       \
+"       blcs    " #wake                         \
+        :                                       \
+        : "r" (ptr), "I" (RW_LOCK_BIAS)         \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+#define __down_op_read(ptr,fail)                \
+        __down_op(ptr, fail)
+
+#define __up_op_read(ptr,wake)                  \
+        ({                                      \
+        __asm__ __volatile__(                   \
+        "@ up_op_read\n"                        \
+"       mrs     ip, cpsr\n"                     \
+"       orr     lr, ip, #128\n"                 \
+"       msr     cpsr_c, lr\n"                   \
+"       ldr     lr, [%0]\n"                     \
+"       adds    lr, lr, %1\n"                   \
+"       str     lr, [%0]\n"                     \
+"       msr     cpsr_c, ip\n"                   \
+"       moveq   ip, %0\n"                       \
+"       bleq    " #wake                         \
+        :                                       \
+        : "r" (ptr), "I" (1)                    \
+        : "ip", "lr", "cc", "memory");          \
+        })
+
+#endif
+
+#endif
diff --git a/include/asm-arm/mach/arch.h b/include/asm-arm/mach/arch.h
new file mode 100644
index 000000000000..3a32e929ec8c
--- /dev/null
+++ b/include/asm-arm/mach/arch.h
@@ -0,0 +1,92 @@
+/*
+ *  linux/include/asm-arm/mach/arch.h
+ *
+ *  Copyright (C) 2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASSEMBLY__
+
+struct tag;
+struct meminfo;
+struct sys_timer;
+
+struct machine_desc {
+        /*
+         * Note! The first five elements are used
+         * by assembler code in head-armv.S
+         */
+        unsigned int            nr;             /* architecture number  */
+        unsigned int            phys_ram;       /* start of physical ram */
+        unsigned int            phys_io;        /* start of physical io */
+        unsigned int            io_pg_offst;    /* byte offset for io 
+                                                 * page tabe entry      */
+
+        const char              *name;          /* architecture name    */
+        unsigned int            param_offset;   /* parameter page       */
+
+        unsigned int            video_start;    /* start of video RAM   */
+        unsigned int            video_end;      /* end of video RAM     */
+
+        unsigned int            reserve_lp0 :1; /* never has lp0        */
+        unsigned int            reserve_lp1 :1; /* never has lp1        */
+        unsigned int            reserve_lp2 :1; /* never has lp2        */
+        unsigned int            soft_reboot :1; /* soft reboot          */
+        void                    (*fixup)(struct machine_desc *,
+                                         struct tag *, char **,
+                                         struct meminfo *);
+        void                    (*map_io)(void);/* IO mapping function  */
+        void                    (*init_irq)(void);
+        struct sys_timer        *timer;         /* system tick timer    */
+        void                    (*init_machine)(void);
+};
+
+/*
+ * Set of macros to define architecture features.  This is built into
+ * a table by the linker.
+ */
+#define MACHINE_START(_type,_name)              \
+const struct machine_desc __mach_desc_##_type   \
+ __attribute__((__section__(".arch.info"))) = { \
+        .nr             = MACH_TYPE_##_type,    \
+        .name           = _name,
+
+#define MAINTAINER(n)
+
+#define BOOT_MEM(_pram,_pio,_vio)               \
+        .phys_ram       = _pram,                \
+        .phys_io        = _pio,                 \
+        .io_pg_offst    = ((_vio)>>18)&0xfffc,
+
+#define BOOT_PARAMS(_params)                    \
+        .param_offset   = _params,
+
+#define VIDEO(_start,_end)                      \
+        .video_start    = _start,               \
+        .video_end      = _end,
+
+#define DISABLE_PARPORT(_n)                     \
+        .reserve_lp##_n = 1,
+
+#define SOFT_REBOOT                             \
+        .soft_reboot    = 1,
+
+#define FIXUP(_func)                            \
+        .fixup          = _func,
+
+#define MAPIO(_func)                            \
+        .map_io         = _func,
+
+#define INITIRQ(_func)                          \
+        .init_irq       = _func,
+
+#define INIT_MACHINE(_func)                     \
+        .init_machine   = _func,
+
+#define MACHINE_END                             \
+};
+
+#endif
diff --git a/include/asm-arm/mach/dma.h b/include/asm-arm/mach/dma.h
new file mode 100644
index 000000000000..31bf716106ee
--- /dev/null
+++ b/include/asm-arm/mach/dma.h
@@ -0,0 +1,55 @@
+/*
+ *  linux/include/asm-arm/mach/dma.h
+ *
+ *  Copyright (C) 1998-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  This header file describes the interface between the generic DMA handler
+ *  (dma.c) and the architecture-specific DMA backends (dma-*.c)
+ */
+
+struct dma_struct;
+typedef struct dma_struct dma_t;
+
+struct dma_ops {
+        int     (*request)(dmach_t, dma_t *);           /* optional */
+        void    (*free)(dmach_t, dma_t *);              /* optional */
+        void    (*enable)(dmach_t, dma_t *);            /* mandatory */
+        void    (*disable)(dmach_t, dma_t *);           /* mandatory */
+        int     (*residue)(dmach_t, dma_t *);           /* optional */
+        int     (*setspeed)(dmach_t, dma_t *, int);     /* optional */
+        char    *type;
+};
+
+struct dma_struct {
+        struct scatterlist buf;         /* single DMA                   */
+        int             sgcount;        /* number of DMA SG             */
+        struct scatterlist *sg;         /* DMA Scatter-Gather List      */
+
+        unsigned int    active:1;       /* Transfer active              */
+        unsigned int    invalid:1;      /* Address/Count changed        */
+        unsigned int    using_sg:1;     /* using scatter list?          */
+        dmamode_t       dma_mode;       /* DMA mode                     */
+        int             speed;          /* DMA speed                    */
+
+        unsigned int    lock;           /* Device is allocated          */
+        const char      *device_id;     /* Device name                  */
+
+        unsigned int    dma_base;       /* Controller base address      */
+        int             dma_irq;        /* Controller IRQ               */
+        struct scatterlist cur_sg;      /* Current controller buffer    */
+        unsigned int    state;
+
+        struct dma_ops  *d_ops;
+};
+
+/* Prototype: void arch_dma_init(dma)
+ * Purpose  : Initialise architecture specific DMA
+ * Params   : dma - pointer to array of DMA structures
+ */
+extern void arch_dma_init(dma_t *dma);
+
+extern void isa_init_dma(dma_t *dma);
diff --git a/include/asm-arm/mach/flash.h b/include/asm-arm/mach/flash.h
new file mode 100644
index 000000000000..a92887d4b2cb
--- /dev/null
+++ b/include/asm-arm/mach/flash.h
@@ -0,0 +1,34 @@
+/*
+ *  linux/include/asm-arm/mach/flash.h
+ *
+ *  Copyright (C) 2003 Russell King, All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_MACH_FLASH_H
+#define ASMARM_MACH_FLASH_H
+
+struct mtd_partition;
+
+/*
+ * map_name:    the map probe function name
+ * width:       width of mapped device
+ * init:        method called at driver/device initialisation
+ * exit:        method called at driver/device removal
+ * set_vpp:     method called to enable or disable VPP
+ * parts:       optional array of mtd_partitions for static partitioning
+ * nr_parts:    number of mtd_partitions for static partitoning
+ */
+struct flash_platform_data {
+        const char      *map_name;
+        unsigned int    width;
+        int             (*init)(void);
+        void            (*exit)(void);
+        void            (*set_vpp)(int on);
+        struct mtd_partition *parts;
+        unsigned int    nr_parts;
+};
+
+#endif
diff --git a/include/asm-arm/mach/irda.h b/include/asm-arm/mach/irda.h
new file mode 100644
index 000000000000..58984d9c0b0b
--- /dev/null
+++ b/include/asm-arm/mach/irda.h
@@ -0,0 +1,20 @@
+/*
+ *  linux/include/asm-arm/mach/irda.h
+ *
+ *  Copyright (C) 2004 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_MACH_IRDA_H
+#define __ASM_ARM_MACH_IRDA_H
+
+struct irda_platform_data {
+        int (*startup)(struct device *);
+        void (*shutdown)(struct device *);
+        int (*set_power)(struct device *, unsigned int state);
+        void (*set_speed)(struct device *, unsigned int speed);
+};
+
+#endif
diff --git a/include/asm-arm/mach/irq.h b/include/asm-arm/mach/irq.h
new file mode 100644
index 000000000000..a43a353f6c7b
--- /dev/null
+++ b/include/asm-arm/mach/irq.h
@@ -0,0 +1,127 @@
+/*
+ *  linux/include/asm-arm/mach/irq.h
+ *
+ *  Copyright (C) 1995-2000 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_MACH_IRQ_H
+#define __ASM_ARM_MACH_IRQ_H
+
+struct irqdesc;
+struct pt_regs;
+struct seq_file;
+
+typedef void (*irq_handler_t)(unsigned int, struct irqdesc *, struct pt_regs *);
+typedef void (*irq_control_t)(unsigned int);
+
+struct irqchip {
+        /*
+         * Acknowledge the IRQ.
+         * If this is a level-based IRQ, then it is expected to mask the IRQ
+         * as well.
+         */
+        void (*ack)(unsigned int);
+        /*
+         * Mask the IRQ in hardware.
+         */
+        void (*mask)(unsigned int);
+        /*
+         * Unmask the IRQ in hardware.
+         */
+        void (*unmask)(unsigned int);
+        /*
+         * Ask the hardware to re-trigger the IRQ.
+         * Note: This method _must_ _not_ call the interrupt handler.
+         * If you are unable to retrigger the interrupt, do not
+         * provide a function, or if you do, return non-zero.
+         */
+        int (*retrigger)(unsigned int);
+        /*
+         * Set the type of the IRQ.
+         */
+        int (*type)(unsigned int, unsigned int);
+        /*
+         * Set wakeup-enable on the selected IRQ
+         */
+        int (*wake)(unsigned int, unsigned int);
+
+#ifdef CONFIG_SMP
+        /*
+         * Route an interrupt to a CPU
+         */
+        void (*set_cpu)(struct irqdesc *desc, unsigned int irq, unsigned int cpu);
+#endif
+};
+
+struct irqdesc {
+        irq_handler_t   handle;
+        struct irqchip  *chip;
+        struct irqaction *action;
+        struct list_head pend;
+        void            *chipdata;
+        void            *data;
+        unsigned int    disable_depth;
+
+        unsigned int    triggered: 1;           /* IRQ has occurred           */
+        unsigned int    running  : 1;           /* IRQ is running             */
+        unsigned int    pending  : 1;           /* IRQ is pending             */
+        unsigned int    probing  : 1;           /* IRQ in use for a probe     */
+        unsigned int    probe_ok : 1;           /* IRQ can be used for probe  */
+        unsigned int    valid    : 1;           /* IRQ claimable              */
+        unsigned int    noautoenable : 1;       /* don't automatically enable IRQ */
+        unsigned int    unused   :25;
+
+        struct proc_dir_entry *procdir;
+
+#ifdef CONFIG_SMP
+        cpumask_t       affinity;
+        unsigned int    cpu;
+#endif
+
+        /*
+         * IRQ lock detection
+         */
+        unsigned int    lck_cnt;
+        unsigned int    lck_pc;
+        unsigned int    lck_jif;
+};
+
+extern struct irqdesc irq_desc[];
+
+/*
+ * This is internal.  Do not use it.
+ */
+extern void (*init_arch_irq)(void);
+extern void init_FIQ(void);
+extern int show_fiq_list(struct seq_file *, void *);
+void __set_irq_handler(unsigned int irq, irq_handler_t, int);
+
+/*
+ * External stuff.
+ */
+#define set_irq_handler(irq,handler)            __set_irq_handler(irq,handler,0)
+#define set_irq_chained_handler(irq,handler)    __set_irq_handler(irq,handler,1)
+#define set_irq_data(irq,d)                     do { irq_desc[irq].data = d; } while (0)
+#define set_irq_chipdata(irq,d)                 do { irq_desc[irq].chipdata = d; } while (0)
+#define get_irq_chipdata(irq)                   (irq_desc[irq].chipdata)
+
+void set_irq_chip(unsigned int irq, struct irqchip *);
+void set_irq_flags(unsigned int irq, unsigned int flags);
+
+#define IRQF_VALID      (1 << 0)
+#define IRQF_PROBE      (1 << 1)
+#define IRQF_NOAUTOEN   (1 << 2)
+
+/*
+ * Built-in IRQ handlers.
+ */
+void do_level_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs);
+void do_edge_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs);
+void do_simple_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs);
+void do_bad_IRQ(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs);
+void dummy_mask_unmask_irq(unsigned int irq);
+
+#endif
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
new file mode 100644
index 000000000000..9ac47cf8d2e4
--- /dev/null
+++ b/include/asm-arm/mach/map.h
@@ -0,0 +1,33 @@
+/*
+ *  linux/include/asm-arm/map.h
+ *
+ *  Copyright (C) 1999-2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Page table mapping constructs and function prototypes
+ */
+struct map_desc {
+        unsigned long virtual;
+        unsigned long physical;
+        unsigned long length;
+        unsigned int type;
+};
+
+struct meminfo;
+
+#define MT_DEVICE               0
+#define MT_CACHECLEAN           1
+#define MT_MINICLEAN            2
+#define MT_LOW_VECTORS          3
+#define MT_HIGH_VECTORS         4
+#define MT_MEMORY               5
+#define MT_ROM                  6
+#define MT_IXP2000_DEVICE       7
+
+extern void create_memmap_holes(struct meminfo *);
+extern void memtable_init(struct meminfo *);
+extern void iotable_init(struct map_desc *, int);
+extern void setup_io_desc(void);
diff --git a/include/asm-arm/mach/mmc.h b/include/asm-arm/mach/mmc.h
new file mode 100644
index 000000000000..1b3555d4b41e
--- /dev/null
+++ b/include/asm-arm/mach/mmc.h
@@ -0,0 +1,15 @@
+/*
+ *  linux/include/asm-arm/mach/mmc.h
+ */
+#ifndef ASMARM_MACH_MMC_H
+#define ASMARM_MACH_MMC_H
+
+#include <linux/mmc/protocol.h>
+
+struct mmc_platform_data {
+        unsigned int ocr_mask;                  /* available voltages */
+        u32 (*translate_vdd)(struct device *, unsigned int);
+        unsigned int (*status)(struct device *);
+};
+
+#endif
diff --git a/include/asm-arm/mach/pci.h b/include/asm-arm/mach/pci.h
new file mode 100644
index 000000000000..25d540ed0079
--- /dev/null
+++ b/include/asm-arm/mach/pci.h
@@ -0,0 +1,75 @@
+/*
+ *  linux/include/asm-arm/mach/pci.h
+ *
+ *  Copyright (C) 2000 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+struct pci_sys_data;
+struct pci_bus;
+
+struct hw_pci {
+        struct list_head buses;
+        int             nr_controllers;
+        int             (*setup)(int nr, struct pci_sys_data *);
+        struct pci_bus *(*scan)(int nr, struct pci_sys_data *);
+        void            (*preinit)(void);
+        void            (*postinit)(void);
+        u8              (*swizzle)(struct pci_dev *dev, u8 *pin);
+        int             (*map_irq)(struct pci_dev *dev, u8 slot, u8 pin);
+};
+
+/*
+ * Per-controller structure
+ */
+struct pci_sys_data {
+        struct list_head node;
+        int             busnr;          /* primary bus number                   */
+        unsigned long   mem_offset;     /* bus->cpu memory mapping offset       */
+        unsigned long   io_offset;      /* bus->cpu IO mapping offset           */
+        struct pci_bus  *bus;           /* PCI bus                              */
+        struct resource *resource[3];   /* Primary PCI bus resources            */
+                                        /* Bridge swizzling                     */
+        u8              (*swizzle)(struct pci_dev *, u8 *);
+                                        /* IRQ mapping                          */
+        int             (*map_irq)(struct pci_dev *, u8, u8);
+        struct hw_pci   *hw;
+};
+
+/*
+ * This is the standard PCI-PCI bridge swizzling algorithm.
+ */
+u8 pci_std_swizzle(struct pci_dev *dev, u8 *pinp);
+
+/*
+ * Call this with your hw_pci struct to initialise the PCI system.
+ */
+void pci_common_init(struct hw_pci *);
+
+/*
+ * PCI controllers
+ */
+extern int iop321_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
+extern void iop321_init(void);
+
+extern int iop331_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *);
+extern void iop331_init(void);
+
+extern int dc21285_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
+extern void dc21285_preinit(void);
+extern void dc21285_postinit(void);
+
+extern int via82c505_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *via82c505_scan_bus(int nr, struct pci_sys_data *);
+extern void via82c505_init(void *sysdata);
+
+extern int pci_v3_setup(int nr, struct pci_sys_data *);
+extern struct pci_bus *pci_v3_scan_bus(int nr, struct pci_sys_data *);
+extern void pci_v3_preinit(void);
+extern void pci_v3_postinit(void);
diff --git a/include/asm-arm/mach/serial_sa1100.h b/include/asm-arm/mach/serial_sa1100.h
new file mode 100644
index 000000000000..9162018585df
--- /dev/null
+++ b/include/asm-arm/mach/serial_sa1100.h
@@ -0,0 +1,32 @@
+/*
+ *  linux/include/asm-arm/mach/serial_sa1100.h
+ *
+ *  Author: Nicolas Pitre
+ *
+ * Moved to include/asm-arm/mach and changed lots, Russell King
+ *
+ * Low level machine dependent UART functions.
+ */
+#include <linux/config.h>
+
+struct uart_port;
+struct uart_info;
+
+/*
+ * This is a temporary structure for registering these
+ * functions; it is intended to be discarded after boot.
+ */
+struct sa1100_port_fns {
+        void    (*set_mctrl)(struct uart_port *, u_int);
+        u_int   (*get_mctrl)(struct uart_port *);
+        void    (*pm)(struct uart_port *, u_int, u_int);
+        int     (*set_wake)(struct uart_port *, u_int);
+};
+
+#ifdef CONFIG_SERIAL_SA1100
+void sa1100_register_uart_fns(struct sa1100_port_fns *fns);
+void sa1100_register_uart(int idx, int port);
+#else
+#define sa1100_register_uart_fns(fns) do { } while (0)
+#define sa1100_register_uart(idx,port) do { } while (0)
+#endif
diff --git a/include/asm-arm/mach/sharpsl_param.h b/include/asm-arm/mach/sharpsl_param.h
new file mode 100644
index 000000000000..7a24ecf04220
--- /dev/null
+++ b/include/asm-arm/mach/sharpsl_param.h
@@ -0,0 +1,37 @@
+/*
+ * Hardware parameter area specific to Sharp SL series devices
+ *
+ * Copyright (c) 2005 Richard Purdie
+ *
+ * Based on Sharp's 2.4 kernel patches
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+struct sharpsl_param_info {
+  unsigned int comadj_keyword;
+  unsigned int comadj;
+
+  unsigned int uuid_keyword;
+  unsigned char uuid[16];
+
+  unsigned int touch_keyword;
+  unsigned int touch_xp;
+  unsigned int touch_yp;
+  unsigned int touch_xd;
+  unsigned int touch_yd;
+
+  unsigned int adadj_keyword;
+  unsigned int adadj;
+
+  unsigned int phad_keyword;
+  unsigned int phadadj;
+} __attribute__((packed));
+
+
+extern struct sharpsl_param_info sharpsl_param;
+extern void sharpsl_save_param(void);
+
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
new file mode 100644
index 000000000000..5cf4fd659fd5
--- /dev/null
+++ b/include/asm-arm/mach/time.h
@@ -0,0 +1,54 @@
+/*
+ * linux/include/asm-arm/mach/time.h
+ *
+ * Copyright (C) 2004 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_MACH_TIME_H
+#define __ASM_ARM_MACH_TIME_H
+
+#include <linux/sysdev.h>
+
+/*
+ * This is our kernel timer structure.
+ *
+ * - init
+ *   Initialise the kernels jiffy timer source, claim interrupt
+ *   using setup_irq.  This is called early on during initialisation
+ *   while interrupts are still disabled on the local CPU.
+ * - suspend
+ *   Suspend the kernel jiffy timer source, if necessary.  This
+ *   is called with interrupts disabled, after all normal devices
+ *   have been suspended.  If no action is required, set this to
+ *   NULL.
+ * - resume
+ *   Resume the kernel jiffy timer source, if necessary.  This
+ *   is called with interrupts disabled before any normal devices
+ *   are resumed.  If no action is required, set this to NULL.
+ * - offset
+ *   Return the timer offset in microseconds since the last timer
+ *   interrupt.  Note: this must take account of any unprocessed
+ *   timer interrupt which may be pending.
+ */
+struct sys_timer {
+        struct sys_device       dev;
+        void                    (*init)(void);
+        void                    (*suspend)(void);
+        void                    (*resume)(void);
+        unsigned long           (*offset)(void);
+};
+
+extern struct sys_timer *system_timer;
+extern void timer_tick(struct pt_regs *);
+
+/*
+ * Kernel time keeping support.
+ */
+extern int (*set_rtc)(void);
+extern void save_time_delta(struct timespec *delta, struct timespec *rtc);
+extern void restore_time_delta(struct timespec *delta, struct timespec *rtc);
+
+#endif
diff --git a/include/asm-arm/mc146818rtc.h b/include/asm-arm/mc146818rtc.h
new file mode 100644
index 000000000000..7b81e0c42543
--- /dev/null
+++ b/include/asm-arm/mc146818rtc.h
@@ -0,0 +1,28 @@
+/*
+ * Machine dependent access functions for RTC registers.
+ */
+#ifndef _ASM_MC146818RTC_H
+#define _ASM_MC146818RTC_H
+
+#include <asm/arch/irqs.h>
+#include <asm/io.h>
+
+#ifndef RTC_PORT
+#define RTC_PORT(x)     (0x70 + (x))
+#define RTC_ALWAYS_BCD  1       /* RTC operates in binary mode */
+#endif
+
+/*
+ * The yet supported machines all access the RTC index register via
+ * an ISA port access but the way to access the date register differs ...
+ */
+#define CMOS_READ(addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+inb_p(RTC_PORT(1)); \
+})
+#define CMOS_WRITE(val, addr) ({ \
+outb_p((addr),RTC_PORT(0)); \
+outb_p((val),RTC_PORT(1)); \
+})
+
+#endif /* _ASM_MC146818RTC_H */
diff --git a/include/asm-arm/memory.h b/include/asm-arm/memory.h
new file mode 100644
index 000000000000..e47bea7d1723
--- /dev/null
+++ b/include/asm-arm/memory.h
@@ -0,0 +1,200 @@
+/*
+ *  linux/include/asm-arm/memory.h
+ *
+ *  Copyright (C) 2000-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Note: this file should not be included by non-asm/.h files
+ */
+#ifndef __ASM_ARM_MEMORY_H
+#define __ASM_ARM_MEMORY_H
+
+#include <linux/config.h>
+#include <linux/compiler.h>
+#include <asm/arch/memory.h>
+
+#ifndef TASK_SIZE
+/*
+ * TASK_SIZE - the maximum size of a user space task.
+ * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area
+ */
+#define TASK_SIZE               (0xbf000000UL)
+#define TASK_UNMAPPED_BASE      (0x40000000UL)
+#endif
+
+/*
+ * The maximum size of a 26-bit user space task.
+ */
+#define TASK_SIZE_26            (0x04000000UL)
+
+/*
+ * Page offset: 3GB
+ */
+#ifndef PAGE_OFFSET
+#define PAGE_OFFSET             (0xc0000000UL)
+#endif
+
+/*
+ * Physical vs virtual RAM address space conversion.  These are
+ * private definitions which should NOT be used outside memory.h
+ * files.  Use virt_to_phys/phys_to_virt/__pa/__va instead.
+ */
+#ifndef __virt_to_phys
+#define __virt_to_phys(x)       ((x) - PAGE_OFFSET + PHYS_OFFSET)
+#define __phys_to_virt(x)       ((x) - PHYS_OFFSET + PAGE_OFFSET)
+#endif
+
+/*
+ * The module space lives between the addresses given by TASK_SIZE
+ * and PAGE_OFFSET - it must be within 32MB of the kernel text.
+ */
+#define MODULE_END      (PAGE_OFFSET)
+#define MODULE_START    (MODULE_END - 16*1048576)
+
+#if TASK_SIZE > MODULE_START
+#error Top of user space clashes with start of module space
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * The DMA mask corresponding to the maximum bus address allocatable
+ * using GFP_DMA.  The default here places no restriction on DMA
+ * allocations.  This must be the smallest DMA mask in the system,
+ * so a successful GFP_DMA allocation will always satisfy this.
+ */
+#ifndef ISA_DMA_THRESHOLD
+#define ISA_DMA_THRESHOLD       (0xffffffffULL)
+#endif
+
+#ifndef arch_adjust_zones
+#define arch_adjust_zones(node,size,holes) do { } while (0)
+#endif
+
+/*
+ * PFNs are used to describe any physical page; this means
+ * PFN 0 == physical address 0.
+ *
+ * This is the PFN of the first RAM page in the kernel
+ * direct-mapped view.  We assume this is the first page
+ * of RAM in the mem_map as well.
+ */
+#define PHYS_PFN_OFFSET (PHYS_OFFSET >> PAGE_SHIFT)
+
+/*
+ * These are *only* valid on the kernel direct mapped RAM memory.
+ * Note: Drivers should NOT use these.  They are the wrong
+ * translation for translating DMA addresses.  Use the driver
+ * DMA support - see dma-mapping.h.
+ */
+static inline unsigned long virt_to_phys(void *x)
+{
+        return __virt_to_phys((unsigned long)(x));
+}
+
+static inline void *phys_to_virt(unsigned long x)
+{
+        return (void *)(__phys_to_virt((unsigned long)(x)));
+}
+
+/*
+ * Drivers should NOT use these either.
+ */
+#define __pa(x)                 __virt_to_phys((unsigned long)(x))
+#define __va(x)                 ((void *)__phys_to_virt((unsigned long)(x)))
+
+/*
+ * Virtual <-> DMA view memory address translations
+ * Again, these are *only* valid on the kernel direct mapped RAM
+ * memory.  Use of these is *deprecated* (and that doesn't mean
+ * use the __ prefixed forms instead.)  See dma-mapping.h.
+ */
+static inline __deprecated unsigned long virt_to_bus(void *x)
+{
+        return __virt_to_bus((unsigned long)x);
+}
+
+static inline __deprecated void *bus_to_virt(unsigned long x)
+{
+        return (void *)__bus_to_virt(x);
+}
+
+/*
+ * Conversion between a struct page and a physical address.
+ *
+ * Note: when converting an unknown physical address to a
+ * struct page, the resulting pointer must be validated
+ * using VALID_PAGE().  It must return an invalid struct page
+ * for any physical address not corresponding to a system
+ * RAM address.
+ *
+ *  page_to_pfn(page)   convert a struct page * to a PFN number
+ *  pfn_to_page(pfn)    convert a _valid_ PFN number to struct page *
+ *  pfn_valid(pfn)      indicates whether a PFN number is valid
+ *
+ *  virt_to_page(k)     convert a _valid_ virtual address to struct page *
+ *  virt_addr_valid(k)  indicates whether a virtual address is valid
+ */
+#ifndef CONFIG_DISCONTIGMEM
+
+#define page_to_pfn(page)       (((page) - mem_map) + PHYS_PFN_OFFSET)
+#define pfn_to_page(pfn)        ((mem_map + (pfn)) - PHYS_PFN_OFFSET)
+#define pfn_valid(pfn)          ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
+
+#define virt_to_page(kaddr)     (pfn_to_page(__pa(kaddr) >> PAGE_SHIFT))
+#define virt_addr_valid(kaddr)  ((unsigned long)(kaddr) >= PAGE_OFFSET && (unsigned long)(kaddr) < (unsigned long)high_memory)
+
+#define PHYS_TO_NID(addr)       (0)
+
+#else /* CONFIG_DISCONTIGMEM */
+
+/*
+ * This is more complex.  We have a set of mem_map arrays spread
+ * around in memory.
+ */
+#include <linux/numa.h>
+
+#define page_to_pfn(page)                                       \
+        (( (page) - page_zone(page)->zone_mem_map)              \
+          + page_zone(page)->zone_start_pfn)
+#define pfn_to_page(pfn)                                        \
+        (PFN_TO_MAPBASE(pfn) + LOCAL_MAP_NR((pfn) << PAGE_SHIFT))
+#define pfn_valid(pfn)          (PFN_TO_NID(pfn) < MAX_NUMNODES)
+
+#define virt_to_page(kaddr)                                     \
+        (ADDR_TO_MAPBASE(kaddr) + LOCAL_MAP_NR(kaddr))
+#define virt_addr_valid(kaddr)  (KVADDR_TO_NID(kaddr) < MAX_NUMNODES)
+
+/*
+ * Common discontigmem stuff.
+ *  PHYS_TO_NID is used by the ARM kernel/setup.c
+ */
+#define PHYS_TO_NID(addr)       PFN_TO_NID((addr) >> PAGE_SHIFT)
+
+#endif /* !CONFIG_DISCONTIGMEM */
+
+/*
+ * For BIO.  "will die".  Kill me when bio_to_phys() and bvec_to_phys() die.
+ */
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
+
+/*
+ * Optional device DMA address remapping. Do _not_ use directly!
+ * We should really eliminate virt_to_bus() here - it's deprecated.
+ */
+#ifndef __arch_page_to_dma
+#define page_to_dma(dev, page)          ((dma_addr_t)__virt_to_bus((unsigned long)page_address(page)))
+#define dma_to_virt(dev, addr)          ((void *)__bus_to_virt(addr))
+#define virt_to_dma(dev, addr)          ((dma_addr_t)__virt_to_bus((unsigned long)(addr)))
+#else
+#define page_to_dma(dev, page)          (__arch_page_to_dma(dev, page))
+#define dma_to_virt(dev, addr)          (__arch_dma_to_virt(dev, addr))
+#define virt_to_dma(dev, addr)          (__arch_virt_to_dma(dev, addr))
+#endif
+
+#endif
+
+#endif
diff --git a/include/asm-arm/mman.h b/include/asm-arm/mman.h
new file mode 100644
index 000000000000..8e4f69c4fa5f
--- /dev/null
+++ b/include/asm-arm/mman.h
@@ -0,0 +1,43 @@
+#ifndef __ARM_MMAN_H__
+#define __ARM_MMAN_H__
+
+#define PROT_READ       0x1             /* page can be read */
+#define PROT_WRITE      0x2             /* page can be written */
+#define PROT_EXEC       0x4             /* page can be executed */
+#define PROT_SEM        0x8             /* page may be used for atomic ops */
+#define PROT_NONE       0x0             /* page can not be accessed */
+#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
+
+#define MAP_SHARED      0x01            /* Share changes */
+#define MAP_PRIVATE     0x02            /* Changes are private */
+#define MAP_TYPE        0x0f            /* Mask for type of mapping */
+#define MAP_FIXED       0x10            /* Interpret addr exactly */
+#define MAP_ANONYMOUS   0x20            /* don't use a file */
+
+#define MAP_GROWSDOWN   0x0100          /* stack-like segment */
+#define MAP_DENYWRITE   0x0800          /* ETXTBSY */
+#define MAP_EXECUTABLE  0x1000          /* mark it as an executable */
+#define MAP_LOCKED      0x2000          /* pages are locked */
+#define MAP_NORESERVE   0x4000          /* don't check for reservations */
+#define MAP_POPULATE    0x8000          /* populate (prefault) page tables */
+#define MAP_NONBLOCK    0x10000         /* do not block on IO */
+
+#define MS_ASYNC        1               /* sync memory asynchronously */
+#define MS_INVALIDATE   2               /* invalidate the caches */
+#define MS_SYNC         4               /* synchronous memory sync */
+
+#define MCL_CURRENT     1               /* lock all current mappings */
+#define MCL_FUTURE      2               /* lock all future mappings */
+
+#define MADV_NORMAL     0x0             /* default page-in behavior */
+#define MADV_RANDOM     0x1             /* page-in minimum required */
+#define MADV_SEQUENTIAL 0x2             /* read-ahead aggressively */
+#define MADV_WILLNEED   0x3             /* pre-fault pages */
+#define MADV_DONTNEED   0x4             /* discard these pages */
+
+/* compatibility flags */
+#define MAP_ANON        MAP_ANONYMOUS
+#define MAP_FILE        0
+
+#endif /* __ARM_MMAN_H__ */
diff --git a/include/asm-arm/mmu.h b/include/asm-arm/mmu.h
new file mode 100644
index 000000000000..a457cb71984f
--- /dev/null
+++ b/include/asm-arm/mmu.h
@@ -0,0 +1,16 @@
+#ifndef __ARM_MMU_H
+#define __ARM_MMU_H
+
+typedef struct {
+#if __LINUX_ARM_ARCH__ >= 6
+        unsigned int id;
+#endif
+} mm_context_t;
+
+#if __LINUX_ARM_ARCH__ >= 6
+#define ASID(mm)        ((mm)->context.id & 255)
+#else
+#define ASID(mm)        (0)
+#endif
+
+#endif
diff --git a/include/asm-arm/mmu_context.h b/include/asm-arm/mmu_context.h
new file mode 100644
index 000000000000..4af9c411c617
--- /dev/null
+++ b/include/asm-arm/mmu_context.h
@@ -0,0 +1,96 @@
+/*
+ *  linux/include/asm-arm/mmu_context.h
+ *
+ *  Copyright (C) 1996 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996 RMK     Created
+ */
+#ifndef __ASM_ARM_MMU_CONTEXT_H
+#define __ASM_ARM_MMU_CONTEXT_H
+
+#include <asm/proc-fns.h>
+
+#if __LINUX_ARM_ARCH__ >= 6
+
+/*
+ * On ARMv6, we have the following structure in the Context ID:
+ *
+ * 31                         7          0
+ * +-------------------------+-----------+
+ * |      process ID         |   ASID    |
+ * +-------------------------+-----------+
+ * |              context ID             |
+ * +-------------------------------------+
+ *
+ * The ASID is used to tag entries in the CPU caches and TLBs.
+ * The context ID is used by debuggers and trace logic, and
+ * should be unique within all running processes.
+ */
+#define ASID_BITS       8
+#define ASID_MASK       ((~0) << ASID_BITS)
+
+extern unsigned int cpu_last_asid;
+
+void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
+void __new_context(struct mm_struct *mm);
+
+static inline void check_context(struct mm_struct *mm)
+{
+        if (unlikely((mm->context.id ^ cpu_last_asid) >> ASID_BITS))
+                __new_context(mm);
+}
+
+#define init_new_context(tsk,mm)        (__init_new_context(tsk,mm),0)
+
+#else
+
+#define check_context(mm)               do { } while (0)
+#define init_new_context(tsk,mm)        0
+
+#endif
+
+#define destroy_context(mm)             do { } while(0)
+
+/*
+ * This is called when "tsk" is about to enter lazy TLB mode.
+ *
+ * mm:  describes the currently active mm context
+ * tsk: task which is entering lazy tlb
+ * cpu: cpu number which is entering lazy tlb
+ *
+ * tsk->mm will be NULL
+ */
+static inline void
+enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+/*
+ * This is the actual mm switch as far as the scheduler
+ * is concerned.  No registers are touched.  We avoid
+ * calling the CPU specific function when the mm hasn't
+ * actually changed.
+ */
+static inline void
+switch_mm(struct mm_struct *prev, struct mm_struct *next,
+          struct task_struct *tsk)
+{
+        unsigned int cpu = smp_processor_id();
+
+        if (prev != next) {
+                cpu_set(cpu, next->cpu_vm_mask);
+                check_context(next);
+                cpu_switch_mm(next->pgd, next);
+                cpu_clear(cpu, prev->cpu_vm_mask);
+        }
+}
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+#define activate_mm(prev,next)  switch_mm(prev, next, NULL)
+
+#endif
diff --git a/include/asm-arm/mmzone.h b/include/asm-arm/mmzone.h
new file mode 100644
index 000000000000..b87de151f0a4
--- /dev/null
+++ b/include/asm-arm/mmzone.h
@@ -0,0 +1,30 @@
+/*
+ *  linux/include/asm-arm/mmzone.h
+ *
+ *  1999-12-29  Nicolas Pitre           Created
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_MMZONE_H
+#define __ASM_MMZONE_H
+
+/*
+ * Currently defined in arch/arm/mm/discontig.c
+ */
+extern pg_data_t discontig_node_data[];
+
+/*
+ * Return a pointer to the node data for node n.
+ */
+#define NODE_DATA(nid)          (&discontig_node_data[nid])
+
+/*
+ * NODE_MEM_MAP gives the kaddr for the mem_map of the node.
+ */
+#define NODE_MEM_MAP(nid)       (NODE_DATA(nid)->node_mem_map)
+
+#include <asm/arch/memory.h>
+
+#endif
diff --git a/include/asm-arm/module.h b/include/asm-arm/module.h
new file mode 100644
index 000000000000..24b168dc31a3
--- /dev/null
+++ b/include/asm-arm/module.h
@@ -0,0 +1,18 @@
+#ifndef _ASM_ARM_MODULE_H
+#define _ASM_ARM_MODULE_H
+
+struct mod_arch_specific
+{
+        int foo;
+};
+
+#define Elf_Shdr        Elf32_Shdr
+#define Elf_Sym         Elf32_Sym
+#define Elf_Ehdr        Elf32_Ehdr
+
+/*
+ * Include the ARM architecture version.
+ */
+#define MODULE_ARCH_VERMAGIC    "ARMv" __stringify(__LINUX_ARM_ARCH__) " "
+
+#endif /* _ASM_ARM_MODULE_H */
diff --git a/include/asm-arm/msgbuf.h b/include/asm-arm/msgbuf.h
new file mode 100644
index 000000000000..33b35b946eaa
--- /dev/null
+++ b/include/asm-arm/msgbuf.h
@@ -0,0 +1,31 @@
+#ifndef _ASMARM_MSGBUF_H
+#define _ASMARM_MSGBUF_H
+
+/* 
+ * The msqid64_ds structure for arm architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        unsigned long   __unused1;
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        unsigned long   __unused2;
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long   __unused3;
+        unsigned long  msg_cbytes;      /* current number of bytes on queue */
+        unsigned long  msg_qnum;        /* number of messages in queue */
+        unsigned long  msg_qbytes;      /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+#endif /* _ASMARM_MSGBUF_H */
diff --git a/include/asm-arm/namei.h b/include/asm-arm/namei.h
new file mode 100644
index 000000000000..a402d3b9d0f7
--- /dev/null
+++ b/include/asm-arm/namei.h
@@ -0,0 +1,25 @@
+/* 
+ * linux/include/asm-arm/namei.h
+ *
+ * Routines to handle famous /usr/gnemul
+ * Derived from the Sparc version of this file
+ *
+ * Included from linux/fs/namei.c
+ */
+
+#ifndef __ASMARM_NAMEI_H
+#define __ASMARM_NAMEI_H
+
+#define ARM_BSD_EMUL "usr/gnemul/bsd/"
+
+static inline char *__emul_prefix(void)
+{
+        switch (current->personality) {
+        case PER_BSD:
+                return ARM_BSD_EMUL;
+        default:
+                return NULL;
+        }
+}
+
+#endif /* __ASMARM_NAMEI_H */
diff --git a/include/asm-arm/numnodes.h b/include/asm-arm/numnodes.h
new file mode 100644
index 000000000000..5d2a1034a02e
--- /dev/null
+++ b/include/asm-arm/numnodes.h
@@ -0,0 +1,24 @@
+/*
+ *  linux/include/asm-arm/numnodes.h
+ *
+ *  Copyright (C) 2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* This declaration for the size of the NUMA (CONFIG_DISCONTIGMEM)
+ * memory node table is the default.
+ *
+ * A good place to override this value is include/asm/arch/memory.h.
+ */
+
+#ifndef __ASM_ARM_NUMNODES_H
+#define __ASM_ARM_NUMNODES_H
+
+#ifndef NODES_SHIFT
+# define NODES_SHIFT    2       /* Normally, Max 4 Nodes */
+#endif
+
+#endif
diff --git a/include/asm-arm/nwflash.h b/include/asm-arm/nwflash.h
new file mode 100644
index 000000000000..04e5a557a884
--- /dev/null
+++ b/include/asm-arm/nwflash.h
@@ -0,0 +1,9 @@
+#ifndef _FLASH_H
+#define _FLASH_H
+
+#define FLASH_MINOR              160    /* MAJOR is 10 - miscdevice */
+#define CMD_WRITE_DISABLE        0
+#define CMD_WRITE_ENABLE         0x28
+#define CMD_WRITE_BASE64K_ENABLE 0x47
+
+#endif /* _FLASH_H */
diff --git a/include/asm-arm/page.h b/include/asm-arm/page.h
new file mode 100644
index 000000000000..4ca3a8e9348f
--- /dev/null
+++ b/include/asm-arm/page.h
@@ -0,0 +1,197 @@
+/*
+ *  linux/include/asm-arm/page.h
+ *
+ *  Copyright (C) 1995-2003 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASMARM_PAGE_H
+#define _ASMARM_PAGE_H
+
+#include <linux/config.h>
+
+/* PAGE_SHIFT determines the page size */
+#define PAGE_SHIFT              12
+#define PAGE_SIZE               (1UL << PAGE_SHIFT)
+#define PAGE_MASK               (~(PAGE_SIZE-1))
+
+#ifdef __KERNEL__
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/glue.h>
+
+/*
+ *      User Space Model
+ *      ================
+ *
+ *      This section selects the correct set of functions for dealing with
+ *      page-based copying and clearing for user space for the particular
+ *      processor(s) we're building for.
+ *
+ *      We have the following to choose from:
+ *        v3            - ARMv3
+ *        v4wt          - ARMv4 with writethrough cache, without minicache
+ *        v4wb          - ARMv4 with writeback cache, without minicache
+ *        v4_mc         - ARMv4 with minicache
+ *        xscale        - Xscale
+ */
+#undef _USER
+#undef MULTI_USER
+
+#ifdef CONFIG_CPU_COPY_V3
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER v3
+# endif
+#endif
+
+#ifdef CONFIG_CPU_COPY_V4WT
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER v4wt
+# endif
+#endif
+
+#ifdef CONFIG_CPU_COPY_V4WB
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER v4wb
+# endif
+#endif
+
+#ifdef CONFIG_CPU_SA1100
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER v4_mc
+# endif
+#endif
+
+#ifdef CONFIG_CPU_XSCALE
+# ifdef _USER
+#  define MULTI_USER 1
+# else
+#  define _USER xscale_mc
+# endif
+#endif
+
+#ifdef CONFIG_CPU_COPY_V6
+# define MULTI_USER 1
+#endif
+
+#if !defined(_USER) && !defined(MULTI_USER)
+#error Unknown user operations model
+#endif
+
+struct cpu_user_fns {
+        void (*cpu_clear_user_page)(void *p, unsigned long user);
+        void (*cpu_copy_user_page)(void *to, const void *from,
+                                   unsigned long user);
+};
+
+#ifdef MULTI_USER
+extern struct cpu_user_fns cpu_user;
+
+#define __cpu_clear_user_page   cpu_user.cpu_clear_user_page
+#define __cpu_copy_user_page    cpu_user.cpu_copy_user_page
+
+#else
+
+#define __cpu_clear_user_page   __glue(_USER,_clear_user_page)
+#define __cpu_copy_user_page    __glue(_USER,_copy_user_page)
+
+extern void __cpu_clear_user_page(void *p, unsigned long user);
+extern void __cpu_copy_user_page(void *to, const void *from,
+                                 unsigned long user);
+#endif
+
+#define clear_user_page(addr,vaddr,pg)                  \
+        do {                                            \
+                preempt_disable();                      \
+                __cpu_clear_user_page(addr, vaddr);     \
+                preempt_enable();                       \
+        } while (0)
+
+#define copy_user_page(to,from,vaddr,pg)                \
+        do {                                            \
+                preempt_disable();                      \
+                __cpu_copy_user_page(to, from, vaddr);  \
+                preempt_enable();                       \
+        } while (0)
+
+#define clear_page(page)        memzero((void *)(page), PAGE_SIZE)
+extern void copy_page(void *to, const void *from);
+
+#undef STRICT_MM_TYPECHECKS
+
+#ifdef STRICT_MM_TYPECHECKS
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct { unsigned long pte; } pte_t;
+typedef struct { unsigned long pmd; } pmd_t;
+typedef struct { unsigned long pgd[2]; } pgd_t;
+typedef struct { unsigned long pgprot; } pgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define pmd_val(x)      ((x).pmd)
+#define pgd_val(x)      ((x).pgd[0])
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+#else
+/*
+ * .. while these make it easier on the compiler
+ */
+typedef unsigned long pte_t;
+typedef unsigned long pmd_t;
+typedef unsigned long pgd_t[2];
+typedef unsigned long pgprot_t;
+
+#define pte_val(x)      (x)
+#define pmd_val(x)      (x)
+#define pgd_val(x)      ((x)[0])
+#define pgprot_val(x)   (x)
+
+#define __pte(x)        (x)
+#define __pmd(x)        (x)
+#define __pgprot(x)     (x)
+
+#endif /* STRICT_MM_TYPECHECKS */
+
+/* Pure 2^n version of get_order */
+static inline int get_order(unsigned long size)
+{
+        int order;
+
+        size = (size-1) >> (PAGE_SHIFT-1);
+        order = -1;
+        do {
+                size >>= 1;
+                order++;
+        } while (size);
+        return order;
+}
+
+#include <asm/memory.h>
+
+#endif /* !__ASSEMBLY__ */
+
+#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
+                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/asm-arm/param.h b/include/asm-arm/param.h
new file mode 100644
index 000000000000..94223d4d7e88
--- /dev/null
+++ b/include/asm-arm/param.h
@@ -0,0 +1,36 @@
+/*
+ *  linux/include/asm-arm/param.h
+ *
+ *  Copyright (C) 1995-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PARAM_H
+#define __ASM_PARAM_H
+
+#ifdef __KERNEL__
+# include <asm/arch/param.h>            /* for kernel version of HZ */
+
+# ifndef HZ
+#  define HZ            100             /* Internal kernel timer frequency */
+# endif
+
+# define USER_HZ        100             /* User interfaces are in "ticks" */
+# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
+#else
+# define HZ             100
+#endif
+
+#define EXEC_PAGESIZE   4096
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+/* max length of hostname */
+#define MAXHOSTNAMELEN  64
+
+#endif
+
diff --git a/include/asm-arm/parport.h b/include/asm-arm/parport.h
new file mode 100644
index 000000000000..f2f90c76ddd1
--- /dev/null
+++ b/include/asm-arm/parport.h
@@ -0,0 +1,18 @@
+/*
+ *  linux/include/asm-arm/parport.h: ARM-specific parport initialisation
+ *
+ *  Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
+ *
+ * This file should only be included by drivers/parport/parport_pc.c.
+ */
+
+#ifndef __ASMARM_PARPORT_H
+#define __ASMARM_PARPORT_H
+
+static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
+static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
+{
+        return parport_pc_find_isa_ports (autoirq, autodma);
+}
+
+#endif /* !(_ASMARM_PARPORT_H) */
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
new file mode 100644
index 000000000000..40ffaefbeb1a
--- /dev/null
+++ b/include/asm-arm/pci.h
@@ -0,0 +1,59 @@
+#ifndef ASMARM_PCI_H
+#define ASMARM_PCI_H
+
+#ifdef __KERNEL__
+#include <linux/config.h>
+#include <asm-generic/pci-dma-compat.h>
+
+#include <asm/hardware.h> /* for PCIBIOS_MIN_* */
+
+#define pcibios_scan_all_fns(a, b)      0
+
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+        /* No special bus mastering setup handling */
+}
+
+static inline void pcibios_penalize_isa_irq(int irq)
+{
+        /* We don't do dynamic PCI IRQ allocation */
+}
+
+/*
+ * The PCI address space does equal the physical memory address space.
+ * The networking and block device layers use this boolean for bounce
+ * buffer decisions.
+ */
+#define PCI_DMA_BUS_IS_PHYS     (0)
+
+/*
+ * We don't support DAC DMA cycles.
+ */
+#define pci_dac_dma_supported(pci_dev, mask)    (0)
+
+/*
+ * Whether pci_unmap_{single,page} is a nop depends upon the
+ * configuration.
+ */
+#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       dma_addr_t ADDR_NAME;
+#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         __u32 LEN_NAME;
+#define pci_unmap_addr(PTR, ADDR_NAME)          ((PTR)->ADDR_NAME)
+#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
+#define pci_unmap_len(PTR, LEN_NAME)            ((PTR)->LEN_NAME)
+#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   (((PTR)->LEN_NAME) = (VAL))
+
+#define HAVE_PCI_MMAP
+extern int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
+                               enum pci_mmap_state mmap_state, int write_combine);
+
+extern void
+pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
+                         struct resource *res);
+
+static inline void pcibios_add_platform_entries(struct pci_dev *dev)
+{
+}
+
+#endif /* __KERNEL__ */
+ 
+#endif
diff --git a/include/asm-arm/percpu.h b/include/asm-arm/percpu.h
new file mode 100644
index 000000000000..b4e32d8ec072
--- /dev/null
+++ b/include/asm-arm/percpu.h
@@ -0,0 +1,6 @@
+#ifndef __ARM_PERCPU
+#define __ARM_PERCPU
+
+#include <asm-generic/percpu.h>
+
+#endif
diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h
new file mode 100644
index 000000000000..e814f8144f8b
--- /dev/null
+++ b/include/asm-arm/pgalloc.h
@@ -0,0 +1,130 @@
+/*
+ *  linux/include/asm-arm/pgalloc.h
+ *
+ *  Copyright (C) 2000-2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASMARM_PGALLOC_H
+#define _ASMARM_PGALLOC_H
+
+#include <asm/processor.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+
+/*
+ * Since we have only two-level page tables, these are trivial
+ */
+#define pmd_alloc_one(mm,addr)          ({ BUG(); ((pmd_t *)2); })
+#define pmd_free(pmd)                   do { } while (0)
+#define pgd_populate(mm,pmd,pte)        BUG()
+
+extern pgd_t *get_pgd_slow(struct mm_struct *mm);
+extern void free_pgd_slow(pgd_t *pgd);
+
+#define pgd_alloc(mm)                   get_pgd_slow(mm)
+#define pgd_free(pgd)                   free_pgd_slow(pgd)
+
+#define check_pgt_cache()               do { } while (0)
+
+/*
+ * Allocate one PTE table.
+ *
+ * This actually allocates two hardware PTE tables, but we wrap this up
+ * into one table thus:
+ *
+ *  +------------+
+ *  |  h/w pt 0  |
+ *  +------------+
+ *  |  h/w pt 1  |
+ *  +------------+
+ *  | Linux pt 0 |
+ *  +------------+
+ *  | Linux pt 1 |
+ *  +------------+
+ */
+static inline pte_t *
+pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr)
+{
+        pte_t *pte;
+
+        pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
+        if (pte) {
+                clean_dcache_area(pte, sizeof(pte_t) * PTRS_PER_PTE);
+                pte += PTRS_PER_PTE;
+        }
+
+        return pte;
+}
+
+static inline struct page *
+pte_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        struct page *pte;
+
+        pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
+        if (pte) {
+                void *page = page_address(pte);
+                clean_dcache_area(page, sizeof(pte_t) * PTRS_PER_PTE);
+        }
+
+        return pte;
+}
+
+/*
+ * Free one PTE table.
+ */
+static inline void pte_free_kernel(pte_t *pte)
+{
+        if (pte) {
+                pte -= PTRS_PER_PTE;
+                free_page((unsigned long)pte);
+        }
+}
+
+static inline void pte_free(struct page *pte)
+{
+        __free_page(pte);
+}
+
+/*
+ * Populate the pmdp entry with a pointer to the pte.  This pmd is part
+ * of the mm address space.
+ *
+ * Ensure that we always set both PMD entries.
+ */
+static inline void
+pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep)
+{
+        unsigned long pte_ptr = (unsigned long)ptep;
+        unsigned long pmdval;
+
+        BUG_ON(mm != &init_mm);
+
+        /*
+         * The pmd must be loaded with the physical
+         * address of the PTE table
+         */
+        pte_ptr -= PTRS_PER_PTE * sizeof(void *);
+        pmdval = __pa(pte_ptr) | _PAGE_KERNEL_TABLE;
+        pmdp[0] = __pmd(pmdval);
+        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
+        flush_pmd_entry(pmdp);
+}
+
+static inline void
+pmd_populate(struct mm_struct *mm, pmd_t *pmdp, struct page *ptep)
+{
+        unsigned long pmdval;
+
+        BUG_ON(mm == &init_mm);
+
+        pmdval = page_to_pfn(ptep) << PAGE_SHIFT | _PAGE_USER_TABLE;
+        pmdp[0] = __pmd(pmdval);
+        pmdp[1] = __pmd(pmdval + 256 * sizeof(pte_t));
+        flush_pmd_entry(pmdp);
+}
+
+#endif
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
new file mode 100644
index 000000000000..91ffb1f4cd10
--- /dev/null
+++ b/include/asm-arm/pgtable.h
@@ -0,0 +1,433 @@
+/*
+ *  linux/include/asm-arm/pgtable.h
+ *
+ *  Copyright (C) 1995-2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASMARM_PGTABLE_H
+#define _ASMARM_PGTABLE_H
+
+#include <asm-generic/4level-fixup.h>
+
+#include <asm/memory.h>
+#include <asm/proc-fns.h>
+#include <asm/arch/vmalloc.h>
+
+/*
+ * Hardware-wise, we have a two level page table structure, where the first
+ * level has 4096 entries, and the second level has 256 entries.  Each entry
+ * is one 32-bit word.  Most of the bits in the second level entry are used
+ * by hardware, and there aren't any "accessed" and "dirty" bits.
+ *
+ * Linux on the other hand has a three level page table structure, which can
+ * be wrapped to fit a two level page table structure easily - using the PGD
+ * and PTE only.  However, Linux also expects one "PTE" table per page, and
+ * at least a "dirty" bit.
+ *
+ * Therefore, we tweak the implementation slightly - we tell Linux that we
+ * have 2048 entries in the first level, each of which is 8 bytes (iow, two
+ * hardware pointers to the second level.)  The second level contains two
+ * hardware PTE tables arranged contiguously, followed by Linux versions
+ * which contain the state information Linux needs.  We, therefore, end up
+ * with 512 entries in the "PTE" level.
+ *
+ * This leads to the page tables having the following layout:
+ *
+ *    pgd             pte
+ * |        |
+ * +--------+ +0
+ * |        |-----> +------------+ +0
+ * +- - - - + +4    |  h/w pt 0  |
+ * |        |-----> +------------+ +1024
+ * +--------+ +8    |  h/w pt 1  |
+ * |        |       +------------+ +2048
+ * +- - - - +       | Linux pt 0 |
+ * |        |       +------------+ +3072
+ * +--------+       | Linux pt 1 |
+ * |        |       +------------+ +4096
+ *
+ * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
+ * PTE_xxx for definitions of bits appearing in the "h/w pt".
+ *
+ * PMD_xxx definitions refer to bits in the first level page table.
+ *
+ * The "dirty" bit is emulated by only granting hardware write permission
+ * iff the page is marked "writable" and "dirty" in the Linux PTE.  This
+ * means that a write to a clean page will cause a permission fault, and
+ * the Linux MM layer will mark the page dirty via handle_pte_fault().
+ * For the hardware to notice the permission change, the TLB entry must
+ * be flushed, and ptep_establish() does that for us.
+ *
+ * The "accessed" or "young" bit is emulated by a similar method; we only
+ * allow accesses to the page if the "young" bit is set.  Accesses to the
+ * page will cause a fault, and handle_pte_fault() will set the young bit
+ * for us as long as the page is marked present in the corresponding Linux
+ * PTE entry.  Again, ptep_establish() will ensure that the TLB is up to
+ * date.
+ *
+ * However, when the "young" bit is cleared, we deny access to the page
+ * by clearing the hardware PTE.  Currently Linux does not flush the TLB
+ * for us in this case, which means the TLB will retain the transation
+ * until either the TLB entry is evicted under pressure, or a context
+ * switch which changes the user space mapping occurs.
+ */
+#define PTRS_PER_PTE            512
+#define PTRS_PER_PMD            1
+#define PTRS_PER_PGD            2048
+
+/*
+ * PMD_SHIFT determines the size of the area a second-level page table can map
+ * PGDIR_SHIFT determines what a third-level page table entry can map
+ */
+#define PMD_SHIFT               21
+#define PGDIR_SHIFT             21
+
+#define LIBRARY_TEXT_START      0x0c000000
+
+#ifndef __ASSEMBLY__
+extern void __pte_error(const char *file, int line, unsigned long val);
+extern void __pmd_error(const char *file, int line, unsigned long val);
+extern void __pgd_error(const char *file, int line, unsigned long val);
+
+#define pte_ERROR(pte)          __pte_error(__FILE__, __LINE__, pte_val(pte))
+#define pmd_ERROR(pmd)          __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
+#define pgd_ERROR(pgd)          __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
+#endif /* !__ASSEMBLY__ */
+
+#define PMD_SIZE                (1UL << PMD_SHIFT)
+#define PMD_MASK                (~(PMD_SIZE-1))
+#define PGDIR_SIZE              (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK              (~(PGDIR_SIZE-1))
+
+#define FIRST_USER_PGD_NR       1
+#define USER_PTRS_PER_PGD       ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
+
+/*
+ * ARMv6 supersection address mask and size definitions.
+ */
+#define SUPERSECTION_SHIFT      24
+#define SUPERSECTION_SIZE       (1UL << SUPERSECTION_SHIFT)
+#define SUPERSECTION_MASK       (~(SUPERSECTION_SIZE-1))
+
+/*
+ * Hardware page table definitions.
+ *
+ * + Level 1 descriptor (PMD)
+ *   - common
+ */
+#define PMD_TYPE_MASK           (3 << 0)
+#define PMD_TYPE_FAULT          (0 << 0)
+#define PMD_TYPE_TABLE          (1 << 0)
+#define PMD_TYPE_SECT           (2 << 0)
+#define PMD_BIT4                (1 << 4)
+#define PMD_DOMAIN(x)           ((x) << 5)
+#define PMD_PROTECTION          (1 << 9)        /* v5 */
+/*
+ *   - section
+ */
+#define PMD_SECT_BUFFERABLE     (1 << 2)
+#define PMD_SECT_CACHEABLE      (1 << 3)
+#define PMD_SECT_AP_WRITE       (1 << 10)
+#define PMD_SECT_AP_READ        (1 << 11)
+#define PMD_SECT_TEX(x)         ((x) << 12)     /* v5 */
+#define PMD_SECT_APX            (1 << 15)       /* v6 */
+#define PMD_SECT_S              (1 << 16)       /* v6 */
+#define PMD_SECT_nG             (1 << 17)       /* v6 */
+#define PMD_SECT_SUPER          (1 << 18)       /* v6 */
+
+#define PMD_SECT_UNCACHED       (0)
+#define PMD_SECT_BUFFERED       (PMD_SECT_BUFFERABLE)
+#define PMD_SECT_WT             (PMD_SECT_CACHEABLE)
+#define PMD_SECT_WB             (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
+#define PMD_SECT_MINICACHE      (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
+#define PMD_SECT_WBWA           (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
+
+/*
+ *   - coarse table (not used)
+ */
+
+/*
+ * + Level 2 descriptor (PTE)
+ *   - common
+ */
+#define PTE_TYPE_MASK           (3 << 0)
+#define PTE_TYPE_FAULT          (0 << 0)
+#define PTE_TYPE_LARGE          (1 << 0)
+#define PTE_TYPE_SMALL          (2 << 0)
+#define PTE_TYPE_EXT            (3 << 0)        /* v5 */
+#define PTE_BUFFERABLE          (1 << 2)
+#define PTE_CACHEABLE           (1 << 3)
+
+/*
+ *   - extended small page/tiny page
+ */
+#define PTE_EXT_AP_MASK         (3 << 4)
+#define PTE_EXT_AP_UNO_SRO      (0 << 4)
+#define PTE_EXT_AP_UNO_SRW      (1 << 4)
+#define PTE_EXT_AP_URO_SRW      (2 << 4)
+#define PTE_EXT_AP_URW_SRW      (3 << 4)
+#define PTE_EXT_TEX(x)          ((x) << 6)      /* v5 */
+
+/*
+ *   - small page
+ */
+#define PTE_SMALL_AP_MASK       (0xff << 4)
+#define PTE_SMALL_AP_UNO_SRO    (0x00 << 4)
+#define PTE_SMALL_AP_UNO_SRW    (0x55 << 4)
+#define PTE_SMALL_AP_URO_SRW    (0xaa << 4)
+#define PTE_SMALL_AP_URW_SRW    (0xff << 4)
+
+/*
+ * "Linux" PTE definitions.
+ *
+ * We keep two sets of PTEs - the hardware and the linux version.
+ * This allows greater flexibility in the way we map the Linux bits
+ * onto the hardware tables, and allows us to have YOUNG and DIRTY
+ * bits.
+ *
+ * The PTE table pointer refers to the hardware entries; the "Linux"
+ * entries are stored 1024 bytes below.
+ */
+#define L_PTE_PRESENT           (1 << 0)
+#define L_PTE_FILE              (1 << 1)        /* only when !PRESENT */
+#define L_PTE_YOUNG             (1 << 1)
+#define L_PTE_BUFFERABLE        (1 << 2)        /* matches PTE */
+#define L_PTE_CACHEABLE         (1 << 3)        /* matches PTE */
+#define L_PTE_USER              (1 << 4)
+#define L_PTE_WRITE             (1 << 5)
+#define L_PTE_EXEC              (1 << 6)
+#define L_PTE_DIRTY             (1 << 7)
+
+#ifndef __ASSEMBLY__
+
+#include <asm/domain.h>
+
+#define _PAGE_USER_TABLE        (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
+#define _PAGE_KERNEL_TABLE      (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
+
+/*
+ * The following macros handle the cache and bufferable bits...
+ */
+#define _L_PTE_DEFAULT  L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE
+#define _L_PTE_READ     L_PTE_USER | L_PTE_EXEC
+
+extern pgprot_t         pgprot_kernel;
+
+#define PAGE_NONE       __pgprot(_L_PTE_DEFAULT)
+#define PAGE_COPY       __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
+#define PAGE_SHARED     __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE)
+#define PAGE_READONLY   __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
+#define PAGE_KERNEL     pgprot_kernel
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The table below defines the page protection levels that we insert into our
+ * Linux page table version.  These get translated into the best that the
+ * architecture can perform.  Note that on most ARM hardware:
+ *  1) We cannot do execute protection
+ *  2) If we could do execute protection, then read is implied
+ *  3) write implies read permissions
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY
+#define __P100  PAGE_READONLY
+#define __P101  PAGE_READONLY
+#define __P110  PAGE_COPY
+#define __P111  PAGE_COPY
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED
+#define __S100  PAGE_READONLY
+#define __S101  PAGE_READONLY
+#define __S110  PAGE_SHARED
+#define __S111  PAGE_SHARED
+
+#ifndef __ASSEMBLY__
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern struct page *empty_zero_page;
+#define ZERO_PAGE(vaddr)        (empty_zero_page)
+
+#define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
+#define pfn_pte(pfn,prot)       (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
+
+#define pte_none(pte)           (!pte_val(pte))
+#define pte_clear(mm,addr,ptep) set_pte_at((mm),(addr),(ptep), __pte(0))
+#define pte_page(pte)           (pfn_to_page(pte_pfn(pte)))
+#define pte_offset_kernel(dir,addr)     (pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_offset_map(dir,addr)        (pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_offset_map_nested(dir,addr) (pmd_page_kernel(*(dir)) + __pte_index(addr))
+#define pte_unmap(pte)          do { } while (0)
+#define pte_unmap_nested(pte)   do { } while (0)
+
+#define set_pte(ptep, pte)      cpu_set_pte(ptep,pte)
+#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+#define pte_present(pte)        (pte_val(pte) & L_PTE_PRESENT)
+#define pte_read(pte)           (pte_val(pte) & L_PTE_USER)
+#define pte_write(pte)          (pte_val(pte) & L_PTE_WRITE)
+#define pte_exec(pte)           (pte_val(pte) & L_PTE_EXEC)
+#define pte_dirty(pte)          (pte_val(pte) & L_PTE_DIRTY)
+#define pte_young(pte)          (pte_val(pte) & L_PTE_YOUNG)
+
+/*
+ * The following only works if pte_present() is not true.
+ */
+#define pte_file(pte)           (pte_val(pte) & L_PTE_FILE)
+#define pte_to_pgoff(x)         (pte_val(x) >> 2)
+#define pgoff_to_pte(x)         __pte(((x) << 2) | L_PTE_FILE)
+
+#define PTE_FILE_MAX_BITS       30
+
+#define PTE_BIT_FUNC(fn,op) \
+static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
+
+/*PTE_BIT_FUNC(rdprotect, &= ~L_PTE_USER);*/
+/*PTE_BIT_FUNC(mkread,    |= L_PTE_USER);*/
+PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
+PTE_BIT_FUNC(mkwrite,   |= L_PTE_WRITE);
+PTE_BIT_FUNC(exprotect, &= ~L_PTE_EXEC);
+PTE_BIT_FUNC(mkexec,    |= L_PTE_EXEC);
+PTE_BIT_FUNC(mkclean,   &= ~L_PTE_DIRTY);
+PTE_BIT_FUNC(mkdirty,   |= L_PTE_DIRTY);
+PTE_BIT_FUNC(mkold,     &= ~L_PTE_YOUNG);
+PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);
+
+/*
+ * Mark the prot value as uncacheable and unbufferable.
+ */
+#define pgprot_noncached(prot)  __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
+#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~L_PTE_CACHEABLE)
+
+#define pmd_none(pmd)           (!pmd_val(pmd))
+#define pmd_present(pmd)        (pmd_val(pmd))
+#define pmd_bad(pmd)            (pmd_val(pmd) & 2)
+
+#define copy_pmd(pmdpd,pmdps)           \
+        do {                            \
+                pmdpd[0] = pmdps[0];    \
+                pmdpd[1] = pmdps[1];    \
+                flush_pmd_entry(pmdpd); \
+        } while (0)
+
+#define pmd_clear(pmdp)                 \
+        do {                            \
+                pmdp[0] = __pmd(0);     \
+                pmdp[1] = __pmd(0);     \
+                clean_pmd_entry(pmdp);  \
+        } while (0)
+
+static inline pte_t *pmd_page_kernel(pmd_t pmd)
+{
+        unsigned long ptr;
+
+        ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
+        ptr += PTRS_PER_PTE * sizeof(void *);
+
+        return __va(ptr);
+}
+
+#define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
+
+/*
+ * Permanent address of a page. We never have highmem, so this is trivial.
+ */
+#define pages_to_mb(x)          ((x) >> (20 - PAGE_SHIFT))
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ */
+#define mk_pte(page,prot)       pfn_pte(page_to_pfn(page),prot)
+
+/*
+ * The "pgd_xxx()" functions here are trivial for a folded two-level
+ * setup: the pgd is never bad, and a pmd always exists (as it's folded
+ * into the pgd entry)
+ */
+#define pgd_none(pgd)           (0)
+#define pgd_bad(pgd)            (0)
+#define pgd_present(pgd)        (1)
+#define pgd_clear(pgdp)         do { } while (0)
+#define set_pgd(pgd,pgdp)       do { } while (0)
+
+#define page_pte_prot(page,prot)        mk_pte(page, prot)
+#define page_pte(page)          mk_pte(page, __pgprot(0))
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(addr)         ((addr) >> PGDIR_SHIFT)
+
+#define pgd_offset(mm, addr)    ((mm)->pgd+pgd_index(addr))
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(addr)      pgd_offset(&init_mm, addr)
+
+/* Find an entry in the second-level page table.. */
+#define pmd_offset(dir, addr)   ((pmd_t *)(dir))
+
+/* Find an entry in the third-level page table.. */
+#define __pte_index(addr)       (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER;
+        pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
+        return pte;
+}
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+/* Encode and decode a swap entry.
+ *
+ * We support up to 32GB of swap on 4k machines
+ */
+#define __swp_type(x)           (((x).val >> 2) & 0x7f)
+#define __swp_offset(x)         ((x).val >> 9)
+#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+/* FIXME: this is not correct */
+#define kern_addr_valid(addr)   (1)
+
+#include <asm-generic/pgtable.h>
+
+/*
+ * We provide our own arch_get_unmapped_area to cope with VIPT caches.
+ */
+#define HAVE_ARCH_UNMAPPED_AREA
+
+/*
+ * remap a physical address `phys' of size `size' with page protection `prot'
+ * into virtual address `from'
+ */
+#define io_remap_page_range(vma,from,phys,size,prot) \
+                remap_pfn_range(vma, from, (phys) >> PAGE_SHIFT, size, prot)
+
+#define io_remap_pfn_range(vma,from,pfn,size,prot) \
+                remap_pfn_range(vma, from, pfn, size, prot)
+
+#define MK_IOSPACE_PFN(space, pfn)      (pfn)
+#define GET_IOSPACE(pfn)                0
+#define GET_PFN(pfn)                    (pfn)
+
+#define pgtable_cache_init() do { } while (0)
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASMARM_PGTABLE_H */
diff --git a/include/asm-arm/poll.h b/include/asm-arm/poll.h
new file mode 100644
index 000000000000..2744ca831f5d
--- /dev/null
+++ b/include/asm-arm/poll.h
@@ -0,0 +1,26 @@
+#ifndef __ASMARM_POLL_H
+#define __ASMARM_POLL_H
+
+/* These are specified by iBCS2 */
+#define POLLIN          0x0001
+#define POLLPRI         0x0002
+#define POLLOUT         0x0004
+#define POLLERR         0x0008
+#define POLLHUP         0x0010
+#define POLLNVAL        0x0020
+
+/* The rest seem to be more-or-less nonstandard. Check them! */
+#define POLLRDNORM      0x0040
+#define POLLRDBAND      0x0080
+#define POLLWRNORM      0x0100
+#define POLLWRBAND      0x0200
+#define POLLMSG         0x0400
+#define POLLREMOVE      0x1000
+
+struct pollfd {
+        int fd;
+        short events;
+        short revents;
+};
+
+#endif
diff --git a/include/asm-arm/posix_types.h b/include/asm-arm/posix_types.h
new file mode 100644
index 000000000000..e142a2a016ca
--- /dev/null
+++ b/include/asm-arm/posix_types.h
@@ -0,0 +1,81 @@
+/*
+ *  linux/include/asm-arm/posix_types.h
+ *
+ *  Copyright (C) 1996-1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   27-06-1996 RMK     Created
+ */
+#ifndef __ARCH_ARM_POSIX_TYPES_H
+#define __ARCH_ARM_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long           __kernel_ino_t;
+typedef unsigned short          __kernel_mode_t;
+typedef unsigned short          __kernel_nlink_t;
+typedef long                    __kernel_off_t;
+typedef int                     __kernel_pid_t;
+typedef unsigned short          __kernel_ipc_pid_t;
+typedef unsigned short          __kernel_uid_t;
+typedef unsigned short          __kernel_gid_t;
+typedef unsigned int            __kernel_size_t;
+typedef int                     __kernel_ssize_t;
+typedef int                     __kernel_ptrdiff_t;
+typedef long                    __kernel_time_t;
+typedef long                    __kernel_suseconds_t;
+typedef long                    __kernel_clock_t;
+typedef int                     __kernel_timer_t;
+typedef int                     __kernel_clockid_t;
+typedef int                     __kernel_daddr_t;
+typedef char *                  __kernel_caddr_t;
+typedef unsigned short          __kernel_uid16_t;
+typedef unsigned short          __kernel_gid16_t;
+typedef unsigned int            __kernel_uid32_t;
+typedef unsigned int            __kernel_gid32_t;
+
+typedef unsigned short          __kernel_old_uid_t;
+typedef unsigned short          __kernel_old_gid_t;
+typedef unsigned short          __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long               __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+        int     val[2];
+#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+        int     __val[2];
+#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef  __FD_SET
+#define __FD_SET(fd, fdsetp) \
+                (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] |= (1<<((fd) & 31)))
+
+#undef  __FD_CLR
+#define __FD_CLR(fd, fdsetp) \
+                (((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] &= ~(1<<((fd) & 31)))
+
+#undef  __FD_ISSET
+#define __FD_ISSET(fd, fdsetp) \
+                ((((fd_set *)(fdsetp))->fds_bits[(fd) >> 5] & (1<<((fd) & 31))) != 0)
+
+#undef  __FD_ZERO
+#define __FD_ZERO(fdsetp) \
+                (memset (fdsetp, 0, sizeof (*(fd_set *)(fdsetp))))
+
+#endif
+
+#endif
diff --git a/include/asm-arm/proc-fns.h b/include/asm-arm/proc-fns.h
new file mode 100644
index 000000000000..7bef2bf6be51
--- /dev/null
+++ b/include/asm-arm/proc-fns.h
@@ -0,0 +1,174 @@
+/*
+ *  linux/include/asm-arm/proc-fns.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROCFNS_H
+#define __ASM_PROCFNS_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+/*
+ * Work out if we need multiple CPU support
+ */
+#undef MULTI_CPU
+#undef CPU_NAME
+
+/*
+ * CPU_NAME - the prefix for CPU related functions
+ */
+
+#ifdef CONFIG_CPU_32
+# ifdef CONFIG_CPU_ARM610
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm6
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM710
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm7
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM720T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm720
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM920T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm920
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM922T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm922
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM925T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm925
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM926T
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm926
+#  endif
+# endif
+# ifdef CONFIG_CPU_SA110
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_sa110
+#  endif
+# endif
+# ifdef CONFIG_CPU_SA1100
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_sa1100
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM1020
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm1020
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM1020E
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm1020e
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM1022
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm1022
+#  endif
+# endif
+# ifdef CONFIG_CPU_ARM1026
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_arm1026
+#  endif
+# endif
+# ifdef CONFIG_CPU_XSCALE
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_xscale
+#  endif
+# endif
+# ifdef CONFIG_CPU_V6
+#  ifdef CPU_NAME
+#   undef  MULTI_CPU
+#   define MULTI_CPU
+#  else
+#   define CPU_NAME cpu_v6
+#  endif
+# endif
+#endif
+
+#ifndef __ASSEMBLY__
+
+#ifndef MULTI_CPU
+#include "asm/cpu-single.h"
+#else
+#include "asm/cpu-multi32.h"
+#endif
+
+#include <asm/memory.h>
+
+#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
+
+#define cpu_get_pgd()   \
+        ({                                              \
+                unsigned long pg;                       \
+                __asm__("mrc    p15, 0, %0, c2, c0, 0"  \
+                         : "=r" (pg) : : "cc");         \
+                pg &= ~0x3fff;                          \
+                (pgd_t *)phys_to_virt(pg);              \
+        })
+
+#endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+#endif /* __ASM_PROCFNS_H */
diff --git a/include/asm-arm/processor.h b/include/asm-arm/processor.h
new file mode 100644
index 000000000000..4a9845997a75
--- /dev/null
+++ b/include/asm-arm/processor.h
@@ -0,0 +1,118 @@
+/*
+ *  linux/include/asm-arm/processor.h
+ *
+ *  Copyright (C) 1995-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_PROCESSOR_H
+#define __ASM_ARM_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#ifdef __KERNEL__
+
+#include <asm/ptrace.h>
+#include <asm/procinfo.h>
+#include <asm/types.h>
+
+#define KERNEL_STACK_SIZE       PAGE_SIZE
+
+union debug_insn {
+        u32     arm;
+        u16     thumb;
+};
+
+struct debug_entry {
+        u32                     address;
+        union debug_insn        insn;
+};
+
+struct debug_info {
+        int                     nsaved;
+        struct debug_entry      bp[2];
+};
+
+struct thread_struct {
+                                                        /* fault info     */
+        unsigned long           address;
+        unsigned long           trap_no;
+        unsigned long           error_code;
+                                                        /* debugging      */
+        struct debug_info       debug;
+};
+
+#define INIT_THREAD  {  }
+
+#define start_thread(regs,pc,sp)                                        \
+({                                                                      \
+        unsigned long *stack = (unsigned long *)sp;                     \
+        set_fs(USER_DS);                                                \
+        memzero(regs->uregs, sizeof(regs->uregs));                      \
+        if (current->personality & ADDR_LIMIT_32BIT)                    \
+                regs->ARM_cpsr = USR_MODE;                              \
+        else                                                            \
+                regs->ARM_cpsr = USR26_MODE;                            \
+        if (elf_hwcap & HWCAP_THUMB && pc & 1)                          \
+                regs->ARM_cpsr |= PSR_T_BIT;                            \
+        regs->ARM_pc = pc & ~1;         /* pc */                        \
+        regs->ARM_sp = sp;              /* sp */                        \
+        regs->ARM_r2 = stack[2];        /* r2 (envp) */                 \
+        regs->ARM_r1 = stack[1];        /* r1 (argv) */                 \
+        regs->ARM_r0 = stack[0];        /* r0 (argc) */                 \
+})
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+extern void release_thread(struct task_struct *);
+
+/* Prepare to copy thread state - unlazy all lazy status */
+#define prepare_to_copy(tsk)    do { } while (0)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define cpu_relax()                     barrier()
+
+/*
+ * Create a new kernel thread
+ */
+extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+
+#define KSTK_EIP(tsk)   (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1019])
+#define KSTK_ESP(tsk)   (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1017])
+
+/*
+ * Prefetching support - only ARMv5.
+ */
+#if __LINUX_ARM_ARCH__ >= 5
+
+#define ARCH_HAS_PREFETCH
+#define prefetch(ptr)                           \
+        ({                                      \
+                __asm__ __volatile__(           \
+                "pld\t%0"                       \
+                :                               \
+                : "o" (*(char *)(ptr))          \
+                : "cc");                        \
+        })
+
+#define ARCH_HAS_PREFETCHW
+#define prefetchw(ptr)  prefetch(ptr)
+
+#define ARCH_HAS_SPINLOCK_PREFETCH
+#define spin_lock_prefetch(x) do { } while (0)
+
+#endif
+
+#endif
+
+#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/include/asm-arm/procinfo.h b/include/asm-arm/procinfo.h
new file mode 100644
index 000000000000..a9c75b2c314f
--- /dev/null
+++ b/include/asm-arm/procinfo.h
@@ -0,0 +1,60 @@
+/*
+ *  linux/include/asm-arm/procinfo.h
+ *
+ *  Copyright (C) 1996-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_PROCINFO_H
+#define __ASM_PROCINFO_H
+
+#ifndef __ASSEMBLY__
+
+struct cpu_tlb_fns;
+struct cpu_user_fns;
+struct cpu_cache_fns;
+struct processor;
+
+/*
+ * Note!  struct processor is always defined if we're
+ * using MULTI_CPU, otherwise this entry is unused,
+ * but still exists.
+ *
+ * NOTE! The following structure is defined by assembly
+ * language, NOT C code.  For more information, check:
+ *  arch/arm/mm/proc-*.S and arch/arm/kernel/head.S
+ */
+struct proc_info_list {
+        unsigned int            cpu_val;
+        unsigned int            cpu_mask;
+        unsigned long           __cpu_mmu_flags;        /* used by head.S */
+        unsigned long           __cpu_flush;            /* used by head.S */
+        const char              *arch_name;
+        const char              *elf_name;
+        unsigned int            elf_hwcap;
+        const char              *cpu_name;
+        struct processor        *proc;
+        struct cpu_tlb_fns      *tlb;
+        struct cpu_user_fns     *user;
+        struct cpu_cache_fns    *cache;
+};
+
+extern unsigned int elf_hwcap;
+
+#endif  /* __ASSEMBLY__ */
+
+#define PROC_INFO_SZ    48
+
+#define HWCAP_SWP       1
+#define HWCAP_HALF      2
+#define HWCAP_THUMB     4
+#define HWCAP_26BIT     8       /* Play it safe */
+#define HWCAP_FAST_MULT 16
+#define HWCAP_FPA       32
+#define HWCAP_VFP       64
+#define HWCAP_EDSP      128
+#define HWCAP_JAVA      256
+
+#endif
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
new file mode 100644
index 000000000000..604e3a186cf9
--- /dev/null
+++ b/include/asm-arm/ptrace.h
@@ -0,0 +1,155 @@
+/*
+ *  linux/include/asm-arm/ptrace.h
+ *
+ *  Copyright (C) 1996-2003 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_PTRACE_H
+#define __ASM_ARM_PTRACE_H
+
+#include <linux/config.h>
+
+#define PTRACE_GETREGS          12
+#define PTRACE_SETREGS          13
+#define PTRACE_GETFPREGS        14
+#define PTRACE_SETFPREGS        15
+
+#define PTRACE_GETWMMXREGS      18
+#define PTRACE_SETWMMXREGS      19
+
+#define PTRACE_OLDSETOPTIONS    21
+
+#define PTRACE_GET_THREAD_AREA  22
+/*
+ * PSR bits
+ */
+#define USR26_MODE      0x00000000
+#define FIQ26_MODE      0x00000001
+#define IRQ26_MODE      0x00000002
+#define SVC26_MODE      0x00000003
+#define USR_MODE        0x00000010
+#define FIQ_MODE        0x00000011
+#define IRQ_MODE        0x00000012
+#define SVC_MODE        0x00000013
+#define ABT_MODE        0x00000017
+#define UND_MODE        0x0000001b
+#define SYSTEM_MODE     0x0000001f
+#define MODE32_BIT      0x00000010
+#define MODE_MASK       0x0000001f
+#define PSR_T_BIT       0x00000020
+#define PSR_F_BIT       0x00000040
+#define PSR_I_BIT       0x00000080
+#define PSR_J_BIT       0x01000000
+#define PSR_Q_BIT       0x08000000
+#define PSR_V_BIT       0x10000000
+#define PSR_C_BIT       0x20000000
+#define PSR_Z_BIT       0x40000000
+#define PSR_N_BIT       0x80000000
+#define PCMASK          0
+
+/*
+ * Groups of PSR bits
+ */
+#define PSR_f           0xff000000      /* Flags                */
+#define PSR_s           0x00ff0000      /* Status               */
+#define PSR_x           0x0000ff00      /* Extension            */
+#define PSR_c           0x000000ff      /* Control              */
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+        long uregs[18];
+};
+
+#define ARM_cpsr        uregs[16]
+#define ARM_pc          uregs[15]
+#define ARM_lr          uregs[14]
+#define ARM_sp          uregs[13]
+#define ARM_ip          uregs[12]
+#define ARM_fp          uregs[11]
+#define ARM_r10         uregs[10]
+#define ARM_r9          uregs[9]
+#define ARM_r8          uregs[8]
+#define ARM_r7          uregs[7]
+#define ARM_r6          uregs[6]
+#define ARM_r5          uregs[5]
+#define ARM_r4          uregs[4]
+#define ARM_r3          uregs[3]
+#define ARM_r2          uregs[2]
+#define ARM_r1          uregs[1]
+#define ARM_r0          uregs[0]
+#define ARM_ORIG_r0     uregs[17]
+
+#ifdef __KERNEL__
+
+#define user_mode(regs) \
+        (((regs)->ARM_cpsr & 0xf) == 0)
+
+#ifdef CONFIG_ARM_THUMB
+#define thumb_mode(regs) \
+        (((regs)->ARM_cpsr & PSR_T_BIT))
+#else
+#define thumb_mode(regs) (0)
+#endif
+
+#define processor_mode(regs) \
+        ((regs)->ARM_cpsr & MODE_MASK)
+
+#define interrupts_enabled(regs) \
+        (!((regs)->ARM_cpsr & PSR_I_BIT))
+
+#define fast_interrupts_enabled(regs) \
+        (!((regs)->ARM_cpsr & PSR_F_BIT))
+
+#define condition_codes(regs) \
+        ((regs)->ARM_cpsr & (PSR_V_BIT|PSR_C_BIT|PSR_Z_BIT|PSR_N_BIT))
+        
+/* Are the current registers suitable for user mode?
+ * (used to maintain security in signal handlers)
+ */
+static inline int valid_user_regs(struct pt_regs *regs)
+{
+        if (user_mode(regs) &&
+            (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0)
+                return 1;
+
+        /*
+         * Force CPSR to something logical...
+         */
+        regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
+
+        return 0;
+}
+
+#endif  /* __KERNEL__ */
+
+#define pc_pointer(v) \
+        ((v) & ~PCMASK)
+
+#define instruction_pointer(regs) \
+        (pc_pointer((regs)->ARM_pc))
+
+#ifdef CONFIG_SMP
+extern unsigned long profile_pc(struct pt_regs *regs);
+#else
+#define profile_pc(regs) instruction_pointer(regs)
+#endif
+
+#ifdef __KERNEL__
+extern void show_regs(struct pt_regs *);
+
+#define predicate(x)    (x & 0xf0000000)
+#define PREDICATE_ALWAYS        0xe0000000
+
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif
+
diff --git a/include/asm-arm/resource.h b/include/asm-arm/resource.h
new file mode 100644
index 000000000000..734b581b5b6a
--- /dev/null
+++ b/include/asm-arm/resource.h
@@ -0,0 +1,6 @@
+#ifndef _ARM_RESOURCE_H
+#define _ARM_RESOURCE_H
+
+#include <asm-generic/resource.h>
+
+#endif
diff --git a/include/asm-arm/rtc.h b/include/asm-arm/rtc.h
new file mode 100644
index 000000000000..aa7e16b2e225
--- /dev/null
+++ b/include/asm-arm/rtc.h
@@ -0,0 +1,46 @@
+/*
+ *  linux/include/asm-arm/rtc.h
+ *
+ *  Copyright (C) 2003 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef ASMARM_RTC_H
+#define ASMARM_RTC_H
+
+struct module;
+
+struct rtc_ops {
+        struct module   *owner;
+        int             (*open)(void);
+        void            (*release)(void);
+        int             (*ioctl)(unsigned int, unsigned long);
+
+        void            (*read_time)(struct rtc_time *);
+        int             (*set_time)(struct rtc_time *);
+        void            (*read_alarm)(struct rtc_wkalrm *);
+        int             (*set_alarm)(struct rtc_wkalrm *);
+        int             (*proc)(char *buf);
+};
+
+void rtc_time_to_tm(unsigned long, struct rtc_time *);
+int rtc_tm_to_time(struct rtc_time *, unsigned long *);
+int rtc_valid_tm(struct rtc_time *);
+void rtc_next_alarm_time(struct rtc_time *, struct rtc_time *, struct rtc_time *);
+void rtc_update(unsigned long, unsigned long);
+int register_rtc(struct rtc_ops *);
+void unregister_rtc(struct rtc_ops *);
+
+static inline int rtc_periodic_alarm(struct rtc_time *tm)
+{
+        return  (tm->tm_year == -1) ||
+                ((unsigned)tm->tm_mon >= 12) ||
+                ((unsigned)(tm->tm_mday - 1) >= 31) ||
+                ((unsigned)tm->tm_hour > 23) ||
+                ((unsigned)tm->tm_min > 59) ||
+                ((unsigned)tm->tm_sec > 59);
+}
+
+#endif
diff --git a/include/asm-arm/scatterlist.h b/include/asm-arm/scatterlist.h
new file mode 100644
index 000000000000..83b876fb04cc
--- /dev/null
+++ b/include/asm-arm/scatterlist.h
@@ -0,0 +1,25 @@
+#ifndef _ASMARM_SCATTERLIST_H
+#define _ASMARM_SCATTERLIST_H
+
+#include <asm/memory.h>
+#include <asm/types.h>
+
+struct scatterlist {
+        struct page     *page;          /* buffer page                   */
+        unsigned int    offset;         /* buffer offset                 */
+        dma_addr_t      dma_address;    /* dma address                   */
+        unsigned int    length;         /* length                        */
+        char            *__address;     /* for set_dma_addr              */
+};
+
+/*
+ * These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->length)
+
+#endif /* _ASMARM_SCATTERLIST_H */
diff --git a/include/asm-arm/sections.h b/include/asm-arm/sections.h
new file mode 100644
index 000000000000..2b8c5160388f
--- /dev/null
+++ b/include/asm-arm/sections.h
@@ -0,0 +1 @@
+#include <asm-generic/sections.h>
diff --git a/include/asm-arm/segment.h b/include/asm-arm/segment.h
new file mode 100644
index 000000000000..9e24c21f6304
--- /dev/null
+++ b/include/asm-arm/segment.h
@@ -0,0 +1,11 @@
+#ifndef __ASM_ARM_SEGMENT_H
+#define __ASM_ARM_SEGMENT_H
+
+#define __KERNEL_CS   0x0
+#define __KERNEL_DS   0x0
+
+#define __USER_CS     0x1
+#define __USER_DS     0x1
+
+#endif /* __ASM_ARM_SEGMENT_H */
+
diff --git a/include/asm-arm/semaphore-helper.h b/include/asm-arm/semaphore-helper.h
new file mode 100644
index 000000000000..1d7f1987edb9
--- /dev/null
+++ b/include/asm-arm/semaphore-helper.h
@@ -0,0 +1,84 @@
+#ifndef ASMARM_SEMAPHORE_HELPER_H
+#define ASMARM_SEMAPHORE_HELPER_H
+
+/*
+ * These two _must_ execute atomically wrt each other.
+ */
+static inline void wake_one_more(struct semaphore * sem)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&semaphore_wake_lock, flags);
+        if (atomic_read(&sem->count) <= 0)
+                sem->waking++;
+        spin_unlock_irqrestore(&semaphore_wake_lock, flags);
+}
+
+static inline int waking_non_zero(struct semaphore *sem)
+{
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&semaphore_wake_lock, flags);
+        if (sem->waking > 0) {
+                sem->waking--;
+                ret = 1;
+        }
+        spin_unlock_irqrestore(&semaphore_wake_lock, flags);
+        return ret;
+}
+
+/*
+ * waking non zero interruptible
+ *      1       got the lock
+ *      0       go to sleep
+ *      -EINTR  interrupted
+ *
+ * We must undo the sem->count down_interruptible() increment while we are
+ * protected by the spinlock in order to make this atomic_inc() with the
+ * atomic_read() in wake_one_more(), otherwise we can race. -arca
+ */
+static inline int waking_non_zero_interruptible(struct semaphore *sem,
+                                                struct task_struct *tsk)
+{
+        unsigned long flags;
+        int ret = 0;
+
+        spin_lock_irqsave(&semaphore_wake_lock, flags);
+        if (sem->waking > 0) {
+                sem->waking--;
+                ret = 1;
+        } else if (signal_pending(tsk)) {
+                atomic_inc(&sem->count);
+                ret = -EINTR;
+        }
+        spin_unlock_irqrestore(&semaphore_wake_lock, flags);
+        return ret;     
+}
+
+/*
+ * waking_non_zero_try_lock:
+ *      1       failed to lock
+ *      0       got the lock
+ *
+ * We must undo the sem->count down_interruptible() increment while we are
+ * protected by the spinlock in order to make this atomic_inc() with the
+ * atomic_read() in wake_one_more(), otherwise we can race. -arca
+ */
+static inline int waking_non_zero_trylock(struct semaphore *sem)
+{
+        unsigned long flags;
+        int ret = 1;
+
+        spin_lock_irqsave(&semaphore_wake_lock, flags);
+        if (sem->waking <= 0)
+                atomic_inc(&sem->count);
+        else {
+                sem->waking--;
+                ret = 0;
+        }
+        spin_unlock_irqrestore(&semaphore_wake_lock, flags);
+        return ret;
+}
+
+#endif
diff --git a/include/asm-arm/semaphore.h b/include/asm-arm/semaphore.h
new file mode 100644
index 000000000000..60f33e6eb800
--- /dev/null
+++ b/include/asm-arm/semaphore.h
@@ -0,0 +1,106 @@
+/*
+ * linux/include/asm-arm/semaphore.h
+ */
+#ifndef __ASM_ARM_SEMAPHORE_H
+#define __ASM_ARM_SEMAPHORE_H
+
+#include <linux/linkage.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <linux/rwsem.h>
+
+#include <asm/atomic.h>
+#include <asm/locks.h>
+
+struct semaphore {
+        atomic_t count;
+        int sleepers;
+        wait_queue_head_t wait;
+};
+
+#define __SEMAPHORE_INIT(name, cnt)                             \
+{                                                               \
+        .count  = ATOMIC_INIT(cnt),                             \
+        .wait   = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait),   \
+}
+
+#define __MUTEX_INITIALIZER(name) __SEMAPHORE_INIT(name,1)
+
+#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
+        struct semaphore name = __SEMAPHORE_INIT(name,count)
+
+#define DECLARE_MUTEX(name)             __DECLARE_SEMAPHORE_GENERIC(name,1)
+#define DECLARE_MUTEX_LOCKED(name)      __DECLARE_SEMAPHORE_GENERIC(name,0)
+
+static inline void sema_init(struct semaphore *sem, int val)
+{
+        atomic_set(&sem->count, val);
+        sem->sleepers = 0;
+        init_waitqueue_head(&sem->wait);
+}
+
+static inline void init_MUTEX(struct semaphore *sem)
+{
+        sema_init(sem, 1);
+}
+
+static inline void init_MUTEX_LOCKED(struct semaphore *sem)
+{
+        sema_init(sem, 0);
+}
+
+static inline int sema_count(struct semaphore *sem)
+{
+        return atomic_read(&sem->count);
+}
+
+/*
+ * special register calling convention
+ */
+asmlinkage void __down_failed(void);
+asmlinkage int  __down_interruptible_failed(void);
+asmlinkage int  __down_trylock_failed(void);
+asmlinkage void __up_wakeup(void);
+
+extern void __down(struct semaphore * sem);
+extern int  __down_interruptible(struct semaphore * sem);
+extern int  __down_trylock(struct semaphore * sem);
+extern void __up(struct semaphore * sem);
+
+/*
+ * This is ugly, but we want the default case to fall through.
+ * "__down" is the actual routine that waits...
+ */
+static inline void down(struct semaphore * sem)
+{
+        might_sleep();
+        __down_op(sem, __down_failed);
+}
+
+/*
+ * This is ugly, but we want the default case to fall through.
+ * "__down_interruptible" is the actual routine that waits...
+ */
+static inline int down_interruptible (struct semaphore * sem)
+{
+        might_sleep();
+        return __down_op_ret(sem, __down_interruptible_failed);
+}
+
+static inline int down_trylock(struct semaphore *sem)
+{
+        return __down_op_ret(sem, __down_trylock_failed);
+}
+
+/*
+ * Note! This is subtle. We jump to wake people up only if
+ * the semaphore was negative (== somebody was waiting on it).
+ * The default case (no contention) will result in NO
+ * jumps for both down() and up().
+ */
+static inline void up(struct semaphore * sem)
+{
+        __up_op(sem, __up_wakeup);
+}
+
+#endif
diff --git a/include/asm-arm/sembuf.h b/include/asm-arm/sembuf.h
new file mode 100644
index 000000000000..1c0283954289
--- /dev/null
+++ b/include/asm-arm/sembuf.h
@@ -0,0 +1,25 @@
+#ifndef _ASMARM_SEMBUF_H
+#define _ASMARM_SEMBUF_H
+
+/* 
+ * The semid64_ds structure for arm architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;              /* last semop time */
+        unsigned long   __unused1;
+        __kernel_time_t sem_ctime;              /* last change time */
+        unsigned long   __unused2;
+        unsigned long   sem_nsems;              /* no. of semaphores in array */
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _ASMARM_SEMBUF_H */
diff --git a/include/asm-arm/serial.h b/include/asm-arm/serial.h
new file mode 100644
index 000000000000..015b262dc145
--- /dev/null
+++ b/include/asm-arm/serial.h
@@ -0,0 +1,19 @@
+/*
+ *  linux/include/asm-arm/serial.h
+ *
+ *  Copyright (C) 1996 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Changelog:
+ *   15-10-1996 RMK     Created
+ */
+
+#ifndef __ASM_SERIAL_H
+#define __ASM_SERIAL_H
+
+#define BASE_BAUD       (1843200 / 16)
+
+#endif
diff --git a/include/asm-arm/setup.h b/include/asm-arm/setup.h
new file mode 100644
index 000000000000..adcbd79762bf
--- /dev/null
+++ b/include/asm-arm/setup.h
@@ -0,0 +1,218 @@
+/*
+ *  linux/include/asm/setup.h
+ *
+ *  Copyright (C) 1997-1999 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Structure passed to kernel to tell it about the
+ *  hardware it's running on.  See Documentation/arm/Setup
+ *  for more info.
+ */
+#ifndef __ASMARM_SETUP_H
+#define __ASMARM_SETUP_H
+
+#define COMMAND_LINE_SIZE 1024
+
+/* The list ends with an ATAG_NONE node. */
+#define ATAG_NONE       0x00000000
+
+struct tag_header {
+        u32 size;
+        u32 tag;
+};
+
+/* The list must start with an ATAG_CORE node */
+#define ATAG_CORE       0x54410001
+
+struct tag_core {
+        u32 flags;              /* bit 0 = read-only */
+        u32 pagesize;
+        u32 rootdev;
+};
+
+/* it is allowed to have multiple ATAG_MEM nodes */
+#define ATAG_MEM        0x54410002
+
+struct tag_mem32 {
+        u32     size;
+        u32     start;  /* physical start address */
+};
+
+/* VGA text type displays */
+#define ATAG_VIDEOTEXT  0x54410003
+
+struct tag_videotext {
+        u8              x;
+        u8              y;
+        u16             video_page;
+        u8              video_mode;
+        u8              video_cols;
+        u16             video_ega_bx;
+        u8              video_lines;
+        u8              video_isvga;
+        u16             video_points;
+};
+
+/* describes how the ramdisk will be used in kernel */
+#define ATAG_RAMDISK    0x54410004
+
+struct tag_ramdisk {
+        u32 flags;      /* bit 0 = load, bit 1 = prompt */
+        u32 size;       /* decompressed ramdisk size in _kilo_ bytes */
+        u32 start;      /* starting block of floppy-based RAM disk image */
+};
+
+/* describes where the compressed ramdisk image lives (virtual address) */
+/*
+ * this one accidentally used virtual addresses - as such,
+ * it's deprecated.
+ */
+#define ATAG_INITRD     0x54410005
+
+/* describes where the compressed ramdisk image lives (physical address) */
+#define ATAG_INITRD2    0x54420005
+
+struct tag_initrd {
+        u32 start;      /* physical start address */
+        u32 size;       /* size of compressed ramdisk image in bytes */
+};
+
+/* board serial number. "64 bits should be enough for everybody" */
+#define ATAG_SERIAL     0x54410006
+
+struct tag_serialnr {
+        u32 low;
+        u32 high;
+};
+
+/* board revision */
+#define ATAG_REVISION   0x54410007
+
+struct tag_revision {
+        u32 rev;
+};
+
+/* initial values for vesafb-type framebuffers. see struct screen_info
+ * in include/linux/tty.h
+ */
+#define ATAG_VIDEOLFB   0x54410008
+
+struct tag_videolfb {
+        u16             lfb_width;
+        u16             lfb_height;
+        u16             lfb_depth;
+        u16             lfb_linelength;
+        u32             lfb_base;
+        u32             lfb_size;
+        u8              red_size;
+        u8              red_pos;
+        u8              green_size;
+        u8              green_pos;
+        u8              blue_size;
+        u8              blue_pos;
+        u8              rsvd_size;
+        u8              rsvd_pos;
+};
+
+/* command line: \0 terminated string */
+#define ATAG_CMDLINE    0x54410009
+
+struct tag_cmdline {
+        char    cmdline[1];     /* this is the minimum size */
+};
+
+/* acorn RiscPC specific information */
+#define ATAG_ACORN      0x41000101
+
+struct tag_acorn {
+        u32 memc_control_reg;
+        u32 vram_pages;
+        u8 sounddefault;
+        u8 adfsdrives;
+};
+
+/* footbridge memory clock, see arch/arm/mach-footbridge/arch.c */
+#define ATAG_MEMCLK     0x41000402
+
+struct tag_memclk {
+        u32 fmemclk;
+};
+
+struct tag {
+        struct tag_header hdr;
+        union {
+                struct tag_core         core;
+                struct tag_mem32        mem;
+                struct tag_videotext    videotext;
+                struct tag_ramdisk      ramdisk;
+                struct tag_initrd       initrd;
+                struct tag_serialnr     serialnr;
+                struct tag_revision     revision;
+                struct tag_videolfb     videolfb;
+                struct tag_cmdline      cmdline;
+
+                /*
+                 * Acorn specific
+                 */
+                struct tag_acorn        acorn;
+
+                /*
+                 * DC21285 specific
+                 */
+                struct tag_memclk       memclk;
+        } u;
+};
+
+struct tagtable {
+        u32 tag;
+        int (*parse)(const struct tag *);
+};
+
+#define __tag __attribute_used__ __attribute__((__section__(".taglist")))
+#define __tagtable(tag, fn) \
+static struct tagtable __tagtable_##fn __tag = { tag, fn }
+
+#define tag_member_present(tag,member)                          \
+        ((unsigned long)(&((struct tag *)0L)->member + 1)       \
+                <= (tag)->hdr.size * 4)
+
+#define tag_next(t)     ((struct tag *)((u32 *)(t) + (t)->hdr.size))
+#define tag_size(type)  ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
+
+#define for_each_tag(t,base)            \
+        for (t = base; t->hdr.size; t = tag_next(t))
+
+/*
+ * Memory map description
+ */
+#ifdef CONFIG_ARCH_LH7A40X
+# define NR_BANKS 16
+#else
+# define NR_BANKS 8
+#endif
+
+struct meminfo {
+        int nr_banks;
+        struct {
+                unsigned long start;
+                unsigned long size;
+                int           node;
+        } bank[NR_BANKS];
+};
+
+/*
+ * Early command line parameters.
+ */
+struct early_params {
+        const char *arg;
+        void (*fn)(char **p);
+};
+
+#define __early_param(name,fn)                                  \
+static struct early_params __early_##fn __attribute_used__      \
+__attribute__((__section__("__early_param"))) = { name, fn }
+
+#endif
diff --git a/include/asm-arm/shmbuf.h b/include/asm-arm/shmbuf.h
new file mode 100644
index 000000000000..2e5c67ba1c97
--- /dev/null
+++ b/include/asm-arm/shmbuf.h
@@ -0,0 +1,42 @@
+#ifndef _ASMARM_SHMBUF_H
+#define _ASMARM_SHMBUF_H
+
+/* 
+ * The shmid64_ds structure for arm architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm       shm_perm;       /* operation perms */
+        size_t                  shm_segsz;      /* size of segment (bytes) */
+        __kernel_time_t         shm_atime;      /* last attach time */
+        unsigned long           __unused1;
+        __kernel_time_t         shm_dtime;      /* last detach time */
+        unsigned long           __unused2;
+        __kernel_time_t         shm_ctime;      /* last change time */
+        unsigned long           __unused3;
+        __kernel_pid_t          shm_cpid;       /* pid of creator */
+        __kernel_pid_t          shm_lpid;       /* pid of last operator */
+        unsigned long           shm_nattch;     /* no. of current attaches */
+        unsigned long           __unused4;
+        unsigned long           __unused5;
+};
+
+struct shminfo64 {
+        unsigned long   shmmax;
+        unsigned long   shmmin;
+        unsigned long   shmmni;
+        unsigned long   shmseg;
+        unsigned long   shmall;
+        unsigned long   __unused1;
+        unsigned long   __unused2;
+        unsigned long   __unused3;
+        unsigned long   __unused4;
+};
+
+#endif /* _ASMARM_SHMBUF_H */
diff --git a/include/asm-arm/shmparam.h b/include/asm-arm/shmparam.h
new file mode 100644
index 000000000000..a5223b3a9bf9
--- /dev/null
+++ b/include/asm-arm/shmparam.h
@@ -0,0 +1,16 @@
+#ifndef _ASMARM_SHMPARAM_H
+#define _ASMARM_SHMPARAM_H
+
+/*
+ * This should be the size of the virtually indexed cache/ways,
+ * or page size, whichever is greater since the cache aliases
+ * every size/ways bytes.
+ */
+#define SHMLBA  (4 * PAGE_SIZE)          /* attach addr a multiple of this */
+
+/*
+ * Enforce SHMLBA in shmat
+ */
+#define __ARCH_FORCE_SHMLBA
+
+#endif /* _ASMARM_SHMPARAM_H */
diff --git a/include/asm-arm/sigcontext.h b/include/asm-arm/sigcontext.h
new file mode 100644
index 000000000000..fc0b80b6a6fc
--- /dev/null
+++ b/include/asm-arm/sigcontext.h
@@ -0,0 +1,34 @@
+#ifndef _ASMARM_SIGCONTEXT_H
+#define _ASMARM_SIGCONTEXT_H
+
+/*
+ * Signal context structure - contains all info to do with the state
+ * before the signal handler was invoked.  Note: only add new entries
+ * to the end of the structure.
+ */
+struct sigcontext {
+        unsigned long trap_no;
+        unsigned long error_code;
+        unsigned long oldmask;
+        unsigned long arm_r0;
+        unsigned long arm_r1;
+        unsigned long arm_r2;
+        unsigned long arm_r3;
+        unsigned long arm_r4;
+        unsigned long arm_r5;
+        unsigned long arm_r6;
+        unsigned long arm_r7;
+        unsigned long arm_r8;
+        unsigned long arm_r9;
+        unsigned long arm_r10;
+        unsigned long arm_fp;
+        unsigned long arm_ip;
+        unsigned long arm_sp;
+        unsigned long arm_lr;
+        unsigned long arm_pc;
+        unsigned long arm_cpsr;
+        unsigned long fault_address;
+};
+
+
+#endif
diff --git a/include/asm-arm/siginfo.h b/include/asm-arm/siginfo.h
new file mode 100644
index 000000000000..5e21852e6039
--- /dev/null
+++ b/include/asm-arm/siginfo.h
@@ -0,0 +1,6 @@
+#ifndef _ASMARM_SIGINFO_H
+#define _ASMARM_SIGINFO_H
+
+#include <asm-generic/siginfo.h>
+
+#endif
diff --git a/include/asm-arm/signal.h b/include/asm-arm/signal.h
new file mode 100644
index 000000000000..b033e5fd60fa
--- /dev/null
+++ b/include/asm-arm/signal.h
@@ -0,0 +1,194 @@
+#ifndef _ASMARM_SIGNAL_H
+#define _ASMARM_SIGNAL_H
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+
+#ifdef __KERNEL__
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+#define _NSIG           64
+#define _NSIG_BPW       32
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t;             /* at least 32 bits */
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+#define NSIG            32
+typedef unsigned long sigset_t;
+
+#endif /* __KERNEL__ */
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+#define SIGSWI          32
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_NOCLDSTOP         flag to turn off SIGCHLD when children stop.
+ * SA_NOCLDWAIT         flag on SIGCHLD to inhibit zombies.
+ * SA_SIGINFO           deliver the signal with SIGINFO structs
+ * SA_THIRTYTWO         delivers the signal in 32-bit mode, even if the task 
+ *                      is running in 26-bit.
+ * SA_ONSTACK           allows alternate signal stacks (see sigaltstack(2)).
+ * SA_RESTART           flag to get restarting signals (which were the default long ago)
+ * SA_INTERRUPT         is a no-op, but left due to historical reasons. Use the
+ * SA_NODEFER           prevents the current signal from being masked in the handler.
+ * SA_RESETHAND         clears the handler when the signal is delivered.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001
+#define SA_NOCLDWAIT    0x00000002
+#define SA_SIGINFO      0x00000004
+#define SA_THIRTYTWO    0x02000000
+#define SA_RESTORER     0x04000000
+#define SA_ONSTACK      0x08000000
+#define SA_RESTART      0x10000000
+#define SA_NODEFER      0x40000000
+#define SA_RESETHAND    0x80000000
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+#define SA_INTERRUPT    0x20000000 /* dummy -- ignored */
+
+
+/* 
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+
+#ifdef __KERNEL__
+
+/*
+ * These values of sa_flags are used only by the kernel as part of the
+ * irq handling routines.
+ *
+ * SA_INTERRUPT is also used by the irq handling routines.
+ * SA_SHIRQ is for shared interrupt support on PCI and EISA.
+ */
+#define SA_PROBE                0x80000000
+#define SA_SAMPLE_RANDOM        0x10000000
+#define SA_IRQNOMASK            0x08000000
+#define SA_SHIRQ                0x04000000
+#endif
+
+#define SIG_BLOCK          0    /* for blocking signals */
+#define SIG_UNBLOCK        1    /* for unblocking signals */
+#define SIG_SETMASK        2    /* for setting the signal mask */
+
+/* Type of a signal handler.  */
+typedef void __signalfn_t(int);
+typedef __signalfn_t __user *__sighandler_t;
+
+typedef void __restorefn_t(void);
+typedef __restorefn_t __user *__sigrestore_t;
+
+#define SIG_DFL ((__sighandler_t)0)     /* default signal handling */
+#define SIG_IGN ((__sighandler_t)1)     /* ignore signal */
+#define SIG_ERR ((__sighandler_t)-1)    /* error return from signal */
+
+#ifdef __KERNEL__
+struct old_sigaction {
+        __sighandler_t sa_handler;
+        old_sigset_t sa_mask;
+        unsigned long sa_flags;
+        __sigrestore_t sa_restorer;
+};
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        __sigrestore_t sa_restorer;
+        sigset_t sa_mask;               /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+struct sigaction {
+        union {
+          __sighandler_t _sa_handler;
+          void (*_sa_sigaction)(int, struct siginfo *, void *);
+        } _u;
+        sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer)(void);
+};
+
+#define sa_handler      _u._sa_handler
+#define sa_sigaction    _u._sa_sigaction
+
+#endif /* __KERNEL__ */
+
+typedef struct sigaltstack {
+        void __user *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+#include <asm/sigcontext.h>
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+#endif
+
+#endif
diff --git a/include/asm-arm/sizes.h b/include/asm-arm/sizes.h
new file mode 100644
index 000000000000..7f50ae0edf1b
--- /dev/null
+++ b/include/asm-arm/sizes.h
@@ -0,0 +1,52 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+/* DO NOT EDIT!! - this file automatically generated
+ *                 from .s file by awk -f s2h.awk
+ */
+/*  Size definitions
+ *  Copyright (C) ARM Limited 1998. All rights reserved.
+ */
+
+#ifndef __sizes_h
+#define __sizes_h                       1
+
+/* handy sizes */
+#define SZ_1K                           0x00000400
+#define SZ_4K                           0x00001000
+#define SZ_8K                           0x00002000
+#define SZ_16K                          0x00004000
+#define SZ_64K                          0x00010000
+#define SZ_128K                         0x00020000
+#define SZ_256K                         0x00040000
+#define SZ_512K                         0x00080000
+
+#define SZ_1M                           0x00100000
+#define SZ_2M                           0x00200000
+#define SZ_4M                           0x00400000
+#define SZ_8M                           0x00800000
+#define SZ_16M                          0x01000000
+#define SZ_32M                          0x02000000
+#define SZ_64M                          0x04000000
+#define SZ_128M                         0x08000000
+#define SZ_256M                         0x10000000
+#define SZ_512M                         0x20000000
+
+#define SZ_1G                           0x40000000
+#define SZ_2G                           0x80000000
+
+#endif
+
+/*         END */
diff --git a/include/asm-arm/smp.h b/include/asm-arm/smp.h
new file mode 100644
index 000000000000..f21fd8f6bcdd
--- /dev/null
+++ b/include/asm-arm/smp.h
@@ -0,0 +1,58 @@
+/*
+ *  linux/include/asm-arm/smp.h
+ *
+ *  Copyright (C) 2004-2005 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_SMP_H
+#define __ASM_ARM_SMP_H
+
+#include <linux/config.h>
+#include <linux/threads.h>
+#include <linux/cpumask.h>
+#include <linux/thread_info.h>
+
+#include <asm/arch/smp.h>
+
+#ifndef CONFIG_SMP
+# error "<asm-arm/smp.h> included in non-SMP build"
+#endif
+
+#define smp_processor_id()      (current_thread_info()->cpu)
+
+extern cpumask_t cpu_present_mask;
+#define cpu_possible_map cpu_present_mask
+
+/*
+ * at the moment, there's not a big penalty for changing CPUs
+ * (the >big< penalty is running SMP in the first place)
+ */
+#define PROC_CHANGE_PENALTY             15
+
+struct seq_file;
+
+/*
+ * generate IPI list text
+ */
+extern void show_ipi_list(struct seq_file *p);
+
+/*
+ * Move global data into per-processor storage.
+ */
+extern void smp_store_cpu_info(unsigned int cpuid);
+
+/*
+ * Raise an IPI cross call on CPUs in callmap.
+ */
+extern void smp_cross_call(cpumask_t callmap);
+
+/*
+ * Boot a secondary CPU, and assign it the specified idle task.
+ * This also gives us the initial stack to use for this CPU.
+ */
+extern int boot_secondary(unsigned int cpu, struct task_struct *);
+
+#endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/include/asm-arm/socket.h b/include/asm-arm/socket.h
new file mode 100644
index 000000000000..46d20585d951
--- /dev/null
+++ b/include/asm-arm/socket.h
@@ -0,0 +1,50 @@
+#ifndef _ASMARM_SOCKET_H
+#define _ASMARM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockopt(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED     16
+#define SO_PEERCRED     17
+#define SO_RCVLOWAT     18
+#define SO_SNDLOWAT     19
+#define SO_RCVTIMEO     20
+#define SO_SNDTIMEO     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+
+#define SO_PEERSEC              31
+
+#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-arm/sockios.h b/include/asm-arm/sockios.h
new file mode 100644
index 000000000000..77c34087d513
--- /dev/null
+++ b/include/asm-arm/sockios.h
@@ -0,0 +1,12 @@
+#ifndef __ARCH_ARM_SOCKIOS_H
+#define __ARCH_ARM_SOCKIOS_H
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906          /* Get stamp */
+
+#endif
diff --git a/include/asm-arm/spinlock.h b/include/asm-arm/spinlock.h
new file mode 100644
index 000000000000..182323619caa
--- /dev/null
+++ b/include/asm-arm/spinlock.h
@@ -0,0 +1,169 @@
+#ifndef __ASM_SPINLOCK_H
+#define __ASM_SPINLOCK_H
+
+#if __LINUX_ARM_ARCH__ < 6
+#error SMP not supported on pre-ARMv6 CPUs
+#endif
+
+/*
+ * ARMv6 Spin-locking.
+ *
+ * We (exclusively) read the old value, and decrement it.  If it
+ * hits zero, we may have won the lock, so we try (exclusively)
+ * storing it.
+ *
+ * Unlocked value: 0
+ * Locked value: 1
+ */
+typedef struct {
+        volatile unsigned int lock;
+#ifdef CONFIG_PREEMPT
+        unsigned int break_lock;
+#endif
+} spinlock_t;
+
+#define SPIN_LOCK_UNLOCKED      (spinlock_t) { 0 }
+
+#define spin_lock_init(x)       do { *(x) = SPIN_LOCK_UNLOCKED; } while (0)
+#define spin_is_locked(x)       ((x)->lock != 0)
+#define spin_unlock_wait(x)     do { barrier(); } while (spin_is_locked(x))
+#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
+
+static inline void _raw_spin_lock(spinlock_t *lock)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__(
+"1:     ldrex   %0, [%1]\n"
+"       teq     %0, #0\n"
+"       strexeq %0, %2, [%1]\n"
+"       teqeq   %0, #0\n"
+"       bne     1b"
+        : "=&r" (tmp)
+        : "r" (&lock->lock), "r" (1)
+        : "cc", "memory");
+}
+
+static inline int _raw_spin_trylock(spinlock_t *lock)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__(
+"       ldrex   %0, [%1]\n"
+"       teq     %0, #0\n"
+"       strexeq %0, %2, [%1]"
+        : "=&r" (tmp)
+        : "r" (&lock->lock), "r" (1)
+        : "cc", "memory");
+
+        return tmp == 0;
+}
+
+static inline void _raw_spin_unlock(spinlock_t *lock)
+{
+        __asm__ __volatile__(
+"       str     %1, [%0]"
+        :
+        : "r" (&lock->lock), "r" (0)
+        : "cc", "memory");
+}
+
+/*
+ * RWLOCKS
+ */
+typedef struct {
+        volatile unsigned int lock;
+#ifdef CONFIG_PREEMPT
+        unsigned int break_lock;
+#endif
+} rwlock_t;
+
+#define RW_LOCK_UNLOCKED        (rwlock_t) { 0 }
+#define rwlock_init(x)          do { *(x) + RW_LOCK_UNLOCKED; } while (0)
+
+/*
+ * Write locks are easy - we just set bit 31.  When unlocking, we can
+ * just write zero since the lock is exclusively held.
+ */
+static inline void _raw_write_lock(rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__(
+"1:     ldrex   %0, [%1]\n"
+"       teq     %0, #0\n"
+"       strexeq %0, %2, [%1]\n"
+"       teq     %0, #0\n"
+"       bne     1b"
+        : "=&r" (tmp)
+        : "r" (&rw->lock), "r" (0x80000000)
+        : "cc", "memory");
+}
+
+static inline void _raw_write_unlock(rwlock_t *rw)
+{
+        __asm__ __volatile__(
+        "str    %1, [%0]"
+        :
+        : "r" (&rw->lock), "r" (0)
+        : "cc", "memory");
+}
+
+/*
+ * Read locks are a bit more hairy:
+ *  - Exclusively load the lock value.
+ *  - Increment it.
+ *  - Store new lock value if positive, and we still own this location.
+ *    If the value is negative, we've already failed.
+ *  - If we failed to store the value, we want a negative result.
+ *  - If we failed, try again.
+ * Unlocking is similarly hairy.  We may have multiple read locks
+ * currently active.  However, we know we won't have any write
+ * locks.
+ */
+static inline void _raw_read_lock(rwlock_t *rw)
+{
+        unsigned long tmp, tmp2;
+
+        __asm__ __volatile__(
+"1:     ldrex   %0, [%2]\n"
+"       adds    %0, %0, #1\n"
+"       strexpl %1, %0, [%2]\n"
+"       rsbpls  %0, %1, #0\n"
+"       bmi     1b"
+        : "=&r" (tmp), "=&r" (tmp2)
+        : "r" (&rw->lock)
+        : "cc", "memory");
+}
+
+static inline void _raw_read_unlock(rwlock_t *rw)
+{
+        __asm__ __volatile__(
+"1:     ldrex   %0, [%2]\n"
+"       sub     %0, %0, #1\n"
+"       strex   %1, %0, [%2]\n"
+"       teq     %1, #0\n"
+"       bne     1b"
+        : "=&r" (tmp), "=&r" (tmp2)
+        : "r" (&rw->lock)
+        : "cc", "memory");
+}
+
+#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
+
+static inline int _raw_write_trylock(rwlock_t *rw)
+{
+        unsigned long tmp;
+
+        __asm__ __volatile__(
+"1:     ldrex   %0, [%1]\n"
+"       teq     %0, #0\n"
+"       strexeq %0, %2, [%1]"
+        : "=&r" (tmp)
+        : "r" (&rw->lock), "r" (0x80000000)
+        : "cc", "memory");
+
+        return tmp == 0;
+}
+
+#endif /* __ASM_SPINLOCK_H */
diff --git a/include/asm-arm/stat.h b/include/asm-arm/stat.h
new file mode 100644
index 000000000000..ca8e7a8436da
--- /dev/null
+++ b/include/asm-arm/stat.h
@@ -0,0 +1,94 @@
+#ifndef _ASMARM_STAT_H
+#define _ASMARM_STAT_H
+
+struct __old_kernel_stat {
+        unsigned short st_dev;
+        unsigned short st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned long  st_size;
+        unsigned long  st_atime;
+        unsigned long  st_mtime;
+        unsigned long  st_ctime;
+};
+
+#define STAT_HAVE_NSEC 
+
+struct stat {
+#if defined(__ARMEB__)
+        unsigned short st_dev;
+        unsigned short __pad1;
+#else
+        unsigned long  st_dev;
+#endif
+        unsigned long  st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+#if defined(__ARMEB__)
+        unsigned short st_rdev;
+        unsigned short __pad2;
+#else
+        unsigned long  st_rdev;
+#endif
+        unsigned long  st_size;
+        unsigned long  st_blksize;
+        unsigned long  st_blocks;
+        unsigned long  st_atime;
+        unsigned long  st_atime_nsec;
+        unsigned long  st_mtime;
+        unsigned long  st_mtime_nsec;
+        unsigned long  st_ctime;
+        unsigned long  st_ctime_nsec;
+        unsigned long  __unused4;
+        unsigned long  __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ * Note: The kernel zero's the padded region because glibc might read them
+ * in the hope that the kernel has stretched to using larger sizes.
+ */
+struct stat64 {
+        unsigned long long      st_dev;
+        unsigned char   __pad0[4];
+
+#define STAT64_HAS_BROKEN_ST_INO        1
+        unsigned long   __st_ino;
+        unsigned int    st_mode;
+        unsigned int    st_nlink;
+
+        unsigned long   st_uid;
+        unsigned long   st_gid;
+
+        unsigned long long      st_rdev;
+        unsigned char   __pad3[4];
+
+        long long       st_size;
+        unsigned long   st_blksize;
+
+#if defined(__ARMEB__)
+        unsigned long   __pad4;         /* Future possible st_blocks hi bits */
+        unsigned long   st_blocks;      /* Number 512-byte blocks allocated. */
+#else /* Must be little */
+        unsigned long   st_blocks;      /* Number 512-byte blocks allocated. */
+        unsigned long   __pad4;         /* Future possible st_blocks hi bits */
+#endif
+
+        unsigned long   st_atime;
+        unsigned long   st_atime_nsec;
+
+        unsigned long   st_mtime;
+        unsigned long   st_mtime_nsec;
+
+        unsigned long   st_ctime;
+        unsigned long   st_ctime_nsec;
+
+        unsigned long long      st_ino;
+};
+
+#endif
diff --git a/include/asm-arm/statfs.h b/include/asm-arm/statfs.h
new file mode 100644
index 000000000000..e81f82783b87
--- /dev/null
+++ b/include/asm-arm/statfs.h
@@ -0,0 +1,6 @@
+#ifndef _ASMARM_STATFS_H
+#define _ASMARM_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif
diff --git a/include/asm-arm/string.h b/include/asm-arm/string.h
new file mode 100644
index 000000000000..2a8ab162412f
--- /dev/null
+++ b/include/asm-arm/string.h
@@ -0,0 +1,43 @@
+#ifndef __ASM_ARM_STRING_H
+#define __ASM_ARM_STRING_H
+
+/*
+ * We don't do inline string functions, since the
+ * optimised inline asm versions are not small.
+ */
+
+#define __HAVE_ARCH_STRRCHR
+extern char * strrchr(const char * s, int c);
+
+#define __HAVE_ARCH_STRCHR
+extern char * strchr(const char * s, int c);
+
+#define __HAVE_ARCH_MEMCPY
+extern void * memcpy(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMMOVE
+extern void * memmove(void *, const void *, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMCHR
+extern void * memchr(const void *, int, __kernel_size_t);
+
+#define __HAVE_ARCH_MEMZERO
+#define __HAVE_ARCH_MEMSET
+extern void * memset(void *, int, __kernel_size_t);
+
+extern void __memzero(void *ptr, __kernel_size_t n);
+
+#define memset(p,v,n)                                                   \
+        ({                                                              \
+                if ((n) != 0) {                                         \
+                        if (__builtin_constant_p((v)) && (v) == 0)      \
+                                __memzero((p),(n));                     \
+                        else                                            \
+                                memset((p),(v),(n));                    \
+                }                                                       \
+                (p);                                                    \
+        })
+
+#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
+
+#endif
diff --git a/include/asm-arm/suspend.h b/include/asm-arm/suspend.h
new file mode 100644
index 000000000000..cf0d0bdee74d
--- /dev/null
+++ b/include/asm-arm/suspend.h
@@ -0,0 +1,4 @@
+#ifndef _ASMARM_SUSPEND_H
+#define _ASMARM_SUSPEND_H
+
+#endif
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
new file mode 100644
index 000000000000..b5731290b4e5
--- /dev/null
+++ b/include/asm-arm/system.h
@@ -0,0 +1,390 @@
+#ifndef __ASM_ARM_SYSTEM_H
+#define __ASM_ARM_SYSTEM_H
+
+#ifdef __KERNEL__
+
+#include <linux/config.h>
+
+#define CPU_ARCH_UNKNOWN        0
+#define CPU_ARCH_ARMv3          1
+#define CPU_ARCH_ARMv4          2
+#define CPU_ARCH_ARMv4T         3
+#define CPU_ARCH_ARMv5          4
+#define CPU_ARCH_ARMv5T         5
+#define CPU_ARCH_ARMv5TE        6
+#define CPU_ARCH_ARMv5TEJ       7
+#define CPU_ARCH_ARMv6          8
+
+/*
+ * CR1 bits (CP#15 CR1)
+ */
+#define CR_M    (1 << 0)        /* MMU enable                           */
+#define CR_A    (1 << 1)        /* Alignment abort enable               */
+#define CR_C    (1 << 2)        /* Dcache enable                        */
+#define CR_W    (1 << 3)        /* Write buffer enable                  */
+#define CR_P    (1 << 4)        /* 32-bit exception handler             */
+#define CR_D    (1 << 5)        /* 32-bit data address range            */
+#define CR_L    (1 << 6)        /* Implementation defined               */
+#define CR_B    (1 << 7)        /* Big endian                           */
+#define CR_S    (1 << 8)        /* System MMU protection                */
+#define CR_R    (1 << 9)        /* ROM MMU protection                   */
+#define CR_F    (1 << 10)       /* Implementation defined               */
+#define CR_Z    (1 << 11)       /* Implementation defined               */
+#define CR_I    (1 << 12)       /* Icache enable                        */
+#define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
+#define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
+#define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
+#define CR_DT   (1 << 16)
+#define CR_IT   (1 << 18)
+#define CR_ST   (1 << 19)
+#define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
+#define CR_U    (1 << 22)       /* Unaligned access operation           */
+#define CR_XP   (1 << 23)       /* Extended page tables                 */
+#define CR_VE   (1 << 24)       /* Vectored interrupts                  */
+
+#define CPUID_ID        0
+#define CPUID_CACHETYPE 1
+#define CPUID_TCM       2
+#define CPUID_TLBTYPE   3
+
+#define read_cpuid(reg)                                                 \
+        ({                                                              \
+                unsigned int __val;                                     \
+                asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
+                    : "=r" (__val)                                      \
+                    :                                                   \
+                    : "cc");                                            \
+                __val;                                                  \
+        })
+
+/*
+ * This is used to ensure the compiler did actually allocate the register we
+ * asked it for some inline assembly sequences.  Apparently we can't trust
+ * the compiler from one version to another so a bit of paranoia won't hurt.
+ * This string is meant to be concatenated with the inline asm string and
+ * will cause compilation to stop on mismatch.
+ * (for details, see gcc PR 15089)
+ */
+#define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+#ifndef __ASSEMBLY__
+
+#include <linux/linkage.h>
+
+struct thread_info;
+struct task_struct;
+
+/* information about the system we're running on */
+extern unsigned int system_rev;
+extern unsigned int system_serial_low;
+extern unsigned int system_serial_high;
+extern unsigned int mem_fclk_21285;
+
+struct pt_regs;
+
+void die(const char *msg, struct pt_regs *regs, int err)
+                __attribute__((noreturn));
+
+void die_if_kernel(const char *str, struct pt_regs *regs, int err);
+
+void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
+                                       struct pt_regs *),
+                     int sig, const char *name);
+
+#include <asm/proc-fns.h>
+
+#define xchg(ptr,x) \
+        ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+#define tas(ptr) (xchg((ptr),1))
+
+extern asmlinkage void __backtrace(void);
+
+extern int cpu_architecture(void);
+
+#define set_cr(x)                                       \
+        __asm__ __volatile__(                           \
+        "mcr    p15, 0, %0, c1, c0, 0   @ set CR"       \
+        : : "r" (x) : "cc")
+
+#define get_cr()                                        \
+        ({                                              \
+        unsigned int __val;                             \
+        __asm__ __volatile__(                           \
+        "mrc    p15, 0, %0, c1, c0, 0   @ get CR"       \
+        : "=r" (__val) : : "cc");                       \
+        __val;                                          \
+        })
+
+extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
+extern unsigned long cr_alignment;      /* defined in entry-armv.S */
+
+#define UDBG_UNDEFINED  (1 << 0)
+#define UDBG_SYSCALL    (1 << 1)
+#define UDBG_BADABORT   (1 << 2)
+#define UDBG_SEGV       (1 << 3)
+#define UDBG_BUS        (1 << 4)
+
+extern unsigned int user_debug;
+
+#if __LINUX_ARM_ARCH__ >= 4
+#define vectors_high()  (cr_alignment & CR_V)
+#else
+#define vectors_high()  (0)
+#endif
+
+#define mb() __asm__ __volatile__ ("" : : : "memory")
+#define rmb() mb()
+#define wmb() mb()
+#define read_barrier_depends() do { } while(0)
+#define set_mb(var, value)  do { var = value; mb(); } while (0)
+#define set_wmb(var, value) do { var = value; wmb(); } while (0)
+#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
+
+#ifdef CONFIG_SMP
+/*
+ * Define our own context switch locking.  This allows us to enable
+ * interrupts over the context switch, otherwise we end up with high
+ * interrupt latency.  The real problem area is switch_mm() which may
+ * do a full cache flush.
+ */
+#define prepare_arch_switch(rq,next)                                    \
+do {                                                                    \
+        spin_lock(&(next)->switch_lock);                                \
+        spin_unlock_irq(&(rq)->lock);                                   \
+} while (0)
+
+#define finish_arch_switch(rq,prev)                                     \
+        spin_unlock(&(prev)->switch_lock)
+
+#define task_running(rq,p)                                              \
+        ((rq)->curr == (p) || spin_is_locked(&(p)->switch_lock))
+#else
+/*
+ * Our UP-case is more simple, but we assume knowledge of how
+ * spin_unlock_irq() and friends are implemented.  This avoids
+ * us needlessly decrementing and incrementing the preempt count.
+ */
+#define prepare_arch_switch(rq,next)    local_irq_enable()
+#define finish_arch_switch(rq,prev)     spin_unlock(&(rq)->lock)
+#define task_running(rq,p)              ((rq)->curr == (p))
+#endif
+
+/*
+ * switch_to(prev, next) should switch from task `prev' to `next'
+ * `prev' will never be the same as `next'.  schedule() itself
+ * contains the memory barrier to tell GCC not to cache `current'.
+ */
+extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
+
+#define switch_to(prev,next,last)                                       \
+do {                                                                    \
+        last = __switch_to(prev,prev->thread_info,next->thread_info);   \
+} while (0)
+
+/*
+ * CPU interrupt mask handling.
+ */
+#if __LINUX_ARM_ARCH__ >= 6
+
+#define local_irq_save(x)                                       \
+        ({                                                      \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_save\n"     \
+        "cpsid  i"                                              \
+        : "=r" (x) : : "memory", "cc");                         \
+        })
+
+#define local_irq_enable()  __asm__("cpsie i    @ __sti" : : : "memory", "cc")
+#define local_irq_disable() __asm__("cpsid i    @ __cli" : : : "memory", "cc")
+#define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
+#define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
+
+#else
+
+/*
+ * Save the current interrupt enable state & disable IRQs
+ */
+#define local_irq_save(x)                                       \
+        ({                                                      \
+                unsigned long temp;                             \
+                (void) (&temp == &x);                           \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_save\n"     \
+"       orr     %1, %0, #128\n"                                 \
+"       msr     cpsr_c, %1"                                     \
+        : "=r" (x), "=r" (temp)                                 \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+        
+/*
+ * Enable IRQs
+ */
+#define local_irq_enable()                                      \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_enable\n"   \
+"       bic     %0, %0, #128\n"                                 \
+"       msr     cpsr_c, %0"                                     \
+        : "=r" (temp)                                           \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+
+/*
+ * Disable IRQs
+ */
+#define local_irq_disable()                                     \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_irq_disable\n"  \
+"       orr     %0, %0, #128\n"                                 \
+"       msr     cpsr_c, %0"                                     \
+        : "=r" (temp)                                           \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+
+/*
+ * Enable FIQs
+ */
+#define local_fiq_enable()                                      \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ stf\n"                \
+"       bic     %0, %0, #64\n"                                  \
+"       msr     cpsr_c, %0"                                     \
+        : "=r" (temp)                                           \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+
+/*
+ * Disable FIQs
+ */
+#define local_fiq_disable()                                     \
+        ({                                                      \
+                unsigned long temp;                             \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ clf\n"                \
+"       orr     %0, %0, #64\n"                                  \
+"       msr     cpsr_c, %0"                                     \
+        : "=r" (temp)                                           \
+        :                                                       \
+        : "memory", "cc");                                      \
+        })
+
+#endif
+
+/*
+ * Save the current interrupt enable state.
+ */
+#define local_save_flags(x)                                     \
+        ({                                                      \
+        __asm__ __volatile__(                                   \
+        "mrs    %0, cpsr                @ local_save_flags"     \
+        : "=r" (x) : : "memory", "cc");                         \
+        })
+
+/*
+ * restore saved IRQ & FIQ state
+ */
+#define local_irq_restore(x)                                    \
+        __asm__ __volatile__(                                   \
+        "msr    cpsr_c, %0              @ local_irq_restore\n"  \
+        :                                                       \
+        : "r" (x)                                               \
+        : "memory", "cc")
+
+#define irqs_disabled()                 \
+({                                      \
+        unsigned long flags;            \
+        local_save_flags(flags);        \
+        flags & PSR_I_BIT;              \
+})
+
+#ifdef CONFIG_SMP
+#error SMP not supported
+
+#define smp_mb()                mb()
+#define smp_rmb()               rmb()
+#define smp_wmb()               wmb()
+#define smp_read_barrier_depends()              read_barrier_depends()
+
+#else
+
+#define smp_mb()                barrier()
+#define smp_rmb()               barrier()
+#define smp_wmb()               barrier()
+#define smp_read_barrier_depends()              do { } while(0)
+
+#if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
+/*
+ * On the StrongARM, "swp" is terminally broken since it bypasses the
+ * cache totally.  This means that the cache becomes inconsistent, and,
+ * since we use normal loads/stores as well, this is really bad.
+ * Typically, this causes oopsen in filp_close, but could have other,
+ * more disasterous effects.  There are two work-arounds:
+ *  1. Disable interrupts and emulate the atomic swap
+ *  2. Clean the cache, perform atomic swap, flush the cache
+ *
+ * We choose (1) since its the "easiest" to achieve here and is not
+ * dependent on the processor type.
+ */
+#define swp_is_buggy
+#endif
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
+{
+        extern void __bad_xchg(volatile void *, int);
+        unsigned long ret;
+#ifdef swp_is_buggy
+        unsigned long flags;
+#endif
+
+        switch (size) {
+#ifdef swp_is_buggy
+                case 1:
+                        local_irq_save(flags);
+                        ret = *(volatile unsigned char *)ptr;
+                        *(volatile unsigned char *)ptr = x;
+                        local_irq_restore(flags);
+                        break;
+
+                case 4:
+                        local_irq_save(flags);
+                        ret = *(volatile unsigned long *)ptr;
+                        *(volatile unsigned long *)ptr = x;
+                        local_irq_restore(flags);
+                        break;
+#else
+                case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
+                                        : "=&r" (ret)
+                                        : "r" (x), "r" (ptr)
+                                        : "memory", "cc");
+                        break;
+                case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
+                                        : "=&r" (ret)
+                                        : "r" (x), "r" (ptr)
+                                        : "memory", "cc");
+                        break;
+#endif
+                default: __bad_xchg(ptr, size), ret = 0;
+        }
+
+        return ret;
+}
+
+#endif /* CONFIG_SMP */
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+
+#endif
diff --git a/include/asm-arm/termbits.h b/include/asm-arm/termbits.h
new file mode 100644
index 000000000000..bbc6e1d24d3f
--- /dev/null
+++ b/include/asm-arm/termbits.h
@@ -0,0 +1,171 @@
+#ifndef __ASM_ARM_TERMBITS_H
+#define __ASM_ARM_TERMBITS_H
+
+typedef unsigned char   cc_t;
+typedef unsigned int    speed_t;
+typedef unsigned int    tcflag_t;
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IUCLC   0001000
+#define IXON    0002000
+#define IXANY   0004000
+#define IXOFF   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define OLCUC   0000002
+#define ONLCR   0000004
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060
+#define   CS5   0000000
+#define   CS6   0000020
+#define   CS7   0000040
+#define   CS8   0000060
+#define CSTOPB  0000100
+#define CREAD   0000200
+#define PARENB  0000400
+#define PARODD  0001000
+#define HUPCL   0002000
+#define CLOCAL  0004000
+#define CBAUDEX 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000  /* input baud rate (not used) */
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
+#define CRTSCTS   020000000000          /* flow control */
+
+/* c_lflag bits */
+#define ISIG    0000001
+#define ICANON  0000002
+#define XCASE   0000004
+#define ECHO    0000010
+#define ECHOE   0000020
+#define ECHOK   0000040
+#define ECHONL  0000100
+#define NOFLSH  0000200
+#define TOSTOP  0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE  0004000
+#define FLUSHO  0010000
+#define PENDIN  0040000
+#define IEXTEN  0100000
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif  /* __ASM_ARM_TERMBITS_H */
diff --git a/include/asm-arm/termios.h b/include/asm-arm/termios.h
new file mode 100644
index 000000000000..7b8f5e8ae063
--- /dev/null
+++ b/include/asm-arm/termios.h
@@ -0,0 +1,108 @@
+#ifndef __ASM_ARM_TERMIOS_H
+#define __ASM_ARM_TERMIOS_H
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag;         /* input mode flags */
+        unsigned short c_oflag;         /* output mode flags */
+        unsigned short c_cflag;         /* control mode flags */
+        unsigned short c_lflag;         /* local mode flags */
+        unsigned char c_line;           /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+#ifdef __KERNEL__
+/*      intr=^C         quit=^|         erase=del       kill=^U
+        eof=^D          vtime=\0        vmin=\1         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         eol=\0
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+#endif
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+/* line disciplines */
+#define N_TTY           0
+#define N_SLIP          1
+#define N_MOUSE         2
+#define N_PPP           3
+#define N_STRIP         4
+#define N_AX25          5
+#define N_X25           6       /* X.25 async */
+#define N_6PACK         7
+#define N_MASC          8       /* Reserved for Mobitex module <kaz@cafe.net> */
+#define N_R3964         9       /* Reserved for Simatic R3964 module */
+#define N_PROFIBUS_FDL  10      /* Reserved for Profibus <Dave@mvhi.com> */
+#define N_IRDA          11      /* Linux IrDa - http://irda.sourceforge.net/ */
+#define N_SMSBLOCK      12      /* SMS block mode - for talking to GSM data cards about SMS messages */
+#define N_HDLC          13      /* synchronous HDLC */
+#define N_SYNC_PPP      14
+#define N_HCI           15  /* Bluetooth HCI UART */
+
+#ifdef __KERNEL__
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) {              \
+        unsigned short __tmp;                                   \
+        get_user(__tmp,&(termio)->x);                           \
+        *(unsigned short *) &(termios)->x = __tmp;              \
+}
+
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line,  &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif  /* __KERNEL__ */
+
+#endif  /* __ASM_ARM_TERMIOS_H */
diff --git a/include/asm-arm/therm.h b/include/asm-arm/therm.h
new file mode 100644
index 000000000000..e51c923ecdf3
--- /dev/null
+++ b/include/asm-arm/therm.h
@@ -0,0 +1,28 @@
+/*
+ * linux/include/asm-arm/therm.h: Definitions for Dallas Semiconductor
+ *  DS1620 thermometer driver (as used in the Rebel.com NetWinder)
+ */
+#ifndef __ASM_THERM_H
+#define __ASM_THERM_H
+
+/* ioctl numbers for /dev/therm */
+#define CMD_SET_THERMOSTATE     0x53
+#define CMD_GET_THERMOSTATE     0x54
+#define CMD_GET_STATUS          0x56
+#define CMD_GET_TEMPERATURE     0x57
+#define CMD_SET_THERMOSTATE2    0x58
+#define CMD_GET_THERMOSTATE2    0x59
+#define CMD_GET_TEMPERATURE2    0x5a
+#define CMD_GET_FAN             0x5b
+#define CMD_SET_FAN             0x5c
+
+#define FAN_OFF                 0
+#define FAN_ON                  1
+#define FAN_ALWAYS_ON           2
+
+struct therm {
+        int hi;
+        int lo;
+};
+
+#endif
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
new file mode 100644
index 000000000000..a61618fb433c
--- /dev/null
+++ b/include/asm-arm/thread_info.h
@@ -0,0 +1,147 @@
+/*
+ *  linux/include/asm-arm/thread_info.h
+ *
+ *  Copyright (C) 2002 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARM_THREAD_INFO_H
+#define __ASM_ARM_THREAD_INFO_H
+
+#ifdef __KERNEL__
+
+#include <asm/fpstate.h>
+
+#ifndef __ASSEMBLY__
+
+struct task_struct;
+struct exec_domain;
+
+#include <asm/ptrace.h>
+#include <asm/types.h>
+#include <asm/domain.h>
+
+typedef unsigned long mm_segment_t;
+
+struct cpu_context_save {
+        __u32   r4;
+        __u32   r5;
+        __u32   r6;
+        __u32   r7;
+        __u32   r8;
+        __u32   r9;
+        __u32   sl;
+        __u32   fp;
+        __u32   sp;
+        __u32   pc;
+        __u32   extra[2];               /* Xscale 'acc' register, etc */
+};
+
+/*
+ * low level task data that entry.S needs immediate access to.
+ * __switch_to() assumes cpu_context follows immediately after cpu_domain.
+ */
+struct thread_info {
+        unsigned long           flags;          /* low level flags */
+        __s32                   preempt_count;  /* 0 => preemptable, <0 => bug */
+        mm_segment_t            addr_limit;     /* address limit */
+        struct task_struct      *task;          /* main task structure */
+        struct exec_domain      *exec_domain;   /* execution domain */
+        __u32                   cpu;            /* cpu */
+        __u32                   cpu_domain;     /* cpu domain */
+        struct cpu_context_save cpu_context;    /* cpu context */
+        __u8                    used_cp[16];    /* thread used copro */
+        unsigned long           tp_value;
+        union fp_state          fpstate;
+        union vfp_state         vfpstate;
+        struct restart_block    restart_block;
+};
+
+#define INIT_THREAD_INFO(tsk)                                           \
+{                                                                       \
+        .task           = &tsk,                                         \
+        .exec_domain    = &default_exec_domain,                         \
+        .flags          = 0,                                            \
+        .preempt_count  = 1,                                            \
+        .addr_limit     = KERNEL_DS,                                    \
+        .cpu_domain     = domain_val(DOMAIN_USER, DOMAIN_MANAGER) |     \
+                          domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) |   \
+                          domain_val(DOMAIN_IO, DOMAIN_CLIENT),         \
+        .restart_block  = {                                             \
+                .fn     = do_no_restart_syscall,                        \
+        },                                                              \
+}
+
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+#define THREAD_SIZE             8192
+
+/*
+ * how to get the thread information struct from C
+ */
+static inline struct thread_info *current_thread_info(void) __attribute_const__;
+
+static inline struct thread_info *current_thread_info(void)
+{
+        register unsigned long sp asm ("sp");
+        return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
+}
+
+extern struct thread_info *alloc_thread_info(struct task_struct *task);
+extern void free_thread_info(struct thread_info *);
+
+#define get_thread_info(ti)     get_task_struct((ti)->task)
+#define put_thread_info(ti)     put_task_struct((ti)->task)
+
+#define thread_saved_pc(tsk)    \
+        ((unsigned long)(pc_pointer((tsk)->thread_info->cpu_context.pc)))
+#define thread_saved_fp(tsk)    \
+        ((unsigned long)((tsk)->thread_info->cpu_context.fp))
+
+extern void iwmmxt_task_disable(struct thread_info *);
+extern void iwmmxt_task_copy(struct thread_info *, void *);
+extern void iwmmxt_task_restore(struct thread_info *, void *);
+extern void iwmmxt_task_release(struct thread_info *);
+
+#endif
+
+/*
+ * We use bit 30 of the preempt_count to indicate that kernel
+ * preemption is occuring.  See include/asm-arm/hardirq.h.
+ */
+#define PREEMPT_ACTIVE  0x40000000
+
+/*
+ * thread information flags:
+ *  TIF_SYSCALL_TRACE   - syscall trace active
+ *  TIF_NOTIFY_RESUME   - resumption notification requested
+ *  TIF_SIGPENDING      - signal pending
+ *  TIF_NEED_RESCHED    - rescheduling necessary
+ *  TIF_USEDFPU         - FPU was used by this task this quantum (SMP)
+ *  TIF_POLLING_NRFLAG  - true if poll_idle() is polling TIF_NEED_RESCHED
+ */
+#define TIF_NOTIFY_RESUME       0
+#define TIF_SIGPENDING          1
+#define TIF_NEED_RESCHED        2
+#define TIF_SYSCALL_TRACE       8
+#define TIF_POLLING_NRFLAG      16
+#define TIF_USING_IWMMXT        17
+#define TIF_MEMDIE              18
+
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
+#define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
+#define _TIF_POLLING_NRFLAG     (1 << TIF_POLLING_NRFLAG)
+#define _TIF_USING_IWMMXT       (1 << TIF_USING_IWMMXT)
+
+/*
+ * Change these and you break ASM code in entry-common.S
+ */
+#define _TIF_WORK_MASK          0x000000ff
+
+#endif /* __KERNEL__ */
+#endif /* __ASM_ARM_THREAD_INFO_H */
diff --git a/include/asm-arm/timex.h b/include/asm-arm/timex.h
new file mode 100644
index 000000000000..7b8d4cb24be0
--- /dev/null
+++ b/include/asm-arm/timex.h
@@ -0,0 +1,24 @@
+/*
+ *  linux/include/asm-arm/timex.h
+ *
+ *  Copyright (C) 1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Architecture Specific TIME specifications
+ */
+#ifndef _ASMARM_TIMEX_H
+#define _ASMARM_TIMEX_H
+
+#include <asm/arch/timex.h>
+
+typedef unsigned long cycles_t;
+
+static inline cycles_t get_cycles (void)
+{
+        return 0;
+}
+
+#endif
diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h
new file mode 100644
index 000000000000..9bb325c54645
--- /dev/null
+++ b/include/asm-arm/tlb.h
@@ -0,0 +1,102 @@
+/*
+ *  linux/include/asm-arm/tlb.h
+ *
+ *  Copyright (C) 2002 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ *  Experimentation shows that on a StrongARM, it appears to be faster
+ *  to use the "invalidate whole tlb" rather than "invalidate single
+ *  tlb" for this.
+ *
+ *  This appears true for both the process fork+exit case, as well as
+ *  the munmap-large-area case.
+ */
+#ifndef __ASMARM_TLB_H
+#define __ASMARM_TLB_H
+
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <asm/pgalloc.h>
+
+/*
+ * TLB handling.  This allows us to remove pages from the page
+ * tables, and efficiently handle the TLB issues.
+ */
+struct mmu_gather {
+        struct mm_struct        *mm;
+        unsigned int            freed;
+        unsigned int            fullmm;
+
+        unsigned int            flushes;
+        unsigned int            avoided_flushes;
+};
+
+DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
+
+static inline struct mmu_gather *
+tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+{
+        int cpu = smp_processor_id();
+        struct mmu_gather *tlb = &per_cpu(mmu_gathers, cpu);
+
+        tlb->mm = mm;
+        tlb->freed = 0;
+        tlb->fullmm = full_mm_flush;
+
+        return tlb;
+}
+
+static inline void
+tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
+{
+        struct mm_struct *mm = tlb->mm;
+        unsigned long freed = tlb->freed;
+        int rss = get_mm_counter(mm, rss);
+
+        if (rss < freed)
+                freed = rss;
+        add_mm_counter(mm, rss, -freed);
+
+        if (tlb->fullmm)
+                flush_tlb_mm(mm);
+
+        /* keep the page table cache within bounds */
+        check_pgt_cache();
+}
+
+static inline unsigned int tlb_is_full_mm(struct mmu_gather *tlb)
+{
+        return tlb->fullmm;
+}
+
+#define tlb_remove_tlb_entry(tlb,ptep,address)  do { } while (0)
+
+/*
+ * In the case of tlb vma handling, we can optimise these away in the
+ * case where we're doing a full MM flush.  When we're doing a munmap,
+ * the vmas are adjusted to only cover the region to be torn down.
+ */
+static inline void
+tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
+{
+        if (!tlb->fullmm)
+                flush_cache_range(vma, vma->vm_start, vma->vm_end);
+}
+
+static inline void
+tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
+{
+        if (!tlb->fullmm)
+                flush_tlb_range(vma, vma->vm_start, vma->vm_end);
+}
+
+#define tlb_remove_page(tlb,page)       free_page_and_swap_cache(page)
+#define pte_free_tlb(tlb,ptep)          pte_free(ptep)
+#define pmd_free_tlb(tlb,pmdp)          pmd_free(pmdp)
+
+#define tlb_migrate_finish(mm)          do { } while (0)
+
+#endif
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
new file mode 100644
index 000000000000..8a864b118569
--- /dev/null
+++ b/include/asm-arm/tlbflush.h
@@ -0,0 +1,404 @@
+/*
+ *  linux/include/asm-arm/tlbflush.h
+ *
+ *  Copyright (C) 1999-2003 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASMARM_TLBFLUSH_H
+#define _ASMARM_TLBFLUSH_H
+
+#include <linux/config.h>
+#include <asm/glue.h>
+
+#define TLB_V3_PAGE     (1 << 0)
+#define TLB_V4_U_PAGE   (1 << 1)
+#define TLB_V4_D_PAGE   (1 << 2)
+#define TLB_V4_I_PAGE   (1 << 3)
+#define TLB_V6_U_PAGE   (1 << 4)
+#define TLB_V6_D_PAGE   (1 << 5)
+#define TLB_V6_I_PAGE   (1 << 6)
+
+#define TLB_V3_FULL     (1 << 8)
+#define TLB_V4_U_FULL   (1 << 9)
+#define TLB_V4_D_FULL   (1 << 10)
+#define TLB_V4_I_FULL   (1 << 11)
+#define TLB_V6_U_FULL   (1 << 12)
+#define TLB_V6_D_FULL   (1 << 13)
+#define TLB_V6_I_FULL   (1 << 14)
+
+#define TLB_V6_U_ASID   (1 << 16)
+#define TLB_V6_D_ASID   (1 << 17)
+#define TLB_V6_I_ASID   (1 << 18)
+
+#define TLB_DCLEAN      (1 << 30)
+#define TLB_WB          (1 << 31)
+
+/*
+ *      MMU TLB Model
+ *      =============
+ *
+ *      We have the following to choose from:
+ *        v3    - ARMv3
+ *        v4    - ARMv4 without write buffer
+ *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
+ *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
+ *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
+ */
+#undef _TLB
+#undef MULTI_TLB
+
+#define v3_tlb_flags    (TLB_V3_FULL | TLB_V3_PAGE)
+
+#ifdef CONFIG_CPU_TLB_V3
+# define v3_possible_flags      v3_tlb_flags
+# define v3_always_flags        v3_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v3
+# endif
+#else
+# define v3_possible_flags      0
+# define v3_always_flags        (-1UL)
+#endif
+
+#define v4_tlb_flags    (TLB_V4_U_FULL | TLB_V4_U_PAGE)
+
+#ifdef CONFIG_CPU_TLB_V4WT
+# define v4_possible_flags      v4_tlb_flags
+# define v4_always_flags        v4_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v4
+# endif
+#else
+# define v4_possible_flags      0
+# define v4_always_flags        (-1UL)
+#endif
+
+#define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
+                         TLB_V4_I_FULL | TLB_V4_D_FULL | \
+                         TLB_V4_I_PAGE | TLB_V4_D_PAGE)
+
+#ifdef CONFIG_CPU_TLB_V4WBI
+# define v4wbi_possible_flags   v4wbi_tlb_flags
+# define v4wbi_always_flags     v4wbi_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v4wbi
+# endif
+#else
+# define v4wbi_possible_flags   0
+# define v4wbi_always_flags     (-1UL)
+#endif
+
+#define v4wb_tlb_flags  (TLB_WB | TLB_DCLEAN | \
+                         TLB_V4_I_FULL | TLB_V4_D_FULL | \
+                         TLB_V4_D_PAGE)
+
+#ifdef CONFIG_CPU_TLB_V4WB
+# define v4wb_possible_flags    v4wb_tlb_flags
+# define v4wb_always_flags      v4wb_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v4wb
+# endif
+#else
+# define v4wb_possible_flags    0
+# define v4wb_always_flags      (-1UL)
+#endif
+
+#define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
+                         TLB_V6_I_FULL | TLB_V6_D_FULL | \
+                         TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
+                         TLB_V6_I_ASID | TLB_V6_D_ASID)
+
+#ifdef CONFIG_CPU_TLB_V6
+# define v6wbi_possible_flags   v6wbi_tlb_flags
+# define v6wbi_always_flags     v6wbi_tlb_flags
+# ifdef _TLB
+#  define MULTI_TLB 1
+# else
+#  define _TLB v6wbi
+# endif
+#else
+# define v6wbi_possible_flags   0
+# define v6wbi_always_flags     (-1UL)
+#endif
+
+#ifndef _TLB
+#error Unknown TLB model
+#endif
+
+#ifndef __ASSEMBLY__
+
+struct cpu_tlb_fns {
+        void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
+        void (*flush_kern_range)(unsigned long, unsigned long);
+        unsigned long tlb_flags;
+};
+
+/*
+ * Select the calling method
+ */
+#ifdef MULTI_TLB
+
+#define __cpu_flush_user_tlb_range      cpu_tlb.flush_user_range
+#define __cpu_flush_kern_tlb_range      cpu_tlb.flush_kern_range
+
+#else
+
+#define __cpu_flush_user_tlb_range      __glue(_TLB,_flush_user_tlb_range)
+#define __cpu_flush_kern_tlb_range      __glue(_TLB,_flush_kern_tlb_range)
+
+extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
+extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
+
+#endif
+
+extern struct cpu_tlb_fns cpu_tlb;
+
+#define __cpu_tlb_flags                 cpu_tlb.tlb_flags
+
+/*
+ *      TLB Management
+ *      ==============
+ *
+ *      The arch/arm/mm/tlb-*.S files implement these methods.
+ *
+ *      The TLB specific code is expected to perform whatever tests it
+ *      needs to determine if it should invalidate the TLB for each
+ *      call.  Start addresses are inclusive and end addresses are
+ *      exclusive; it is safe to round these addresses down.
+ *
+ *      flush_tlb_all()
+ *
+ *              Invalidate the entire TLB.
+ *
+ *      flush_tlb_mm(mm)
+ *
+ *              Invalidate all TLB entries in a particular address
+ *              space.
+ *              - mm    - mm_struct describing address space
+ *
+ *      flush_tlb_range(mm,start,end)
+ *
+ *              Invalidate a range of TLB entries in the specified
+ *              address space.
+ *              - mm    - mm_struct describing address space
+ *              - start - start address (may not be aligned)
+ *              - end   - end address (exclusive, may not be aligned)
+ *
+ *      flush_tlb_page(vaddr,vma)
+ *
+ *              Invalidate the specified page in the specified address range.
+ *              - vaddr - virtual address (may not be aligned)
+ *              - vma   - vma_struct describing address range
+ *
+ *      flush_kern_tlb_page(kaddr)
+ *
+ *              Invalidate the TLB entry for the specified page.  The address
+ *              will be in the kernels virtual memory space.  Current uses
+ *              only require the D-TLB to be invalidated.
+ *              - kaddr - Kernel virtual memory address
+ */
+
+/*
+ * We optimise the code below by:
+ *  - building a set of TLB flags that might be set in __cpu_tlb_flags
+ *  - building a set of TLB flags that will always be set in __cpu_tlb_flags
+ *  - if we're going to need __cpu_tlb_flags, access it once and only once
+ *
+ * This allows us to build optimal assembly for the single-CPU type case,
+ * and as close to optimal given the compiler constrants for multi-CPU
+ * case.  We could do better for the multi-CPU case if the compiler
+ * implemented the "%?" method, but this has been discontinued due to too
+ * many people getting it wrong.
+ */
+#define possible_tlb_flags      (v3_possible_flags | \
+                                 v4_possible_flags | \
+                                 v4wbi_possible_flags | \
+                                 v4wb_possible_flags | \
+                                 v6wbi_possible_flags)
+
+#define always_tlb_flags        (v3_always_flags & \
+                                 v4_always_flags & \
+                                 v4wbi_always_flags & \
+                                 v4wb_always_flags & \
+                                 v6wbi_always_flags)
+
+#define tlb_flag(f)     ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
+
+static inline void flush_tlb_all(void)
+{
+        const int zero = 0;
+        const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+        if (tlb_flag(TLB_WB))
+                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+
+        if (tlb_flag(TLB_V3_FULL))
+                asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
+        if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
+                asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
+        if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
+                asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
+        if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
+                asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+}
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+        const int zero = 0;
+        const int asid = ASID(mm);
+        const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+        if (tlb_flag(TLB_WB))
+                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+
+        if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
+                if (tlb_flag(TLB_V3_FULL))
+                        asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
+                if (tlb_flag(TLB_V4_U_FULL))
+                        asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
+                if (tlb_flag(TLB_V4_D_FULL))
+                        asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
+                if (tlb_flag(TLB_V4_I_FULL))
+                        asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+        }
+
+        if (tlb_flag(TLB_V6_U_ASID))
+                asm("mcr%? p15, 0, %0, c8, c7, 2" : : "r" (asid));
+        if (tlb_flag(TLB_V6_D_ASID))
+                asm("mcr%? p15, 0, %0, c8, c6, 2" : : "r" (asid));
+        if (tlb_flag(TLB_V6_I_ASID))
+                asm("mcr%? p15, 0, %0, c8, c5, 2" : : "r" (asid));
+}
+
+static inline void
+flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
+{
+        const int zero = 0;
+        const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+        uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
+
+        if (tlb_flag(TLB_WB))
+                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+
+        if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
+                if (tlb_flag(TLB_V3_PAGE))
+                        asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (uaddr));
+                if (tlb_flag(TLB_V4_U_PAGE))
+                        asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
+                if (tlb_flag(TLB_V4_D_PAGE))
+                        asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
+                if (tlb_flag(TLB_V4_I_PAGE))
+                        asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
+                if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
+                        asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+        }
+
+        if (tlb_flag(TLB_V6_U_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
+        if (tlb_flag(TLB_V6_D_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
+        if (tlb_flag(TLB_V6_I_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
+}
+
+static inline void flush_tlb_kernel_page(unsigned long kaddr)
+{
+        const int zero = 0;
+        const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+        kaddr &= PAGE_MASK;
+
+        if (tlb_flag(TLB_WB))
+                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
+
+        if (tlb_flag(TLB_V3_PAGE))
+                asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (kaddr));
+        if (tlb_flag(TLB_V4_U_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
+        if (tlb_flag(TLB_V4_D_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
+        if (tlb_flag(TLB_V4_I_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+        if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
+                asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
+
+        if (tlb_flag(TLB_V6_U_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
+        if (tlb_flag(TLB_V6_D_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
+        if (tlb_flag(TLB_V6_I_PAGE))
+                asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+}
+
+/*
+ *      flush_pmd_entry
+ *
+ *      Flush a PMD entry (word aligned, or double-word aligned) to
+ *      RAM if the TLB for the CPU we are running on requires this.
+ *      This is typically used when we are creating PMD entries.
+ *
+ *      clean_pmd_entry
+ *
+ *      Clean (but don't drain the write buffer) if the CPU requires
+ *      these operations.  This is typically used when we are removing
+ *      PMD entries.
+ */
+static inline void flush_pmd_entry(pmd_t *pmd)
+{
+        const unsigned int zero = 0;
+        const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+        if (tlb_flag(TLB_DCLEAN))
+                asm("mcr%?      p15, 0, %0, c7, c10, 1  @ flush_pmd"
+                        : : "r" (pmd));
+        if (tlb_flag(TLB_WB))
+                asm("mcr%?      p15, 0, %0, c7, c10, 4  @ flush_pmd"
+                        : : "r" (zero));
+}
+
+static inline void clean_pmd_entry(pmd_t *pmd)
+{
+        const unsigned int __tlb_flag = __cpu_tlb_flags;
+
+        if (tlb_flag(TLB_DCLEAN))
+                asm("mcr%?      p15, 0, %0, c7, c10, 1  @ flush_pmd"
+                        : : "r" (pmd));
+}
+
+#undef tlb_flag
+#undef always_tlb_flags
+#undef possible_tlb_flags
+
+/*
+ * Convert calls to our calling convention.
+ */
+#define flush_tlb_range(vma,start,end)  __cpu_flush_user_tlb_range(start,end,vma)
+#define flush_tlb_kernel_range(s,e)     __cpu_flush_kern_tlb_range(s,e)
+
+/*
+ * if PG_dcache_dirty is set for the page, we need to ensure that any
+ * cache entries for the kernels virtual memory range are written
+ * back to the page.
+ */
+extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
+
+/*
+ * ARM processors do not cache TLB tables in RAM.
+ */
+#define flush_tlb_pgtables(mm,start,end)        do { } while (0)
+
+#endif
+
+#endif
diff --git a/include/asm-arm/topology.h b/include/asm-arm/topology.h
new file mode 100644
index 000000000000..accbd7cad9b5
--- /dev/null
+++ b/include/asm-arm/topology.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_ARM_TOPOLOGY_H
+#define _ASM_ARM_TOPOLOGY_H
+
+#include <asm-generic/topology.h>
+
+#endif /* _ASM_ARM_TOPOLOGY_H */
diff --git a/include/asm-arm/traps.h b/include/asm-arm/traps.h
new file mode 100644
index 000000000000..d4f34dc83eb0
--- /dev/null
+++ b/include/asm-arm/traps.h
@@ -0,0 +1,18 @@
+#ifndef _ASMARM_TRAP_H
+#define _ASMARM_TRAP_H
+
+#include <linux/list.h>
+
+struct undef_hook {
+        struct list_head node;
+        u32 instr_mask;
+        u32 instr_val;
+        u32 cpsr_mask;
+        u32 cpsr_val;
+        int (*fn)(struct pt_regs *regs, unsigned int instr);
+};
+
+void register_undef_hook(struct undef_hook *hook);
+void unregister_undef_hook(struct undef_hook *hook);
+
+#endif
diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h
new file mode 100644
index 000000000000..f4c92e4c8c02
--- /dev/null
+++ b/include/asm-arm/types.h
@@ -0,0 +1,62 @@
+#ifndef __ASM_ARM_TYPES_H
+#define __ASM_ARM_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+typedef u32 dma64_addr_t;
+
+typedef unsigned int kmem_bufctl_t;
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __KERNEL__ */
+
+#endif
+
diff --git a/include/asm-arm/uaccess.h b/include/asm-arm/uaccess.h
new file mode 100644
index 000000000000..a7c018b8a0d4
--- /dev/null
+++ b/include/asm-arm/uaccess.h
@@ -0,0 +1,438 @@
+/*
+ *  linux/include/asm-arm/uaccess.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _ASMARM_UACCESS_H
+#define _ASMARM_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <linux/sched.h>
+#include <asm/errno.h>
+#include <asm/memory.h>
+#include <asm/domain.h>
+#include <asm/system.h>
+
+#define VERIFY_READ 0
+#define VERIFY_WRITE 1
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry
+{
+        unsigned long insn, fixup;
+};
+
+extern int fixup_exception(struct pt_regs *regs);
+
+/*
+ * Note that this is actually 0x1,0000,0000
+ */
+#define KERNEL_DS       0x00000000
+#define USER_DS         TASK_SIZE
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current_thread_info()->addr_limit)
+
+static inline void set_fs (mm_segment_t fs)
+{
+        current_thread_info()->addr_limit = fs;
+        modify_domain(DOMAIN_KERNEL, fs ? DOMAIN_CLIENT : DOMAIN_MANAGER);
+}
+
+#define segment_eq(a,b) ((a) == (b))
+
+#define __addr_ok(addr) ({ \
+        unsigned long flag; \
+        __asm__("cmp %2, %0; movlo %0, #0" \
+                : "=&r" (flag) \
+                : "0" (current_thread_info()->addr_limit), "r" (addr) \
+                : "cc"); \
+        (flag == 0); })
+
+/* We use 33-bit arithmetic here... */
+#define __range_ok(addr,size) ({ \
+        unsigned long flag, sum; \
+        __chk_user_ptr(addr);   \
+        __asm__("adds %1, %2, %3; sbcccs %1, %1, %0; movcc %0, #0" \
+                : "=&r" (flag), "=&r" (sum) \
+                : "r" (addr), "Ir" (size), "0" (current_thread_info()->addr_limit) \
+                : "cc"); \
+        flag; })
+
+#define access_ok(type,addr,size)       (__range_ok(addr,size) == 0)
+
+/* this function will go away soon - use access_ok() instead */
+static inline int __deprecated verify_area(int type, const void __user *addr, unsigned long size)
+{
+        return access_ok(type, addr, size) ? 0 : -EFAULT;
+}
+
+/*
+ * Single-value transfer routines.  They automatically use the right
+ * size if we just have the right pointer type.  Note that the functions
+ * which read from user space (*get_*) need to take care not to leak
+ * kernel data even if the calling code is buggy and fails to check
+ * the return value.  This means zeroing out the destination variable
+ * or buffer on error.  Normally this is done out of line by the
+ * fixup code, but there are a few places where it intrudes on the
+ * main code path.  When we only write to user space, there is no
+ * problem.
+ *
+ * The "__xxx" versions of the user access functions do not verify the
+ * address space - it must have been done previously with a separate
+ * "access_ok()" call.
+ *
+ * The "xxx_error" versions set the third argument to EFAULT if an
+ * error occurs, and leave it unchanged on success.  Note that these
+ * versions are void (ie, don't return a value as such).
+ */
+
+extern int __get_user_1(void *);
+extern int __get_user_2(void *);
+extern int __get_user_4(void *);
+extern int __get_user_8(void *);
+extern int __get_user_bad(void);
+
+#define __get_user_x(__r2,__p,__e,__s,__i...)                           \
+           __asm__ __volatile__ (                                       \
+                __asmeq("%0", "r0") __asmeq("%1", "r2")                 \
+                "bl     __get_user_" #__s                               \
+                : "=&r" (__e), "=r" (__r2)                              \
+                : "0" (__p)                                             \
+                : __i, "cc")
+
+#define get_user(x,p)                                                   \
+        ({                                                              \
+                const register typeof(*(p)) __user *__p asm("r0") = (p);\
+                register typeof(*(p)) __r2 asm("r2");                   \
+                register int __e asm("r0");                             \
+                switch (sizeof(*(__p))) {                               \
+                case 1:                                                 \
+                        __get_user_x(__r2, __p, __e, 1, "lr");          \
+                        break;                                          \
+                case 2:                                                 \
+                        __get_user_x(__r2, __p, __e, 2, "r3", "lr");    \
+                        break;                                          \
+                case 4:                                                 \
+                        __get_user_x(__r2, __p, __e, 4, "lr");          \
+                        break;                                          \
+                case 8:                                                 \
+                        __get_user_x(__r2, __p, __e, 8, "lr");          \
+                        break;                                          \
+                default: __e = __get_user_bad(); break;                 \
+                }                                                       \
+                x = __r2;                                               \
+                __e;                                                    \
+        })
+
+#define __get_user(x,ptr)                                               \
+({                                                                      \
+        long __gu_err = 0;                                              \
+        __get_user_err((x),(ptr),__gu_err);                             \
+        __gu_err;                                                       \
+})
+
+#define __get_user_error(x,ptr,err)                                     \
+({                                                                      \
+        __get_user_err((x),(ptr),err);                                  \
+        (void) 0;                                                       \
+})
+
+#define __get_user_err(x,ptr,err)                                       \
+do {                                                                    \
+        unsigned long __gu_addr = (unsigned long)(ptr);                 \
+        unsigned long __gu_val;                                         \
+        __chk_user_ptr(ptr);                                            \
+        switch (sizeof(*(ptr))) {                                       \
+        case 1: __get_user_asm_byte(__gu_val,__gu_addr,err);    break;  \
+        case 2: __get_user_asm_half(__gu_val,__gu_addr,err);    break;  \
+        case 4: __get_user_asm_word(__gu_val,__gu_addr,err);    break;  \
+        default: (__gu_val) = __get_user_bad();                         \
+        }                                                               \
+        (x) = (__typeof__(*(ptr)))__gu_val;                             \
+} while (0)
+
+#define __get_user_asm_byte(x,addr,err)                         \
+        __asm__ __volatile__(                                   \
+        "1:     ldrbt   %1,[%2],#0\n"                           \
+        "2:\n"                                                  \
+        "       .section .fixup,\"ax\"\n"                       \
+        "       .align  2\n"                                    \
+        "3:     mov     %0, %3\n"                               \
+        "       mov     %1, #0\n"                               \
+        "       b       2b\n"                                   \
+        "       .previous\n"                                    \
+        "       .section __ex_table,\"a\"\n"                    \
+        "       .align  3\n"                                    \
+        "       .long   1b, 3b\n"                               \
+        "       .previous"                                      \
+        : "+r" (err), "=&r" (x)                                 \
+        : "r" (addr), "i" (-EFAULT)                             \
+        : "cc")
+
+#ifndef __ARMEB__
+#define __get_user_asm_half(x,__gu_addr,err)                    \
+({                                                              \
+        unsigned long __b1, __b2;                               \
+        __get_user_asm_byte(__b1, __gu_addr, err);              \
+        __get_user_asm_byte(__b2, __gu_addr + 1, err);          \
+        (x) = __b1 | (__b2 << 8);                               \
+})
+#else
+#define __get_user_asm_half(x,__gu_addr,err)                    \
+({                                                              \
+        unsigned long __b1, __b2;                               \
+        __get_user_asm_byte(__b1, __gu_addr, err);              \
+        __get_user_asm_byte(__b2, __gu_addr + 1, err);          \
+        (x) = (__b1 << 8) | __b2;                               \
+})
+#endif
+
+#define __get_user_asm_word(x,addr,err)                         \
+        __asm__ __volatile__(                                   \
+        "1:     ldrt    %1,[%2],#0\n"                           \
+        "2:\n"                                                  \
+        "       .section .fixup,\"ax\"\n"                       \
+        "       .align  2\n"                                    \
+        "3:     mov     %0, %3\n"                               \
+        "       mov     %1, #0\n"                               \
+        "       b       2b\n"                                   \
+        "       .previous\n"                                    \
+        "       .section __ex_table,\"a\"\n"                    \
+        "       .align  3\n"                                    \
+        "       .long   1b, 3b\n"                               \
+        "       .previous"                                      \
+        : "+r" (err), "=&r" (x)                                 \
+        : "r" (addr), "i" (-EFAULT)                             \
+        : "cc")
+
+extern int __put_user_1(void *, unsigned int);
+extern int __put_user_2(void *, unsigned int);
+extern int __put_user_4(void *, unsigned int);
+extern int __put_user_8(void *, unsigned long long);
+extern int __put_user_bad(void);
+
+#define __put_user_x(__r2,__p,__e,__s)                                  \
+           __asm__ __volatile__ (                                       \
+                __asmeq("%0", "r0") __asmeq("%2", "r2")                 \
+                "bl     __put_user_" #__s                               \
+                : "=&r" (__e)                                           \
+                : "0" (__p), "r" (__r2)                                 \
+                : "ip", "lr", "cc")
+
+#define put_user(x,p)                                                   \
+        ({                                                              \
+                const register typeof(*(p)) __r2 asm("r2") = (x);       \
+                const register typeof(*(p)) __user *__p asm("r0") = (p);\
+                register int __e asm("r0");                             \
+                switch (sizeof(*(__p))) {                               \
+                case 1:                                                 \
+                        __put_user_x(__r2, __p, __e, 1);                \
+                        break;                                          \
+                case 2:                                                 \
+                        __put_user_x(__r2, __p, __e, 2);                \
+                        break;                                          \
+                case 4:                                                 \
+                        __put_user_x(__r2, __p, __e, 4);                \
+                        break;                                          \
+                case 8:                                                 \
+                        __put_user_x(__r2, __p, __e, 8);                \
+                        break;                                          \
+                default: __e = __put_user_bad(); break;                 \
+                }                                                       \
+                __e;                                                    \
+        })
+
+#define __put_user(x,ptr)                                               \
+({                                                                      \
+        long __pu_err = 0;                                              \
+        __put_user_err((x),(ptr),__pu_err);                             \
+        __pu_err;                                                       \
+})
+
+#define __put_user_error(x,ptr,err)                                     \
+({                                                                      \
+        __put_user_err((x),(ptr),err);                                  \
+        (void) 0;                                                       \
+})
+
+#define __put_user_err(x,ptr,err)                                       \
+do {                                                                    \
+        unsigned long __pu_addr = (unsigned long)(ptr);                 \
+        __typeof__(*(ptr)) __pu_val = (x);                              \
+        __chk_user_ptr(ptr);                                            \
+        switch (sizeof(*(ptr))) {                                       \
+        case 1: __put_user_asm_byte(__pu_val,__pu_addr,err);    break;  \
+        case 2: __put_user_asm_half(__pu_val,__pu_addr,err);    break;  \
+        case 4: __put_user_asm_word(__pu_val,__pu_addr,err);    break;  \
+        case 8: __put_user_asm_dword(__pu_val,__pu_addr,err);   break;  \
+        default: __put_user_bad();                                      \
+        }                                                               \
+} while (0)
+
+#define __put_user_asm_byte(x,__pu_addr,err)                    \
+        __asm__ __volatile__(                                   \
+        "1:     strbt   %1,[%2],#0\n"                           \
+        "2:\n"                                                  \
+        "       .section .fixup,\"ax\"\n"                       \
+        "       .align  2\n"                                    \
+        "3:     mov     %0, %3\n"                               \
+        "       b       2b\n"                                   \
+        "       .previous\n"                                    \
+        "       .section __ex_table,\"a\"\n"                    \
+        "       .align  3\n"                                    \
+        "       .long   1b, 3b\n"                               \
+        "       .previous"                                      \
+        : "+r" (err)                                            \
+        : "r" (x), "r" (__pu_addr), "i" (-EFAULT)               \
+        : "cc")
+
+#ifndef __ARMEB__
+#define __put_user_asm_half(x,__pu_addr,err)                    \
+({                                                              \
+        unsigned long __temp = (unsigned long)(x);              \
+        __put_user_asm_byte(__temp, __pu_addr, err);            \
+        __put_user_asm_byte(__temp >> 8, __pu_addr + 1, err);   \
+})
+#else
+#define __put_user_asm_half(x,__pu_addr,err)                    \
+({                                                              \
+        unsigned long __temp = (unsigned long)(x);              \
+        __put_user_asm_byte(__temp >> 8, __pu_addr, err);       \
+        __put_user_asm_byte(__temp, __pu_addr + 1, err);        \
+})
+#endif
+
+#define __put_user_asm_word(x,__pu_addr,err)                    \
+        __asm__ __volatile__(                                   \
+        "1:     strt    %1,[%2],#0\n"                           \
+        "2:\n"                                                  \
+        "       .section .fixup,\"ax\"\n"                       \
+        "       .align  2\n"                                    \
+        "3:     mov     %0, %3\n"                               \
+        "       b       2b\n"                                   \
+        "       .previous\n"                                    \
+        "       .section __ex_table,\"a\"\n"                    \
+        "       .align  3\n"                                    \
+        "       .long   1b, 3b\n"                               \
+        "       .previous"                                      \
+        : "+r" (err)                                            \
+        : "r" (x), "r" (__pu_addr), "i" (-EFAULT)               \
+        : "cc")
+
+#ifndef __ARMEB__
+#define __reg_oper0     "%R2"
+#define __reg_oper1     "%Q2"
+#else
+#define __reg_oper0     "%Q2"
+#define __reg_oper1     "%R2"
+#endif
+
+#define __put_user_asm_dword(x,__pu_addr,err)                   \
+        __asm__ __volatile__(                                   \
+        "1:     strt    " __reg_oper1 ", [%1], #4\n"            \
+        "2:     strt    " __reg_oper0 ", [%1], #0\n"            \
+        "3:\n"                                                  \
+        "       .section .fixup,\"ax\"\n"                       \
+        "       .align  2\n"                                    \
+        "4:     mov     %0, %3\n"                               \
+        "       b       3b\n"                                   \
+        "       .previous\n"                                    \
+        "       .section __ex_table,\"a\"\n"                    \
+        "       .align  3\n"                                    \
+        "       .long   1b, 4b\n"                               \
+        "       .long   2b, 4b\n"                               \
+        "       .previous"                                      \
+        : "+r" (err), "+r" (__pu_addr)                          \
+        : "r" (x), "i" (-EFAULT)                                \
+        : "cc")
+
+extern unsigned long __arch_copy_from_user(void *to, const void __user *from, unsigned long n);
+extern unsigned long __arch_copy_to_user(void __user *to, const void *from, unsigned long n);
+extern unsigned long __arch_clear_user(void __user *addr, unsigned long n);
+extern unsigned long __arch_strncpy_from_user(char *to, const char __user *from, unsigned long count);
+extern unsigned long __arch_strnlen_user(const char __user *s, long n);
+
+static inline unsigned long copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        if (access_ok(VERIFY_READ, from, n))
+                n = __arch_copy_from_user(to, from, n);
+        else /* security hole - plug it */
+                memzero(to, n);
+        return n;
+}
+
+static inline unsigned long __copy_from_user(void *to, const void __user *from, unsigned long n)
+{
+        return __arch_copy_from_user(to, from, n);
+}
+
+static inline unsigned long copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        if (access_ok(VERIFY_WRITE, to, n))
+                n = __arch_copy_to_user(to, from, n);
+        return n;
+}
+
+static inline unsigned long __copy_to_user(void __user *to, const void *from, unsigned long n)
+{
+        return __arch_copy_to_user(to, from, n);
+}
+
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+static inline unsigned long clear_user (void __user *to, unsigned long n)
+{
+        if (access_ok(VERIFY_WRITE, to, n))
+                n = __arch_clear_user(to, n);
+        return n;
+}
+
+static inline unsigned long __clear_user (void __user *to, unsigned long n)
+{
+        return __arch_clear_user(to, n);
+}
+
+static inline long strncpy_from_user (char *dst, const char __user *src, long count)
+{
+        long res = -EFAULT;
+        if (access_ok(VERIFY_READ, src, 1))
+                res = __arch_strncpy_from_user(dst, src, count);
+        return res;
+}
+
+static inline long __strncpy_from_user (char *dst, const char __user *src, long count)
+{
+        return __arch_strncpy_from_user(dst, src, count);
+}
+
+#define strlen_user(s)  strnlen_user(s, ~0UL >> 1)
+
+static inline long strnlen_user(const char __user *s, long n)
+{
+        unsigned long res = 0;
+
+        if (__addr_ok(s))
+                res = __arch_strnlen_user(s, n);
+
+        return res;
+}
+
+#endif /* _ASMARM_UACCESS_H */
diff --git a/include/asm-arm/ucontext.h b/include/asm-arm/ucontext.h
new file mode 100644
index 000000000000..f853130137cc
--- /dev/null
+++ b/include/asm-arm/ucontext.h
@@ -0,0 +1,12 @@
+#ifndef _ASMARM_UCONTEXT_H
+#define _ASMARM_UCONTEXT_H
+
+struct ucontext {
+        unsigned long     uc_flags;
+        struct ucontext  *uc_link;
+        stack_t           uc_stack;
+        struct sigcontext uc_mcontext;
+        sigset_t          uc_sigmask;   /* mask last for extensibility */
+};
+
+#endif /* !_ASMARM_UCONTEXT_H */
diff --git a/include/asm-arm/unaligned.h b/include/asm-arm/unaligned.h
new file mode 100644
index 000000000000..1b39c2f322c9
--- /dev/null
+++ b/include/asm-arm/unaligned.h
@@ -0,0 +1,191 @@
+#ifndef __ASM_ARM_UNALIGNED_H
+#define __ASM_ARM_UNALIGNED_H
+
+#include <asm/types.h>
+
+extern int __bug_unaligned_x(void *ptr);
+
+/*
+ * What is the most efficient way of loading/storing an unaligned value?
+ *
+ * That is the subject of this file.  Efficiency here is defined as
+ * minimum code size with minimum register usage for the common cases.
+ * It is currently not believed that long longs are common, so we
+ * trade efficiency for the chars, shorts and longs against the long
+ * longs.
+ *
+ * Current stats with gcc 2.7.2.2 for these functions:
+ *
+ *      ptrsize get:    code    regs    put:    code    regs
+ *      1               1       1               1       2
+ *      2               3       2               3       2
+ *      4               7       3               7       3
+ *      8               20      6               16      6
+ *
+ * gcc 2.95.1 seems to code differently:
+ *
+ *      ptrsize get:    code    regs    put:    code    regs
+ *      1               1       1               1       2
+ *      2               3       2               3       2
+ *      4               7       4               7       4
+ *      8               19      8               15      6
+ *
+ * which may or may not be more efficient (depending upon whether
+ * you can afford the extra registers).  Hopefully the gcc 2.95
+ * is inteligent enough to decide if it is better to use the
+ * extra register, but evidence so far seems to suggest otherwise.
+ *
+ * Unfortunately, gcc is not able to optimise the high word
+ * out of long long >> 32, or the low word from long long << 32
+ */
+
+#define __get_unaligned_2_le(__p)                                       \
+        (__p[0] | __p[1] << 8)
+
+#define __get_unaligned_2_be(__p)                                       \
+        (__p[0] << 8 | __p[1])
+
+#define __get_unaligned_4_le(__p)                                       \
+        (__p[0] | __p[1] << 8 | __p[2] << 16 | __p[3] << 24)
+
+#define __get_unaligned_4_be(__p)                                       \
+        (__p[0] << 24 | __p[1] << 16 | __p[2] << 8 | __p[3])
+
+#define __get_unaligned_le(ptr)                                 \
+        ({                                                      \
+                __typeof__(*(ptr)) __v;                         \
+                __u8 *__p = (__u8 *)(ptr);                      \
+                switch (sizeof(*(ptr))) {                       \
+                case 1: __v = *(ptr);                   break;  \
+                case 2: __v = __get_unaligned_2_le(__p);        break;  \
+                case 4: __v = __get_unaligned_4_le(__p);        break;  \
+                case 8: {                                       \
+                                unsigned int __v1, __v2;        \
+                                __v2 = __get_unaligned_4_le((__p+4)); \
+                                __v1 = __get_unaligned_4_le(__p);       \
+                                __v = ((unsigned long long)__v2 << 32 | __v1);  \
+                        }                                       \
+                        break;                                  \
+                default: __v = __bug_unaligned_x(__p);  break;  \
+                }                                               \
+                __v;                                            \
+        })
+
+#define __get_unaligned_be(ptr)                                 \
+        ({                                                      \
+                __typeof__(*(ptr)) __v;                         \
+                __u8 *__p = (__u8 *)(ptr);                      \
+                switch (sizeof(*(ptr))) {                       \
+                case 1: __v = *(ptr);                   break;  \
+                case 2: __v = __get_unaligned_2_be(__p);        break;  \
+                case 4: __v = __get_unaligned_4_be(__p);        break;  \
+                case 8: {                                       \
+                                unsigned int __v1, __v2;        \
+                                __v2 = __get_unaligned_4_be(__p); \
+                                __v1 = __get_unaligned_4_be((__p+4));   \
+                                __v = ((unsigned long long)__v2 << 32 | __v1);  \
+                        }                                       \
+                        break;                                  \
+                default: __v = __bug_unaligned_x(__p);  break;  \
+                }                                               \
+                __v;                                            \
+        })
+
+
+static inline void __put_unaligned_2_le(__u32 __v, register __u8 *__p)
+{
+        *__p++ = __v;
+        *__p++ = __v >> 8;
+}
+
+static inline void __put_unaligned_2_be(__u32 __v, register __u8 *__p)
+{
+        *__p++ = __v >> 8;
+        *__p++ = __v;
+}
+
+static inline void __put_unaligned_4_le(__u32 __v, register __u8 *__p)
+{
+        __put_unaligned_2_le(__v >> 16, __p + 2);
+        __put_unaligned_2_le(__v, __p);
+}
+
+static inline void __put_unaligned_4_be(__u32 __v, register __u8 *__p)
+{
+        __put_unaligned_2_be(__v >> 16, __p);
+        __put_unaligned_2_be(__v, __p + 2);
+}
+
+static inline void __put_unaligned_8_le(const unsigned long long __v, register __u8 *__p)
+{
+        /*
+         * tradeoff: 8 bytes of stack for all unaligned puts (2
+         * instructions), or an extra register in the long long
+         * case - go for the extra register.
+         */
+        __put_unaligned_4_le(__v >> 32, __p+4);
+        __put_unaligned_4_le(__v, __p);
+}
+
+static inline void __put_unaligned_8_be(const unsigned long long __v, register __u8 *__p)
+{
+        /*
+         * tradeoff: 8 bytes of stack for all unaligned puts (2
+         * instructions), or an extra register in the long long
+         * case - go for the extra register.
+         */
+        __put_unaligned_4_be(__v >> 32, __p);
+        __put_unaligned_4_be(__v, __p+4);
+}
+
+/*
+ * Try to store an unaligned value as efficiently as possible.
+ */
+#define __put_unaligned_le(val,ptr)                                     \
+        ({                                                      \
+                switch (sizeof(*(ptr))) {                       \
+                case 1:                                         \
+                        *(ptr) = (val);                         \
+                        break;                                  \
+                case 2: __put_unaligned_2_le((val),(__u8 *)(ptr));      \
+                        break;                                  \
+                case 4: __put_unaligned_4_le((val),(__u8 *)(ptr));      \
+                        break;                                  \
+                case 8: __put_unaligned_8_le((val),(__u8 *)(ptr)); \
+                        break;                                  \
+                default: __bug_unaligned_x(ptr);                \
+                        break;                                  \
+                }                                               \
+                (void) 0;                                       \
+        })
+
+#define __put_unaligned_be(val,ptr)                                     \
+        ({                                                      \
+                switch (sizeof(*(ptr))) {                       \
+                case 1:                                         \
+                        *(ptr) = (val);                         \
+                        break;                                  \
+                case 2: __put_unaligned_2_be((val),(__u8 *)(ptr));      \
+                        break;                                  \
+                case 4: __put_unaligned_4_be((val),(__u8 *)(ptr));      \
+                        break;                                  \
+                case 8: __put_unaligned_8_be((val),(__u8 *)(ptr)); \
+                        break;                                  \
+                default: __bug_unaligned_x(ptr);                \
+                        break;                                  \
+                }                                               \
+                (void) 0;                                       \
+        })
+
+/*
+ * Select endianness
+ */
+#ifndef __ARMEB__
+#define get_unaligned   __get_unaligned_le
+#define put_unaligned   __put_unaligned_le
+#else
+#define get_unaligned   __get_unaligned_be
+#define put_unaligned   __put_unaligned_be
+#endif
+
+#endif
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
new file mode 100644
index 000000000000..a19ec09eaa01
--- /dev/null
+++ b/include/asm-arm/unistd.h
@@ -0,0 +1,558 @@
+/*
+ *  linux/include/asm-arm/unistd.h
+ *
+ *  Copyright (C) 2001-2005 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Please forward _all_ changes to this file to rmk@arm.linux.org.uk,
+ * no matter what the change is.  Thanks!
+ */
+#ifndef __ASM_ARM_UNISTD_H
+#define __ASM_ARM_UNISTD_H
+
+#include <linux/linkage.h>
+
+#if defined(__thumb__)
+#define __NR_SYSCALL_BASE       0
+#else
+#define __NR_SYSCALL_BASE       0x900000
+#endif
+
+/*
+ * This file contains the system call numbers.
+ */
+
+#define __NR_restart_syscall            (__NR_SYSCALL_BASE+  0)
+#define __NR_exit                       (__NR_SYSCALL_BASE+  1)
+#define __NR_fork                       (__NR_SYSCALL_BASE+  2)
+#define __NR_read                       (__NR_SYSCALL_BASE+  3)
+#define __NR_write                      (__NR_SYSCALL_BASE+  4)
+#define __NR_open                       (__NR_SYSCALL_BASE+  5)
+#define __NR_close                      (__NR_SYSCALL_BASE+  6)
+                                        /* 7 was sys_waitpid */
+#define __NR_creat                      (__NR_SYSCALL_BASE+  8)
+#define __NR_link                       (__NR_SYSCALL_BASE+  9)
+#define __NR_unlink                     (__NR_SYSCALL_BASE+ 10)
+#define __NR_execve                     (__NR_SYSCALL_BASE+ 11)
+#define __NR_chdir                      (__NR_SYSCALL_BASE+ 12)
+#define __NR_time                       (__NR_SYSCALL_BASE+ 13)
+#define __NR_mknod                      (__NR_SYSCALL_BASE+ 14)
+#define __NR_chmod                      (__NR_SYSCALL_BASE+ 15)
+#define __NR_lchown                     (__NR_SYSCALL_BASE+ 16)
+                                        /* 17 was sys_break */
+                                        /* 18 was sys_stat */
+#define __NR_lseek                      (__NR_SYSCALL_BASE+ 19)
+#define __NR_getpid                     (__NR_SYSCALL_BASE+ 20)
+#define __NR_mount                      (__NR_SYSCALL_BASE+ 21)
+#define __NR_umount                     (__NR_SYSCALL_BASE+ 22)
+#define __NR_setuid                     (__NR_SYSCALL_BASE+ 23)
+#define __NR_getuid                     (__NR_SYSCALL_BASE+ 24)
+#define __NR_stime                      (__NR_SYSCALL_BASE+ 25)
+#define __NR_ptrace                     (__NR_SYSCALL_BASE+ 26)
+#define __NR_alarm                      (__NR_SYSCALL_BASE+ 27)
+                                        /* 28 was sys_fstat */
+#define __NR_pause                      (__NR_SYSCALL_BASE+ 29)
+#define __NR_utime                      (__NR_SYSCALL_BASE+ 30)
+                                        /* 31 was sys_stty */
+                                        /* 32 was sys_gtty */
+#define __NR_access                     (__NR_SYSCALL_BASE+ 33)
+#define __NR_nice                       (__NR_SYSCALL_BASE+ 34)
+                                        /* 35 was sys_ftime */
+#define __NR_sync                       (__NR_SYSCALL_BASE+ 36)
+#define __NR_kill                       (__NR_SYSCALL_BASE+ 37)
+#define __NR_rename                     (__NR_SYSCALL_BASE+ 38)
+#define __NR_mkdir                      (__NR_SYSCALL_BASE+ 39)
+#define __NR_rmdir                      (__NR_SYSCALL_BASE+ 40)
+#define __NR_dup                        (__NR_SYSCALL_BASE+ 41)
+#define __NR_pipe                       (__NR_SYSCALL_BASE+ 42)
+#define __NR_times                      (__NR_SYSCALL_BASE+ 43)
+                                        /* 44 was sys_prof */
+#define __NR_brk                        (__NR_SYSCALL_BASE+ 45)
+#define __NR_setgid                     (__NR_SYSCALL_BASE+ 46)
+#define __NR_getgid                     (__NR_SYSCALL_BASE+ 47)
+                                        /* 48 was sys_signal */
+#define __NR_geteuid                    (__NR_SYSCALL_BASE+ 49)
+#define __NR_getegid                    (__NR_SYSCALL_BASE+ 50)
+#define __NR_acct                       (__NR_SYSCALL_BASE+ 51)
+#define __NR_umount2                    (__NR_SYSCALL_BASE+ 52)
+                                        /* 53 was sys_lock */
+#define __NR_ioctl                      (__NR_SYSCALL_BASE+ 54)
+#define __NR_fcntl                      (__NR_SYSCALL_BASE+ 55)
+                                        /* 56 was sys_mpx */
+#define __NR_setpgid                    (__NR_SYSCALL_BASE+ 57)
+                                        /* 58 was sys_ulimit */
+                                        /* 59 was sys_olduname */
+#define __NR_umask                      (__NR_SYSCALL_BASE+ 60)
+#define __NR_chroot                     (__NR_SYSCALL_BASE+ 61)
+#define __NR_ustat                      (__NR_SYSCALL_BASE+ 62)
+#define __NR_dup2                       (__NR_SYSCALL_BASE+ 63)
+#define __NR_getppid                    (__NR_SYSCALL_BASE+ 64)
+#define __NR_getpgrp                    (__NR_SYSCALL_BASE+ 65)
+#define __NR_setsid                     (__NR_SYSCALL_BASE+ 66)
+#define __NR_sigaction                  (__NR_SYSCALL_BASE+ 67)
+                                        /* 68 was sys_sgetmask */
+                                        /* 69 was sys_ssetmask */
+#define __NR_setreuid                   (__NR_SYSCALL_BASE+ 70)
+#define __NR_setregid                   (__NR_SYSCALL_BASE+ 71)
+#define __NR_sigsuspend                 (__NR_SYSCALL_BASE+ 72)
+#define __NR_sigpending                 (__NR_SYSCALL_BASE+ 73)
+#define __NR_sethostname                (__NR_SYSCALL_BASE+ 74)
+#define __NR_setrlimit                  (__NR_SYSCALL_BASE+ 75)
+#define __NR_getrlimit                  (__NR_SYSCALL_BASE+ 76) /* Back compat 2GB limited rlimit */
+#define __NR_getrusage                  (__NR_SYSCALL_BASE+ 77)
+#define __NR_gettimeofday               (__NR_SYSCALL_BASE+ 78)
+#define __NR_settimeofday               (__NR_SYSCALL_BASE+ 79)
+#define __NR_getgroups                  (__NR_SYSCALL_BASE+ 80)
+#define __NR_setgroups                  (__NR_SYSCALL_BASE+ 81)
+#define __NR_select                     (__NR_SYSCALL_BASE+ 82)
+#define __NR_symlink                    (__NR_SYSCALL_BASE+ 83)
+                                        /* 84 was sys_lstat */
+#define __NR_readlink                   (__NR_SYSCALL_BASE+ 85)
+#define __NR_uselib                     (__NR_SYSCALL_BASE+ 86)
+#define __NR_swapon                     (__NR_SYSCALL_BASE+ 87)
+#define __NR_reboot                     (__NR_SYSCALL_BASE+ 88)
+#define __NR_readdir                    (__NR_SYSCALL_BASE+ 89)
+#define __NR_mmap                       (__NR_SYSCALL_BASE+ 90)
+#define __NR_munmap                     (__NR_SYSCALL_BASE+ 91)
+#define __NR_truncate                   (__NR_SYSCALL_BASE+ 92)
+#define __NR_ftruncate                  (__NR_SYSCALL_BASE+ 93)
+#define __NR_fchmod                     (__NR_SYSCALL_BASE+ 94)
+#define __NR_fchown                     (__NR_SYSCALL_BASE+ 95)
+#define __NR_getpriority                (__NR_SYSCALL_BASE+ 96)
+#define __NR_setpriority                (__NR_SYSCALL_BASE+ 97)
+                                        /* 98 was sys_profil */
+#define __NR_statfs                     (__NR_SYSCALL_BASE+ 99)
+#define __NR_fstatfs                    (__NR_SYSCALL_BASE+100)
+                                        /* 101 was sys_ioperm */
+#define __NR_socketcall                 (__NR_SYSCALL_BASE+102)
+#define __NR_syslog                     (__NR_SYSCALL_BASE+103)
+#define __NR_setitimer                  (__NR_SYSCALL_BASE+104)
+#define __NR_getitimer                  (__NR_SYSCALL_BASE+105)
+#define __NR_stat                       (__NR_SYSCALL_BASE+106)
+#define __NR_lstat                      (__NR_SYSCALL_BASE+107)
+#define __NR_fstat                      (__NR_SYSCALL_BASE+108)
+                                        /* 109 was sys_uname */
+                                        /* 110 was sys_iopl */
+#define __NR_vhangup                    (__NR_SYSCALL_BASE+111)
+                                        /* 112 was sys_idle */
+#define __NR_syscall                    (__NR_SYSCALL_BASE+113) /* syscall to call a syscall! */
+#define __NR_wait4                      (__NR_SYSCALL_BASE+114)
+#define __NR_swapoff                    (__NR_SYSCALL_BASE+115)
+#define __NR_sysinfo                    (__NR_SYSCALL_BASE+116)
+#define __NR_ipc                        (__NR_SYSCALL_BASE+117)
+#define __NR_fsync                      (__NR_SYSCALL_BASE+118)
+#define __NR_sigreturn                  (__NR_SYSCALL_BASE+119)
+#define __NR_clone                      (__NR_SYSCALL_BASE+120)
+#define __NR_setdomainname              (__NR_SYSCALL_BASE+121)
+#define __NR_uname                      (__NR_SYSCALL_BASE+122)
+                                        /* 123 was sys_modify_ldt */
+#define __NR_adjtimex                   (__NR_SYSCALL_BASE+124)
+#define __NR_mprotect                   (__NR_SYSCALL_BASE+125)
+#define __NR_sigprocmask                (__NR_SYSCALL_BASE+126)
+                                        /* 127 was sys_create_module */
+#define __NR_init_module                (__NR_SYSCALL_BASE+128)
+#define __NR_delete_module              (__NR_SYSCALL_BASE+129)
+                                        /* 130 was sys_get_kernel_syms */
+#define __NR_quotactl                   (__NR_SYSCALL_BASE+131)
+#define __NR_getpgid                    (__NR_SYSCALL_BASE+132)
+#define __NR_fchdir                     (__NR_SYSCALL_BASE+133)
+#define __NR_bdflush                    (__NR_SYSCALL_BASE+134)
+#define __NR_sysfs                      (__NR_SYSCALL_BASE+135)
+#define __NR_personality                (__NR_SYSCALL_BASE+136)
+                                        /* 137 was sys_afs_syscall */
+#define __NR_setfsuid                   (__NR_SYSCALL_BASE+138)
+#define __NR_setfsgid                   (__NR_SYSCALL_BASE+139)
+#define __NR__llseek                    (__NR_SYSCALL_BASE+140)
+#define __NR_getdents                   (__NR_SYSCALL_BASE+141)
+#define __NR__newselect                 (__NR_SYSCALL_BASE+142)
+#define __NR_flock                      (__NR_SYSCALL_BASE+143)
+#define __NR_msync                      (__NR_SYSCALL_BASE+144)
+#define __NR_readv                      (__NR_SYSCALL_BASE+145)
+#define __NR_writev                     (__NR_SYSCALL_BASE+146)
+#define __NR_getsid                     (__NR_SYSCALL_BASE+147)
+#define __NR_fdatasync                  (__NR_SYSCALL_BASE+148)
+#define __NR__sysctl                    (__NR_SYSCALL_BASE+149)
+#define __NR_mlock                      (__NR_SYSCALL_BASE+150)
+#define __NR_munlock                    (__NR_SYSCALL_BASE+151)
+#define __NR_mlockall                   (__NR_SYSCALL_BASE+152)
+#define __NR_munlockall                 (__NR_SYSCALL_BASE+153)
+#define __NR_sched_setparam             (__NR_SYSCALL_BASE+154)
+#define __NR_sched_getparam             (__NR_SYSCALL_BASE+155)
+#define __NR_sched_setscheduler         (__NR_SYSCALL_BASE+156)
+#define __NR_sched_getscheduler         (__NR_SYSCALL_BASE+157)
+#define __NR_sched_yield                (__NR_SYSCALL_BASE+158)
+#define __NR_sched_get_priority_max     (__NR_SYSCALL_BASE+159)
+#define __NR_sched_get_priority_min     (__NR_SYSCALL_BASE+160)
+#define __NR_sched_rr_get_interval      (__NR_SYSCALL_BASE+161)
+#define __NR_nanosleep                  (__NR_SYSCALL_BASE+162)
+#define __NR_mremap                     (__NR_SYSCALL_BASE+163)
+#define __NR_setresuid                  (__NR_SYSCALL_BASE+164)
+#define __NR_getresuid                  (__NR_SYSCALL_BASE+165)
+                                        /* 166 was sys_vm86 */
+                                        /* 167 was sys_query_module */
+#define __NR_poll                       (__NR_SYSCALL_BASE+168)
+#define __NR_nfsservctl                 (__NR_SYSCALL_BASE+169)
+#define __NR_setresgid                  (__NR_SYSCALL_BASE+170)
+#define __NR_getresgid                  (__NR_SYSCALL_BASE+171)
+#define __NR_prctl                      (__NR_SYSCALL_BASE+172)
+#define __NR_rt_sigreturn               (__NR_SYSCALL_BASE+173)
+#define __NR_rt_sigaction               (__NR_SYSCALL_BASE+174)
+#define __NR_rt_sigprocmask             (__NR_SYSCALL_BASE+175)
+#define __NR_rt_sigpending              (__NR_SYSCALL_BASE+176)
+#define __NR_rt_sigtimedwait            (__NR_SYSCALL_BASE+177)
+#define __NR_rt_sigqueueinfo            (__NR_SYSCALL_BASE+178)
+#define __NR_rt_sigsuspend              (__NR_SYSCALL_BASE+179)
+#define __NR_pread64                    (__NR_SYSCALL_BASE+180)
+#define __NR_pwrite64                   (__NR_SYSCALL_BASE+181)
+#define __NR_chown                      (__NR_SYSCALL_BASE+182)
+#define __NR_getcwd                     (__NR_SYSCALL_BASE+183)
+#define __NR_capget                     (__NR_SYSCALL_BASE+184)
+#define __NR_capset                     (__NR_SYSCALL_BASE+185)
+#define __NR_sigaltstack                (__NR_SYSCALL_BASE+186)
+#define __NR_sendfile                   (__NR_SYSCALL_BASE+187)
+                                        /* 188 reserved */
+                                        /* 189 reserved */
+#define __NR_vfork                      (__NR_SYSCALL_BASE+190)
+#define __NR_ugetrlimit                 (__NR_SYSCALL_BASE+191) /* SuS compliant getrlimit */
+#define __NR_mmap2                      (__NR_SYSCALL_BASE+192)
+#define __NR_truncate64                 (__NR_SYSCALL_BASE+193)
+#define __NR_ftruncate64                (__NR_SYSCALL_BASE+194)
+#define __NR_stat64                     (__NR_SYSCALL_BASE+195)
+#define __NR_lstat64                    (__NR_SYSCALL_BASE+196)
+#define __NR_fstat64                    (__NR_SYSCALL_BASE+197)
+#define __NR_lchown32                   (__NR_SYSCALL_BASE+198)
+#define __NR_getuid32                   (__NR_SYSCALL_BASE+199)
+#define __NR_getgid32                   (__NR_SYSCALL_BASE+200)
+#define __NR_geteuid32                  (__NR_SYSCALL_BASE+201)
+#define __NR_getegid32                  (__NR_SYSCALL_BASE+202)
+#define __NR_setreuid32                 (__NR_SYSCALL_BASE+203)
+#define __NR_setregid32                 (__NR_SYSCALL_BASE+204)
+#define __NR_getgroups32                (__NR_SYSCALL_BASE+205)
+#define __NR_setgroups32                (__NR_SYSCALL_BASE+206)
+#define __NR_fchown32                   (__NR_SYSCALL_BASE+207)
+#define __NR_setresuid32                (__NR_SYSCALL_BASE+208)
+#define __NR_getresuid32                (__NR_SYSCALL_BASE+209)
+#define __NR_setresgid32                (__NR_SYSCALL_BASE+210)
+#define __NR_getresgid32                (__NR_SYSCALL_BASE+211)
+#define __NR_chown32                    (__NR_SYSCALL_BASE+212)
+#define __NR_setuid32                   (__NR_SYSCALL_BASE+213)
+#define __NR_setgid32                   (__NR_SYSCALL_BASE+214)
+#define __NR_setfsuid32                 (__NR_SYSCALL_BASE+215)
+#define __NR_setfsgid32                 (__NR_SYSCALL_BASE+216)
+#define __NR_getdents64                 (__NR_SYSCALL_BASE+217)
+#define __NR_pivot_root                 (__NR_SYSCALL_BASE+218)
+#define __NR_mincore                    (__NR_SYSCALL_BASE+219)
+#define __NR_madvise                    (__NR_SYSCALL_BASE+220)
+#define __NR_fcntl64                    (__NR_SYSCALL_BASE+221)
+                                        /* 222 for tux */
+                                        /* 223 is unused */
+#define __NR_gettid                     (__NR_SYSCALL_BASE+224)
+#define __NR_readahead                  (__NR_SYSCALL_BASE+225)
+#define __NR_setxattr                   (__NR_SYSCALL_BASE+226)
+#define __NR_lsetxattr                  (__NR_SYSCALL_BASE+227)
+#define __NR_fsetxattr                  (__NR_SYSCALL_BASE+228)
+#define __NR_getxattr                   (__NR_SYSCALL_BASE+229)
+#define __NR_lgetxattr                  (__NR_SYSCALL_BASE+230)
+#define __NR_fgetxattr                  (__NR_SYSCALL_BASE+231)
+#define __NR_listxattr                  (__NR_SYSCALL_BASE+232)
+#define __NR_llistxattr                 (__NR_SYSCALL_BASE+233)
+#define __NR_flistxattr                 (__NR_SYSCALL_BASE+234)
+#define __NR_removexattr                (__NR_SYSCALL_BASE+235)
+#define __NR_lremovexattr               (__NR_SYSCALL_BASE+236)
+#define __NR_fremovexattr               (__NR_SYSCALL_BASE+237)
+#define __NR_tkill                      (__NR_SYSCALL_BASE+238)
+#define __NR_sendfile64                 (__NR_SYSCALL_BASE+239)
+#define __NR_futex                      (__NR_SYSCALL_BASE+240)
+#define __NR_sched_setaffinity          (__NR_SYSCALL_BASE+241)
+#define __NR_sched_getaffinity          (__NR_SYSCALL_BASE+242)
+#define __NR_io_setup                   (__NR_SYSCALL_BASE+243)
+#define __NR_io_destroy                 (__NR_SYSCALL_BASE+244)
+#define __NR_io_getevents               (__NR_SYSCALL_BASE+245)
+#define __NR_io_submit                  (__NR_SYSCALL_BASE+246)
+#define __NR_io_cancel                  (__NR_SYSCALL_BASE+247)
+#define __NR_exit_group                 (__NR_SYSCALL_BASE+248)
+#define __NR_lookup_dcookie             (__NR_SYSCALL_BASE+249)
+#define __NR_epoll_create               (__NR_SYSCALL_BASE+250)
+#define __NR_epoll_ctl                  (__NR_SYSCALL_BASE+251)
+#define __NR_epoll_wait                 (__NR_SYSCALL_BASE+252)
+#define __NR_remap_file_pages           (__NR_SYSCALL_BASE+253)
+                                        /* 254 for set_thread_area */
+                                        /* 255 for get_thread_area */
+#define __NR_set_tid_address            (__NR_SYSCALL_BASE+256)
+#define __NR_timer_create               (__NR_SYSCALL_BASE+257)
+#define __NR_timer_settime              (__NR_SYSCALL_BASE+258)
+#define __NR_timer_gettime              (__NR_SYSCALL_BASE+259)
+#define __NR_timer_getoverrun           (__NR_SYSCALL_BASE+260)
+#define __NR_timer_delete               (__NR_SYSCALL_BASE+261)
+#define __NR_clock_settime              (__NR_SYSCALL_BASE+262)
+#define __NR_clock_gettime              (__NR_SYSCALL_BASE+263)
+#define __NR_clock_getres               (__NR_SYSCALL_BASE+264)
+#define __NR_clock_nanosleep            (__NR_SYSCALL_BASE+265)
+#define __NR_statfs64                   (__NR_SYSCALL_BASE+266)
+#define __NR_fstatfs64                  (__NR_SYSCALL_BASE+267)
+#define __NR_tgkill                     (__NR_SYSCALL_BASE+268)
+#define __NR_utimes                     (__NR_SYSCALL_BASE+269)
+#define __NR_fadvise64_64               (__NR_SYSCALL_BASE+270)
+#define __NR_pciconfig_iobase           (__NR_SYSCALL_BASE+271)
+#define __NR_pciconfig_read             (__NR_SYSCALL_BASE+272)
+#define __NR_pciconfig_write            (__NR_SYSCALL_BASE+273)
+#define __NR_mq_open                    (__NR_SYSCALL_BASE+274)
+#define __NR_mq_unlink                  (__NR_SYSCALL_BASE+275)
+#define __NR_mq_timedsend               (__NR_SYSCALL_BASE+276)
+#define __NR_mq_timedreceive            (__NR_SYSCALL_BASE+277)
+#define __NR_mq_notify                  (__NR_SYSCALL_BASE+278)
+#define __NR_mq_getsetattr              (__NR_SYSCALL_BASE+279)
+#define __NR_waitid                     (__NR_SYSCALL_BASE+280)
+
+#if 0 /* reserve these for un-muxing socketcall */
+#define __NR_socket                     (__NR_SYSCALL_BASE+281)
+#define __NR_bind                       (__NR_SYSCALL_BASE+282)
+#define __NR_connect                    (__NR_SYSCALL_BASE+283)
+#define __NR_listen                     (__NR_SYSCALL_BASE+284)
+#define __NR_accept                     (__NR_SYSCALL_BASE+285)
+#define __NR_getsockname                (__NR_SYSCALL_BASE+286)
+#define __NR_getpeername                (__NR_SYSCALL_BASE+287)
+#define __NR_socketpair                 (__NR_SYSCALL_BASE+288)
+#define __NR_send                       (__NR_SYSCALL_BASE+289)
+#define __NR_sendto                     (__NR_SYSCALL_BASE+290)
+#define __NR_recv                       (__NR_SYSCALL_BASE+291)
+#define __NR_recvfrom                   (__NR_SYSCALL_BASE+292)
+#define __NR_shutdown                   (__NR_SYSCALL_BASE+293)
+#define __NR_setsockopt                 (__NR_SYSCALL_BASE+294)
+#define __NR_getsockopt                 (__NR_SYSCALL_BASE+295)
+#define __NR_sendmsg                    (__NR_SYSCALL_BASE+296)
+#define __NR_recvmsg                    (__NR_SYSCALL_BASE+297)
+#endif
+
+#if 0 /* reserve these for un-muxing ipc */
+#define __NR_semop                      (__NR_SYSCALL_BASE+298)
+#define __NR_semget                     (__NR_SYSCALL_BASE+299)
+#define __NR_semctl                     (__NR_SYSCALL_BASE+300)
+#define __NR_msgsnd                     (__NR_SYSCALL_BASE+301)
+#define __NR_msgrcv                     (__NR_SYSCALL_BASE+302)
+#define __NR_msgget                     (__NR_SYSCALL_BASE+303)
+#define __NR_msgctl                     (__NR_SYSCALL_BASE+304)
+#define __NR_shmat                      (__NR_SYSCALL_BASE+305)
+#define __NR_shmdt                      (__NR_SYSCALL_BASE+306)
+#define __NR_shmget                     (__NR_SYSCALL_BASE+307)
+#define __NR_shmctl                     (__NR_SYSCALL_BASE+308)
+#endif
+
+#define __NR_add_key                    (__NR_SYSCALL_BASE+309)
+#define __NR_request_key                (__NR_SYSCALL_BASE+310)
+#define __NR_keyctl                     (__NR_SYSCALL_BASE+311)
+
+#if 0 /* reserved for un-muxing ipc */
+#define __NR_semtimedop                 (__NR_SYSCALL_BASE+312)
+#endif
+
+#define __NR_vserver                    (__NR_SYSCALL_BASE+313)
+
+/*
+ * The following SWIs are ARM private.
+ */
+#define __ARM_NR_BASE                   (__NR_SYSCALL_BASE+0x0f0000)
+#define __ARM_NR_breakpoint             (__ARM_NR_BASE+1)
+#define __ARM_NR_cacheflush             (__ARM_NR_BASE+2)
+#define __ARM_NR_usr26                  (__ARM_NR_BASE+3)
+#define __ARM_NR_usr32                  (__ARM_NR_BASE+4)
+
+#define __ARM_NR_set_tls                (__ARM_NR_BASE+0x800)
+
+#define __sys2(x) #x
+#define __sys1(x) __sys2(x)
+
+#ifndef __syscall
+#if defined(__thumb__)
+#define __syscall(name)                                 \
+        "push   {r7}\n\t"                               \
+        "mov    r7, #" __sys1(__NR_##name) "\n\t"       \
+        "swi    0\n\t"                                  \
+        "pop    {r7}"
+#else
+#define __syscall(name) "swi\t" __sys1(__NR_##name) ""
+#endif
+#endif
+
+#define __syscall_return(type, res)                                     \
+do {                                                                    \
+        if ((unsigned long)(res) >= (unsigned long)(-129)) {            \
+                errno = -(res);                                         \
+                res = -1;                                               \
+        }                                                               \
+        return (type) (res);                                            \
+} while (0)
+
+#define _syscall0(type,name)                                            \
+type name(void) {                                                       \
+  register long __res_r0 __asm__("r0");                                 \
+  long __res;                                                           \
+  __asm__ __volatile__ (                                                \
+  __syscall(name)                                                       \
+        : "=r" (__res_r0)                                               \
+        :                                                               \
+        : "lr");                                                        \
+  __res = __res_r0;                                                     \
+  __syscall_return(type,__res);                                         \
+}
+
+#define _syscall1(type,name,type1,arg1)                                 \
+type name(type1 arg1) {                                                 \
+  register long __r0 __asm__("r0") = (long)arg1;                        \
+  register long __res_r0 __asm__("r0");                                 \
+  long __res;                                                           \
+  __asm__ __volatile__ (                                                \
+  __syscall(name)                                                       \
+        : "=r" (__res_r0)                                               \
+        : "r" (__r0)                                                    \
+        : "lr");                                                        \
+  __res = __res_r0;                                                     \
+  __syscall_return(type,__res);                                         \
+}
+
+#define _syscall2(type,name,type1,arg1,type2,arg2)                      \
+type name(type1 arg1,type2 arg2) {                                      \
+  register long __r0 __asm__("r0") = (long)arg1;                        \
+  register long __r1 __asm__("r1") = (long)arg2;                        \
+  register long __res_r0 __asm__("r0");                                 \
+  long __res;                                                           \
+  __asm__ __volatile__ (                                                \
+  __syscall(name)                                                       \
+        : "=r" (__res_r0)                                               \
+        : "r" (__r0),"r" (__r1)                                         \
+        : "lr");                                                        \
+  __res = __res_r0;                                                     \
+  __syscall_return(type,__res);                                         \
+}
+
+
+#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)           \
+type name(type1 arg1,type2 arg2,type3 arg3) {                           \
+  register long __r0 __asm__("r0") = (long)arg1;                        \
+  register long __r1 __asm__("r1") = (long)arg2;                        \
+  register long __r2 __asm__("r2") = (long)arg3;                        \
+  register long __res_r0 __asm__("r0");                                 \
+  long __res;                                                           \
+  __asm__ __volatile__ (                                                \
+  __syscall(name)                                                       \
+        : "=r" (__res_r0)                                               \
+        : "r" (__r0),"r" (__r1),"r" (__r2)                              \
+        : "lr");                                                        \
+  __res = __res_r0;                                                     \
+  __syscall_return(type,__res);                                         \
+}
+
+
+#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4)\
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) {             \
+  register long __r0 __asm__("r0") = (long)arg1;                        \
+  register long __r1 __asm__("r1") = (long)arg2;                        \
+  register long __r2 __asm__("r2") = (long)arg3;                        \
+  register long __r3 __asm__("r3") = (long)arg4;                        \
+  register long __res_r0 __asm__("r0");                                 \
+  long __res;                                                           \
+  __asm__ __volatile__ (                                                \
+  __syscall(name)                                                       \
+        : "=r" (__res_r0)                                               \
+        : "r" (__r0),"r" (__r1),"r" (__r2),"r" (__r3)                   \
+        : "lr");                                                        \
+  __res = __res_r0;                                                     \
+  __syscall_return(type,__res);                                         \
+}
+  
+
+#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5)     \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) { \
+  register long __r0 __asm__("r0") = (long)arg1;                        \
+  register long __r1 __asm__("r1") = (long)arg2;                        \
+  register long __r2 __asm__("r2") = (long)arg3;                        \
+  register long __r3 __asm__("r3") = (long)arg4;                        \
+  register long __r4 __asm__("r4") = (long)arg5;                        \
+  register long __res_r0 __asm__("r0");                                 \
+  long __res;                                                           \
+  __asm__ __volatile__ (                                                \
+  __syscall(name)                                                       \
+        : "=r" (__res_r0)                                               \
+        : "r" (__r0),"r" (__r1),"r" (__r2),"r" (__r3),"r" (__r4)        \
+        : "lr");                                                        \
+  __res = __res_r0;                                                     \
+  __syscall_return(type,__res);                                         \
+}
+
+#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6)  \
+type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) {     \
+  register long __r0 __asm__("r0") = (long)arg1;                        \
+  register long __r1 __asm__("r1") = (long)arg2;                        \
+  register long __r2 __asm__("r2") = (long)arg3;                        \
+  register long __r3 __asm__("r3") = (long)arg4;                        \
+  register long __r4 __asm__("r4") = (long)arg5;                        \
+  register long __r5 __asm__("r5") = (long)arg6;                        \
+  register long __res_r0 __asm__("r0");                                 \
+  long __res;                                                           \
+  __asm__ __volatile__ (                                                \
+  __syscall(name)                                                       \
+        : "=r" (__res_r0)                                               \
+        : "r" (__r0),"r" (__r1),"r" (__r2),"r" (__r3), "r" (__r4),"r" (__r5)            \
+        : "lr");                                                        \
+  __res = __res_r0;                                                     \
+  __syscall_return(type,__res);                                         \
+}
+
+#ifdef __KERNEL__
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_OLD_READDIR
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_UTIME
+#define __ARCH_WANT_SYS_SOCKETCALL
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_OLD_GETRLIMIT
+#define __ARCH_WANT_SYS_OLDUMOUNT
+#define __ARCH_WANT_SYS_SIGPENDING
+#define __ARCH_WANT_SYS_SIGPROCMASK
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#endif
+
+#ifdef __KERNEL_SYSCALLS__
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/syscalls.h>
+
+extern long execve(const char *file, char **argv, char **envp);
+
+struct pt_regs;
+asmlinkage int sys_execve(char *filenamei, char **argv, char **envp,
+                        struct pt_regs *regs);
+asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp,
+                        struct pt_regs *regs);
+asmlinkage int sys_fork(struct pt_regs *regs);
+asmlinkage int sys_vfork(struct pt_regs *regs);
+asmlinkage int sys_pipe(unsigned long *fildes);
+asmlinkage int sys_ptrace(long request, long pid, long addr, long data);
+struct sigaction;
+asmlinkage long sys_rt_sigaction(int sig,
+                                const struct sigaction __user *act,
+                                struct sigaction __user *oact,
+                                size_t sigsetsize);
+
+#endif
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
+
+#endif /* __ASM_ARM_UNISTD_H */
diff --git a/include/asm-arm/user.h b/include/asm-arm/user.h
new file mode 100644
index 000000000000..3e8b0f879159
--- /dev/null
+++ b/include/asm-arm/user.h
@@ -0,0 +1,84 @@
+#ifndef _ARM_USER_H
+#define _ARM_USER_H
+
+#include <asm/page.h>
+#include <asm/ptrace.h>
+/* Core file format: The core file is written in such a way that gdb
+   can understand it and provide useful information to the user (under
+   linux we use the 'trad-core' bfd).  There are quite a number of
+   obstacles to being able to view the contents of the floating point
+   registers, and until these are solved you will not be able to view the
+   contents of them.  Actually, you can read in the core file and look at
+   the contents of the user struct to find out what the floating point
+   registers contain.
+   The actual file contents are as follows:
+   UPAGE: 1 page consisting of a user struct that tells gdb what is present
+   in the file.  Directly after this is a copy of the task_struct, which
+   is currently not used by gdb, but it may come in useful at some point.
+   All of the registers are stored as part of the upage.  The upage should
+   always be only one page.
+   DATA: The data area is stored.  We use current->end_text to
+   current->brk to pick up all of the user variables, plus any memory
+   that may have been malloced.  No attempt is made to determine if a page
+   is demand-zero or if a page is totally unused, we just cover the entire
+   range.  All of the addresses are rounded in such a way that an integral
+   number of pages is written.
+   STACK: We need the stack information in order to get a meaningful
+   backtrace.  We need to write the data from (esp) to
+   current->start_stack, so we round each of these off in order to be able
+   to write an integer number of pages.
+   The minimum core file size is 3 pages, or 12288 bytes.
+*/
+
+struct user_fp {
+        struct fp_reg {
+                unsigned int sign1:1;
+                unsigned int unused:15;
+                unsigned int sign2:1;
+                unsigned int exponent:14;
+                unsigned int j:1;
+                unsigned int mantissa1:31;
+                unsigned int mantissa0:32;
+        } fpregs[8];
+        unsigned int fpsr:32;
+        unsigned int fpcr:32;
+        unsigned char ftype[8];
+        unsigned int init_flag;
+};
+
+/* When the kernel dumps core, it starts by dumping the user struct -
+   this will be used by gdb to figure out where the data and stack segments
+   are within the file, and what virtual addresses to use. */
+struct user{
+/* We start with the registers, to mimic the way that "memory" is returned
+   from the ptrace(3,...) function.  */
+  struct pt_regs regs;          /* Where the registers are actually stored */
+/* ptrace does not yet supply these.  Someday.... */
+  int u_fpvalid;                /* True if math co-processor being used. */
+                                /* for this mess. Not yet used. */
+/* The rest of this junk is to help gdb figure out what goes where */
+  unsigned long int u_tsize;    /* Text segment size (pages). */
+  unsigned long int u_dsize;    /* Data segment size (pages). */
+  unsigned long int u_ssize;    /* Stack segment size (pages). */
+  unsigned long start_code;     /* Starting virtual address of text. */
+  unsigned long start_stack;    /* Starting virtual address of stack area.
+                                   This is actually the bottom of the stack,
+                                   the top of the stack is always found in the
+                                   esp register.  */
+  long int signal;              /* Signal that caused the core dump. */
+  int reserved;                 /* No longer used */
+  struct pt_regs * u_ar0;       /* Used by gdb to help find the values for */
+                                /* the registers. */
+  unsigned long magic;          /* To uniquely identify a core file */
+  char u_comm[32];              /* User command that was responsible */
+  int u_debugreg[8];
+  struct user_fp u_fp;          /* FP state */
+  struct user_fp_struct * u_fp0;/* Used by gdb to help find the values for */
+                                /* the FP registers. */
+};
+#define NBPG PAGE_SIZE
+#define UPAGES 1
+#define HOST_TEXT_START_ADDR (u.start_code)
+#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
+
+#endif /* _ARM_USER_H */
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
new file mode 100644
index 000000000000..14c5e0946c47
--- /dev/null
+++ b/include/asm-arm/vfp.h
@@ -0,0 +1,78 @@
+/*
+ * linux/include/asm-arm/vfp.h
+ *
+ * VFP register definitions.
+ * First, the standard VFP set.
+ */
+
+#define FPSID                   cr0
+#define FPSCR                   cr1
+#define FPEXC                   cr8
+
+/* FPSID bits */
+#define FPSID_IMPLEMENTER_BIT   (24)
+#define FPSID_IMPLEMENTER_MASK  (0xff << FPSID_IMPLEMENTER_BIT)
+#define FPSID_SOFTWARE          (1<<23)
+#define FPSID_FORMAT_BIT        (21)
+#define FPSID_FORMAT_MASK       (0x3  << FPSID_FORMAT_BIT)
+#define FPSID_NODOUBLE          (1<<20)
+#define FPSID_ARCH_BIT          (16)
+#define FPSID_ARCH_MASK         (0xF  << FPSID_ARCH_BIT)
+#define FPSID_PART_BIT          (8)
+#define FPSID_PART_MASK         (0xFF << FPSID_PART_BIT)
+#define FPSID_VARIANT_BIT       (4)
+#define FPSID_VARIANT_MASK      (0xF  << FPSID_VARIANT_BIT)
+#define FPSID_REV_BIT           (0)
+#define FPSID_REV_MASK          (0xF  << FPSID_REV_BIT)
+
+/* FPEXC bits */
+#define FPEXC_EXCEPTION         (1<<31)
+#define FPEXC_ENABLE            (1<<30)
+
+/* FPSCR bits */
+#define FPSCR_DEFAULT_NAN       (1<<25)
+#define FPSCR_FLUSHTOZERO       (1<<24)
+#define FPSCR_ROUND_NEAREST     (0<<22)
+#define FPSCR_ROUND_PLUSINF     (1<<22)
+#define FPSCR_ROUND_MINUSINF    (2<<22)
+#define FPSCR_ROUND_TOZERO      (3<<22)
+#define FPSCR_RMODE_BIT         (22)
+#define FPSCR_RMODE_MASK        (3 << FPSCR_RMODE_BIT)
+#define FPSCR_STRIDE_BIT        (20)
+#define FPSCR_STRIDE_MASK       (3 << FPSCR_STRIDE_BIT)
+#define FPSCR_LENGTH_BIT        (16)
+#define FPSCR_LENGTH_MASK       (7 << FPSCR_LENGTH_BIT)
+#define FPSCR_IOE               (1<<8)
+#define FPSCR_DZE               (1<<9)
+#define FPSCR_OFE               (1<<10)
+#define FPSCR_UFE               (1<<11)
+#define FPSCR_IXE               (1<<12)
+#define FPSCR_IDE               (1<<15)
+#define FPSCR_IOC               (1<<0)
+#define FPSCR_DZC               (1<<1)
+#define FPSCR_OFC               (1<<2)
+#define FPSCR_UFC               (1<<3)
+#define FPSCR_IXC               (1<<4)
+#define FPSCR_IDC               (1<<7)
+
+/*
+ * VFP9-S specific.
+ */
+#define FPINST                  cr9
+#define FPINST2                 cr10
+
+/* FPEXC bits */
+#define FPEXC_FPV2              (1<<28)
+#define FPEXC_LENGTH_BIT        (8)
+#define FPEXC_LENGTH_MASK       (7 << FPEXC_LENGTH_BIT)
+#define FPEXC_INV               (1 << 7)
+#define FPEXC_UFC               (1 << 3)
+#define FPEXC_OFC               (1 << 2)
+#define FPEXC_IOC               (1 << 0)
+
+/* Bit patterns for decoding the packaged operation descriptors */
+#define VFPOPDESC_LENGTH_BIT    (9)
+#define VFPOPDESC_LENGTH_MASK   (0x07 << VFPOPDESC_LENGTH_BIT)
+#define VFPOPDESC_UNUSED_BIT    (24)
+#define VFPOPDESC_UNUSED_MASK   (0xFF << VFPOPDESC_UNUSED_BIT)
+#define VFPOPDESC_OPDESC_MASK   (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK))
diff --git a/include/asm-arm/vfpmacros.h b/include/asm-arm/vfpmacros.h
new file mode 100644
index 000000000000..15bd6e74c9cf
--- /dev/null
+++ b/include/asm-arm/vfpmacros.h
@@ -0,0 +1,25 @@
+/*
+ * linux/include/asm-arm/vfpmacros.h
+ *
+ * Assembler-only file containing VFP macros and register definitions.
+ */
+#include "vfp.h"
+
+@ Macros to allow building with old toolkits (with no VFP support)
+        .macro  VFPFMRX, rd, sysreg, cond
+        MRC\cond        p10, 7, \rd, \sysreg, cr0, 0    @ FMRX  \rd, \sysreg
+        .endm
+
+        .macro  VFPFMXR, sysreg, rd, cond
+        MCR\cond        p10, 7, \rd, \sysreg, cr0, 0    @ FMXR  \sysreg, \rd
+        .endm
+
+        @ read all the working registers back into the VFP
+        .macro  VFPFLDMIA, base
+        LDC     p11, cr0, [\base],#33*4             @ FLDMIAX \base!, {d0-d15}
+        .endm
+
+        @ write all the working registers out of the VFP
+        .macro  VFPFSTMIA, base
+        STC     p11, cr0, [\base],#33*4             @ FSTMIAX \base!, {d0-d15}
+        .endm
diff --git a/include/asm-arm/vga.h b/include/asm-arm/vga.h
new file mode 100644
index 000000000000..926e5ee128e9
--- /dev/null
+++ b/include/asm-arm/vga.h
@@ -0,0 +1,12 @@
+#ifndef ASMARM_VGA_H
+#define ASMARM_VGA_H
+
+#include <asm/hardware.h>
+#include <asm/io.h>
+
+#define VGA_MAP_MEM(x)  (PCIMEM_BASE + (x))
+
+#define vga_readb(x)    (*((volatile unsigned char *)x))
+#define vga_writeb(x,y) (*((volatile unsigned char *)y) = (x))
+
+#endif
diff --git a/include/asm-arm/xor.h b/include/asm-arm/xor.h
new file mode 100644
index 000000000000..e7c4cf58bed1
--- /dev/null
+++ b/include/asm-arm/xor.h
@@ -0,0 +1,141 @@
+/*
+ *  linux/include/asm-arm/xor.h
+ *
+ *  Copyright (C) 2001 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <asm-generic/xor.h>
+
+#define __XOR(a1, a2) a1 ^= a2
+
+#define GET_BLOCK_2(dst) \
+        __asm__("ldmia  %0, {%1, %2}" \
+                : "=r" (dst), "=r" (a1), "=r" (a2) \
+                : "0" (dst))
+
+#define GET_BLOCK_4(dst) \
+        __asm__("ldmia  %0, {%1, %2, %3, %4}" \
+                : "=r" (dst), "=r" (a1), "=r" (a2), "=r" (a3), "=r" (a4) \
+                : "0" (dst))
+
+#define XOR_BLOCK_2(src) \
+        __asm__("ldmia  %0!, {%1, %2}" \
+                : "=r" (src), "=r" (b1), "=r" (b2) \
+                : "0" (src)); \
+        __XOR(a1, b1); __XOR(a2, b2);
+
+#define XOR_BLOCK_4(src) \
+        __asm__("ldmia  %0!, {%1, %2, %3, %4}" \
+                : "=r" (src), "=r" (b1), "=r" (b2), "=r" (b3), "=r" (b4) \
+                : "0" (src)); \
+        __XOR(a1, b1); __XOR(a2, b2); __XOR(a3, b3); __XOR(a4, b4)
+
+#define PUT_BLOCK_2(dst) \
+        __asm__ __volatile__("stmia     %0!, {%2, %3}" \
+                : "=r" (dst) \
+                : "0" (dst), "r" (a1), "r" (a2))
+
+#define PUT_BLOCK_4(dst) \
+        __asm__ __volatile__("stmia     %0!, {%2, %3, %4, %5}" \
+                : "=r" (dst) \
+                : "0" (dst), "r" (a1), "r" (a2), "r" (a3), "r" (a4))
+
+static void
+xor_arm4regs_2(unsigned long bytes, unsigned long *p1, unsigned long *p2)
+{
+        unsigned int lines = bytes / sizeof(unsigned long) / 4;
+        register unsigned int a1 __asm__("r4");
+        register unsigned int a2 __asm__("r5");
+        register unsigned int a3 __asm__("r6");
+        register unsigned int a4 __asm__("r7");
+        register unsigned int b1 __asm__("r8");
+        register unsigned int b2 __asm__("r9");
+        register unsigned int b3 __asm__("ip");
+        register unsigned int b4 __asm__("lr");
+
+        do {
+                GET_BLOCK_4(p1);
+                XOR_BLOCK_4(p2);
+                PUT_BLOCK_4(p1);
+        } while (--lines);
+}
+
+static void
+xor_arm4regs_3(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+                unsigned long *p3)
+{
+        unsigned int lines = bytes / sizeof(unsigned long) / 4;
+        register unsigned int a1 __asm__("r4");
+        register unsigned int a2 __asm__("r5");
+        register unsigned int a3 __asm__("r6");
+        register unsigned int a4 __asm__("r7");
+        register unsigned int b1 __asm__("r8");
+        register unsigned int b2 __asm__("r9");
+        register unsigned int b3 __asm__("ip");
+        register unsigned int b4 __asm__("lr");
+
+        do {
+                GET_BLOCK_4(p1);
+                XOR_BLOCK_4(p2);
+                XOR_BLOCK_4(p3);
+                PUT_BLOCK_4(p1);
+        } while (--lines);
+}
+
+static void
+xor_arm4regs_4(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+                unsigned long *p3, unsigned long *p4)
+{
+        unsigned int lines = bytes / sizeof(unsigned long) / 2;
+        register unsigned int a1 __asm__("r8");
+        register unsigned int a2 __asm__("r9");
+        register unsigned int b1 __asm__("ip");
+        register unsigned int b2 __asm__("lr");
+
+        do {
+                GET_BLOCK_2(p1);
+                XOR_BLOCK_2(p2);
+                XOR_BLOCK_2(p3);
+                XOR_BLOCK_2(p4);
+                PUT_BLOCK_2(p1);
+        } while (--lines);
+}
+
+static void
+xor_arm4regs_5(unsigned long bytes, unsigned long *p1, unsigned long *p2,
+                unsigned long *p3, unsigned long *p4, unsigned long *p5)
+{
+        unsigned int lines = bytes / sizeof(unsigned long) / 2;
+        register unsigned int a1 __asm__("r8");
+        register unsigned int a2 __asm__("r9");
+        register unsigned int b1 __asm__("ip");
+        register unsigned int b2 __asm__("lr");
+
+        do {
+                GET_BLOCK_2(p1);
+                XOR_BLOCK_2(p2);
+                XOR_BLOCK_2(p3);
+                XOR_BLOCK_2(p4);
+                XOR_BLOCK_2(p5);
+                PUT_BLOCK_2(p1);
+        } while (--lines);
+}
+
+static struct xor_block_template xor_block_arm4regs = {
+        .name   = "arm4regs",
+        .do_2   = xor_arm4regs_2,
+        .do_3   = xor_arm4regs_3,
+        .do_4   = xor_arm4regs_4,
+        .do_5   = xor_arm4regs_5,
+};
+
+#undef XOR_TRY_TEMPLATES
+#define XOR_TRY_TEMPLATES                       \
+        do {                                    \
+                xor_speed(&xor_block_arm4regs); \
+                xor_speed(&xor_block_8regs);    \
+                xor_speed(&xor_block_32regs);   \
+        } while (0)