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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-03-02 17:41:59 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-03-21 17:05:45 -0500
commitf80658137fc8b789a71953adeca194a5a4747427 (patch)
tree55a634d2720412f2d70546576f7bc5e035e8b1b3 /include/asm-arm
parentec1248e70edc5cf7b485efcc7b41e44e10f422e5 (diff)
[ARM] Move HZ definition into Kconfig
Move the HZ definition into Kconfig, and set appropriate defaults for platforms. Remove mostly empty asm/arch/param.h include file. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-aaec2000/param.h15
-rw-r--r--include/asm-arm/arch-at91rm9200/param.h28
-rw-r--r--include/asm-arm/arch-cl7500/param.h5
-rw-r--r--include/asm-arm/arch-clps711x/param.h19
-rw-r--r--include/asm-arm/arch-ebsa110/param.h4
-rw-r--r--include/asm-arm/arch-ebsa285/param.h3
-rw-r--r--include/asm-arm/arch-h720x/param.h10
-rw-r--r--include/asm-arm/arch-imx/param.h19
-rw-r--r--include/asm-arm/arch-integrator/param.h19
-rw-r--r--include/asm-arm/arch-iop3xx/param.h3
-rw-r--r--include/asm-arm/arch-ixp2000/param.h3
-rw-r--r--include/asm-arm/arch-ixp4xx/param.h3
-rw-r--r--include/asm-arm/arch-l7200/param.h19
-rw-r--r--include/asm-arm/arch-lh7a40x/param.h9
-rw-r--r--include/asm-arm/arch-omap/param.h8
-rw-r--r--include/asm-arm/arch-pxa/param.h3
-rw-r--r--include/asm-arm/arch-realview/param.h19
-rw-r--r--include/asm-arm/arch-rpc/param.h3
-rw-r--r--include/asm-arm/arch-s3c2410/param.h27
-rw-r--r--include/asm-arm/arch-sa1100/param.h3
-rw-r--r--include/asm-arm/arch-shark/param.h5
-rw-r--r--include/asm-arm/arch-versatile/param.h19
-rw-r--r--include/asm-arm/param.h7
23 files changed, 1 insertions, 252 deletions
diff --git a/include/asm-arm/arch-aaec2000/param.h b/include/asm-arm/arch-aaec2000/param.h
deleted file mode 100644
index 139936c2faf2..000000000000
--- a/include/asm-arm/arch-aaec2000/param.h
+++ /dev/null
@@ -1,15 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-aaec2000/param.h
3 *
4 * Copyright (c) 2005 Nicolas Bellido Y Ortega
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_PARAM_H
12#define __ASM_ARCH_PARAM_H
13
14#endif /* __ASM_ARCH_PARAM_H */
15
diff --git a/include/asm-arm/arch-at91rm9200/param.h b/include/asm-arm/arch-at91rm9200/param.h
deleted file mode 100644
index 9480f8446852..000000000000
--- a/include/asm-arm/arch-at91rm9200/param.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * include/asm-arm/arch-at91rm9200/param.h
3 *
4 * Copyright (C) 2003 SAN People
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef __ASM_ARCH_PARAM_H
22#define __ASM_ARCH_PARAM_H
23
24/*
25 * We use default params
26 */
27
28#endif
diff --git a/include/asm-arm/arch-cl7500/param.h b/include/asm-arm/arch-cl7500/param.h
deleted file mode 100644
index 974bf69fbb1a..000000000000
--- a/include/asm-arm/arch-cl7500/param.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-cl7500/param.h
3 *
4 * Copyright (C) 1999 Nexus Electronics Ltd
5 */
diff --git a/include/asm-arm/arch-clps711x/param.h b/include/asm-arm/arch-clps711x/param.h
deleted file mode 100644
index 86f6bd29623d..000000000000
--- a/include/asm-arm/arch-clps711x/param.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-clps711x/param.h
3 *
4 * Copyright (C) 2000 Deep Blue Solutions Ltd.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-ebsa110/param.h b/include/asm-arm/arch-ebsa110/param.h
deleted file mode 100644
index be19b08d1c75..000000000000
--- a/include/asm-arm/arch-ebsa110/param.h
+++ /dev/null
@@ -1,4 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-ebsa110/param.h
3 */
4#define HZ 200
diff --git a/include/asm-arm/arch-ebsa285/param.h b/include/asm-arm/arch-ebsa285/param.h
deleted file mode 100644
index 3827103b27a0..000000000000
--- a/include/asm-arm/arch-ebsa285/param.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-ebsa285/param.h
3 */
diff --git a/include/asm-arm/arch-h720x/param.h b/include/asm-arm/arch-h720x/param.h
deleted file mode 100644
index 2b80235f9847..000000000000
--- a/include/asm-arm/arch-h720x/param.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-h720x/param.h
3 *
4 * Copyright (C) 2000 Jungjun Kim
5 */
6
7#ifndef __ASM_ARCH_PARAM_H
8#define __ASM_ARCH_PARAM_H
9
10#endif
diff --git a/include/asm-arm/arch-imx/param.h b/include/asm-arm/arch-imx/param.h
deleted file mode 100644
index 7c724f03333e..000000000000
--- a/include/asm-arm/arch-imx/param.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-imx/param.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-integrator/param.h b/include/asm-arm/arch-integrator/param.h
deleted file mode 100644
index afa582ff3717..000000000000
--- a/include/asm-arm/arch-integrator/param.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-integrator/param.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-iop3xx/param.h b/include/asm-arm/arch-iop3xx/param.h
deleted file mode 100644
index acf404e87358..000000000000
--- a/include/asm-arm/arch-iop3xx/param.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/param.h
3 */
diff --git a/include/asm-arm/arch-ixp2000/param.h b/include/asm-arm/arch-ixp2000/param.h
deleted file mode 100644
index 2646d9e5919d..000000000000
--- a/include/asm-arm/arch-ixp2000/param.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-ixp2000/param.h
3 */
diff --git a/include/asm-arm/arch-ixp4xx/param.h b/include/asm-arm/arch-ixp4xx/param.h
deleted file mode 100644
index 8a757125e5e7..000000000000
--- a/include/asm-arm/arch-ixp4xx/param.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-ixp4xx/param.h
3 */
diff --git a/include/asm-arm/arch-l7200/param.h b/include/asm-arm/arch-l7200/param.h
deleted file mode 100644
index 9962a12ab158..000000000000
--- a/include/asm-arm/arch-l7200/param.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-l7200/param.h
3 *
4 * Copyright (C) 2000 Rob Scott (rscott@mtrob.fdns.net)
5 * Steve Hill (sjhill@cotw.com)
6 *
7 * This file contains the hardware definitions for the
8 * LinkUp Systems L7200 SOC development board.
9 *
10 * Changelog:
11 * 04-21-2000 RS Created L7200 version
12 * 04-25-2000 SJH Cleaned up file
13 * 05-03-2000 SJH Change comments and rate
14 */
15
16/*
17 * See 'time.h' for how the RTC HZ rate is set
18 */
19#define HZ 128
diff --git a/include/asm-arm/arch-lh7a40x/param.h b/include/asm-arm/arch-lh7a40x/param.h
deleted file mode 100644
index acad0bc5deba..000000000000
--- a/include/asm-arm/arch-lh7a40x/param.h
+++ /dev/null
@@ -1,9 +0,0 @@
1/* include/asm-arm/arch-lh7a40x/param.h
2 *
3 * Copyright (C) 2004 Coastal Environmental Systems
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
diff --git a/include/asm-arm/arch-omap/param.h b/include/asm-arm/arch-omap/param.h
deleted file mode 100644
index face9ad41e97..000000000000
--- a/include/asm-arm/arch-omap/param.h
+++ /dev/null
@@ -1,8 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/param.h
3 *
4 */
5
6#ifdef CONFIG_OMAP_32K_TIMER_HZ
7#define HZ CONFIG_OMAP_32K_TIMER_HZ
8#endif
diff --git a/include/asm-arm/arch-pxa/param.h b/include/asm-arm/arch-pxa/param.h
deleted file mode 100644
index 3197d82d7573..000000000000
--- a/include/asm-arm/arch-pxa/param.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-pxa/param.h
3 */
diff --git a/include/asm-arm/arch-realview/param.h b/include/asm-arm/arch-realview/param.h
deleted file mode 100644
index 89b1235d32bd..000000000000
--- a/include/asm-arm/arch-realview/param.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-realview/param.h
3 *
4 * Copyright (C) 2002 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/arch-rpc/param.h b/include/asm-arm/arch-rpc/param.h
deleted file mode 100644
index 721dcd658858..000000000000
--- a/include/asm-arm/arch-rpc/param.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-rpc/param.h
3 */
diff --git a/include/asm-arm/arch-s3c2410/param.h b/include/asm-arm/arch-s3c2410/param.h
deleted file mode 100644
index 483d3f149883..000000000000
--- a/include/asm-arm/arch-s3c2410/param.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/param.h
2 *
3 * (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - Machine parameters
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 02-Sep-2003 BJD Created file
14 * 12-Mar-2004 BJD Added include protection
15*/
16
17#ifndef __ASM_ARCH_PARAM_H
18#define __ASM_ARCH_PARAM_H
19
20/* we cannot get our timer down to 100Hz with the setup as is, but we can
21 * manage 200 clock ticks per second... if this is a problem, we can always
22 * add a software pre-scaler to the evil timer systems.
23*/
24
25#define HZ 200
26
27#endif /* __ASM_ARCH_PARAM_H */
diff --git a/include/asm-arm/arch-sa1100/param.h b/include/asm-arm/arch-sa1100/param.h
deleted file mode 100644
index 867488909ecd..000000000000
--- a/include/asm-arm/arch-sa1100/param.h
+++ /dev/null
@@ -1,3 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-sa1100/param.h
3 */
diff --git a/include/asm-arm/arch-shark/param.h b/include/asm-arm/arch-shark/param.h
deleted file mode 100644
index 997eeb71de00..000000000000
--- a/include/asm-arm/arch-shark/param.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-shark/param.h
3 *
4 * by Alexander Schulz
5 */
diff --git a/include/asm-arm/arch-versatile/param.h b/include/asm-arm/arch-versatile/param.h
deleted file mode 100644
index 34b897335f87..000000000000
--- a/include/asm-arm/arch-versatile/param.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-versatile/param.h
3 *
4 * Copyright (C) 2002 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
diff --git a/include/asm-arm/param.h b/include/asm-arm/param.h
index 94223d4d7e88..15806468ba72 100644
--- a/include/asm-arm/param.h
+++ b/include/asm-arm/param.h
@@ -11,12 +11,7 @@
11#define __ASM_PARAM_H 11#define __ASM_PARAM_H
12 12
13#ifdef __KERNEL__ 13#ifdef __KERNEL__
14# include <asm/arch/param.h> /* for kernel version of HZ */ 14# define HZ CONFIG_HZ /* Internal kernel timer frequency */
15
16# ifndef HZ
17# define HZ 100 /* Internal kernel timer frequency */
18# endif
19
20# define USER_HZ 100 /* User interfaces are in "ticks" */ 15# define USER_HZ 100 /* User interfaces are in "ticks" */
21# define CLOCKS_PER_SEC (USER_HZ) /* like times() */ 16# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
22#else 17#else
="hl kwb">r14 ld r14,PACA_EXDBG+EX_R14(r13) ld r15,PACA_EXDBG+EX_R15(r13) bl .save_nvgprs bl .DebugException b .ret_from_except MASKABLE_EXCEPTION(0x260, perfmon, .performance_monitor_exception, ACK_NONE) /* Doorbell interrupt */ MASKABLE_EXCEPTION(0x2070, doorbell, .doorbell_exception, ACK_NONE) /* Doorbell critical Interrupt */ START_EXCEPTION(doorbell_crit); CRIT_EXCEPTION_PROLOG(0x2080, PROLOG_ADDITION_NONE) // EXCEPTION_COMMON(0x2080, PACA_EXCRIT, INTS_DISABLE_ALL) // bl special_reg_save_crit // CHECK_NAPPING(); // addi r3,r1,STACK_FRAME_OVERHEAD // bl .doorbell_critical_exception // b ret_from_crit_except b . MASKABLE_EXCEPTION(0x2c0, guest_doorbell, .unknown_exception, ACK_NONE) MASKABLE_EXCEPTION(0x2e0, guest_doorbell_crit, .unknown_exception, ACK_NONE) MASKABLE_EXCEPTION(0x310, hypercall, .unknown_exception, ACK_NONE) MASKABLE_EXCEPTION(0x320, ehpriv, .unknown_exception, ACK_NONE) /* * An interrupt came in while soft-disabled; clear EE in SRR1, * clear paca->hard_enabled and return. */ masked_interrupt_book3e: mtcr r10 stb r11,PACAHARDIRQEN(r13) mfspr r10,SPRN_SRR1 rldicl r11,r10,48,1 /* clear MSR_EE */ rotldi r10,r11,16 mtspr SPRN_SRR1,r10 ld r10,PACA_EXGEN+EX_R10(r13); /* restore registers */ ld r11,PACA_EXGEN+EX_R11(r13); mfspr r13,SPRN_SPRG_GEN_SCRATCH; rfi b . /* * This is called from 0x300 and 0x400 handlers after the prologs with * r14 and r15 containing the fault address and error code, with the * original values stashed away in the PACA */ storage_fault_common: std r14,_DAR(r1) std r15,_DSISR(r1) addi r3,r1,STACK_FRAME_OVERHEAD mr r4,r14 mr r5,r15 ld r14,PACA_EXGEN+EX_R14(r13) ld r15,PACA_EXGEN+EX_R15(r13) INTS_RESTORE_HARD bl .do_page_fault cmpdi r3,0 bne- 1f b .ret_from_except_lite 1: bl .save_nvgprs mr r5,r3 addi r3,r1,STACK_FRAME_OVERHEAD ld r4,_DAR(r1) bl .bad_page_fault b .ret_from_except /* * Alignment exception doesn't fit entirely in the 0x100 bytes so it * continues here. */ alignment_more: std r14,_DAR(r1) std r15,_DSISR(r1) addi r3,r1,STACK_FRAME_OVERHEAD ld r14,PACA_EXGEN+EX_R14(r13) ld r15,PACA_EXGEN+EX_R15(r13) bl .save_nvgprs INTS_RESTORE_HARD bl .alignment_exception b .ret_from_except /* * We branch here from entry_64.S for the last stage of the exception * return code path. MSR:EE is expected to be off at that point */ _GLOBAL(exception_return_book3e) b 1f /* This is the return from load_up_fpu fast path which could do with * less GPR restores in fact, but for now we have a single return path */ .globl fast_exception_return fast_exception_return: wrteei 0 1: mr r0,r13 ld r10,_MSR(r1) REST_4GPRS(2, r1) andi. r6,r10,MSR_PR REST_2GPRS(6, r1) beq 1f ACCOUNT_CPU_USER_EXIT(r10, r11) ld r0,GPR13(r1) 1: stdcx. r0,0,r1 /* to clear the reservation */ ld r8,_CCR(r1) ld r9,_LINK(r1) ld r10,_CTR(r1) ld r11,_XER(r1) mtcr r8 mtlr r9 mtctr r10 mtxer r11 REST_2GPRS(8, r1) ld r10,GPR10(r1) ld r11,GPR11(r1) ld r12,GPR12(r1) mtspr SPRN_SPRG_GEN_SCRATCH,r0 std r10,PACA_EXGEN+EX_R10(r13); std r11,PACA_EXGEN+EX_R11(r13); ld r10,_NIP(r1) ld r11,_MSR(r1) ld r0,GPR0(r1) ld r1,GPR1(r1) mtspr SPRN_SRR0,r10 mtspr SPRN_SRR1,r11 ld r10,PACA_EXGEN+EX_R10(r13) ld r11,PACA_EXGEN+EX_R11(r13) mfspr r13,SPRN_SPRG_GEN_SCRATCH rfi /* * Trampolines used when spotting a bad kernel stack pointer in * the exception entry code. * * TODO: move some bits like SRR0 read to trampoline, pass PACA * index around, etc... to handle crit & mcheck */ BAD_STACK_TRAMPOLINE(0x000) BAD_STACK_TRAMPOLINE(0x100) BAD_STACK_TRAMPOLINE(0x200) BAD_STACK_TRAMPOLINE(0x260) BAD_STACK_TRAMPOLINE(0x2c0) BAD_STACK_TRAMPOLINE(0x2e0) BAD_STACK_TRAMPOLINE(0x300) BAD_STACK_TRAMPOLINE(0x310) BAD_STACK_TRAMPOLINE(0x320) BAD_STACK_TRAMPOLINE(0x400) BAD_STACK_TRAMPOLINE(0x500) BAD_STACK_TRAMPOLINE(0x600) BAD_STACK_TRAMPOLINE(0x700) BAD_STACK_TRAMPOLINE(0x800) BAD_STACK_TRAMPOLINE(0x900) BAD_STACK_TRAMPOLINE(0x980) BAD_STACK_TRAMPOLINE(0x9f0) BAD_STACK_TRAMPOLINE(0xa00) BAD_STACK_TRAMPOLINE(0xb00) BAD_STACK_TRAMPOLINE(0xc00) BAD_STACK_TRAMPOLINE(0xd00) BAD_STACK_TRAMPOLINE(0xe00) BAD_STACK_TRAMPOLINE(0xf00) BAD_STACK_TRAMPOLINE(0xf20) BAD_STACK_TRAMPOLINE(0x2070) BAD_STACK_TRAMPOLINE(0x2080) .globl bad_stack_book3e bad_stack_book3e: /* XXX: Needs to make SPRN_SPRG_GEN depend on exception type */ mfspr r10,SPRN_SRR0; /* read SRR0 before touching stack */ ld r1,PACAEMERGSP(r13) subi r1,r1,64+INT_FRAME_SIZE std r10,_NIP(r1) std r11,_MSR(r1) ld r10,PACA_EXGEN+EX_R1(r13) /* FIXME for crit & mcheck */ lwz r11,PACA_EXGEN+EX_CR(r13) /* FIXME for crit & mcheck */ std r10,GPR1(r1) std r11,_CCR(r1) mfspr r10,SPRN_DEAR mfspr r11,SPRN_ESR std r10,_DAR(r1) std r11,_DSISR(r1) std r0,GPR0(r1); /* save r0 in stackframe */ \ std r2,GPR2(r1); /* save r2 in stackframe */ \ SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \ SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \ std r9,GPR9(r1); /* save r9 in stackframe */ \ ld r3,PACA_EXGEN+EX_R10(r13);/* get back r10 */ \ ld r4,PACA_EXGEN+EX_R11(r13);/* get back r11 */ \ mfspr r5,SPRN_SPRG_GEN_SCRATCH;/* get back r13 XXX can be wrong */ \ std r3,GPR10(r1); /* save r10 to stackframe */ \ std r4,GPR11(r1); /* save r11 to stackframe */ \ std r12,GPR12(r1); /* save r12 in stackframe */ \ std r5,GPR13(r1); /* save it to stackframe */ \ mflr r10 mfctr r11 mfxer r12 std r10,_LINK(r1) std r11,_CTR(r1) std r12,_XER(r1) SAVE_10GPRS(14,r1) SAVE_8GPRS(24,r1) lhz r12,PACA_TRAP_SAVE(r13) std r12,_TRAP(r1) addi r11,r1,INT_FRAME_SIZE std r11,0(r1) li r12,0 std r12,0(r11) ld r2,PACATOC(r13) 1: addi r3,r1,STACK_FRAME_OVERHEAD bl .kernel_bad_stack b 1b /* * Setup the initial TLB for a core. This current implementation * assume that whatever we are running off will not conflict with * the new mapping at PAGE_OFFSET. */ _GLOBAL(initial_tlb_book3e) /* Look for the first TLB with IPROT set */ mfspr r4,SPRN_TLB0CFG andi. r3,r4,TLBnCFG_IPROT lis r3,MAS0_TLBSEL(0)@h bne found_iprot mfspr r4,SPRN_TLB1CFG andi. r3,r4,TLBnCFG_IPROT lis r3,MAS0_TLBSEL(1)@h bne found_iprot mfspr r4,SPRN_TLB2CFG andi. r3,r4,TLBnCFG_IPROT lis r3,MAS0_TLBSEL(2)@h bne found_iprot lis r3,MAS0_TLBSEL(3)@h mfspr r4,SPRN_TLB3CFG /* fall through */ found_iprot: andi. r5,r4,TLBnCFG_HES bne have_hes mflr r8 /* save LR */ /* 1. Find the index of the entry we're executing in * * r3 = MAS0_TLBSEL (for the iprot array) * r4 = SPRN_TLBnCFG */ bl invstr /* Find our address */ invstr: mflr r6 /* Make it accessible */ mfmsr r7 rlwinm r5,r7,27,31,31 /* extract MSR[IS] */ mfspr r7,SPRN_PID slwi r7,r7,16 or r7,r7,r5 mtspr SPRN_MAS6,r7 tlbsx 0,r6 /* search MSR[IS], SPID=PID */ mfspr r3,SPRN_MAS0 rlwinm r5,r3,16,20,31 /* Extract MAS0(Entry) */ mfspr r7,SPRN_MAS1 /* Insure IPROT set */ oris r7,r7,MAS1_IPROT@h mtspr SPRN_MAS1,r7 tlbwe /* 2. Invalidate all entries except the entry we're executing in * * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in * r4 = SPRN_TLBnCFG * r5 = ESEL of entry we are running in */ andi. r4,r4,TLBnCFG_N_ENTRY /* Extract # entries */ li r6,0 /* Set Entry counter to 0 */ 1: mr r7,r3 /* Set MAS0(TLBSEL) */ rlwimi r7,r6,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r6) */ mtspr SPRN_MAS0,r7 tlbre mfspr r7,SPRN_MAS1 rlwinm r7,r7,0,2,31 /* Clear MAS1 Valid and IPROT */ cmpw r5,r6 beq skpinv /* Dont update the current execution TLB */ mtspr SPRN_MAS1,r7 tlbwe isync skpinv: addi r6,r6,1 /* Increment */ cmpw r6,r4 /* Are we done? */ bne 1b /* If not, repeat */ /* Invalidate all TLBs */ PPC_TLBILX_ALL(0,0) sync isync /* 3. Setup a temp mapping and jump to it * * r3 = MAS0 w/TLBSEL & ESEL for the entry we are running in * r5 = ESEL of entry we are running in */ andi. r7,r5,0x1 /* Find an entry not used and is non-zero */ addi r7,r7,0x1 mr r4,r3 /* Set MAS0(TLBSEL) = 1 */ mtspr SPRN_MAS0,r4 tlbre rlwimi r4,r7,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r7) */ mtspr SPRN_MAS0,r4 mfspr r7,SPRN_MAS1 xori r6,r7,MAS1_TS /* Setup TMP mapping in the other Address space */ mtspr SPRN_MAS1,r6 tlbwe mfmsr r6 xori r6,r6,MSR_IS mtspr SPRN_SRR1,r6 bl 1f /* Find our address */ 1: mflr r6 addi r6,r6,(2f - 1b) mtspr SPRN_SRR0,r6 rfi 2: /* 4. Clear out PIDs & Search info * * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping * r5 = MAS3 */ li r6,0 mtspr SPRN_MAS6,r6 mtspr SPRN_PID,r6 /* 5. Invalidate mapping we started in * * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping * r5 = MAS3 */ mtspr SPRN_MAS0,r3 tlbre mfspr r6,SPRN_MAS1 rlwinm r6,r6,0,2,0 /* clear IPROT */ mtspr SPRN_MAS1,r6 tlbwe /* Invalidate TLB1 */ PPC_TLBILX_ALL(0,0) sync isync /* The mapping only needs to be cache-coherent on SMP */ #ifdef CONFIG_SMP #define M_IF_SMP MAS2_M #else #define M_IF_SMP 0 #endif /* 6. Setup KERNELBASE mapping in TLB[0] * * r3 = MAS0 w/TLBSEL & ESEL for the entry we started in * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping * r5 = MAS3 */ rlwinm r3,r3,0,16,3 /* clear ESEL */ mtspr SPRN_MAS0,r3 lis r6,(MAS1_VALID|MAS1_IPROT)@h ori r6,r6,(MAS1_TSIZE(BOOK3E_PAGESZ_1GB))@l mtspr SPRN_MAS1,r6 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET | M_IF_SMP) mtspr SPRN_MAS2,r6 rlwinm r5,r5,0,0,25 ori r5,r5,MAS3_SR | MAS3_SW | MAS3_SX mtspr SPRN_MAS3,r5 li r5,-1 rlwinm r5,r5,0,0,25 tlbwe /* 7. Jump to KERNELBASE mapping * * r4 = MAS0 w/TLBSEL & ESEL for the temp mapping */ /* Now we branch the new virtual address mapped by this entry */ LOAD_REG_IMMEDIATE(r6,2f) lis r7,MSR_KERNEL@h ori r7,r7,MSR_KERNEL@l mtspr SPRN_SRR0,r6 mtspr SPRN_SRR1,r7 rfi /* start execution out of TLB1[0] entry */ 2: /* 8. Clear out the temp mapping * * r4 = MAS0 w/TLBSEL & ESEL for the entry we are running in */ mtspr SPRN_MAS0,r4 tlbre mfspr r5,SPRN_MAS1 rlwinm r5,r5,0,2,0 /* clear IPROT */ mtspr SPRN_MAS1,r5 tlbwe /* Invalidate TLB1 */ PPC_TLBILX_ALL(0,0) sync isync /* We translate LR and return */ tovirt(r8,r8) mtlr r8 blr have_hes: /* Setup MAS 0,1,2,3 and 7 for tlbwe of a 1G entry that maps the * kernel linear mapping. We also set MAS8 once for all here though * that will have to be made dependent on whether we are running under * a hypervisor I suppose. */ /* BEWARE, MAGIC * This code is called as an ordinary function on the boot CPU. But to * avoid duplication, this code is also used in SCOM bringup of * secondary CPUs. We read the code between the initial_tlb_code_start * and initial_tlb_code_end labels one instruction at a time and RAM it * into the new core via SCOM. That doesn't process branches, so there * must be none between those two labels. It also means if this code * ever takes any parameters, the SCOM code must also be updated to * provide them. */ .globl a2_tlbinit_code_start a2_tlbinit_code_start: ori r11,r3,MAS0_WQ_ALLWAYS oris r11,r11,MAS0_ESEL(3)@h /* Use way 3: workaround A2 erratum 376 */ mtspr SPRN_MAS0,r11 lis r3,(MAS1_VALID | MAS1_IPROT)@h ori r3,r3,BOOK3E_PAGESZ_1GB << MAS1_TSIZE_SHIFT mtspr SPRN_MAS1,r3 LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET | MAS2_M) mtspr SPRN_MAS2,r3 li r3,MAS3_SR | MAS3_SW | MAS3_SX mtspr SPRN_MAS7_MAS3,r3 li r3,0 mtspr SPRN_MAS8,r3 /* Write the TLB entry */ tlbwe .globl a2_tlbinit_after_linear_map a2_tlbinit_after_linear_map: /* Now we branch the new virtual address mapped by this entry */ LOAD_REG_IMMEDIATE(r3,1f) mtctr r3 bctr 1: /* We are now running at PAGE_OFFSET, clean the TLB of everything * else (including IPROTed things left by firmware) * r4 = TLBnCFG * r3 = current address (more or less) */ li r5,0 mtspr SPRN_MAS6,r5 tlbsx 0,r3 rlwinm r9,r4,0,TLBnCFG_N_ENTRY rlwinm r10,r4,8,0xff addi r10,r10,-1 /* Get inner loop mask */ li r3,1 mfspr r5,SPRN_MAS1 rlwinm r5,r5,0,(~(MAS1_VALID|MAS1_IPROT)) mfspr r6,SPRN_MAS2 rldicr r6,r6,0,51 /* Extract EPN */ mfspr r7,SPRN_MAS0 rlwinm r7,r7,0,0xffff0fff /* Clear HES and WQ */ rlwinm r8,r7,16,0xfff /* Extract ESEL */ 2: add r4,r3,r8 and r4,r4,r10 rlwimi r7,r4,16,MAS0_ESEL_MASK mtspr SPRN_MAS0,r7 mtspr SPRN_MAS1,r5 mtspr SPRN_MAS2,r6 tlbwe addi r3,r3,1 and. r4,r3,r10 bne 3f addis r6,r6,(1<<30)@h 3: cmpw r3,r9 blt 2b .globl a2_tlbinit_after_iprot_flush a2_tlbinit_after_iprot_flush: #ifdef CONFIG_PPC_EARLY_DEBUG_WSP /* Now establish early debug mappings if applicable */ /* Restore the MAS0 we used for linear mapping load */ mtspr SPRN_MAS0,r11 lis r3,(MAS1_VALID | MAS1_IPROT)@h ori r3,r3,(BOOK3E_PAGESZ_4K << MAS1_TSIZE_SHIFT) mtspr SPRN_MAS1,r3 LOAD_REG_IMMEDIATE(r3, WSP_UART_VIRT | MAS2_I | MAS2_G) mtspr SPRN_MAS2,r3 LOAD_REG_IMMEDIATE(r3, WSP_UART_PHYS | MAS3_SR | MAS3_SW) mtspr SPRN_MAS7_MAS3,r3 /* re-use the MAS8 value from the linear mapping */ tlbwe #endif /* CONFIG_PPC_EARLY_DEBUG_WSP */ PPC_TLBILX(0,0,0) sync isync .globl a2_tlbinit_code_end a2_tlbinit_code_end: /* We translate LR and return */ mflr r3 tovirt(r3,r3) mtlr r3 blr /* * Main entry (boot CPU, thread 0) * * We enter here from head_64.S, possibly after the prom_init trampoline * with r3 and r4 already saved to r31 and 30 respectively and in 64 bits * mode. Anything else is as it was left by the bootloader * * Initial requirements of this port: * * - Kernel loaded at 0 physical * - A good lump of memory mapped 0:0 by UTLB entry 0 * - MSR:IS & MSR:DS set to 0 * * Note that some of the above requirements will be relaxed in the future * as the kernel becomes smarter at dealing with different initial conditions * but for now you have to be careful */ _GLOBAL(start_initialization_book3e) mflr r28 /* First, we need to setup some initial TLBs to map the kernel * text, data and bss at PAGE_OFFSET. We don't have a real mode * and always use AS 0, so we just set it up to match our link * address and never use 0 based addresses. */ bl .initial_tlb_book3e /* Init global core bits */ bl .init_core_book3e /* Init per-thread bits */ bl .init_thread_book3e /* Return to common init code */ tovirt(r28,r28) mtlr r28 blr /* * Secondary core/processor entry * * This is entered for thread 0 of a secondary core, all other threads * are expected to be stopped. It's similar to start_initialization_book3e * except that it's generally entered from the holding loop in head_64.S * after CPUs have been gathered by Open Firmware. * * We assume we are in 32 bits mode running with whatever TLB entry was * set for us by the firmware or POR engine. */ _GLOBAL(book3e_secondary_core_init_tlb_set) li r4,1 b .generic_secondary_smp_init _GLOBAL(book3e_secondary_core_init) mflr r28 /* Do we need to setup initial TLB entry ? */ cmplwi r4,0 bne 2f /* Setup TLB for this core */ bl .initial_tlb_book3e /* We can return from the above running at a different * address, so recalculate r2 (TOC) */ bl .relative_toc /* Init global core bits */ 2: bl .init_core_book3e /* Init per-thread bits */ 3: bl .init_thread_book3e /* Return to common init code at proper virtual address. * * Due to various previous assumptions, we know we entered this * function at either the final PAGE_OFFSET mapping or using a * 1:1 mapping at 0, so we don't bother doing a complicated check * here, we just ensure the return address has the right top bits. * * Note that if we ever want to be smarter about where we can be * started from, we have to be careful that by the time we reach * the code below we may already be running at a different location * than the one we were called from since initial_tlb_book3e can * have moved us already. */ cmpdi cr0,r28,0 blt 1f lis r3,PAGE_OFFSET@highest sldi r3,r3,32 or r28,r28,r3 1: mtlr r28 blr _GLOBAL(book3e_secondary_thread_init) mflr r28 b 3b _STATIC(init_core_book3e) /* Establish the interrupt vector base */ LOAD_REG_IMMEDIATE(r3, interrupt_base_book3e) mtspr SPRN_IVPR,r3 sync blr _STATIC(init_thread_book3e) lis r3,(SPRN_EPCR_ICM | SPRN_EPCR_GICM)@h mtspr SPRN_EPCR,r3 /* Make sure interrupts are off */ wrteei 0 /* disable all timers and clear out status */ li r3,0 mtspr SPRN_TCR,r3 mfspr r3,SPRN_TSR mtspr SPRN_TSR,r3 blr _GLOBAL(__setup_base_ivors) SET_IVOR(0, 0x020) /* Critical Input */ SET_IVOR(1, 0x000) /* Machine Check */ SET_IVOR(2, 0x060) /* Data Storage */ SET_IVOR(3, 0x080) /* Instruction Storage */ SET_IVOR(4, 0x0a0) /* External Input */ SET_IVOR(5, 0x0c0) /* Alignment */ SET_IVOR(6, 0x0e0) /* Program */ SET_IVOR(7, 0x100) /* FP Unavailable */ SET_IVOR(8, 0x120) /* System Call */ SET_IVOR(9, 0x140) /* Auxiliary Processor Unavailable */ SET_IVOR(10, 0x160) /* Decrementer */ SET_IVOR(11, 0x180) /* Fixed Interval Timer */ SET_IVOR(12, 0x1a0) /* Watchdog Timer */ SET_IVOR(13, 0x1c0) /* Data TLB Error */ SET_IVOR(14, 0x1e0) /* Instruction TLB Error */ SET_IVOR(15, 0x040) /* Debug */ sync blr _GLOBAL(setup_perfmon_ivor) SET_IVOR(35, 0x260) /* Performance Monitor */ blr _GLOBAL(setup_doorbell_ivors) SET_IVOR(36, 0x280) /* Processor Doorbell */ SET_IVOR(37, 0x2a0) /* Processor Doorbell Crit */ /* Check MMUCFG[LPIDSIZE] to determine if we have category E.HV */ mfspr r10,SPRN_MMUCFG rlwinm. r10,r10,0,MMUCFG_LPIDSIZE beqlr SET_IVOR(38, 0x2c0) /* Guest Processor Doorbell */ SET_IVOR(39, 0x2e0) /* Guest Processor Doorbell Crit/MC */ blr _GLOBAL(setup_ehv_ivors) /* * We may be running as a guest and lack E.HV even on a chip * that normally has it. */ mfspr r10,SPRN_MMUCFG rlwinm. r10,r10,0,MMUCFG_LPIDSIZE beqlr SET_IVOR(40, 0x300) /* Embedded Hypervisor System Call */ SET_IVOR(41, 0x320) /* Embedded Hypervisor Privilege */ blr