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authorLen Brown <len.brown@intel.com>2005-09-03 02:44:09 -0400
committerLen Brown <len.brown@intel.com>2005-09-03 02:44:09 -0400
commit129521dcc94f781890f8f668219ab79f0073ff9f (patch)
tree9f70707c88da65577f38814fe37b24c4b4957d64 /include/asm-arm
parent824b558bbe2c298b165cdb54c33718994dda30bb (diff)
parentf505380ba7b98ec97bf25300c2a58aeae903530b (diff)
Merge linux-2.6 into linux-acpi-2.6 test
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h102
-rw-r--r--include/asm-arm/arch-ixp4xx/platform.h19
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h29
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h11
-rw-r--r--include/asm-arm/socket.h2
-rw-r--r--include/asm-arm/unistd.h3
6 files changed, 108 insertions, 58 deletions
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index 7495026e2c18..e350dcb544e8 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -383,39 +383,45 @@ __ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
383 *vaddr++ = inl(io_addr); 383 *vaddr++ = inl(io_addr);
384} 384}
385 385
386#define __is_io_address(p) (((unsigned long)p >= 0x0) && \ 386#define PIO_OFFSET 0x10000UL
387 ((unsigned long)p <= 0x0000ffff)) 387#define PIO_MASK 0x0ffffUL
388
389#define __is_io_address(p) (((unsigned long)p >= PIO_OFFSET) && \
390 ((unsigned long)p <= (PIO_MASK + PIO_OFFSET)))
388static inline unsigned int 391static inline unsigned int
389__ixp4xx_ioread8(void __iomem *port) 392__ixp4xx_ioread8(void __iomem *addr)
390{ 393{
394 unsigned long port = (unsigned long __force)addr;
391 if (__is_io_address(port)) 395 if (__is_io_address(port))
392 return (unsigned int)__ixp4xx_inb((unsigned int)port); 396 return (unsigned int)__ixp4xx_inb(port & PIO_MASK);
393 else 397 else
394#ifndef CONFIG_IXP4XX_INDIRECT_PCI 398#ifndef CONFIG_IXP4XX_INDIRECT_PCI
395 return (unsigned int)__raw_readb((u32)port); 399 return (unsigned int)__raw_readb(port);
396#else 400#else
397 return (unsigned int)__ixp4xx_readb((u32)port); 401 return (unsigned int)__ixp4xx_readb(port);
398#endif 402#endif
399} 403}
400 404
401static inline void 405static inline void
402__ixp4xx_ioread8_rep(u32 port, u8 *vaddr, u32 count) 406__ixp4xx_ioread8_rep(void __iomem *addr, void *vaddr, u32 count)
403{ 407{
408 unsigned long port = (unsigned long __force)addr;
404 if (__is_io_address(port)) 409 if (__is_io_address(port))
405 __ixp4xx_insb(port, vaddr, count); 410 __ixp4xx_insb(port & PIO_MASK, vaddr, count);
406 else 411 else
407#ifndef CONFIG_IXP4XX_INDIRECT_PCI 412#ifndef CONFIG_IXP4XX_INDIRECT_PCI
408 __raw_readsb((void __iomem *)port, vaddr, count); 413 __raw_readsb(addr, vaddr, count);
409#else 414#else
410 __ixp4xx_readsb(port, vaddr, count); 415 __ixp4xx_readsb(port, vaddr, count);
411#endif 416#endif
412} 417}
413 418
414static inline unsigned int 419static inline unsigned int
415__ixp4xx_ioread16(void __iomem *port) 420__ixp4xx_ioread16(void __iomem *addr)
416{ 421{
422 unsigned long port = (unsigned long __force)addr;
417 if (__is_io_address(port)) 423 if (__is_io_address(port))
418 return (unsigned int)__ixp4xx_inw((unsigned int)port); 424 return (unsigned int)__ixp4xx_inw(port & PIO_MASK);
419 else 425 else
420#ifndef CONFIG_IXP4XX_INDIRECT_PCI 426#ifndef CONFIG_IXP4XX_INDIRECT_PCI
421 return le16_to_cpu(__raw_readw((u32)port)); 427 return le16_to_cpu(__raw_readw((u32)port));
@@ -425,23 +431,25 @@ __ixp4xx_ioread16(void __iomem *port)
425} 431}
426 432
427static inline void 433static inline void
428__ixp4xx_ioread16_rep(u32 port, u16 *vaddr, u32 count) 434__ixp4xx_ioread16_rep(void __iomem *addr, void *vaddr, u32 count)
429{ 435{
436 unsigned long port = (unsigned long __force)addr;
430 if (__is_io_address(port)) 437 if (__is_io_address(port))
431 __ixp4xx_insw(port, vaddr, count); 438 __ixp4xx_insw(port & PIO_MASK, vaddr, count);
432 else 439 else
433#ifndef CONFIG_IXP4XX_INDIRECT_PCI 440#ifndef CONFIG_IXP4XX_INDIRECT_PCI
434 __raw_readsw((void __iomem *)port, vaddr, count); 441 __raw_readsw(addr, vaddr, count);
435#else 442#else
436 __ixp4xx_readsw(port, vaddr, count); 443 __ixp4xx_readsw(port, vaddr, count);
437#endif 444#endif
438} 445}
439 446
440static inline unsigned int 447static inline unsigned int
441__ixp4xx_ioread32(void __iomem *port) 448__ixp4xx_ioread32(void __iomem *addr)
442{ 449{
450 unsigned long port = (unsigned long __force)addr;
443 if (__is_io_address(port)) 451 if (__is_io_address(port))
444 return (unsigned int)__ixp4xx_inl((unsigned int)port); 452 return (unsigned int)__ixp4xx_inl(port & PIO_MASK);
445 else { 453 else {
446#ifndef CONFIG_IXP4XX_INDIRECT_PCI 454#ifndef CONFIG_IXP4XX_INDIRECT_PCI
447 return le32_to_cpu(__raw_readl((u32)port)); 455 return le32_to_cpu(__raw_readl((u32)port));
@@ -452,90 +460,100 @@ __ixp4xx_ioread32(void __iomem *port)
452} 460}
453 461
454static inline void 462static inline void
455__ixp4xx_ioread32_rep(u32 port, u32 *vaddr, u32 count) 463__ixp4xx_ioread32_rep(void __iomem *addr, void *vaddr, u32 count)
456{ 464{
465 unsigned long port = (unsigned long __force)addr;
457 if (__is_io_address(port)) 466 if (__is_io_address(port))
458 __ixp4xx_insl(port, vaddr, count); 467 __ixp4xx_insl(port & PIO_MASK, vaddr, count);
459 else 468 else
460#ifndef CONFIG_IXP4XX_INDIRECT_PCI 469#ifndef CONFIG_IXP4XX_INDIRECT_PCI
461 __raw_readsl((void __iomem *)port, vaddr, count); 470 __raw_readsl(addr, vaddr, count);
462#else 471#else
463 __ixp4xx_readsl(port, vaddr, count); 472 __ixp4xx_readsl(port, vaddr, count);
464#endif 473#endif
465} 474}
466 475
467static inline void 476static inline void
468__ixp4xx_iowrite8(u8 value, void __iomem *port) 477__ixp4xx_iowrite8(u8 value, void __iomem *addr)
469{ 478{
479 unsigned long port = (unsigned long __force)addr;
470 if (__is_io_address(port)) 480 if (__is_io_address(port))
471 __ixp4xx_outb(value, (unsigned int)port); 481 __ixp4xx_outb(value, port & PIO_MASK);
472 else 482 else
473#ifndef CONFIG_IXP4XX_INDIRECT_PCI 483#ifndef CONFIG_IXP4XX_INDIRECT_PCI
474 __raw_writeb(value, (u32)port); 484 __raw_writeb(value, port);
475#else 485#else
476 __ixp4xx_writeb(value, (u32)port); 486 __ixp4xx_writeb(value, port);
477#endif 487#endif
478} 488}
479 489
480static inline void 490static inline void
481__ixp4xx_iowrite8_rep(u32 port, u8 *vaddr, u32 count) 491__ixp4xx_iowrite8_rep(void __iomem *addr, const void *vaddr, u32 count)
482{ 492{
493 unsigned long port = (unsigned long __force)addr;
483 if (__is_io_address(port)) 494 if (__is_io_address(port))
484 __ixp4xx_outsb(port, vaddr, count); 495 __ixp4xx_outsb(port & PIO_MASK, vaddr, count);
496 else
485#ifndef CONFIG_IXP4XX_INDIRECT_PCI 497#ifndef CONFIG_IXP4XX_INDIRECT_PCI
486 __raw_writesb((void __iomem *)port, vaddr, count); 498 __raw_writesb(addr, vaddr, count);
487#else 499#else
488 __ixp4xx_writesb(port, vaddr, count); 500 __ixp4xx_writesb(port, vaddr, count);
489#endif 501#endif
490} 502}
491 503
492static inline void 504static inline void
493__ixp4xx_iowrite16(u16 value, void __iomem *port) 505__ixp4xx_iowrite16(u16 value, void __iomem *addr)
494{ 506{
507 unsigned long port = (unsigned long __force)addr;
495 if (__is_io_address(port)) 508 if (__is_io_address(port))
496 __ixp4xx_outw(value, (unsigned int)port); 509 __ixp4xx_outw(value, port & PIO_MASK);
497 else 510 else
498#ifndef CONFIG_IXP4XX_INDIRECT_PCI 511#ifndef CONFIG_IXP4XX_INDIRECT_PCI
499 __raw_writew(cpu_to_le16(value), (u32)port); 512 __raw_writew(cpu_to_le16(value), addr);
500#else 513#else
501 __ixp4xx_writew(value, (u32)port); 514 __ixp4xx_writew(value, port);
502#endif 515#endif
503} 516}
504 517
505static inline void 518static inline void
506__ixp4xx_iowrite16_rep(u32 port, u16 *vaddr, u32 count) 519__ixp4xx_iowrite16_rep(void __iomem *addr, const void *vaddr, u32 count)
507{ 520{
521 unsigned long port = (unsigned long __force)addr;
508 if (__is_io_address(port)) 522 if (__is_io_address(port))
509 __ixp4xx_outsw(port, vaddr, count); 523 __ixp4xx_outsw(port & PIO_MASK, vaddr, count);
524 else
510#ifndef CONFIG_IXP4XX_INDIRECT_PCI 525#ifndef CONFIG_IXP4XX_INDIRECT_PCI
511 __raw_readsw((void __iomem *)port, vaddr, count); 526 __raw_writesw(addr, vaddr, count);
512#else 527#else
513 __ixp4xx_writesw(port, vaddr, count); 528 __ixp4xx_writesw(port, vaddr, count);
514#endif 529#endif
515} 530}
516 531
517static inline void 532static inline void
518__ixp4xx_iowrite32(u32 value, void __iomem *port) 533__ixp4xx_iowrite32(u32 value, void __iomem *addr)
519{ 534{
535 unsigned long port = (unsigned long __force)addr;
520 if (__is_io_address(port)) 536 if (__is_io_address(port))
521 __ixp4xx_outl(value, (unsigned int)port); 537 __ixp4xx_outl(value, port & PIO_MASK);
522 else 538 else
523#ifndef CONFIG_IXP4XX_INDIRECT_PCI 539#ifndef CONFIG_IXP4XX_INDIRECT_PCI
524 __raw_writel(cpu_to_le32(value), (u32)port); 540 __raw_writel(cpu_to_le32(value), port);
525#else 541#else
526 __ixp4xx_writel(value, (u32)port); 542 __ixp4xx_writel(value, port);
527#endif 543#endif
528} 544}
529 545
530static inline void 546static inline void
531__ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count) 547__ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
532{ 548{
549 unsigned long port = (unsigned long __force)addr;
533 if (__is_io_address(port)) 550 if (__is_io_address(port))
534 __ixp4xx_outsl(port, vaddr, count); 551 __ixp4xx_outsl(port & PIO_MASK, vaddr, count);
552 else
535#ifndef CONFIG_IXP4XX_INDIRECT_PCI 553#ifndef CONFIG_IXP4XX_INDIRECT_PCI
536 __raw_readsl((void __iomem *)port, vaddr, count); 554 __raw_writesl(addr, vaddr, count);
537#else 555#else
538 __ixp4xx_outsl(port, vaddr, count); 556 __ixp4xx_writesl(port, vaddr, count);
539#endif 557#endif
540} 558}
541 559
@@ -555,7 +573,7 @@ __ixp4xx_iowrite32_rep(u32 port, u32 *vaddr, u32 count)
555#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c) 573#define iowrite16_rep(p, v, c) __ixp4xx_iowrite16_rep(p, v, c)
556#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c) 574#define iowrite32_rep(p, v, c) __ixp4xx_iowrite32_rep(p, v, c)
557 575
558#define ioport_map(port, nr) ((void __iomem*)port) 576#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
559#define ioport_unmap(addr) 577#define ioport_unmap(addr)
560 578
561#endif // __ASM_ARM_ARCH_IO_H 579#endif // __ASM_ARM_ARCH_IO_H
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
index 3a626c03ea26..d13ee7f78c70 100644
--- a/include/asm-arm/arch-ixp4xx/platform.h
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -83,17 +83,6 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
83#define IXP4XX_GPIO_OUT 0x1 83#define IXP4XX_GPIO_OUT 0x1
84#define IXP4XX_GPIO_IN 0x2 84#define IXP4XX_GPIO_IN 0x2
85 85
86#define IXP4XX_GPIO_INTSTYLE_MASK 0x7C /* Bits [6:2] define interrupt style */
87
88/*
89 * GPIO interrupt types.
90 */
91#define IXP4XX_GPIO_ACTIVE_HIGH 0x4 /* Default */
92#define IXP4XX_GPIO_ACTIVE_LOW 0x8
93#define IXP4XX_GPIO_RISING_EDGE 0x10
94#define IXP4XX_GPIO_FALLING_EDGE 0x20
95#define IXP4XX_GPIO_TRANSITIONAL 0x40
96
97/* GPIO signal types */ 86/* GPIO signal types */
98#define IXP4XX_GPIO_LOW 0 87#define IXP4XX_GPIO_LOW 0
99#define IXP4XX_GPIO_HIGH 1 88#define IXP4XX_GPIO_HIGH 1
@@ -102,7 +91,13 @@ extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
102#define IXP4XX_GPIO_CLK_0 14 91#define IXP4XX_GPIO_CLK_0 14
103#define IXP4XX_GPIO_CLK_1 15 92#define IXP4XX_GPIO_CLK_1 15
104 93
105extern void gpio_line_config(u8 line, u32 style); 94static inline void gpio_line_config(u8 line, u32 direction)
95{
96 if (direction == IXP4XX_GPIO_OUT)
97 *IXP4XX_GPIO_GPOER |= (1 << line);
98 else
99 *IXP4XX_GPIO_GPOER &= ~(1 << line);
100}
106 101
107static inline void gpio_line_get(u8 line, int *value) 102static inline void gpio_line_get(u8 line, int *value)
108{ 103{
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 51f0fe0ac165..939d9e5020a0 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -818,6 +818,23 @@
818#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge 818#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
819 Interrupt Enable */ 819 Interrupt Enable */
820 820
821#define UP2OCR __REG(0x40600020) /* USB Port 2 Output Control register */
822
823#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
824#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
825#define UP2OCR_DPPDE (1 << 2) /* Host Port 2 Transceiver D+ Pull Down Enable */
826#define UP2OCR_DMPDE (1 << 3) /* Host Port 2 Transceiver D- Pull Down Enable */
827#define UP2OCR_DPPUE (1 << 4) /* Host Port 2 Transceiver D+ Pull Up Enable */
828#define UP2OCR_DMPUE (1 << 5) /* Host Port 2 Transceiver D- Pull Up Enable */
829#define UP2OCR_DPPUBE (1 << 6) /* Host Port 2 Transceiver D+ Pull Up Bypass Enable */
830#define UP2OCR_DMPUBE (1 << 7) /* Host Port 2 Transceiver D- Pull Up Bypass Enable */
831#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
832#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
833#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
834#define UP2OCR_HXS (1 << 16) /* Host Port 2 Transceiver Output Select */
835#define UP2OCR_HXOE (1 << 17) /* Host Port 2 Transceiver Output Enable */
836#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
837
821#define UDCCSN(x) __REG2(0x40600100, (x) << 2) 838#define UDCCSN(x) __REG2(0x40600100, (x) << 2)
822#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */ 839#define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
823#define UDCCSR0_SA (1 << 7) /* Setup Active */ 840#define UDCCSR0_SA (1 << 7) /* Setup Active */
@@ -1423,6 +1440,7 @@
1423#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) 1440#define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN)
1424#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) 1441#define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT)
1425#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) 1442#define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT)
1443#define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT)
1426#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) 1444#define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT)
1427#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) 1445#define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT)
1428#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) 1446#define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT)
@@ -1510,6 +1528,8 @@
1510#define PSSR_BFS (1 << 1) /* Battery Fault Status */ 1528#define PSSR_BFS (1 << 1) /* Battery Fault Status */
1511#define PSSR_SSS (1 << 0) /* Software Sleep Status */ 1529#define PSSR_SSS (1 << 0) /* Software Sleep Status */
1512 1530
1531#define PSLR_SL_ROD (1 << 20) /* Sleep-Mode/Depp-Sleep Mode nRESET_OUT Disable */
1532
1513#define PCFR_RO (1 << 15) /* RDH Override */ 1533#define PCFR_RO (1 << 15) /* RDH Override */
1514#define PCFR_PO (1 << 14) /* PH Override */ 1534#define PCFR_PO (1 << 14) /* PH Override */
1515#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */ 1535#define PCFR_GPROD (1 << 12) /* GPIO nRESET_OUT Disable */
@@ -1517,6 +1537,7 @@
1517#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */ 1537#define PCFR_FVC (1 << 10) /* Frequency/Voltage Change */
1518#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */ 1538#define PCFR_DC_EN (1 << 7) /* Sleep/deep-sleep DC-DC Converter Enable */
1519#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */ 1539#define PCFR_PI2CEN (1 << 6) /* Enable PI2C controller */
1540#define PCFR_GPR_EN (1 << 4) /* nRESET_GPIO Pin Enable */
1520#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ 1541#define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1521#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ 1542#define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1522#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ 1543#define PCFR_FP (1 << 1) /* Float PCMCIA controls */
@@ -1810,6 +1831,11 @@
1810#define LCCR0_PDD_S 12 1831#define LCCR0_PDD_S 12
1811#define LCCR0_BM (1 << 20) /* Branch mask */ 1832#define LCCR0_BM (1 << 20) /* Branch mask */
1812#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ 1833#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
1834#define LCCR0_LCDT (1 << 22) /* LCD panel type */
1835#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
1836#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
1837#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
1838#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
1813 1839
1814#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ 1840#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
1815#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ 1841#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
@@ -2062,7 +2088,10 @@
2062#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */ 2088#define UHCFMN __REG(0x4C00003C) /* UHC Frame Number */
2063#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */ 2089#define UHCPERS __REG(0x4C000040) /* UHC Periodic Start */
2064#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */ 2090#define UHCLS __REG(0x4C000044) /* UHC Low Speed Threshold */
2091
2065#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */ 2092#define UHCRHDA __REG(0x4C000048) /* UHC Root Hub Descriptor A */
2093#define UHCRHDA_NOCP (1 << 12) /* No over current protection */
2094
2066#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */ 2095#define UHCRHDB __REG(0x4C00004C) /* UHC Root Hub Descriptor B */
2067#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */ 2096#define UHCRHS __REG(0x4C000050) /* UHC Root Hub Status */
2068#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */ 2097#define UHCRHPS1 __REG(0x4C000054) /* UHC Root Hub Port 1 Status */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index e5e938b79acc..16f4c3cc1388 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -1,7 +1,7 @@
1/* linux/include/asm/arch-s3c2410/regs-clock.h 1/* linux/include/asm/arch-s3c2410/regs-clock.h
2 * 2 *
3 * Copyright (c) 2003,2004 Simtec Electronics <linux@simtec.co.uk> 3 * Copyright (c) 2003,2004,2005 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/ 4 * http://armlinux.simtec.co.uk/
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
@@ -17,6 +17,7 @@
17 * 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion 17 * 29-Sep-2004 Ben Dooks Fixed usage for assembly inclusion
18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat) 18 * 10-Feb-2005 Ben Dooks Fixed CAMDIVN address (Guillaume Gourat)
19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA 19 * 10-Mar-2005 Lucas Villa Real Changed S3C2410_VA to S3C24XX_VA
20 * 27-Aug-2005 Ben Dooks Add clock-slow info
20 */ 21 */
21 22
22#ifndef __ASM_ARM_REGS_CLOCK 23#ifndef __ASM_ARM_REGS_CLOCK
@@ -74,6 +75,12 @@
74#define S3C2410_CLKDIVN_PDIVN (1<<0) 75#define S3C2410_CLKDIVN_PDIVN (1<<0)
75#define S3C2410_CLKDIVN_HDIVN (1<<1) 76#define S3C2410_CLKDIVN_HDIVN (1<<1)
76 77
78#define S3C2410_CLKSLOW_UCLK_OFF (1<<7)
79#define S3C2410_CLKSLOW_MPLL_OFF (1<<5)
80#define S3C2410_CLKSLOW_SLOW (1<<4)
81#define S3C2410_CLKSLOW_SLOWVAL(x) (x)
82#define S3C2410_CLKSLOW_GET_SLOWVAL(x) ((x) & 7)
83
77#ifndef __ASSEMBLY__ 84#ifndef __ASSEMBLY__
78 85
79static inline unsigned int 86static inline unsigned int
diff --git a/include/asm-arm/socket.h b/include/asm-arm/socket.h
index 46d20585d951..3c51da6438c9 100644
--- a/include/asm-arm/socket.h
+++ b/include/asm-arm/socket.h
@@ -14,6 +14,8 @@
14#define SO_BROADCAST 6 14#define SO_BROADCAST 6
15#define SO_SNDBUF 7 15#define SO_SNDBUF 7
16#define SO_RCVBUF 8 16#define SO_RCVBUF 8
17#define SO_SNDBUFFORCE 32
18#define SO_RCVBUFFORCE 33
17#define SO_KEEPALIVE 9 19#define SO_KEEPALIVE 9
18#define SO_OOBINLINE 10 20#define SO_OOBINLINE 10
19#define SO_NO_CHECK 11 21#define SO_NO_CHECK 11
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index abb36e54c966..278de61224d1 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -295,7 +295,7 @@
295#define __NR_fstatfs64 (__NR_SYSCALL_BASE+267) 295#define __NR_fstatfs64 (__NR_SYSCALL_BASE+267)
296#define __NR_tgkill (__NR_SYSCALL_BASE+268) 296#define __NR_tgkill (__NR_SYSCALL_BASE+268)
297#define __NR_utimes (__NR_SYSCALL_BASE+269) 297#define __NR_utimes (__NR_SYSCALL_BASE+269)
298#define __NR_fadvise64_64 (__NR_SYSCALL_BASE+270) 298#define __NR_arm_fadvise64_64 (__NR_SYSCALL_BASE+270)
299#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271) 299#define __NR_pciconfig_iobase (__NR_SYSCALL_BASE+271)
300#define __NR_pciconfig_read (__NR_SYSCALL_BASE+272) 300#define __NR_pciconfig_read (__NR_SYSCALL_BASE+272)
301#define __NR_pciconfig_write (__NR_SYSCALL_BASE+273) 301#define __NR_pciconfig_write (__NR_SYSCALL_BASE+273)
@@ -515,7 +515,6 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
515#define __ARCH_WANT_SYS_TIME 515#define __ARCH_WANT_SYS_TIME
516#define __ARCH_WANT_SYS_UTIME 516#define __ARCH_WANT_SYS_UTIME
517#define __ARCH_WANT_SYS_SOCKETCALL 517#define __ARCH_WANT_SYS_SOCKETCALL
518#define __ARCH_WANT_SYS_FADVISE64
519#define __ARCH_WANT_SYS_GETPGRP 518#define __ARCH_WANT_SYS_GETPGRP
520#define __ARCH_WANT_SYS_LLSEEK 519#define __ARCH_WANT_SYS_LLSEEK
521#define __ARCH_WANT_SYS_NICE 520#define __ARCH_WANT_SYS_NICE