aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm
diff options
context:
space:
mode:
authorCatalin Marinas <catalin.marinas@arm.com>2008-02-04 11:34:58 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-02-04 12:52:21 -0500
commit356cb470b84bda67738ba320a75629acae70e5fa (patch)
treec426d96dda62632d8b2b7ff69c22bc8f90bf4986 /include/asm-arm
parent93c2904d5081468128e66792a85439df314de773 (diff)
[ARM] 4816/1: RealView: Move the platform-specific definitions into board-eb.h
This patch moves the platform specific definitions from platform.h into the board-eb.h file. It drops the INT_* definitions as they are no longer used in irqs.h (moved to board-eb.h). It renames REALVIEW_* macros to REALVIEW_EB_* or REALVIEW_EB11MP_* to distinguish between standard EB and EB + the ARM11MPCore tile. The platform.h file contains common definitions to the RealView platforms and it is only directly included in board-*.h files. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-realview/board-eb.h152
-rw-r--r--include/asm-arm/arch-realview/entry-macro.S5
-rw-r--r--include/asm-arm/arch-realview/hardware.h1
-rw-r--r--include/asm-arm/arch-realview/irqs.h105
-rw-r--r--include/asm-arm/arch-realview/platform.h170
-rw-r--r--include/asm-arm/arch-realview/scu.h4
-rw-r--r--include/asm-arm/arch-realview/uncompress.h2
7 files changed, 181 insertions, 258 deletions
diff --git a/include/asm-arm/arch-realview/board-eb.h b/include/asm-arm/arch-realview/board-eb.h
new file mode 100644
index 000000000000..943efc5de4eb
--- /dev/null
+++ b/include/asm-arm/arch-realview/board-eb.h
@@ -0,0 +1,152 @@
1/*
2 * include/asm-arm/arch-realview/board-eb.h
3 *
4 * Copyright (C) 2007 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __ASM_ARCH_BOARD_EB_H
22#define __ASM_ARCH_BOARD_EB_H
23
24#include <asm/arch/platform.h>
25
26/*
27 * RealView EB + ARM11MPCore peripheral addresses
28 */
29#ifdef CONFIG_REALVIEW_MPCORE_REVB
30#define REALVIEW_EB11MP_SCU_BASE 0x10100000 /* SCU registers */
31#define REALVIEW_EB11MP_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
32#define REALVIEW_EB11MP_TWD_BASE 0x10100700
33#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
34#define REALVIEW_EB11MP_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
35#define REALVIEW_EB11MP_L220_BASE 0x10102000 /* L220 registers */
36#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
37#else
38#define REALVIEW_EB11MP_SCU_BASE 0x1F000000 /* SCU registers */
39#define REALVIEW_EB11MP_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
40#define REALVIEW_EB11MP_TWD_BASE 0x1F000700
41#define REALVIEW_EB11MP_TWD_SIZE 0x00000100
42#define REALVIEW_EB11MP_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
43#define REALVIEW_EB11MP_L220_BASE 0x1F002000 /* L220 registers */
44#define REALVIEW_EB11MP_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
45#endif
46
47#define IRQ_EB_GIC_START 32
48
49/*
50 * RealView EB interrupt sources
51 */
52#define IRQ_EB_WDOG (IRQ_EB_GIC_START + 0) /* Watchdog timer */
53#define IRQ_EB_SOFT (IRQ_EB_GIC_START + 1) /* Software interrupt */
54#define IRQ_EB_COMMRx (IRQ_EB_GIC_START + 2) /* Debug Comm Rx interrupt */
55#define IRQ_EB_COMMTx (IRQ_EB_GIC_START + 3) /* Debug Comm Tx interrupt */
56#define IRQ_EB_TIMER0_1 (IRQ_EB_GIC_START + 4) /* Timer 0 and 1 */
57#define IRQ_EB_TIMER2_3 (IRQ_EB_GIC_START + 5) /* Timer 2 and 3 */
58#define IRQ_EB_GPIO0 (IRQ_EB_GIC_START + 6) /* GPIO 0 */
59#define IRQ_EB_GPIO1 (IRQ_EB_GIC_START + 7) /* GPIO 1 */
60#define IRQ_EB_GPIO2 (IRQ_EB_GIC_START + 8) /* GPIO 2 */
61 /* 9 reserved */
62#define IRQ_EB_RTC (IRQ_EB_GIC_START + 10) /* Real Time Clock */
63#define IRQ_EB_SSP (IRQ_EB_GIC_START + 11) /* Synchronous Serial Port */
64#define IRQ_EB_UART0 (IRQ_EB_GIC_START + 12) /* UART 0 on development chip */
65#define IRQ_EB_UART1 (IRQ_EB_GIC_START + 13) /* UART 1 on development chip */
66#define IRQ_EB_UART2 (IRQ_EB_GIC_START + 14) /* UART 2 on development chip */
67#define IRQ_EB_UART3 (IRQ_EB_GIC_START + 15) /* UART 3 on development chip */
68#define IRQ_EB_SCI (IRQ_EB_GIC_START + 16) /* Smart Card Interface */
69#define IRQ_EB_MMCI0A (IRQ_EB_GIC_START + 17) /* Multimedia Card 0A */
70#define IRQ_EB_MMCI0B (IRQ_EB_GIC_START + 18) /* Multimedia Card 0B */
71#define IRQ_EB_AACI (IRQ_EB_GIC_START + 19) /* Audio Codec */
72#define IRQ_EB_KMI0 (IRQ_EB_GIC_START + 20) /* Keyboard/Mouse port 0 */
73#define IRQ_EB_KMI1 (IRQ_EB_GIC_START + 21) /* Keyboard/Mouse port 1 */
74#define IRQ_EB_CHARLCD (IRQ_EB_GIC_START + 22) /* Character LCD */
75#define IRQ_EB_CLCD (IRQ_EB_GIC_START + 23) /* CLCD controller */
76#define IRQ_EB_DMA (IRQ_EB_GIC_START + 24) /* DMA controller */
77#define IRQ_EB_PWRFAIL (IRQ_EB_GIC_START + 25) /* Power failure */
78#define IRQ_EB_PISMO (IRQ_EB_GIC_START + 26) /* PISMO interface */
79#define IRQ_EB_DoC (IRQ_EB_GIC_START + 27) /* Disk on Chip memory controller */
80#define IRQ_EB_ETH (IRQ_EB_GIC_START + 28) /* Ethernet controller */
81#define IRQ_EB_USB (IRQ_EB_GIC_START + 29) /* USB controller */
82#define IRQ_EB_TSPEN (IRQ_EB_GIC_START + 30) /* Touchscreen pen */
83#define IRQ_EB_TSKPAD (IRQ_EB_GIC_START + 31) /* Touchscreen keypad */
84
85/*
86 * RealView EB + ARM11MPCore interrupt sources (primary GIC on the core tile)
87 */
88#define IRQ_EB11MP_AACI (IRQ_EB_GIC_START + 0)
89#define IRQ_EB11MP_TIMER0_1 (IRQ_EB_GIC_START + 1)
90#define IRQ_EB11MP_TIMER2_3 (IRQ_EB_GIC_START + 2)
91#define IRQ_EB11MP_USB (IRQ_EB_GIC_START + 3)
92#define IRQ_EB11MP_UART0 (IRQ_EB_GIC_START + 4)
93#define IRQ_EB11MP_UART1 (IRQ_EB_GIC_START + 5)
94#define IRQ_EB11MP_RTC (IRQ_EB_GIC_START + 6)
95#define IRQ_EB11MP_KMI0 (IRQ_EB_GIC_START + 7)
96#define IRQ_EB11MP_KMI1 (IRQ_EB_GIC_START + 8)
97#define IRQ_EB11MP_ETH (IRQ_EB_GIC_START + 9)
98#define IRQ_EB11MP_EB_IRQ1 (IRQ_EB_GIC_START + 10) /* main GIC */
99#define IRQ_EB11MP_EB_IRQ2 (IRQ_EB_GIC_START + 11) /* tile GIC */
100#define IRQ_EB11MP_EB_FIQ1 (IRQ_EB_GIC_START + 12) /* main GIC */
101#define IRQ_EB11MP_EB_FIQ2 (IRQ_EB_GIC_START + 13) /* tile GIC */
102#define IRQ_EB11MP_MMCI0A (IRQ_EB_GIC_START + 14)
103#define IRQ_EB11MP_MMCI0B (IRQ_EB_GIC_START + 15)
104
105#define IRQ_EB11MP_PMU_CPU0 (IRQ_EB_GIC_START + 17)
106#define IRQ_EB11MP_PMU_CPU1 (IRQ_EB_GIC_START + 18)
107#define IRQ_EB11MP_PMU_CPU2 (IRQ_EB_GIC_START + 19)
108#define IRQ_EB11MP_PMU_CPU3 (IRQ_EB_GIC_START + 20)
109#define IRQ_EB11MP_PMU_SCU0 (IRQ_EB_GIC_START + 21)
110#define IRQ_EB11MP_PMU_SCU1 (IRQ_EB_GIC_START + 22)
111#define IRQ_EB11MP_PMU_SCU2 (IRQ_EB_GIC_START + 23)
112#define IRQ_EB11MP_PMU_SCU3 (IRQ_EB_GIC_START + 24)
113#define IRQ_EB11MP_PMU_SCU4 (IRQ_EB_GIC_START + 25)
114#define IRQ_EB11MP_PMU_SCU5 (IRQ_EB_GIC_START + 26)
115#define IRQ_EB11MP_PMU_SCU6 (IRQ_EB_GIC_START + 27)
116#define IRQ_EB11MP_PMU_SCU7 (IRQ_EB_GIC_START + 28)
117
118#define IRQ_EB11MP_L220_EVENT (IRQ_EB_GIC_START + 29)
119#define IRQ_EB11MP_L220_SLAVE (IRQ_EB_GIC_START + 30)
120#define IRQ_EB11MP_L220_DECODE (IRQ_EB_GIC_START + 31)
121
122#define IRQ_EB11MP_UART2 -1
123#define IRQ_EB11MP_UART3 -1
124#define IRQ_EB11MP_CLCD -1
125#define IRQ_EB11MP_DMA -1
126#define IRQ_EB11MP_WDOG -1
127#define IRQ_EB11MP_GPIO0 -1
128#define IRQ_EB11MP_GPIO1 -1
129#define IRQ_EB11MP_GPIO2 -1
130#define IRQ_EB11MP_SCI -1
131#define IRQ_EB11MP_SSP -1
132
133#define NR_GIC_EB11MP 2
134
135/*
136 * Only define NR_IRQS if less than NR_IRQS_EB
137 */
138#define NR_IRQS_EB (IRQ_EB_GIC_START + 96)
139
140#if defined(CONFIG_MACH_REALVIEW_EB) \
141 && (!defined(NR_IRQS) || (NR_IRQS < NR_IRQS_EB))
142#undef NR_IRQS
143#define NR_IRQS NR_IRQS_EB
144#endif
145
146#if defined(CONFIG_REALVIEW_MPCORE) \
147 && (!defined(MAX_GIC_NR) || (MAX_GIC_NR < NR_GIC_EB11MP))
148#undef MAX_GIC_NR
149#define MAX_GIC_NR NR_GIC_EB11MP
150#endif
151
152#endif /* __ASM_ARCH_BOARD_EB_H */
diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 3b4e2076603a..629944deed50 100644
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -9,12 +9,17 @@
9 */ 9 */
10#include <asm/hardware.h> 10#include <asm/hardware.h>
11#include <asm/hardware/gic.h> 11#include <asm/hardware/gic.h>
12#include <asm/arch/board-eb.h>
12 13
13 .macro disable_fiq 14 .macro disable_fiq
14 .endm 15 .endm
15 16
16 .macro get_irqnr_preamble, base, tmp 17 .macro get_irqnr_preamble, base, tmp
18#ifdef CONFIG_REALVIEW_MPCORE
19 ldr \base, =IO_ADDRESS(REALVIEW_EB11MP_GIC_CPU_BASE)
20#else
17 ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE) 21 ldr \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
22#endif
18 .endm 23 .endm
19 24
20 .macro arch_ret_to_user, tmp1, tmp2 25 .macro arch_ret_to_user, tmp1, tmp2
diff --git a/include/asm-arm/arch-realview/hardware.h b/include/asm-arm/arch-realview/hardware.h
index aa78fe087ab2..bad8d7ce9bfe 100644
--- a/include/asm-arm/arch-realview/hardware.h
+++ b/include/asm-arm/arch-realview/hardware.h
@@ -23,7 +23,6 @@
23#define __ASM_ARCH_HARDWARE_H 23#define __ASM_ARCH_HARDWARE_H
24 24
25#include <asm/sizes.h> 25#include <asm/sizes.h>
26#include <asm/arch/platform.h>
27 26
28/* macro to get at IO space when running virtually */ 27/* macro to get at IO space when running virtually */
29#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000) 28#define IO_ADDRESS(x) ((((x) & 0x0effffff) | (((x) >> 4) & 0x0f000000)) + 0xf0000000)
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h
index 5a5db56f86b8..ad0c911002fc 100644
--- a/include/asm-arm/arch-realview/irqs.h
+++ b/include/asm-arm/arch-realview/irqs.h
@@ -19,103 +19,18 @@
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */ 20 */
21 21
22#include <asm/arch/platform.h> 22#ifndef __ASM_ARCH_IRQS_H
23#define __ASM_ARCH_IRQS_H
23 24
24#define IRQ_LOCALTIMER 29 25#include <asm/arch/board-eb.h>
25#define IRQ_LOCALWDOG 30
26 26
27/* 27#define IRQ_LOCALTIMER 29
28 * IRQ interrupts definitions are the same the INT definitions 28#define IRQ_LOCALWDOG 30
29 * held within platform.h
30 */
31#define IRQ_GIC_START 32
32#define IRQ_WDOGINT (IRQ_GIC_START + INT_WDOGINT)
33#define IRQ_SOFTINT (IRQ_GIC_START + INT_SOFTINT)
34#define IRQ_COMMRx (IRQ_GIC_START + INT_COMMRx)
35#define IRQ_COMMTx (IRQ_GIC_START + INT_COMMTx)
36#define IRQ_TIMERINT0_1 (IRQ_GIC_START + INT_TIMERINT0_1)
37#define IRQ_TIMERINT2_3 (IRQ_GIC_START + INT_TIMERINT2_3)
38#define IRQ_GPIOINT0 (IRQ_GIC_START + INT_GPIOINT0)
39#define IRQ_GPIOINT1 (IRQ_GIC_START + INT_GPIOINT1)
40#define IRQ_GPIOINT2 (IRQ_GIC_START + INT_GPIOINT2)
41#define IRQ_GPIOINT3 (IRQ_GIC_START + INT_GPIOINT3)
42#define IRQ_RTCINT (IRQ_GIC_START + INT_RTCINT)
43#define IRQ_SSPINT (IRQ_GIC_START + INT_SSPINT)
44#define IRQ_UARTINT0 (IRQ_GIC_START + INT_UARTINT0)
45#define IRQ_UARTINT1 (IRQ_GIC_START + INT_UARTINT1)
46#define IRQ_UARTINT2 (IRQ_GIC_START + INT_UARTINT2)
47#define IRQ_UART3 (IRQ_GIC_START + INT_UARTINT3)
48#define IRQ_SCIINT (IRQ_GIC_START + INT_SCIINT)
49#define IRQ_CLCDINT (IRQ_GIC_START + INT_CLCDINT)
50#define IRQ_DMAINT (IRQ_GIC_START + INT_DMAINT)
51#define IRQ_PWRFAILINT (IRQ_GIC_START + INT_PWRFAILINT)
52#define IRQ_MBXINT (IRQ_GIC_START + INT_MBXINT)
53#define IRQ_GNDINT (IRQ_GIC_START + INT_GNDINT)
54#define IRQ_MMCI0B (IRQ_GIC_START + INT_MMCI0B)
55#define IRQ_MMCI1B (IRQ_GIC_START + INT_MMCI1B)
56#define IRQ_KMI0 (IRQ_GIC_START + INT_KMI0)
57#define IRQ_KMI1 (IRQ_GIC_START + INT_KMI1)
58#define IRQ_SCI3 (IRQ_GIC_START + INT_SCI3)
59#define IRQ_CLCD (IRQ_GIC_START + INT_CLCD)
60#define IRQ_TOUCH (IRQ_GIC_START + INT_TOUCH)
61#define IRQ_KEYPAD (IRQ_GIC_START + INT_KEYPAD)
62#define IRQ_DoC (IRQ_GIC_START + INT_DoC)
63#define IRQ_MMCI0A (IRQ_GIC_START + INT_MMCI0A)
64#define IRQ_MMCI1A (IRQ_GIC_START + INT_MMCI1A)
65#define IRQ_AACI (IRQ_GIC_START + INT_AACI)
66#define IRQ_ETH (IRQ_GIC_START + INT_ETH)
67#define IRQ_USB (IRQ_GIC_START + INT_USB)
68#define IRQ_PMU_CPU0 (IRQ_GIC_START + INT_PMU_CPU0)
69#define IRQ_PMU_CPU1 (IRQ_GIC_START + INT_PMU_CPU1)
70#define IRQ_PMU_CPU2 (IRQ_GIC_START + INT_PMU_CPU2)
71#define IRQ_PMU_CPU3 (IRQ_GIC_START + INT_PMU_CPU3)
72#define IRQ_PMU_SCU0 (IRQ_GIC_START + INT_PMU_SCU0)
73#define IRQ_PMU_SCU1 (IRQ_GIC_START + INT_PMU_SCU1)
74#define IRQ_PMU_SCU2 (IRQ_GIC_START + INT_PMU_SCU2)
75#define IRQ_PMU_SCU3 (IRQ_GIC_START + INT_PMU_SCU3)
76#define IRQ_PMU_SCU4 (IRQ_GIC_START + INT_PMU_SCU4)
77#define IRQ_PMU_SCU5 (IRQ_GIC_START + INT_PMU_SCU5)
78#define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6)
79#define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7)
80 29
81#define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1) 30#define IRQ_GIC_START 32
82#define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2)
83 31
84#define IRQMASK_WDOGINT INTMASK_WDOGINT 32#ifndef NR_IRQS
85#define IRQMASK_SOFTINT INTMASK_SOFTINT 33#error "NR_IRQS not defined by the board-specific files"
86#define IRQMASK_COMMRx INTMASK_COMMRx 34#endif
87#define IRQMASK_COMMTx INTMASK_COMMTx
88#define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1
89#define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3
90#define IRQMASK_GPIOINT0 INTMASK_GPIOINT0
91#define IRQMASK_GPIOINT1 INTMASK_GPIOINT1
92#define IRQMASK_GPIOINT2 INTMASK_GPIOINT2
93#define IRQMASK_GPIOINT3 INTMASK_GPIOINT3
94#define IRQMASK_RTCINT INTMASK_RTCINT
95#define IRQMASK_SSPINT INTMASK_SSPINT
96#define IRQMASK_UARTINT0 INTMASK_UARTINT0
97#define IRQMASK_UARTINT1 INTMASK_UARTINT1
98#define IRQMASK_UARTINT2 INTMASK_UARTINT2
99#define IRQMASK_SCIINT INTMASK_SCIINT
100#define IRQMASK_CLCDINT INTMASK_CLCDINT
101#define IRQMASK_DMAINT INTMASK_DMAINT
102#define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT
103#define IRQMASK_MBXINT INTMASK_MBXINT
104#define IRQMASK_GNDINT INTMASK_GNDINT
105#define IRQMASK_MMCI0B INTMASK_MMCI0B
106#define IRQMASK_MMCI1B INTMASK_MMCI1B
107#define IRQMASK_KMI0 INTMASK_KMI0
108#define IRQMASK_KMI1 INTMASK_KMI1
109#define IRQMASK_SCI3 INTMASK_SCI3
110#define IRQMASK_UART3 INTMASK_UART3
111#define IRQMASK_CLCD INTMASK_CLCD
112#define IRQMASK_TOUCH INTMASK_TOUCH
113#define IRQMASK_KEYPAD INTMASK_KEYPAD
114#define IRQMASK_DoC INTMASK_DoC
115#define IRQMASK_MMCI0A INTMASK_MMCI0A
116#define IRQMASK_MMCI1A INTMASK_MMCI1A
117#define IRQMASK_AACI INTMASK_AACI
118#define IRQMASK_ETH INTMASK_ETH
119#define IRQMASK_USB INTMASK_USB
120 35
121#define NR_IRQS (IRQ_GIC_START + 96) 36#endif
diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index 6e0eab95a3a2..4fd351b5e4a2 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -18,8 +18,8 @@
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */ 19 */
20 20
21#ifndef __address_h 21#ifndef __ASM_ARCH_PLATFORM_H
22#define __address_h 1 22#define __ASM_ARCH_PLATFORM_H
23 23
24/* 24/*
25 * Memory definitions 25 * Memory definitions
@@ -81,11 +81,12 @@
81#define REALVIEW_SYS_24MHz_OFFSET 0x5C 81#define REALVIEW_SYS_24MHz_OFFSET 0x5C
82#define REALVIEW_SYS_MISC_OFFSET 0x60 82#define REALVIEW_SYS_MISC_OFFSET 0x60
83#define REALVIEW_SYS_IOSEL_OFFSET 0x70 83#define REALVIEW_SYS_IOSEL_OFFSET 0x70
84#define REALVIEW_SYS_TEST_OSC0_OFFSET 0x80 84#define REALVIEW_SYS_PROCID_OFFSET 0x84
85#define REALVIEW_SYS_TEST_OSC1_OFFSET 0x84 85#define REALVIEW_SYS_TEST_OSC0_OFFSET 0xC0
86#define REALVIEW_SYS_TEST_OSC2_OFFSET 0x88 86#define REALVIEW_SYS_TEST_OSC1_OFFSET 0xC4
87#define REALVIEW_SYS_TEST_OSC3_OFFSET 0x8C 87#define REALVIEW_SYS_TEST_OSC2_OFFSET 0xC8
88#define REALVIEW_SYS_TEST_OSC4_OFFSET 0x90 88#define REALVIEW_SYS_TEST_OSC3_OFFSET 0xCC
89#define REALVIEW_SYS_TEST_OSC4_OFFSET 0xD0
89 90
90#define REALVIEW_SYS_BASE 0x10000000 91#define REALVIEW_SYS_BASE 0x10000000
91#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET) 92#define REALVIEW_SYS_ID (REALVIEW_SYS_BASE + REALVIEW_SYS_ID_OFFSET)
@@ -114,6 +115,7 @@
114#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET) 115#define REALVIEW_SYS_24MHz (REALVIEW_SYS_BASE + REALVIEW_SYS_24MHz_OFFSET)
115#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET) 116#define REALVIEW_SYS_MISC (REALVIEW_SYS_BASE + REALVIEW_SYS_MISC_OFFSET)
116#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET) 117#define REALVIEW_SYS_IOSEL (REALVIEW_SYS_BASE + REALVIEW_SYS_IOSEL_OFFSET)
118#define REALVIEW_SYS_PROCID (REALVIEW_SYS_BASE + REALVIEW_SYS_PROCID_OFFSET)
117#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET) 119#define REALVIEW_SYS_TEST_OSC0 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC0_OFFSET)
118#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET) 120#define REALVIEW_SYS_TEST_OSC1 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC1_OFFSET)
119#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET) 121#define REALVIEW_SYS_TEST_OSC2 (REALVIEW_SYS_BASE + REALVIEW_SYS_TEST_OSC2_OFFSET)
@@ -203,30 +205,8 @@
203 /* Reserved 0x1001A000 - 0x1001FFFF */ 205 /* Reserved 0x1001A000 - 0x1001FFFF */
204#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */ 206#define REALVIEW_CLCD_BASE 0x10020000 /* CLCD */
205#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */ 207#define REALVIEW_DMAC_BASE 0x10030000 /* DMA controller */
206#ifndef CONFIG_REALVIEW_MPCORE
207#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */ 208#define REALVIEW_GIC_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
208#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */ 209#define REALVIEW_GIC_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
209#else
210#ifdef CONFIG_REALVIEW_MPCORE_REVB
211#define REALVIEW_MPCORE_SCU_BASE 0x10100000 /* SCU registers */
212#define REALVIEW_GIC_CPU_BASE 0x10100100 /* Generic interrupt controller CPU interface */
213#define REALVIEW_TWD_BASE 0x10100700
214#define REALVIEW_TWD_SIZE 0x00000100
215#define REALVIEW_GIC_DIST_BASE 0x10101000 /* Generic interrupt controller distributor */
216#define REALVIEW_MPCORE_L220_BASE 0x10102000 /* L220 registers */
217#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8 /* Register offset for MPCore sysctl */
218#else
219#define REALVIEW_MPCORE_SCU_BASE 0x1F000000 /* SCU registers */
220#define REALVIEW_GIC_CPU_BASE 0x1F000100 /* Generic interrupt controller CPU interface */
221#define REALVIEW_TWD_BASE 0x1F000700
222#define REALVIEW_TWD_SIZE 0x00000100
223#define REALVIEW_GIC_DIST_BASE 0x1F001000 /* Generic interrupt controller distributor */
224#define REALVIEW_MPCORE_L220_BASE 0x1F002000 /* L220 registers */
225#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74 /* Register offset for MPCore sysctl */
226#endif
227#define REALVIEW_GIC1_CPU_BASE 0x10040000 /* Generic interrupt controller CPU interface */
228#define REALVIEW_GIC1_DIST_BASE 0x10041000 /* Generic interrupt controller distributor */
229#endif
230#define REALVIEW_SMC_BASE 0x10080000 /* SMC */ 210#define REALVIEW_SMC_BASE 0x10080000 /* SMC */
231 /* Reserved 0x10090000 - 0x100EFFFF */ 211 /* Reserved 0x10090000 - 0x100EFFFF */
232 212
@@ -283,134 +263,6 @@
283#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */ 263#define REALVIEW_INTREG_OFFSET 0x8 /* Interrupt control */
284#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */ 264#define REALVIEW_DECODE_OFFSET 0xC /* Fitted logic modules */
285 265
286/* ------------------------------------------------------------------------
287 * Interrupts - bit assignment (primary)
288 * ------------------------------------------------------------------------
289 */
290#ifndef CONFIG_REALVIEW_MPCORE
291#define INT_WDOGINT 0 /* Watchdog timer */
292#define INT_SOFTINT 1 /* Software interrupt */
293#define INT_COMMRx 2 /* Debug Comm Rx interrupt */
294#define INT_COMMTx 3 /* Debug Comm Tx interrupt */
295#define INT_TIMERINT0_1 4 /* Timer 0 and 1 */
296#define INT_TIMERINT2_3 5 /* Timer 2 and 3 */
297#define INT_GPIOINT0 6 /* GPIO 0 */
298#define INT_GPIOINT1 7 /* GPIO 1 */
299#define INT_GPIOINT2 8 /* GPIO 2 */
300/* 9 reserved */
301#define INT_RTCINT 10 /* Real Time Clock */
302#define INT_SSPINT 11 /* Synchronous Serial Port */
303#define INT_UARTINT0 12 /* UART 0 on development chip */
304#define INT_UARTINT1 13 /* UART 1 on development chip */
305#define INT_UARTINT2 14 /* UART 2 on development chip */
306#define INT_UARTINT3 15 /* UART 3 on development chip */
307#define INT_SCIINT 16 /* Smart Card Interface */
308#define INT_MMCI0A 17 /* Multimedia Card 0A */
309#define INT_MMCI0B 18 /* Multimedia Card 0B */
310#define INT_AACI 19 /* Audio Codec */
311#define INT_KMI0 20 /* Keyboard/Mouse port 0 */
312#define INT_KMI1 21 /* Keyboard/Mouse port 1 */
313#define INT_CHARLCD 22 /* Character LCD */
314#define INT_CLCDINT 23 /* CLCD controller */
315#define INT_DMAINT 24 /* DMA controller */
316#define INT_PWRFAILINT 25 /* Power failure */
317#define INT_PISMO 26
318#define INT_DoC 27 /* Disk on Chip memory controller */
319#define INT_ETH 28 /* Ethernet controller */
320#define INT_USB 29 /* USB controller */
321#define INT_TSPENINT 30 /* Touchscreen pen */
322#define INT_TSKPADINT 31 /* Touchscreen keypad */
323
324#else
325
326#define MAX_GIC_NR 2
327
328#define INT_AACI 0
329#define INT_TIMERINT0_1 1
330#define INT_TIMERINT2_3 2
331#define INT_USB 3
332#define INT_UARTINT0 4
333#define INT_UARTINT1 5
334#define INT_RTCINT 6
335#define INT_KMI0 7
336#define INT_KMI1 8
337#define INT_ETH 9
338#define INT_EB_IRQ1 10 /* main GIC */
339#define INT_EB_IRQ2 11 /* tile GIC */
340#define INT_EB_FIQ1 12 /* main GIC */
341#define INT_EB_FIQ2 13 /* tile GIC */
342#define INT_MMCI0A 14
343#define INT_MMCI0B 15
344
345#define INT_PMU_CPU0 17
346#define INT_PMU_CPU1 18
347#define INT_PMU_CPU2 19
348#define INT_PMU_CPU3 20
349#define INT_PMU_SCU0 21
350#define INT_PMU_SCU1 22
351#define INT_PMU_SCU2 23
352#define INT_PMU_SCU3 24
353#define INT_PMU_SCU4 25
354#define INT_PMU_SCU5 26
355#define INT_PMU_SCU6 27
356#define INT_PMU_SCU7 28
357
358#define INT_L220_EVENT 29
359#define INT_L220_SLAVE 30
360#define INT_L220_DECODE 31
361
362#define INT_UARTINT2 -1
363#define INT_UARTINT3 -1
364#define INT_CLCDINT -1
365#define INT_DMAINT -1
366#define INT_WDOGINT -1
367#define INT_GPIOINT0 -1
368#define INT_GPIOINT1 -1
369#define INT_GPIOINT2 -1
370#define INT_SCIINT -1
371#define INT_SSPINT -1
372#endif
373
374/*
375 * Interrupt bit positions
376 *
377 */
378#define INTMASK_WDOGINT (1 << INT_WDOGINT)
379#define INTMASK_SOFTINT (1 << INT_SOFTINT)
380#define INTMASK_COMMRx (1 << INT_COMMRx)
381#define INTMASK_COMMTx (1 << INT_COMMTx)
382#define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1)
383#define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3)
384#define INTMASK_GPIOINT0 (1 << INT_GPIOINT0)
385#define INTMASK_GPIOINT1 (1 << INT_GPIOINT1)
386#define INTMASK_GPIOINT2 (1 << INT_GPIOINT2)
387#define INTMASK_RTCINT (1 << INT_RTCINT)
388#define INTMASK_SSPINT (1 << INT_SSPINT)
389#define INTMASK_UARTINT0 (1 << INT_UARTINT0)
390#define INTMASK_UARTINT1 (1 << INT_UARTINT1)
391#define INTMASK_UARTINT2 (1 << INT_UARTINT2)
392#define INTMASK_UARTINT3 (1 << INT_UARTINT3)
393#define INTMASK_SCIINT (1 << INT_SCIINT)
394#define INTMASK_MMCI0A (1 << INT_MMCI0A)
395#define INTMASK_MMCI0B (1 << INT_MMCI0B)
396#define INTMASK_AACI (1 << INT_AACI)
397#define INTMASK_KMI0 (1 << INT_KMI0)
398#define INTMASK_KMI1 (1 << INT_KMI1)
399#define INTMASK_CHARLCD (1 << INT_CHARLCD)
400#define INTMASK_CLCDINT (1 << INT_CLCDINT)
401#define INTMASK_DMAINT (1 << INT_DMAINT)
402#define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT)
403#define INTMASK_PISMO (1 << INT_PISMO)
404#define INTMASK_DoC (1 << INT_DoC)
405#define INTMASK_ETH (1 << INT_ETH)
406#define INTMASK_USB (1 << INT_USB)
407#define INTMASK_TSPENINT (1 << INT_TSPENINT)
408#define INTMASK_TSKPADINT (1 << INT_TSKPADINT)
409
410#define MAXIRQNUM 31
411#define MAXFIQNUM 31
412#define MAXSWINUM 31
413
414/* 266/*
415 * Application Flash 267 * Application Flash
416 * 268 *
@@ -463,6 +315,4 @@
463#define REALVIEW_CSR_BASE 0x10000000 315#define REALVIEW_CSR_BASE 0x10000000
464#define REALVIEW_CSR_SIZE 0x10000000 316#define REALVIEW_CSR_SIZE 0x10000000
465 317
466#endif 318#endif /* __ASM_ARCH_PLATFORM_H */
467
468/* END */
diff --git a/include/asm-arm/arch-realview/scu.h b/include/asm-arm/arch-realview/scu.h
index cc293640178e..08b3db883c36 100644
--- a/include/asm-arm/arch-realview/scu.h
+++ b/include/asm-arm/arch-realview/scu.h
@@ -1,8 +1,8 @@
1#ifndef __ASMARM_ARCH_SCU_H 1#ifndef __ASMARM_ARCH_SCU_H
2#define __ASMARM_ARCH_SCU_H 2#define __ASMARM_ARCH_SCU_H
3 3
4#include <asm/arch/platform.h> 4#include <asm/arch/board-eb.h>
5 5
6#define SCU_BASE REALVIEW_MPCORE_SCU_BASE 6#define SCU_BASE REALVIEW_EB11MP_SCU_BASE
7 7
8#endif 8#endif
diff --git a/include/asm-arm/arch-realview/uncompress.h b/include/asm-arm/arch-realview/uncompress.h
index f05631d76743..3d5c2db07a26 100644
--- a/include/asm-arm/arch-realview/uncompress.h
+++ b/include/asm-arm/arch-realview/uncompress.h
@@ -19,6 +19,8 @@
19 */ 19 */
20#include <asm/hardware.h> 20#include <asm/hardware.h>
21 21
22#include <asm/arch/platform.h>
23
22#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00)) 24#define AMBA_UART_DR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x00))
23#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c)) 25#define AMBA_UART_LCRH (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x2c))
24#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30)) 26#define AMBA_UART_CR (*(volatile unsigned char *) (REALVIEW_UART0_BASE + 0x30))
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 11:22:25 -0500