diff options
author | Ben Dooks <ben-linux@fluff.org> | 2006-12-17 14:50:55 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-12-17 18:37:57 -0500 |
commit | 58d19d6ea608077e83c30e58ae1494246b1f6b82 (patch) | |
tree | 0eb48b7f7e355dd2ddcb7d843d95cc287d79e7b0 /include/asm-arm | |
parent | 3e940b6a90c346a224c97570a97a150a16f1c036 (diff) |
[ARM] 4045/1: S3C24XX: remove old VA for non-shared areas
Remove old (and non-shared) VA addresses from the mappings
in arch/arm/mach-s3c2410/map.h and anywhere they are being
mapped in arch/arm/mach-s3c2410
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-s3c2410/map.h | 24 |
1 files changed, 6 insertions, 18 deletions
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h index 6746114e1a2d..4505aefbad17 100644 --- a/include/asm-arm/arch-s3c2410/map.h +++ b/include/asm-arm/arch-s3c2410/map.h | |||
@@ -47,73 +47,65 @@ | |||
47 | #define S3C24XX_SZ_MEMCTRL SZ_1M | 47 | #define S3C24XX_SZ_MEMCTRL SZ_1M |
48 | 48 | ||
49 | /* USB host controller */ | 49 | /* USB host controller */ |
50 | #define S3C24XX_VA_USBHOST S3C2410_ADDR(0x00200000) | ||
51 | #define S3C2400_PA_USBHOST (0x14200000) | 50 | #define S3C2400_PA_USBHOST (0x14200000) |
52 | #define S3C2410_PA_USBHOST (0x49000000) | 51 | #define S3C2410_PA_USBHOST (0x49000000) |
53 | #define S3C24XX_SZ_USBHOST SZ_1M | 52 | #define S3C24XX_SZ_USBHOST SZ_1M |
54 | 53 | ||
55 | /* DMA controller */ | 54 | /* DMA controller */ |
56 | #define S3C24XX_VA_DMA S3C2410_ADDR(0x00300000) | ||
57 | #define S3C2400_PA_DMA (0x14600000) | 55 | #define S3C2400_PA_DMA (0x14600000) |
58 | #define S3C2410_PA_DMA (0x4B000000) | 56 | #define S3C2410_PA_DMA (0x4B000000) |
59 | #define S3C24XX_SZ_DMA SZ_1M | 57 | #define S3C24XX_SZ_DMA SZ_1M |
60 | 58 | ||
61 | /* Clock and Power management */ | 59 | /* Clock and Power management */ |
62 | #define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00400000) | 60 | #define S3C24XX_VA_CLKPWR S3C2410_ADDR(0x00200000) |
63 | #define S3C2400_PA_CLKPWR (0x14800000) | 61 | #define S3C2400_PA_CLKPWR (0x14800000) |
64 | #define S3C2410_PA_CLKPWR (0x4C000000) | 62 | #define S3C2410_PA_CLKPWR (0x4C000000) |
65 | #define S3C24XX_SZ_CLKPWR SZ_1M | 63 | #define S3C24XX_SZ_CLKPWR SZ_1M |
66 | 64 | ||
67 | /* LCD controller */ | 65 | /* LCD controller */ |
68 | #define S3C24XX_VA_LCD S3C2410_ADDR(0x00600000) | 66 | #define S3C24XX_VA_LCD S3C2410_ADDR(0x00300000) |
69 | #define S3C2400_PA_LCD (0x14A00000) | 67 | #define S3C2400_PA_LCD (0x14A00000) |
70 | #define S3C2410_PA_LCD (0x4D000000) | 68 | #define S3C2410_PA_LCD (0x4D000000) |
71 | #define S3C24XX_SZ_LCD SZ_1M | 69 | #define S3C24XX_SZ_LCD SZ_1M |
72 | 70 | ||
73 | /* NAND flash controller */ | 71 | /* NAND flash controller */ |
74 | #define S3C24XX_VA_NAND S3C2410_ADDR(0x00700000) | ||
75 | #define S3C2410_PA_NAND (0x4E000000) | 72 | #define S3C2410_PA_NAND (0x4E000000) |
76 | #define S3C24XX_SZ_NAND SZ_1M | 73 | #define S3C24XX_SZ_NAND SZ_1M |
77 | 74 | ||
78 | /* MMC controller - available on the S3C2400 */ | 75 | /* MMC controller - available on the S3C2400 */ |
79 | #define S3C2400_VA_MMC S3C2400_ADDR(0x00700000) | ||
80 | #define S3C2400_PA_MMC (0x15A00000) | 76 | #define S3C2400_PA_MMC (0x15A00000) |
81 | #define S3C2400_SZ_MMC SZ_1M | 77 | #define S3C2400_SZ_MMC SZ_1M |
82 | 78 | ||
83 | /* UARTs */ | 79 | /* UARTs */ |
84 | #define S3C24XX_VA_UART S3C2410_ADDR(0x00800000) | 80 | #define S3C24XX_VA_UART S3C2410_ADDR(0x00400000) |
85 | #define S3C2400_PA_UART (0x15000000) | 81 | #define S3C2400_PA_UART (0x15000000) |
86 | #define S3C2410_PA_UART (0x50000000) | 82 | #define S3C2410_PA_UART (0x50000000) |
87 | #define S3C24XX_SZ_UART SZ_1M | 83 | #define S3C24XX_SZ_UART SZ_1M |
88 | 84 | ||
89 | /* Timers */ | 85 | /* Timers */ |
90 | #define S3C24XX_VA_TIMER S3C2410_ADDR(0x00900000) | 86 | #define S3C24XX_VA_TIMER S3C2410_ADDR(0x00500000) |
91 | #define S3C2400_PA_TIMER (0x15100000) | 87 | #define S3C2400_PA_TIMER (0x15100000) |
92 | #define S3C2410_PA_TIMER (0x51000000) | 88 | #define S3C2410_PA_TIMER (0x51000000) |
93 | #define S3C24XX_SZ_TIMER SZ_1M | 89 | #define S3C24XX_SZ_TIMER SZ_1M |
94 | 90 | ||
95 | /* USB Device port */ | 91 | /* USB Device port */ |
96 | #define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00A00000) | 92 | #define S3C24XX_VA_USBDEV S3C2410_ADDR(0x00600000) |
97 | #define S3C2400_PA_USBDEV (0x15200140) | 93 | #define S3C2400_PA_USBDEV (0x15200140) |
98 | #define S3C2410_PA_USBDEV (0x52000000) | 94 | #define S3C2410_PA_USBDEV (0x52000000) |
99 | #define S3C24XX_SZ_USBDEV SZ_1M | 95 | #define S3C24XX_SZ_USBDEV SZ_1M |
100 | 96 | ||
101 | /* Watchdog */ | 97 | /* Watchdog */ |
102 | #define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00B00000) | 98 | #define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000) |
103 | #define S3C2400_PA_WATCHDOG (0x15300000) | 99 | #define S3C2400_PA_WATCHDOG (0x15300000) |
104 | #define S3C2410_PA_WATCHDOG (0x53000000) | 100 | #define S3C2410_PA_WATCHDOG (0x53000000) |
105 | #define S3C24XX_SZ_WATCHDOG SZ_1M | 101 | #define S3C24XX_SZ_WATCHDOG SZ_1M |
106 | 102 | ||
107 | /* IIC hardware controller */ | 103 | /* IIC hardware controller */ |
108 | #define S3C24XX_VA_IIC S3C2410_ADDR(0x00C00000) | ||
109 | #define S3C2400_PA_IIC (0x15400000) | 104 | #define S3C2400_PA_IIC (0x15400000) |
110 | #define S3C2410_PA_IIC (0x54000000) | 105 | #define S3C2410_PA_IIC (0x54000000) |
111 | #define S3C24XX_SZ_IIC SZ_1M | 106 | #define S3C24XX_SZ_IIC SZ_1M |
112 | 107 | ||
113 | #define VA_IIC_BASE (S3C24XX_VA_IIC) | ||
114 | |||
115 | /* IIS controller */ | 108 | /* IIS controller */ |
116 | #define S3C24XX_VA_IIS S3C2410_ADDR(0x00D00000) | ||
117 | #define S3C2400_PA_IIS (0x15508000) | 109 | #define S3C2400_PA_IIS (0x15508000) |
118 | #define S3C2410_PA_IIS (0x55000000) | 110 | #define S3C2410_PA_IIS (0x55000000) |
119 | #define S3C24XX_SZ_IIS SZ_1M | 111 | #define S3C24XX_SZ_IIS SZ_1M |
@@ -134,25 +126,21 @@ | |||
134 | #define S3C24XX_SZ_GPIO SZ_1M | 126 | #define S3C24XX_SZ_GPIO SZ_1M |
135 | 127 | ||
136 | /* RTC */ | 128 | /* RTC */ |
137 | #define S3C24XX_VA_RTC S3C2410_ADDR(0x00F00000) | ||
138 | #define S3C2400_PA_RTC (0x15700040) | 129 | #define S3C2400_PA_RTC (0x15700040) |
139 | #define S3C2410_PA_RTC (0x57000000) | 130 | #define S3C2410_PA_RTC (0x57000000) |
140 | #define S3C24XX_SZ_RTC SZ_1M | 131 | #define S3C24XX_SZ_RTC SZ_1M |
141 | 132 | ||
142 | /* ADC */ | 133 | /* ADC */ |
143 | #define S3C24XX_VA_ADC S3C2410_ADDR(0x01000000) | ||
144 | #define S3C2400_PA_ADC (0x15800000) | 134 | #define S3C2400_PA_ADC (0x15800000) |
145 | #define S3C2410_PA_ADC (0x58000000) | 135 | #define S3C2410_PA_ADC (0x58000000) |
146 | #define S3C24XX_SZ_ADC SZ_1M | 136 | #define S3C24XX_SZ_ADC SZ_1M |
147 | 137 | ||
148 | /* SPI */ | 138 | /* SPI */ |
149 | #define S3C24XX_VA_SPI S3C2410_ADDR(0x01100000) | ||
150 | #define S3C2400_PA_SPI (0x15900000) | 139 | #define S3C2400_PA_SPI (0x15900000) |
151 | #define S3C2410_PA_SPI (0x59000000) | 140 | #define S3C2410_PA_SPI (0x59000000) |
152 | #define S3C24XX_SZ_SPI SZ_1M | 141 | #define S3C24XX_SZ_SPI SZ_1M |
153 | 142 | ||
154 | /* SDI */ | 143 | /* SDI */ |
155 | #define S3C24XX_VA_SDI S3C2410_ADDR(0x01200000) | ||
156 | #define S3C2410_PA_SDI (0x5A000000) | 144 | #define S3C2410_PA_SDI (0x5A000000) |
157 | #define S3C24XX_SZ_SDI SZ_1M | 145 | #define S3C24XX_SZ_SDI SZ_1M |
158 | 146 | ||