Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6

author: David Woodhouse <dwmw2@infradead.org> 2007-07-23 05:20:10 -0400
committer: David Woodhouse <dwmw2@infradead.org> 2007-07-23 05:20:10 -0400
commit: 39fe5434cb9de5da40510028b17b96bc4eb312b3 (patch)
tree: 7a02a317b9ad57da51ca99887c119e779ccf3f13 /include/asm-arm
parent: 0fc72b81d3111d114ab378935b1cf07680ca1289 (diff)
parent: f695baf2df9e0413d3521661070103711545207a (diff)
92 files changed, 3957 insertions, 590 deletions
diff --git a/include/asm-arm/Kbuild b/include/asm-arm/Kbuild
index c68e1680da01..73237bd130a2 100644
--- a/include/asm-arm/Kbuild
+++ b/include/asm-arm/Kbuild
@@ -1 +1,3 @@
 include include/asm-generic/Kbuild.asm
+unifdef-y += hwcap.h
diff --git a/include/asm-arm/a.out.h b/include/asm-arm/a.out.h
index 3e5fe64c4394..d7165e86df25 100644
--- a/include/asm-arm/a.out.h
+++ b/include/asm-arm/a.out.h
@@ -30,6 +30,7 @@ struct exec
 #ifdef __KERNEL__
 #define STACK_TOP       ((current->personality == PER_LINUX_32BIT) ? \
                         TASK_SIZE : TASK_SIZE_26)
+#define STACK_TOP_MAX   TASK_SIZE
 #endif
 #ifndef LIBRARY_START_TEXT
diff --git a/include/asm-arm/arch-at91/at91_dbgu.h b/include/asm-arm/arch-at91/at91_dbgu.h
index b0369e176f7b..8019ffd0ad3b 100644
--- a/include/asm-arm/arch-at91/at91_dbgu.h
+++ b/include/asm-arm/arch-at91/at91_dbgu.h
@@ -16,6 +16,7 @@
 #ifndef AT91_DBGU_H
 #define AT91_DBGU_H
+#ifdef AT91_DBGU
 #define AT91_DBGU_CR            (AT91_DBGU + 0x00)      /* Control Register */
 #define AT91_DBGU_MR            (AT91_DBGU + 0x04)      /* Mode Register */
 #define AT91_DBGU_IER           (AT91_DBGU + 0x08)      /* Interrupt Enable Register */
@@ -30,6 +31,15 @@
 #define AT91_DBGU_CIDR          (AT91_DBGU + 0x40)      /* Chip ID Register */
 #define AT91_DBGU_EXID          (AT91_DBGU + 0x44)      /* Chip ID Extension Register */
+#define AT91_DBGU_FNR           (AT91_DBGU + 0x48)      /* Force NTRST Register [SAM9 only] */
+#define         AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
+#endif /* AT91_DBGU */
+/*
+ * Some AT91 parts that don't have full DEBUG units still support the ID
+ * and extensions register.
+ */
 #define         AT91_CIDR_VERSION       (0x1f << 0)             /* Version of the Device */
 #define         AT91_CIDR_EPROC         (7    << 5)             /* Embedded Processor */
 #define         AT91_CIDR_NVPSIZ        (0xf  << 8)             /* Nonvolatile Program Memory Size */
@@ -53,7 +63,4 @@
 #define         AT91_CIDR_NVPTYP        (7    << 28)            /* Nonvolatile Program Memory Type */
 #define         AT91_CIDR_EXT           (1    << 31)            /* Extension Flag */
-#define AT91_DBGU_FNR           (AT91_DBGU + 0x48)      /* Force NTRST Register [SAM9 only] */
-#define         AT91_DBGU_FNTRST        (1 << 0)                /* Force NTRST */
 #endif
diff --git a/include/asm-arm/arch-at91/at91_mci.h b/include/asm-arm/arch-at91/at91_mci.h
index 40a9876b661a..c2e11cc374ba 100644
--- a/include/asm-arm/arch-at91/at91_mci.h
+++ b/include/asm-arm/arch-at91/at91_mci.h
@@ -26,6 +26,9 @@
 #define AT91_MCI_MR             0x04            /* Mode Register */
 #define         AT91_MCI_CLKDIV         (0xff  <<  0)   /* Clock Divider */
 #define         AT91_MCI_PWSDIV         (7     <<  8)   /* Power Saving Divider */
+#define         AT91_MCI_RDPROOF        (1     << 11)   /* Read Proof Enable [SAM926[03] only] */
+#define         AT91_MCI_WRPROOF        (1     << 12)   /* Write Proof Enable [SAM926[03] only] */
+#define         AT91_MCI_PDCFBYTE       (1     << 13)   /* PDC Force Byte Transfer [SAM926[03] only] */
 #define         AT91_MCI_PDCPADV        (1     << 14)   /* PDC Padding Value */
 #define         AT91_MCI_PDCMODE        (1     << 15)   /* PDC-orientated Mode */
 #define         AT91_MCI_BLKLEN         (0xfff << 18)   /* Data Block Length */
diff --git a/include/asm-arm/arch-at91/at91x40.h b/include/asm-arm/arch-at91/at91x40.h
new file mode 100644
index 000000000000..612203e0177f
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91x40.h
@@ -0,0 +1,55 @@
+/*
+ * include/asm-arm/arch-at91/at91x40.h
+ *
+ * (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef AT91X40_H
+#define AT91X40_H
+/*
+ *      IRQ list.
+ */
+#define AT91_ID_FIQ             0       /* FIQ */
+#define AT91_ID_SYS             1       /* System Peripheral */
+#define AT91X40_ID_USART0       2       /* USART port 0 */
+#define AT91X40_ID_USART1       3       /* USART port 1 */
+#define AT91X40_ID_TC0          4       /* Timer/Counter 0 */
+#define AT91X40_ID_TC1          5       /* Timer/Counter 1*/
+#define AT91X40_ID_TC2          6       /* Timer/Counter 2*/
+#define AT91X40_ID_WD           7       /* Watchdog? */
+#define AT91X40_ID_PIOA         8       /* Parallel IO Controller A */
+#define AT91X40_ID_IRQ0         16      /* External IRQ 0 */
+#define AT91X40_ID_IRQ1         17      /* External IRQ 1 */
+#define AT91X40_ID_IRQ2         18      /* External IRQ 2 */
+/*
+ * System Peripherals (offset from AT91_BASE_SYS)
+ */
+#define AT91_BASE_SYS   0xffc00000
+#define AT91_EBI        (0xffe00000 - AT91_BASE_SYS)    /* External Bus Interface */
+#define AT91_SF         (0xfff00000 - AT91_BASE_SYS)    /* Special Function */
+#define AT91_USART1     (0xfffcc000 - AT91_BASE_SYS)    /* USART 1 */
+#define AT91_USART0     (0xfffd0000 - AT91_BASE_SYS)    /* USART 0 */
+#define AT91_TC         (0xfffe0000 - AT91_BASE_SYS)    /* Timer Counter */
+#define AT91_PIOA       (0xffff0000 - AT91_BASE_SYS)    /* PIO Controller A */
+#define AT91_PS         (0xffff4000 - AT91_BASE_SYS)    /* Power Save */
+#define AT91_WD         (0xffff8000 - AT91_BASE_SYS)    /* Watchdog Timer */
+#define AT91_AIC        (0xfffff000 - AT91_BASE_SYS)    /* Advanced Interrupt Controller */
+/*
+ * The AT91x40 series doesn't have a debug unit like the other AT91 parts.
+ * But it does have a chip identify register and extension ID, so define at
+ * least these here.
+ */
+#define AT91_DBGU_CIDR  (AT91_SF + 0)   /* CIDR in PS segment */
+#define AT91_DBGU_EXID  (AT91_SF + 4)   /* EXID in PS segment */
+#endif /* AT91X40_H */
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 0ce6ee98ed0b..d96b10fd449f 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -64,6 +64,7 @@ extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
 /* Ethernet (EMAC & MACB) */
 struct at91_eth_data {
+        u32             phy_mask;
        u8              phy_irq_pin;    /* PHY IRQ */
        u8              is_rmii;        /* using RMII interface? */
 };
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index ef93c30a9c5f..080cbb401a87 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -28,6 +28,11 @@
 #define ARCH_ID_AT91SAM9RL64    0x019b03a0
+#define ARCH_ID_AT91M40800      0x14080044
+#define ARCH_ID_AT91R40807      0x44080746
+#define ARCH_ID_AT91M40807      0x14080745
+#define ARCH_ID_AT91R40008      0x44000840
 static inline unsigned long at91_cpu_identify(void)
 {
        return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 46835e945aea..8f1cdd38a969 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -26,18 +26,29 @@
 #include <asm/arch/at91sam9263.h>
 #elif defined(CONFIG_ARCH_AT91SAM9RL)
 #include <asm/arch/at91sam9rl.h>
+#elif defined(CONFIG_ARCH_AT91X40)
+#include <asm/arch/at91x40.h>
 #else
 #error "Unsupported AT91 processor"
 #endif
+#ifdef CONFIG_MMU
 /*
 * Remap the peripherals from address 0xFFF78000 .. 0xFFFFFFFF
 * to 0xFEF78000 .. 0xFF000000.  (544Kb)
 */
 #define AT91_IO_PHYS_BASE       0xFFF78000
-#define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
 #define AT91_IO_VIRT_BASE       (0xFF000000 - AT91_IO_SIZE)
+#else
+/*
+ * Identity mapping for the non MMU case.
+ */
+#define AT91_IO_PHYS_BASE       AT91_BASE_SYS
+#define AT91_IO_VIRT_BASE       AT91_IO_PHYS_BASE
+#endif
+#define AT91_IO_SIZE            (0xFFFFFFFF - AT91_IO_PHYS_BASE + 1)
 /* Convert a physical IO address to virtual IO address */
 #define AT91_IO_P2V(x)          ((x) - AT91_IO_PHYS_BASE + AT91_IO_VIRT_BASE)
@@ -66,7 +77,11 @@
 #define AT91_CHIPSELECT_7       0x80000000
 /* SDRAM */
+#ifdef CONFIG_DRAM_BASE
+#define AT91_SDRAM_BASE         CONFIG_DRAM_BASE
+#else
 #define AT91_SDRAM_BASE         AT91_CHIPSELECT_1
+#endif
 /* Clocks */
 #define AT91_SLOW_CLOCK         32768           /* slow clock */
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index 2df1ee12dfb7..a310698fb4da 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -42,6 +42,11 @@
 #define AT91SAM9_MASTER_CLOCK   100000000
 #define CLOCK_TICK_RATE         (AT91SAM9_MASTER_CLOCK/16)
+#elif defined(CONFIG_ARCH_AT91X40)
+#define AT91X40_MASTER_CLOCK    40000000
+#define CLOCK_TICK_RATE         (AT91X40_MASTER_CLOCK)
 #endif
 #endif
diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h
index 30ac587b3b41..272a7e0dc6cf 100644
--- a/include/asm-arm/arch-at91/uncompress.h
+++ b/include/asm-arm/arch-at91/uncompress.h
@@ -33,20 +33,24 @@
 */
 static void putc(int c)
 {
+#ifdef AT91_DBGU
        void __iomem *sys = (void __iomem *) AT91_BASE_SYS;     /* physical address */
        while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXRDY))
                barrier();
        __raw_writel(c, sys + AT91_DBGU_THR);
+#endif
 }
 static inline void flush(void)
 {
+#ifdef AT91_DBGU
        void __iomem *sys = (void __iomem *) AT91_BASE_SYS;     /* physical address */
        /* wait for transmission to complete */
        while (!(__raw_readl(sys + AT91_DBGU_SR) & AT91_DBGU_TXEMPTY))
                barrier();
+#endif
 }
 #define arch_decomp_setup()
diff --git a/include/asm-arm/arch-davinci/clock.h b/include/asm-arm/arch-davinci/clock.h
new file mode 100644
index 000000000000..cc168b7a14f2
--- /dev/null
+++ b/include/asm-arm/arch-davinci/clock.h
@@ -0,0 +1,22 @@
+/*
+ * include/asm-arm/arch-davinci/clock.h
+ *
+ * Clock control driver for DaVinci - header file
+ *
+ * Authors: Vladimir Barinov <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_DAVINCI_CLOCK_H
+#define __ASM_ARCH_DAVINCI_CLOCK_H
+struct clk;
+extern int clk_register(struct clk *clk);
+extern void clk_unregister(struct clk *clk);
+extern int davinci_clk_init(void);
+#endif
diff --git a/include/asm-arm/arch-davinci/gpio.h b/include/asm-arm/arch-davinci/gpio.h
new file mode 100644
index 000000000000..ea24a0e0bfd6
--- /dev/null
+++ b/include/asm-arm/arch-davinci/gpio.h
@@ -0,0 +1,156 @@
+/*
+ * TI DaVinci GPIO Support
+ *
+ * Copyright (c) 2006 David Brownell
+ * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __DAVINCI_GPIO_H
+#define __DAVINCI_GPIO_H
+/*
+ * basic gpio routines
+ *
+ * board-specific init should be done by arch/.../.../board-XXX.c (maybe
+ * initializing banks together) rather than boot loaders; kexec() won't
+ * go through boot loaders.
+ *
+ * the gpio clock will be turned on when gpios are used, and you may also
+ * need to pay attention to PINMUX0 and PINMUX1 to be sure those pins are
+ * used as gpios, not with other peripherals.
+ *
+ * GPIOs are numbered 0..(DAVINCI_N_GPIO-1).  For documentation, and maybe
+ * for later updates, code should write GPIO(N) or:
+ *  - GPIOV18(N) for 1.8V pins, N in 0..53; same as GPIO(0)..GPIO(53)
+ *  - GPIOV33(N) for 3.3V pins, N in 0..17; same as GPIO(54)..GPIO(70)
+ *
+ * For GPIO IRQs use gpio_to_irq(GPIO(N)) or gpio_to_irq(GPIOV33(N)) etc
+ * for now, that's != GPIO(N)
+ */
+#define GPIO(X)         (X)             /* 0 <= X <= 70 */
+#define GPIOV18(X)      (X)             /* 1.8V i/o; 0 <= X <= 53 */
+#define GPIOV33(X)      ((X)+54)        /* 3.3V i/o; 0 <= X <= 17 */
+struct gpio_controller {
+        u32     dir;
+        u32     out_data;
+        u32     set_data;
+        u32     clr_data;
+        u32     in_data;
+        u32     set_rising;
+        u32     clr_rising;
+        u32     set_falling;
+        u32     clr_falling;
+        u32     intstat;
+};
+/* The __gpio_to_controller() and __gpio_mask() functions inline to constants
+ * with constant parameters; or in outlined code they execute at runtime.
+ *
+ * You'd access the controller directly when reading or writing more than
+ * one gpio value at a time, and to support wired logic where the value
+ * being driven by the cpu need not match the value read back.
+ *
+ * These are NOT part of the cross-platform GPIO interface
+ */
+static inline struct gpio_controller *__iomem
+__gpio_to_controller(unsigned gpio)
+{
+        void *__iomem ptr;
+        if (gpio < 32)
+                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x10);
+        else if (gpio < 64)
+                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x38);
+        else if (gpio < DAVINCI_N_GPIO)
+                ptr = (void *__iomem)IO_ADDRESS(DAVINCI_GPIO_BASE + 0x60);
+        else
+                ptr = NULL;
+        return ptr;
+}
+static inline u32 __gpio_mask(unsigned gpio)
+{
+        return 1 << (gpio % 32);
+}
+/* The get/set/clear functions will inline when called with constant
+ * parameters, for low-overhead bitbanging.  Illegal constant parameters
+ * cause link-time errors.
+ *
+ * Otherwise, calls with variable parameters use outlined functions.
+ */
+extern int __error_inval_gpio(void);
+extern void __gpio_set(unsigned gpio, int value);
+extern int __gpio_get(unsigned gpio);
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        if (__builtin_constant_p(value)) {
+                struct gpio_controller  *__iomem g;
+                u32                     mask;
+                if (gpio >= DAVINCI_N_GPIO)
+                        __error_inval_gpio();
+                g = __gpio_to_controller(gpio);
+                mask = __gpio_mask(gpio);
+                if (value)
+                        __raw_writel(mask, &g->set_data);
+                else
+                        __raw_writel(mask, &g->clr_data);
+                return;
+        }
+        __gpio_set(gpio, value);
+}
+/* Returns zero or nonzero; works for gpios configured as inputs OR
+ * as outputs.
+ *
+ * NOTE: changes in reported values are synchronized to the GPIO clock.
+ * This is most easily seen after calling gpio_set_value() and then immediatly
+ * gpio_get_value(), where the gpio_get_value() would return the old value
+ * until the GPIO clock ticks and the new value gets latched.
+ */
+static inline int gpio_get_value(unsigned gpio)
+{
+        struct gpio_controller *__iomem g;
+        if (!__builtin_constant_p(gpio))
+                return __gpio_get(gpio);
+        if (gpio >= DAVINCI_N_GPIO)
+                return __error_inval_gpio();
+        g = __gpio_to_controller(gpio);
+        return !!(__gpio_mask(gpio) & __raw_readl(&g->in_data));
+}
+/* powerup default direction is IN */
+extern int gpio_direction_input(unsigned gpio);
+extern int gpio_direction_output(unsigned gpio, int value);
+#include <asm-generic/gpio.h>   /* cansleep wrappers */
+extern int gpio_request(unsigned gpio, const char *tag);
+extern void gpio_free(unsigned gpio);
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return DAVINCI_N_AINTC_IRQ + gpio;
+}
+static inline int irq_to_gpio(unsigned irq)
+{
+        return irq - DAVINCI_N_AINTC_IRQ;
+}
+#endif                          /* __DAVINCI_GPIO_H */
diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h
index 60362d80229e..a2e8969afaca 100644
--- a/include/asm-arm/arch-davinci/hardware.h
+++ b/include/asm-arm/arch-davinci/hardware.h
@@ -11,4 +11,42 @@
 #ifndef __ASM_ARCH_HARDWARE_H
 #define __ASM_ARCH_HARDWARE_H
+/*
+ * Base register addresses
+ */
+#define DAVINCI_DMA_3PCC_BASE                   (0x01C00000)
+#define DAVINCI_DMA_3PTC0_BASE                  (0x01C10000)
+#define DAVINCI_DMA_3PTC1_BASE                  (0x01C10400)
+#define DAVINCI_I2C_BASE                        (0x01C21000)
+#define DAVINCI_PWM0_BASE                       (0x01C22000)
+#define DAVINCI_PWM1_BASE                       (0x01C22400)
+#define DAVINCI_PWM2_BASE                       (0x01C22800)
+#define DAVINCI_SYSTEM_MODULE_BASE              (0x01C40000)
+#define DAVINCI_PLL_CNTRL0_BASE                 (0x01C40800)
+#define DAVINCI_PLL_CNTRL1_BASE                 (0x01C40C00)
+#define DAVINCI_PWR_SLEEP_CNTRL_BASE            (0x01C41000)
+#define DAVINCI_SYSTEM_DFT_BASE                 (0x01C42000)
+#define DAVINCI_IEEE1394_BASE                   (0x01C60000)
+#define DAVINCI_USB_OTG_BASE                    (0x01C64000)
+#define DAVINCI_CFC_ATA_BASE                    (0x01C66000)
+#define DAVINCI_SPI_BASE                        (0x01C66800)
+#define DAVINCI_GPIO_BASE                       (0x01C67000)
+#define DAVINCI_UHPI_BASE                       (0x01C67800)
+#define DAVINCI_VPSS_REGS_BASE                  (0x01C70000)
+#define DAVINCI_EMAC_CNTRL_REGS_BASE            (0x01C80000)
+#define DAVINCI_EMAC_WRAPPER_CNTRL_REGS_BASE    (0x01C81000)
+#define DAVINCI_EMAC_WRAPPER_RAM_BASE           (0x01C82000)
+#define DAVINCI_MDIO_CNTRL_REGS_BASE            (0x01C84000)
+#define DAVINCI_IMCOP_BASE                      (0x01CC0000)
+#define DAVINCI_ASYNC_EMIF_CNTRL_BASE           (0x01E00000)
+#define DAVINCI_VLYNQ_BASE                      (0x01E01000)
+#define DAVINCI_MCBSP_BASE                      (0x01E02000)
+#define DAVINCI_MMC_SD_BASE                     (0x01E10000)
+#define DAVINCI_MS_BASE                         (0x01E20000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE        (0x02000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE        (0x04000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE        (0x06000000)
+#define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE        (0x08000000)
+#define DAVINCI_VLYNQ_REMOTE_BASE               (0x0C000000)
 #endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-davinci/mux.h b/include/asm-arm/arch-davinci/mux.h
new file mode 100644
index 000000000000..c24b6782804d
--- /dev/null
+++ b/include/asm-arm/arch-davinci/mux.h
@@ -0,0 +1,55 @@
+/*
+ * DaVinci pin multiplexing defines
+ *
+ * Author: Vladimir Barinov, MontaVista Software, Inc. <source@mvista.com>
+ *
+ * 2007 (c) MontaVista Software, Inc. This file is licensed under
+ * the terms of the GNU General Public License version 2. This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_ARCH_MUX_H
+#define __ASM_ARCH_MUX_H
+#define DAVINCI_MUX_AEAW0       0
+#define DAVINCI_MUX_AEAW1       1
+#define DAVINCI_MUX_AEAW2       2
+#define DAVINCI_MUX_AEAW3       3
+#define DAVINCI_MUX_AEAW4       4
+#define DAVINCI_MUX_AECS4       10
+#define DAVINCI_MUX_AECS5       11
+#define DAVINCI_MUX_VLYNQWD0    12
+#define DAVINCI_MUX_VLYNQWD1    13
+#define DAVINCI_MUX_VLSCREN     14
+#define DAVINCI_MUX_VLYNQEN     15
+#define DAVINCI_MUX_HDIREN      16
+#define DAVINCI_MUX_ATAEN       17
+#define DAVINCI_MUX_RGB666      22
+#define DAVINCI_MUX_RGB888      23
+#define DAVINCI_MUX_LOEEN       24
+#define DAVINCI_MUX_LFLDEN      25
+#define DAVINCI_MUX_CWEN        26
+#define DAVINCI_MUX_CFLDEN      27
+#define DAVINCI_MUX_HPIEN       29
+#define DAVINCI_MUX_1394EN      30
+#define DAVINCI_MUX_EMACEN      31
+#define DAVINCI_MUX_LEVEL2      32
+#define DAVINCI_MUX_UART0       (DAVINCI_MUX_LEVEL2 + 0)
+#define DAVINCI_MUX_UART1       (DAVINCI_MUX_LEVEL2 + 1)
+#define DAVINCI_MUX_UART2       (DAVINCI_MUX_LEVEL2 + 2)
+#define DAVINCI_MUX_U2FLO       (DAVINCI_MUX_LEVEL2 + 3)
+#define DAVINCI_MUX_PWM0        (DAVINCI_MUX_LEVEL2 + 4)
+#define DAVINCI_MUX_PWM1        (DAVINCI_MUX_LEVEL2 + 5)
+#define DAVINCI_MUX_PWM2        (DAVINCI_MUX_LEVEL2 + 6)
+#define DAVINCI_MUX_I2C         (DAVINCI_MUX_LEVEL2 + 7)
+#define DAVINCI_MUX_SPI         (DAVINCI_MUX_LEVEL2 + 8)
+#define DAVINCI_MUX_MSTK        (DAVINCI_MUX_LEVEL2 + 9)
+#define DAVINCI_MUX_ASP         (DAVINCI_MUX_LEVEL2 + 10)
+#define DAVINCI_MUX_CLK0        (DAVINCI_MUX_LEVEL2 + 16)
+#define DAVINCI_MUX_CLK1        (DAVINCI_MUX_LEVEL2 + 17)
+#define DAVINCI_MUX_TIMIN       (DAVINCI_MUX_LEVEL2 + 18)
+extern void davinci_mux_peripheral(unsigned int mux, unsigned int enable);
+#endif /* __ASM_ARCH_MUX_H */
diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h
new file mode 100644
index 000000000000..486023263f32
--- /dev/null
+++ b/include/asm-arm/arch-imx/gpio.h
@@ -0,0 +1,102 @@
+#ifndef _IMX_GPIO_H
+#include <asm/arch/imx-regs.h>
+#define IMX_GPIO_ALLOC_MODE_NORMAL      0
+#define IMX_GPIO_ALLOC_MODE_NO_ALLOC    1
+#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC   2
+#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY  4
+#define IMX_GPIO_ALLOC_MODE_RELEASE     8
+extern int imx_gpio_request(unsigned gpio, const char *label);
+extern void imx_gpio_free(unsigned gpio);
+extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
+                                        int alloc_mode, const char *label);
+extern int imx_gpio_direction_input(unsigned gpio);
+extern int imx_gpio_direction_output(unsigned gpio, int value);
+extern void __imx_gpio_set_value(unsigned gpio, int value);
+static inline int imx_gpio_get_value(unsigned gpio)
+{
+        return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK));
+}
+static inline void imx_gpio_set_value_inline(unsigned gpio, int value)
+{
+        unsigned long flags;
+        raw_local_irq_save(flags);
+        if(value)
+                DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK));
+        else
+                DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK));
+        raw_local_irq_restore(flags);
+}
+static inline void imx_gpio_set_value(unsigned gpio, int value)
+{
+        if(__builtin_constant_p(gpio))
+                imx_gpio_set_value_inline(gpio, value);
+        else
+                __imx_gpio_set_value(gpio, value);
+}
+extern int imx_gpio_to_irq(unsigned gpio);
+extern int imx_irq_to_gpio(unsigned irq);
+/*-------------------------------------------------------------------------*/
+/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions
+ * to allow future extension of GPIO logic.
+ */
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        return imx_gpio_request(gpio, label);
+}
+static inline void gpio_free(unsigned gpio)
+{
+        imx_gpio_free(gpio);
+}
+static inline  int gpio_direction_input(unsigned gpio)
+{
+        return imx_gpio_direction_input(gpio);
+}
+static inline int gpio_direction_output(unsigned gpio, int value)
+{
+        return imx_gpio_direction_output(gpio, value);
+}
+static inline int gpio_get_value(unsigned gpio)
+{
+        return imx_gpio_get_value(gpio);
+}
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        imx_gpio_set_value(gpio, value);
+}
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
+static inline int gpio_to_irq(unsigned gpio)
+{
+        return imx_gpio_to_irq(gpio);
+}
+static inline int irq_to_gpio(unsigned irq)
+{
+        return imx_irq_to_gpio(irq);
+}
+#endif
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index 30de404c61f5..fb9de2733879 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -77,6 +77,8 @@
 #define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
 #define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
+#define GPIO_PORT_MAX  3
 #define GPIO_PIN_MASK 0x1f
 #define GPIO_PORT_MASK (0x3 << 5)
diff --git a/include/asm-arm/arch-iop13xx/adma.h b/include/asm-arm/arch-iop13xx/adma.h
new file mode 100644
index 000000000000..04006c1c5fd7
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/adma.h
@@ -0,0 +1,544 @@
+/*
+ * Copyright(c) 2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#ifndef _ADMA_H
+#define _ADMA_H
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/hardware.h>
+#include <asm/hardware/iop_adma.h>
+#define ADMA_ACCR(chan) (chan->mmr_base + 0x0)
+#define ADMA_ACSR(chan) (chan->mmr_base + 0x4)
+#define ADMA_ADAR(chan) (chan->mmr_base + 0x8)
+#define ADMA_IIPCR(chan)        (chan->mmr_base + 0x18)
+#define ADMA_IIPAR(chan)        (chan->mmr_base + 0x1c)
+#define ADMA_IIPUAR(chan)       (chan->mmr_base + 0x20)
+#define ADMA_ANDAR(chan)        (chan->mmr_base + 0x24)
+#define ADMA_ADCR(chan) (chan->mmr_base + 0x28)
+#define ADMA_CARMD(chan)        (chan->mmr_base + 0x2c)
+#define ADMA_ABCR(chan) (chan->mmr_base + 0x30)
+#define ADMA_DLADR(chan)        (chan->mmr_base + 0x34)
+#define ADMA_DUADR(chan)        (chan->mmr_base + 0x38)
+#define ADMA_SLAR(src, chan)    (chan->mmr_base + (0x3c + (src << 3)))
+#define ADMA_SUAR(src, chan)    (chan->mmr_base + (0x40 + (src << 3)))
+struct iop13xx_adma_src {
+        u32 src_addr;
+        union {
+                u32 upper_src_addr;
+                struct {
+                        unsigned int pq_upper_src_addr:24;
+                        unsigned int pq_dmlt:8;
+                };
+        };
+};
+struct iop13xx_adma_desc_ctrl {
+        unsigned int int_en:1;
+        unsigned int xfer_dir:2;
+        unsigned int src_select:4;
+        unsigned int zero_result:1;
+        unsigned int block_fill_en:1;
+        unsigned int crc_gen_en:1;
+        unsigned int crc_xfer_dis:1;
+        unsigned int crc_seed_fetch_dis:1;
+        unsigned int status_write_back_en:1;
+        unsigned int endian_swap_en:1;
+        unsigned int reserved0:2;
+        unsigned int pq_update_xfer_en:1;
+        unsigned int dual_xor_en:1;
+        unsigned int pq_xfer_en:1;
+        unsigned int p_xfer_dis:1;
+        unsigned int reserved1:10;
+        unsigned int relax_order_en:1;
+        unsigned int no_snoop_en:1;
+};
+struct iop13xx_adma_byte_count {
+        unsigned int byte_count:24;
+        unsigned int host_if:3;
+        unsigned int reserved:2;
+        unsigned int zero_result_err_q:1;
+        unsigned int zero_result_err:1;
+        unsigned int tx_complete:1;
+};
+struct iop13xx_adma_desc_hw {
+        u32 next_desc;
+        union {
+                u32 desc_ctrl;
+                struct iop13xx_adma_desc_ctrl desc_ctrl_field;
+        };
+        union {
+                u32 crc_addr;
+                u32 block_fill_data;
+                u32 q_dest_addr;
+        };
+        union {
+                u32 byte_count;
+                struct iop13xx_adma_byte_count byte_count_field;
+        };
+        union {
+                u32 dest_addr;
+                u32 p_dest_addr;
+        };
+        union {
+                u32 upper_dest_addr;
+                u32 pq_upper_dest_addr;
+        };
+        struct iop13xx_adma_src src[1];
+};
+struct iop13xx_adma_desc_dual_xor {
+        u32 next_desc;
+        u32 desc_ctrl;
+        u32 reserved;
+        u32 byte_count;
+        u32 h_dest_addr;
+        u32 h_upper_dest_addr;
+        u32 src0_addr;
+        u32 upper_src0_addr;
+        u32 src1_addr;
+        u32 upper_src1_addr;
+        u32 h_src_addr;
+        u32 h_upper_src_addr;
+        u32 d_src_addr;
+        u32 d_upper_src_addr;
+        u32 d_dest_addr;
+        u32 d_upper_dest_addr;
+};
+struct iop13xx_adma_desc_pq_update {
+        u32 next_desc;
+        u32 desc_ctrl;
+        u32 reserved;
+        u32 byte_count;
+        u32 p_dest_addr;
+        u32 p_upper_dest_addr;
+        u32 src0_addr;
+        u32 upper_src0_addr;
+        u32 src1_addr;
+        u32 upper_src1_addr;
+        u32 p_src_addr;
+        u32 p_upper_src_addr;
+        u32 q_src_addr;
+        struct {
+                unsigned int q_upper_src_addr:24;
+                unsigned int q_dmlt:8;
+        };
+        u32 q_dest_addr;
+        u32 q_upper_dest_addr;
+};
+static inline int iop_adma_get_max_xor(void)
+{
+        return 16;
+}
+static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
+{
+        return __raw_readl(ADMA_ADAR(chan));
+}
+static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
+                                                u32 next_desc_addr)
+{
+        __raw_writel(next_desc_addr, ADMA_ANDAR(chan));
+}
+#define ADMA_STATUS_BUSY (1 << 13)
+static inline char iop_chan_is_busy(struct iop_adma_chan *chan)
+{
+        if (__raw_readl(ADMA_ACSR(chan)) &
+                ADMA_STATUS_BUSY)
+                return 1;
+        else
+                return 0;
+}
+static inline int
+iop_chan_get_desc_align(struct iop_adma_chan *chan, int num_slots)
+{
+        return 1;
+}
+#define iop_desc_is_aligned(x, y) 1
+static inline int
+iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
+{
+        *slots_per_op = 1;
+        return 1;
+}
+#define iop_chan_interrupt_slot_count(s, c) iop_chan_memcpy_slot_count(0, s)
+static inline int
+iop_chan_memset_slot_count(size_t len, int *slots_per_op)
+{
+        *slots_per_op = 1;
+        return 1;
+}
+static inline int
+iop_chan_xor_slot_count(size_t len, int src_cnt, int *slots_per_op)
+{
+        int num_slots;
+        /* slots_to_find = 1 for basic descriptor + 1 per 4 sources above 1
+         * (1 source => 8 bytes) (1 slot => 32 bytes)
+         */
+        num_slots = 1 + (((src_cnt - 1) << 3) >> 5);
+        if (((src_cnt - 1) << 3) & 0x1f)
+                num_slots++;
+        *slots_per_op = num_slots;
+        return num_slots;
+}
+#define ADMA_MAX_BYTE_COUNT     (16 * 1024 * 1024)
+#define IOP_ADMA_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
+#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
+#define IOP_ADMA_XOR_MAX_BYTE_COUNT ADMA_MAX_BYTE_COUNT
+#define iop_chan_zero_sum_slot_count(l, s, o) iop_chan_xor_slot_count(l, s, o)
+static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->dest_addr;
+}
+static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->byte_count_field.byte_count;
+}
+static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        int src_idx)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->src[src_idx].src_addr;
+}
+static inline u32 iop_desc_get_src_count(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->desc_ctrl_field.src_select + 1;
+}
+static inline void
+iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop13xx_adma_desc_ctrl field;
+        } u_desc_ctrl;
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
+        u_desc_ctrl.field.int_en = int_en;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->crc_addr = 0;
+}
+static inline void
+iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop13xx_adma_desc_ctrl field;
+        } u_desc_ctrl;
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
+        u_desc_ctrl.field.block_fill_en = 1;
+        u_desc_ctrl.field.int_en = int_en;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->crc_addr = 0;
+}
+/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
+static inline void
+iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop13xx_adma_desc_ctrl field;
+        } u_desc_ctrl;
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.src_select = src_cnt - 1;
+        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
+        u_desc_ctrl.field.int_en = int_en;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->crc_addr = 0;
+}
+#define iop_desc_init_null_xor(d, s, i) iop_desc_init_xor(d, s, i)
+/* to do: support buffers larger than ADMA_MAX_BYTE_COUNT */
+static inline int
+iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop13xx_adma_desc_ctrl field;
+        } u_desc_ctrl;
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.src_select = src_cnt - 1;
+        u_desc_ctrl.field.xfer_dir = 3; /* local to internal bus */
+        u_desc_ctrl.field.zero_result = 1;
+        u_desc_ctrl.field.status_write_back_en = 1;
+        u_desc_ctrl.field.int_en = int_en;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->crc_addr = 0;
+        return 1;
+}
+static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        u32 byte_count)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->byte_count = byte_count;
+}
+static inline void
+iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
+{
+        int slots_per_op = desc->slots_per_op;
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
+        int i = 0;
+        if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
+                hw_desc->byte_count = len;
+        } else {
+                do {
+                        iter = iop_hw_desc_slot_idx(hw_desc, i);
+                        iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
+                        len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
+                        i += slots_per_op;
+                } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
+                if (len) {
+                        iter = iop_hw_desc_slot_idx(hw_desc, i);
+                        iter->byte_count = len;
+                }
+        }
+}
+static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        dma_addr_t addr)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->dest_addr = addr;
+        hw_desc->upper_dest_addr = 0;
+}
+static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
+                                        dma_addr_t addr)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->src[0].src_addr = addr;
+        hw_desc->src[0].upper_src_addr = 0;
+}
+static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
+                                        int src_idx, dma_addr_t addr)
+{
+        int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc, *iter;
+        int i = 0;
+        do {
+                iter = iop_hw_desc_slot_idx(hw_desc, i);
+                iter->src[src_idx].src_addr = addr;
+                iter->src[src_idx].upper_src_addr = 0;
+                slot_cnt -= slots_per_op;
+                if (slot_cnt) {
+                        i += slots_per_op;
+                        addr += IOP_ADMA_XOR_MAX_BYTE_COUNT;
+                }
+        } while (slot_cnt);
+}
+static inline void
+iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
+        struct iop_adma_chan *chan)
+{
+        iop_desc_init_memcpy(desc, 1);
+        iop_desc_set_byte_count(desc, chan, 0);
+        iop_desc_set_dest_addr(desc, chan, 0);
+        iop_desc_set_memcpy_src_addr(desc, 0);
+}
+#define iop_desc_set_zero_sum_src_addr iop_desc_set_xor_src_addr
+static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
+                                        u32 next_desc_addr)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        BUG_ON(hw_desc->next_desc);
+        hw_desc->next_desc = next_desc_addr;
+}
+static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        return hw_desc->next_desc;
+}
+static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->next_desc = 0;
+}
+static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
+                                                u32 val)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        hw_desc->block_fill_data = val;
+}
+static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
+{
+        struct iop13xx_adma_desc_hw *hw_desc = desc->hw_desc;
+        struct iop13xx_adma_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
+        struct iop13xx_adma_byte_count byte_count = hw_desc->byte_count_field;
+        BUG_ON(!(byte_count.tx_complete && desc_ctrl.zero_result));
+        if (desc_ctrl.pq_xfer_en)
+                return byte_count.zero_result_err_q;
+        else
+                return byte_count.zero_result_err;
+}
+static inline void iop_chan_append(struct iop_adma_chan *chan)
+{
+        u32 adma_accr;
+        adma_accr = __raw_readl(ADMA_ACCR(chan));
+        adma_accr |= 0x2;
+        __raw_writel(adma_accr, ADMA_ACCR(chan));
+}
+static inline void iop_chan_idle(int busy, struct iop_adma_chan *chan)
+{
+        do { } while (0);
+}
+static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
+{
+        return __raw_readl(ADMA_ACSR(chan));
+}
+static inline void iop_chan_disable(struct iop_adma_chan *chan)
+{
+        u32 adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
+        adma_chan_ctrl &= ~0x1;
+        __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
+}
+static inline void iop_chan_enable(struct iop_adma_chan *chan)
+{
+        u32 adma_chan_ctrl;
+        adma_chan_ctrl = __raw_readl(ADMA_ACCR(chan));
+        adma_chan_ctrl |= 0x1;
+        __raw_writel(adma_chan_ctrl, ADMA_ACCR(chan));
+}
+static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(ADMA_ACSR(chan));
+        status &= (1 << 12);
+        __raw_writel(status, ADMA_ACSR(chan));
+}
+static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(ADMA_ACSR(chan));
+        status &= (1 << 11);
+        __raw_writel(status, ADMA_ACSR(chan));
+}
+static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(ADMA_ACSR(chan));
+        status &= (1 << 9) | (1 << 5) | (1 << 4) | (1 << 3);
+        __raw_writel(status, ADMA_ACSR(chan));
+}
+static inline int
+iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(9, &status);
+}
+static inline int
+iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(5, &status);
+}
+static inline int
+iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(4, &status);
+}
+static inline int
+iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(3, &status);
+}
+static inline int
+iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+static inline int
+iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+static inline int
+iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+#endif /* _ADMA_H */
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index e6736c3d1f7f..52b7fab7ef60 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void)
        return id;
 }
+/* WDTCR CP6 R7 Page 9 */
+static inline u32 read_wdtcr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
+}
+/* WDTSR CP6 R8 Page 9 */
+static inline u32 read_wdtsr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtsr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
+}
+/* RCSR - Reset Cause Status Register  */
+static inline u32 read_rcsr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
+        return val;
+}
+extern unsigned long get_iop_tick_rate(void);
 #endif
 /*
@@ -166,12 +199,22 @@ static inline int iop13xx_cpu_id(void)
 #define IOP13XX_INIT_I2C_1            (1 << 1)
 #define IOP13XX_INIT_I2C_2            (1 << 2)
-#define IQ81340_NUM_UART     2
+/* ADMA selection flags */
-#define IQ81340_NUM_I2C      3
+/* INIT_ADMA_DEFAULT = Rely on CONFIG_IOP13XX_ADMA* */
-#define IQ81340_NUM_PHYS_MAP_FLASH 1
+#define IOP13XX_INIT_ADMA_DEFAULT     (0)
-#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
+#define IOP13XX_INIT_ADMA_0           (1 << 0)
-                                IQ81340_NUM_I2C +\
+#define IOP13XX_INIT_ADMA_1           (1 << 1)
-                                IQ81340_NUM_PHYS_MAP_FLASH)
+#define IOP13XX_INIT_ADMA_2           (1 << 2)
+/* Platform devices */
+#define IQ81340_NUM_UART                2
+#define IQ81340_NUM_I2C                 3
+#define IQ81340_NUM_PHYS_MAP_FLASH      1
+#define IQ81340_NUM_ADMA                3
+#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART + \
+                                IQ81340_NUM_I2C + \
+                                IQ81340_NUM_PHYS_MAP_FLASH + \
+                                IQ81340_NUM_ADMA)
 /*========================== PMMR offsets for key registers ============*/
 #define IOP13XX_ATU0_PMMR_OFFSET        0x00048000
@@ -444,22 +487,6 @@ static inline int iop13xx_cpu_id(void)
 /*==============================ADMA UNITS===============================*/
 #define IOP13XX_ADMA_PHYS_BASE(chan)    IOP13XX_REG_ADDR32_PHYS((chan << 9))
 #define IOP13XX_ADMA_UPPER_PA(chan)     (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
-#define IOP13XX_ADMA_OFFSET(chan, ofs)  IOP13XX_REG_ADDR32((chan << 9) + (ofs))
-#define IOP13XX_ADMA_ACCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x0)
-#define IOP13XX_ADMA_ACSR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x4)
-#define IOP13XX_ADMA_ADAR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x8)
-#define IOP13XX_ADMA_IIPCR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x18)
-#define IOP13XX_ADMA_IIPAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x1c)
-#define IOP13XX_ADMA_IIPUAR(chan)    IOP13XX_ADMA_OFFSET(chan, 0x20)
-#define IOP13XX_ADMA_ANDAR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x24)
-#define IOP13XX_ADMA_ADCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x28)
-#define IOP13XX_ADMA_CARMD(chan)     IOP13XX_ADMA_OFFSET(chan, 0x2c)
-#define IOP13XX_ADMA_ABCR(chan)      IOP13XX_ADMA_OFFSET(chan, 0x30)
-#define IOP13XX_ADMA_DLADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x34)
-#define IOP13XX_ADMA_DUADR(chan)     IOP13XX_ADMA_OFFSET(chan, 0x38)
-#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
-#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
 /*==============================XSI BRIDGE===============================*/
 #define IOP13XX_XBG_BECSR               IOP13XX_REG_ADDR32(0x178c)
@@ -486,4 +513,14 @@ static inline int iop13xx_cpu_id(void)
 #define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
 #define IOP13XX_PROCESSOR_FREQ          IOP13XX_REG_ADDR32(0x2180)
+/* Watchdog timer definitions */
+#define IOP_WDTCR_EN_ARM        0x1e1e1e1e
+#define IOP_WDTCR_EN            0xe1e1e1e1
+#define IOP_WDTCR_DIS_ARM       0x1f1f1f1f
+#define IOP_WDTCR_DIS           0xf1f1f1f1
+#define IOP_RCSR_WDT            (1 << 5) /* reset caused by watchdog timer */
+#define IOP13XX_WDTSR_WRITE_EN  (1 << 31) /* used to speed up reset requests */
+#define IOP13XX_WDTCR_IB_RESET  (1 << 0)
 #endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
index 127827058e1f..8575af8db78c 100644
--- a/include/asm-arm/arch-iop13xx/system.h
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -13,43 +13,13 @@ static inline void arch_idle(void)
        cpu_do_idle();
 }
-/* WDTCR CP6 R7 Page 9 */
-static inline u32 read_wdtcr(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
-        return val;
-}
-static inline void write_wdtcr(u32 val)
-{
-        asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
-}
-/* WDTSR CP6 R8 Page 9 */
-static inline u32 read_wdtsr(void)
-{
-        u32 val;
-        asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
-        return val;
-}
-static inline void write_wdtsr(u32 val)
-{
-        asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
-}
-#define IOP13XX_WDTCR_EN_ARM    0x1e1e1e1e
-#define IOP13XX_WDTCR_EN        0xe1e1e1e1
-#define IOP13XX_WDTCR_DIS_ARM   0x1f1f1f1f
-#define IOP13XX_WDTCR_DIS       0xf1f1f1f1
-#define IOP13XX_WDTSR_WRITE_EN  (1 << 31)
-#define IOP13XX_WDTCR_IB_RESET  (1 << 0)
 static inline void arch_reset(char mode)
 {
        /*
         * Reset the internal bus (warning both cores are reset)
         */
-        write_wdtcr(IOP13XX_WDTCR_EN_ARM);
+        write_wdtcr(IOP_WDTCR_EN_ARM);
-        write_wdtcr(IOP13XX_WDTCR_EN);
+        write_wdtcr(IOP_WDTCR_EN);
        write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
        write_wdtcr(0x1000);
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
index b9525d59b7ad..dd9c2934190e 100644
--- a/include/asm-arm/arch-iop13xx/uncompress.h
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -1,7 +1,6 @@
 #include <asm/types.h>
 #include <linux/serial_reg.h>
 #include <asm/hardware.h>
-#include <asm/processor.h>
 #define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
 #define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
@@ -9,7 +8,7 @@
 static inline void putc(char c)
 {
        while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
-                cpu_relax();
+                barrier();
        UART_BASE[UART_TX] = c;
 }
diff --git a/include/asm-arm/arch-iop32x/adma.h b/include/asm-arm/arch-iop32x/adma.h
new file mode 100644
index 000000000000..5ed92037dd10
--- /dev/null
+++ b/include/asm-arm/arch-iop32x/adma.h
@@ -0,0 +1,5 @@
+#ifndef IOP32X_ADMA_H
+#define IOP32X_ADMA_H
+#include <asm/hardware/iop3xx-adma.h>
+#endif
diff --git a/include/asm-arm/arch-iop32x/uncompress.h b/include/asm-arm/arch-iop32x/uncompress.h
index e64f52bf2bce..070f15818fe7 100644
--- a/include/asm-arm/arch-iop32x/uncompress.h
+++ b/include/asm-arm/arch-iop32x/uncompress.h
@@ -26,7 +26,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
        if (machine_is_iq80321())
                uart_base = (volatile u8 *)IQ80321_UART;
-        else if (machine_is_iq31244())
+        else if (machine_is_iq31244() || machine_is_em7210())
                uart_base = (volatile u8 *)IQ31244_UART;
        else
                uart_base = (volatile u8 *)0xfe800000;
diff --git a/include/asm-arm/arch-iop33x/adma.h b/include/asm-arm/arch-iop33x/adma.h
new file mode 100644
index 000000000000..4b92f795f90e
--- /dev/null
+++ b/include/asm-arm/arch-iop33x/adma.h
@@ -0,0 +1,5 @@
+#ifndef IOP33X_ADMA_H
+#define IOP33X_ADMA_H
+#include <asm/hardware/iop3xx-adma.h>
+#endif
diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h
index 3d3820d7ba09..e0791af3bfea 100644
--- a/include/asm-arm/arch-ixp4xx/ixdp425.h
+++ b/include/asm-arm/arch-ixp4xx/ixdp425.h
@@ -32,4 +32,8 @@
 #define IXDP425_PCI_INTC_PIN    9
 #define IXDP425_PCI_INTD_PIN    8
+/* NAND Flash pins */
+#define IXDP425_NAND_NCE_PIN    12
+#define IXDP425_NAND_CMD_BYTE   0x01
+#define IXDP425_NAND_ADDR_BYTE  0x02
diff --git a/include/asm-arm/arch-ixp4xx/udc.h b/include/asm-arm/arch-ixp4xx/udc.h
index 79b850a3be47..dbdec36ff0d1 100644
--- a/include/asm-arm/arch-ixp4xx/udc.h
+++ b/include/asm-arm/arch-ixp4xx/udc.h
@@ -6,25 +6,3 @@
 extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
-static inline int udc_gpio_to_irq(unsigned gpio)
-{
-        return 0;
-}
-static inline void udc_gpio_init_vbus(unsigned gpio)
-{
-}
-static inline void udc_gpio_init_pullup(unsigned gpio)
-{
-}
-static inline int udc_gpio_get(unsigned gpio)
-{
-        return 0;
-}
-static inline void udc_gpio_set(unsigned gpio, int is_on)
-{
-}
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
index 09ae6c91be60..f7a35b78823f 100644
--- a/include/asm-arm/arch-ixp4xx/uncompress.h
+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
@@ -38,9 +38,10 @@ static void flush(void)
 static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 {
        /*
-         * Coyote and gtwx5715 only have UART2 connected
+         * Some boards are using UART2 as console
         */
-        if (machine_is_adi_coyote() || machine_is_gtwx5715())
+        if (machine_is_adi_coyote() || machine_is_gtwx5715() ||
+                         machine_is_gateway7001() || machine_is_wg302v2())
                uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
        else
                uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
diff --git a/include/asm-arm/arch-ks8695/gpio.h b/include/asm-arm/arch-ks8695/gpio.h
new file mode 100644
index 000000000000..65ceea28607b
--- /dev/null
+++ b/include/asm-arm/arch-ks8695/gpio.h
@@ -0,0 +1,79 @@
+/*
+ * include/asm-arm/arch-ks8695/gpio.h
+ *
+ * Copyright (C) 2006 Andrew Victor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_GPIO_H_
+#define __ASM_ARCH_GPIO_H_
+#define KS8695_GPIO_0           0
+#define KS8695_GPIO_1           1
+#define KS8695_GPIO_2           2
+#define KS8695_GPIO_3           3
+#define KS8695_GPIO_4           4
+#define KS8695_GPIO_5           5
+#define KS8695_GPIO_6           6
+#define KS8695_GPIO_7           7
+#define KS8695_GPIO_8           8
+#define KS8695_GPIO_9           9
+#define KS8695_GPIO_10          10
+#define KS8695_GPIO_11          11
+#define KS8695_GPIO_12          12
+#define KS8695_GPIO_13          13
+#define KS8695_GPIO_14          14
+#define KS8695_GPIO_15          15
+/*
+ * Configure GPIO pin as external interrupt source.
+ */
+int __init_or_module ks8695_gpio_interrupt(unsigned int pin, unsigned int type);
+/*
+ * Configure the GPIO line as an input.
+ */
+int __init_or_module gpio_direction_input(unsigned int pin);
+/*
+ * Configure the GPIO line as an output, with default state.
+ */
+int __init_or_module gpio_direction_output(unsigned int pin, unsigned int state);
+/*
+ * Set the state of an output GPIO line.
+ */
+void gpio_set_value(unsigned int pin, unsigned int state);
+/*
+ * Read the state of a GPIO line.
+ */
+int gpio_get_value(unsigned int pin);
+/*
+ * Map GPIO line to IRQ number.
+ */
+int gpio_to_irq(unsigned int pin);
+/*
+ * Map IRQ number to GPIO line.
+ */
+int irq_to_gpio(unsigned int irq);
+#include <asm-generic/gpio.h>
+static inline int gpio_request(unsigned int pin, const char *label)
+{
+        return 0;
+}
+static inline void gpio_free(unsigned int pin)
+{
+}
+#endif
diff --git a/include/asm-arm/arch-mxc/board-mx31ads.h b/include/asm-arm/arch-mxc/board-mx31ads.h
new file mode 100644
index 000000000000..be29b83ad4ae
--- /dev/null
+++ b/include/asm-arm/arch-mxc/board-mx31ads.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
+/*!
+ * @name PBC Controller parameters
+ */
+/*! @{ */
+/*!
+ * Base address of PBC controller
+ */
+#define PBC_BASE_ADDRESS        IO_ADDRESS(CS4_BASE_ADDR)
+/* Offsets for the PBC Controller register */
+/*!
+ * PBC Board status register offset
+ */
+#define PBC_BSTAT               0x000002
+/*!
+ * PBC Board control register 1 set address.
+ */
+#define PBC_BCTRL1_SET          0x000004
+/*!
+ * PBC Board control register 1 clear address.
+ */
+#define PBC_BCTRL1_CLEAR        0x000006
+/*!
+ * PBC Board control register 2 set address.
+ */
+#define PBC_BCTRL2_SET          0x000008
+/*!
+ * PBC Board control register 2 clear address.
+ */
+#define PBC_BCTRL2_CLEAR        0x00000A
+/*!
+ * PBC Board control register 3 set address.
+ */
+#define PBC_BCTRL3_SET          0x00000C
+/*!
+ * PBC Board control register 3 clear address.
+ */
+#define PBC_BCTRL3_CLEAR        0x00000E
+/*!
+ * PBC Board control register 4 set address.
+ */
+#define PBC_BCTRL4_SET          0x000010
+/*!
+ * PBC Board control register 4 clear address.
+ */
+#define PBC_BCTRL4_CLEAR        0x000012
+/*!
+ * PBC Board status register 1.
+ */
+#define PBC_BSTAT1              0x000014
+/*!
+ * PBC Board interrupt status register.
+ */
+#define PBC_INTSTATUS           0x000016
+/*!
+ * PBC Board interrupt current status register.
+ */
+#define PBC_INTCURR_STATUS      0x000018
+/*!
+ * PBC Interrupt mask register set address.
+ */
+#define PBC_INTMASK_SET         0x00001A
+/*!
+ * PBC Interrupt mask register clear address.
+ */
+#define PBC_INTMASK_CLEAR       0x00001C
+/*!
+ * External UART A.
+ */
+#define PBC_SC16C652_UARTA      0x010000
+/*!
+ * External UART B.
+ */
+#define PBC_SC16C652_UARTB      0x010010
+/*!
+ * Ethernet Controller IO base address.
+ */
+#define PBC_CS8900A_IOBASE      0x020000
+/*!
+ * Ethernet Controller Memory base address.
+ */
+#define PBC_CS8900A_MEMBASE     0x021000
+/*!
+ * Ethernet Controller DMA base address.
+ */
+#define PBC_CS8900A_DMABASE     0x022000
+/*!
+ * External chip select 0.
+ */
+#define PBC_XCS0                0x040000
+/*!
+ * LCD Display enable.
+ */
+#define PBC_LCD_EN_B            0x060000
+/*!
+ * Code test debug enable.
+ */
+#define PBC_CODE_B              0x070000
+/*!
+ * PSRAM memory select.
+ */
+#define PBC_PSRAM_B             0x5000000
+#define PBC_INTSTATUS_REG       (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTCURR_STATUS_REG  (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG     (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG   (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT        IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+#define EXPIO_INT_LOW_BAT       (MXC_EXP_IO_BASE + 0)
+#define EXPIO_INT_PB_IRQ        (MXC_EXP_IO_BASE + 1)
+#define EXPIO_INT_OTG_FS_OVR    (MXC_EXP_IO_BASE + 2)
+#define EXPIO_INT_FSH_OVR       (MXC_EXP_IO_BASE + 3)
+#define EXPIO_INT_RES4          (MXC_EXP_IO_BASE + 4)
+#define EXPIO_INT_RES5          (MXC_EXP_IO_BASE + 5)
+#define EXPIO_INT_RES6          (MXC_EXP_IO_BASE + 6)
+#define EXPIO_INT_RES7          (MXC_EXP_IO_BASE + 7)
+#define EXPIO_INT_ENET_INT      (MXC_EXP_IO_BASE + 8)
+#define EXPIO_INT_OTG_FS_INT    (MXC_EXP_IO_BASE + 9)
+#define EXPIO_INT_XUART_INTA    (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB    (MXC_EXP_IO_BASE + 11)
+#define EXPIO_INT_SYNTH_IRQ     (MXC_EXP_IO_BASE + 12)
+#define EXPIO_INT_CE_INT1       (MXC_EXP_IO_BASE + 13)
+#define EXPIO_INT_CE_INT2       (MXC_EXP_IO_BASE + 14)
+#define EXPIO_INT_RES15         (MXC_EXP_IO_BASE + 15)
+#define MXC_MAX_EXP_IO_LINES    16
+#endif                          /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
diff --git a/include/asm-arm/arch-mxc/common.h b/include/asm-arm/arch-mxc/common.h
new file mode 100644
index 000000000000..23b4350edbd6
--- /dev/null
+++ b/include/asm-arm/arch-mxc/common.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_COMMON_H__
+#define __ASM_ARCH_MXC_COMMON_H__
+struct sys_timer;
+extern void mxc_map_io(void);
+extern void mxc_init_irq(void);
+extern struct sys_timer mxc_timer;
+#endif
diff --git a/include/asm-arm/arch-mxc/dma.h b/include/asm-arm/arch-mxc/dma.h
new file mode 100644
index 000000000000..65e639d51d2b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/dma.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_DMA_H__
+#define __ASM_ARCH_MXC_DMA_H__
+/*!
+ * @file dma.h
+ * @brief This file contains Unified DMA API for all MXC platforms.
+ * The API is platform independent.
+ *
+ * @ingroup SDMA
+ */
+#endif
diff --git a/include/asm-arm/arch-mxc/entry-macro.S b/include/asm-arm/arch-mxc/entry-macro.S
new file mode 100644
index 000000000000..b542433afb1b
--- /dev/null
+++ b/include/asm-arm/arch-mxc/entry-macro.S
@@ -0,0 +1,39 @@
+/*
+ *  Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+        @ this macro disables fast irq (not implemented)
+        .macro  disable_fiq
+        .endm
+        .macro  get_irqnr_preamble, base, tmp
+        .endm
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+        @ this macro checks which interrupt occured
+        @ and returns its number in irqnr
+        @ and returns if an interrupt occured in irqstat
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \base, =AVIC_IO_ADDRESS(AVIC_BASE_ADDR)
+        @ Load offset & priority of the highest priority
+        @ interrupt pending from AVIC_NIVECSR
+        ldr     \irqstat, [\base, #0x40]
+        @ Shift to get the decoded IRQ number, using ASR so
+        @ 'no interrupt pending' becomes 0xffffffff
+        mov     \irqnr, \irqstat, asr #16
+        @ set zero flag if IRQ + 1 == 0
+        adds    \tmp, \irqnr, #1
+        .endm
+        @ irq priority table (not used)
+        .macro  irq_prio_table
+        .endm
diff --git a/include/asm-arm/arch-mxc/hardware.h b/include/asm-arm/arch-mxc/hardware.h
new file mode 100644
index 000000000000..3c09b92fef0d
--- /dev/null
+++ b/include/asm-arm/arch-mxc/hardware.h
@@ -0,0 +1,52 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*!
+ * @file hardware.h
+ * @brief This file contains the hardware definitions of the board.
+ *
+ * @ingroup System
+ */
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#define __ASM_ARCH_MXC_HARDWARE_H__
+#include <asm/sizes.h>
+#include <asm/arch/mx31.h>
+#include <asm/arch/mxc.h>
+#define MXC_MAX_GPIO_LINES      (GPIO_NUM_PIN * GPIO_PORT_NUM)
+/*
+ * ---------------------------------------------------------------------------
+ * Board specific defines
+ * ---------------------------------------------------------------------------
+ */
+#define MXC_EXP_IO_BASE         (MXC_GPIO_INT_BASE + MXC_MAX_GPIO_LINES)
+#include <asm/arch/board-mx31ads.h>
+#ifndef MXC_MAX_EXP_IO_LINES
+#define MXC_MAX_EXP_IO_LINES 0
+#endif
+#define MXC_MAX_VIRTUAL_INTS    16
+#define MXC_VIRTUAL_INTS_BASE   (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
+#define MXC_SDIO1_CARD_IRQ      MXC_VIRTUAL_INTS_BASE
+#define MXC_SDIO2_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 1)
+#define MXC_SDIO3_CARD_IRQ      (MXC_VIRTUAL_INTS_BASE + 2)
+#define MXC_MAX_INTS            (MXC_MAX_INT_LINES + \
+                                MXC_MAX_GPIO_LINES + \
+                                MXC_MAX_EXP_IO_LINES + \
+                                MXC_MAX_VIRTUAL_INTS)
+#endif                          /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/include/asm-arm/arch-mxc/io.h b/include/asm-arm/arch-mxc/io.h
new file mode 100644
index 000000000000..cf6c83a4b9f7
--- /dev/null
+++ b/include/asm-arm/arch-mxc/io.h
@@ -0,0 +1,33 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/*!
+ * @file io.h
+ * @brief This file contains some memory mapping macros.
+ * @note There is no real ISA or PCI buses. But have to define these macros
+ * for some drivers to compile.
+ *
+ * @ingroup System
+ */
+#ifndef __ASM_ARCH_MXC_IO_H__
+#define __ASM_ARCH_MXC_IO_H__
+/*! Allow IO space to be anywhere in the memory */
+#define IO_SPACE_LIMIT 0xffffffff
+/*!
+ * io address mapping macro
+ */
+#define __io(a)                 ((void __iomem *)(a))
+#define __mem_pci(a)            (a)
+#endif
diff --git a/include/asm-arm/arch-mxc/irqs.h b/include/asm-arm/arch-mxc/irqs.h
new file mode 100644
index 000000000000..e4686c6bc4bf
--- /dev/null
+++ b/include/asm-arm/arch-mxc/irqs.h
@@ -0,0 +1,38 @@
+/*
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_IRQS_H__
+#define __ASM_ARCH_MXC_IRQS_H__
+#include <asm/hardware.h>
+/*!
+ * @file irqs.h
+ * @brief This file defines the number of normal interrupts and fast interrupts
+ *
+ * @ingroup Interrupt
+ */
+#define MXC_IRQ_TO_EXPIO(irq)   ((irq) - MXC_EXP_IO_BASE)
+#define MXC_IRQ_TO_GPIO(irq)    ((irq) - MXC_GPIO_INT_BASE)
+#define MXC_GPIO_TO_IRQ(x)      (MXC_GPIO_INT_BASE + x)
+/*!
+ * Number of normal interrupts
+ */
+#define NR_IRQS         MXC_MAX_INTS
+/*!
+ * Number of fast interrupts
+ */
+#define NR_FIQS         MXC_MAX_INTS
+#endif                          /* __ASM_ARCH_MXC_IRQS_H__ */
diff --git a/include/asm-arm/arch-mxc/memory.h b/include/asm-arm/arch-mxc/memory.h
new file mode 100644
index 000000000000..c89aac83a407
--- /dev/null
+++ b/include/asm-arm/arch-mxc/memory.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_MEMORY_H__
+#define __ASM_ARCH_MXC_MEMORY_H__
+#include <asm/hardware.h>
+/*!
+ * @file memory.h
+ * @brief This file contains macros needed by the Linux kernel and drivers.
+ *
+ * @ingroup Memory
+ */
+/*!
+ * Virtual view <-> DMA view memory address translations
+ * This macro is used to translate the virtual address to an address
+ * suitable to be passed to set_dma_addr()
+ */
+#define __virt_to_bus(a)        __virt_to_phys(a)
+/*!
+ * Used to convert an address for DMA operations to an address that the
+ * kernel can use.
+ */
+#define __bus_to_virt(a)        __phys_to_virt(a)
+#endif                          /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/include/asm-arm/arch-mxc/mx31.h b/include/asm-arm/arch-mxc/mx31.h
new file mode 100644
index 000000000000..85c49c9e5d15
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mx31.h
@@ -0,0 +1,335 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_MX31_H__
+#define __ASM_ARCH_MXC_MX31_H__
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+/*!
+ * defines the hardware clock tick rate
+ */
+#define CLOCK_TICK_RATE         16625000
+/*
+ * MX31 memory map:
+ *
+ * Virt         Phys            Size    What
+ * ---------------------------------------------------------------------------
+ * F8000000     1FFC0000        16K     IRAM
+ * F9000000     30000000        256M    L2CC
+ * FC000000     43F00000        1M      AIPS 1
+ * FC100000     50000000        1M      SPBA
+ * FC200000     53F00000        1M      AIPS 2
+ * FC500000     60000000        128M    ROMPATCH
+ * FC400000     68000000        128M    AVIC
+ *              70000000        256M    IPU (MAX M2)
+ *              80000000        256M    CSD0 SDRAM/DDR
+ *              90000000        256M    CSD1 SDRAM/DDR
+ *              A0000000        128M    CS0 Flash
+ *              A8000000        128M    CS1 Flash
+ *              B0000000        32M     CS2
+ *              B2000000        32M     CS3
+ * F4000000     B4000000        32M     CS4
+ *              B6000000        32M     CS5
+ * FC320000     B8000000        64K     NAND, SDRAM, WEIM, M3IF, EMI controllers
+ *              C0000000        64M     PCMCIA/CF
+ */
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+#define CS4_BASE_ADDR           0xB4000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
+#define CS4_SIZE                SZ_32M
+#define CS5_BASE_ADDR           0xB6000000
+#define PCMCIA_MEM_BASE_ADDR    0xBC000000
+/*
+ * IRAM
+ */
+#define IRAM_BASE_ADDR          0x1FFC0000      /* internal ram */
+#define IRAM_BASE_ADDR_VIRT     0xF8000000
+#define IRAM_SIZE               SZ_16K
+/*
+ * L2CC
+ */
+#define L2CC_BASE_ADDR          0x30000000
+#define L2CC_BASE_ADDR_VIRT     0xF9000000
+#define L2CC_SIZE               SZ_1M
+/*
+ * AIPS 1
+ */
+#define AIPS1_BASE_ADDR         0x43F00000
+#define AIPS1_BASE_ADDR_VIRT    0xFC000000
+#define AIPS1_SIZE              SZ_1M
+#define MAX_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00004000)
+#define EVTMON_BASE_ADDR        (AIPS1_BASE_ADDR + 0x00008000)
+#define CLKCTL_BASE_ADDR        (AIPS1_BASE_ADDR + 0x0000C000)
+#define ETB_SLOT4_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00010000)
+#define ETB_SLOT5_BASE_ADDR     (AIPS1_BASE_ADDR + 0x00014000)
+#define ECT_CTIO_BASE_ADDR      (AIPS1_BASE_ADDR + 0x00018000)
+#define I2C_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00080000)
+#define I2C3_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00084000)
+#define OTG_BASE_ADDR           (AIPS1_BASE_ADDR + 0x00088000)
+#define ATA_BASE_ADDR           (AIPS1_BASE_ADDR + 0x0008C000)
+#define UART1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00090000)
+#define UART2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x00094000)
+#define I2C2_BASE_ADDR          (AIPS1_BASE_ADDR + 0x00098000)
+#define OWIRE_BASE_ADDR         (AIPS1_BASE_ADDR + 0x0009C000)
+#define SSI1_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000A0000)
+#define CSPI1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000A4000)
+#define KPP_BASE_ADDR           (AIPS1_BASE_ADDR + 0x000A8000)
+#define IOMUXC_BASE_ADDR        (AIPS1_BASE_ADDR + 0x000AC000)
+#define UART4_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B0000)
+#define UART5_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
+#define ECT_IP1_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000B8000)
+#define ECT_IP2_BASE_ADDR       (AIPS1_BASE_ADDR + 0x000BC000)
+/*
+ * SPBA global module enabled #0
+ */
+#define SPBA0_BASE_ADDR         0x50000000
+#define SPBA0_BASE_ADDR_VIRT    0xFC100000
+#define SPBA0_SIZE              SZ_1M
+#define MMC_SDHC1_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00004000)
+#define MMC_SDHC2_BASE_ADDR     (SPBA0_BASE_ADDR + 0x00008000)
+#define UART3_BASE_ADDR         (SPBA0_BASE_ADDR + 0x0000C000)
+#define CSPI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00010000)
+#define SSI2_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00014000)
+#define SIM1_BASE_ADDR          (SPBA0_BASE_ADDR + 0x00018000)
+#define IIM_BASE_ADDR           (SPBA0_BASE_ADDR + 0x0001C000)
+#define ATA_DMA_BASE_ADDR       (SPBA0_BASE_ADDR + 0x00020000)
+#define MSHC1_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define MSHC2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00024000)
+#define SPBA_CTRL_BASE_ADDR     (SPBA0_BASE_ADDR + 0x0003C000)
+/*
+ * AIPS 2
+ */
+#define AIPS2_BASE_ADDR         0x53F00000
+#define AIPS2_BASE_ADDR_VIRT    0xFC200000
+#define AIPS2_SIZE              SZ_1M
+#define CCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x00080000)
+#define CSPI3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
+#define FIRI_BASE_ADDR          (AIPS2_BASE_ADDR + 0x0008C000)
+#define GPT1_BASE_ADDR          (AIPS2_BASE_ADDR + 0x00090000)
+#define EPIT1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00094000)
+#define EPIT2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00098000)
+#define GPIO3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000A4000)
+#define SCC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AC000)
+#define SCM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AE000)
+#define SMN_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000AF000)
+#define RNGA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000B0000)
+#define IPU_CTRL_BASE_ADDR      (AIPS2_BASE_ADDR + 0x000C0000)
+#define AUDMUX_BASE_ADDR        (AIPS2_BASE_ADDR + 0x000C4000)
+#define MPEG4_ENC_BASE_ADDR     (AIPS2_BASE_ADDR + 0x000C8000)
+#define GPIO1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000CC000)
+#define GPIO2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x000D0000)
+#define SDMA_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000D4000)
+#define RTC_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000D8000)
+#define WDOG_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000DC000)
+#define PWM_BASE_ADDR           (AIPS2_BASE_ADDR + 0x000E0000)
+#define RTIC_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000EC000)
+/*
+ * ROMP and AVIC
+ */
+#define ROMP_BASE_ADDR          0x60000000
+#define ROMP_BASE_ADDR_VIRT     0xFC500000
+#define ROMP_SIZE               SZ_1M
+#define AVIC_BASE_ADDR          0x68000000
+#define AVIC_BASE_ADDR_VIRT     0xFC400000
+#define AVIC_SIZE               SZ_1M
+/*
+ * NAND, SDRAM, WEIM, M3IF, EMI controllers
+ */
+#define X_MEMC_BASE_ADDR        0xB8000000
+#define X_MEMC_BASE_ADDR_VIRT   0xFC320000
+#define X_MEMC_SIZE             SZ_64K
+#define NFC_BASE_ADDR           (X_MEMC_BASE_ADDR + 0x0000)
+#define ESDCTL_BASE_ADDR        (X_MEMC_BASE_ADDR + 0x1000)
+#define WEIM_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x2000)
+#define M3IF_BASE_ADDR          (X_MEMC_BASE_ADDR + 0x3000)
+#define EMI_CTL_BASE_ADDR       (X_MEMC_BASE_ADDR + 0x4000)
+#define PCMCIA_CTL_BASE_ADDR    EMI_CTL_BASE_ADDR
+/*
+ * Memory regions and CS
+ */
+#define IPU_MEM_BASE_ADDR       0x70000000
+#define CSD0_BASE_ADDR          0x80000000
+#define CSD1_BASE_ADDR          0x90000000
+#define CS0_BASE_ADDR           0xA0000000
+#define CS1_BASE_ADDR           0xA8000000
+#define CS2_BASE_ADDR           0xB0000000
+#define CS3_BASE_ADDR           0xB2000000
+#define CS4_BASE_ADDR           0xB4000000
+#define CS4_BASE_ADDR_VIRT      0xF4000000
+#define CS4_SIZE                SZ_32M
+#define CS5_BASE_ADDR           0xB6000000
+#define PCMCIA_MEM_BASE_ADDR    0xBC000000
+/*!
+ * This macro defines the physical to virtual address mapping for all the
+ * peripheral modules. It is used by passing in the physical address as x
+ * and returning the virtual address. If the physical address is not mapped,
+ * it returns 0xDEADBEEF
+ */
+#define IO_ADDRESS(x)   \
+        (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\
+        ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\
+        ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
+        ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
+        ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
+        ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
+        ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
+        ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
+        ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
+        0xDEADBEEF)
+/*
+ * define the address mapping macros: in physical address order
+ */
+#define IRAM_IO_ADDRESS(x)  \
+        (((x) - IRAM_BASE_ADDR) + IRAM_BASE_ADDR_VIRT)
+#define L2CC_IO_ADDRESS(x)  \
+        (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
+#define AIPS1_IO_ADDRESS(x)  \
+        (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
+#define SPBA0_IO_ADDRESS(x)  \
+        (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
+#define AIPS2_IO_ADDRESS(x)  \
+        (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
+#define ROMP_IO_ADDRESS(x)  \
+        (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
+#define AVIC_IO_ADDRESS(x)  \
+        (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
+#define CS4_IO_ADDRESS(x)  \
+        (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
+#define X_MEMC_IO_ADDRESS(x)  \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+#define PCMCIA_IO_ADDRESS(x) \
+        (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
+/* Start of physical RAM - On many MX31 platforms, this is the first SDRAM bank (CSD0) */
+#define PHYS_OFFSET             CSD0_BASE_ADDR
+/*
+ * Interrupt numbers
+ */
+#define MXC_INT_PEN_ADS7843     0
+#define MXC_INT_RESV1           1
+#define MXC_INT_CS8900A         2
+#define MXC_INT_I2C3            3
+#define MXC_INT_I2C2            4
+#define MXC_INT_MPEG4_ENCODER   5
+#define MXC_INT_RTIC            6
+#define MXC_INT_FIRI            7
+#define MXC_INT_MMC_SDHC2       8
+#define MXC_INT_MMC_SDHC1       9
+#define MXC_INT_I2C             10
+#define MXC_INT_SSI2            11
+#define MXC_INT_SSI1            12
+#define MXC_INT_CSPI2           13
+#define MXC_INT_CSPI1           14
+#define MXC_INT_ATA             15
+#define MXC_INT_MBX             16
+#define MXC_INT_CSPI3           17
+#define MXC_INT_UART3           18
+#define MXC_INT_IIM             19
+#define MXC_INT_SIM2            20
+#define MXC_INT_SIM1            21
+#define MXC_INT_RNGA            22
+#define MXC_INT_EVTMON          23
+#define MXC_INT_KPP             24
+#define MXC_INT_RTC             25
+#define MXC_INT_PWM             26
+#define MXC_INT_EPIT2           27
+#define MXC_INT_EPIT1           28
+#define MXC_INT_GPT             29
+#define MXC_INT_RESV30          30
+#define MXC_INT_RESV31          31
+#define MXC_INT_UART2           32
+#define MXC_INT_NANDFC          33
+#define MXC_INT_SDMA            34
+#define MXC_INT_USB1            35
+#define MXC_INT_USB2            36
+#define MXC_INT_USB3            37
+#define MXC_INT_USB4            38
+#define MXC_INT_MSHC1           39
+#define MXC_INT_MSHC2           40
+#define MXC_INT_IPU_ERR         41
+#define MXC_INT_IPU_SYN         42
+#define MXC_INT_RESV43          43
+#define MXC_INT_RESV44          44
+#define MXC_INT_UART1           45
+#define MXC_INT_UART4           46
+#define MXC_INT_UART5           47
+#define MXC_INT_ECT             48
+#define MXC_INT_SCC_SCM         49
+#define MXC_INT_SCC_SMN         50
+#define MXC_INT_GPIO2           51
+#define MXC_INT_GPIO1           52
+#define MXC_INT_CCM             53
+#define MXC_INT_PCMCIA          54
+#define MXC_INT_WDOG            55
+#define MXC_INT_GPIO3           56
+#define MXC_INT_RESV57          57
+#define MXC_INT_EXT_POWER       58
+#define MXC_INT_EXT_TEMPER      59
+#define MXC_INT_EXT_SENSOR60    60
+#define MXC_INT_EXT_SENSOR61    61
+#define MXC_INT_EXT_WDOG        62
+#define MXC_INT_EXT_TV          63
+#define MXC_MAX_INT_LINES       64
+#define MXC_GPIO_INT_BASE       MXC_MAX_INT_LINES
+/*!
+ * Number of GPIO port as defined in the IC Spec
+ */
+#define GPIO_PORT_NUM           3
+/*!
+ * Number of GPIO pins per port
+ */
+#define GPIO_NUM_PIN            32
+#define PROD_SIGNATURE          0x1     /* For MX31 */
+#define SYSTEM_REV_MIN          CHIP_REV_1_0
+#define SYSTEM_REV_NUM          3
+#endif                  /*  __ASM_ARCH_MXC_MX31_H__ */
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
new file mode 100644
index 000000000000..0837f1f9ca31
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __ASM_ARCH_MXC_H__
+#define __ASM_ARCH_MXC_H__
+#ifndef __ASM_ARCH_MXC_HARDWARE_H__
+#error "Do not include directly."
+#endif
+/*
+ *****************************************
+ * GPT  Register definitions             *
+ *****************************************
+ */
+#define MXC_GPT_GPTCR           IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
+#define MXC_GPT_GPTPR           IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
+#define MXC_GPT_GPTSR           IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
+#define MXC_GPT_GPTIR           IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
+#define MXC_GPT_GPTOCR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
+#define MXC_GPT_GPTOCR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
+#define MXC_GPT_GPTOCR3         IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
+#define MXC_GPT_GPTICR1         IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
+#define MXC_GPT_GPTICR2         IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
+#define MXC_GPT_GPTCNT          IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
+/*!
+ * GPT Control register bit definitions
+ */
+#define GPTCR_FO3                       (1 << 31)
+#define GPTCR_FO2                       (1 << 30)
+#define GPTCR_FO1                       (1 << 29)
+#define GPTCR_OM3_SHIFT                 26
+#define GPTCR_OM3_MASK                  (7 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_DISCONNECTED          (0 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_TOGGLE                (1 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_CLEAR                 (2 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_SET                   (3 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM3_GENERATE_LOW          (7 << GPTCR_OM3_SHIFT)
+#define GPTCR_OM2_SHIFT                 23
+#define GPTCR_OM2_MASK                  (7 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_DISCONNECTED          (0 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_TOGGLE                (1 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_CLEAR                 (2 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_SET                   (3 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM2_GENERATE_LOW          (7 << GPTCR_OM2_SHIFT)
+#define GPTCR_OM1_SHIFT                 20
+#define GPTCR_OM1_MASK                  (7 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_DISCONNECTED          (0 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_TOGGLE                (1 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_CLEAR                 (2 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_SET                   (3 << GPTCR_OM1_SHIFT)
+#define GPTCR_OM1_GENERATE_LOW          (7 << GPTCR_OM1_SHIFT)
+#define GPTCR_IM2_SHIFT                 18
+#define GPTCR_IM2_MASK                  (3 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_DISABLE       (0 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_RISING        (1 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_FALLING       (2 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM2_CAPTURE_BOTH          (3 << GPTCR_IM2_SHIFT)
+#define GPTCR_IM1_SHIFT                 16
+#define GPTCR_IM1_MASK                  (3 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_DISABLE       (0 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_RISING        (1 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_FALLING       (2 << GPTCR_IM1_SHIFT)
+#define GPTCR_IM1_CAPTURE_BOTH          (3 << GPTCR_IM1_SHIFT)
+#define GPTCR_SWR                       (1 << 15)
+#define GPTCR_FRR                       (1 << 9)
+#define GPTCR_CLKSRC_SHIFT              6
+#define GPTCR_CLKSRC_MASK               (7 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_NOCLOCK            (0 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_HIGHFREQ           (2 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLKIN              (3 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_CLKSRC_CLK32K             (7 << GPTCR_CLKSRC_SHIFT)
+#define GPTCR_STOPEN                    (1 << 5)
+#define GPTCR_DOZEN                     (1 << 4)
+#define GPTCR_WAITEN                    (1 << 3)
+#define GPTCR_DBGEN                     (1 << 2)
+#define GPTCR_ENMOD                     (1 << 1)
+#define GPTCR_ENABLE                    (1 << 0)
+#define GPTSR_OF1                       (1 << 0)
+#define GPTSR_OF2                       (1 << 1)
+#define GPTSR_OF3                       (1 << 2)
+#define GPTSR_IF1                       (1 << 3)
+#define GPTSR_IF2                       (1 << 4)
+#define GPTSR_ROV                       (1 << 5)
+#define GPTIR_OF1IE                     GPTSR_OF1
+#define GPTIR_OF2IE                     GPTSR_OF2
+#define GPTIR_OF3IE                     GPTSR_OF3
+#define GPTIR_IF1IE                     GPTSR_IF1
+#define GPTIR_IF2IE                     GPTSR_IF2
+#define GPTIR_ROVIE                     GPTSR_ROV
+/*
+ *****************************************
+ * AVIC Registers                        *
+ *****************************************
+ */
+#define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
+#define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
+#define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
+#define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
+#define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
+#define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
+#define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
+#define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
+#define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
+#define AVIC_NIPRIORITY7        (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
+#define AVIC_NIPRIORITY6        (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
+#define AVIC_NIPRIORITY5        (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
+#define AVIC_NIPRIORITY4        (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
+#define AVIC_NIPRIORITY3        (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
+#define AVIC_NIPRIORITY2        (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
+#define AVIC_NIPRIORITY1        (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
+#define AVIC_NIPRIORITY0        (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
+#define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
+#define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
+#define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
+#define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
+#define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
+#define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
+#define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
+#define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
+#define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
+#define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
+#define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
+#define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
+#define IIM_PROD_REV_SH         3
+#define IIM_PROD_REV_LEN        5
+#endif                          /*  __ASM_ARCH_MXC_H__ */
diff --git a/include/asm-arm/arch-mxc/system.h b/include/asm-arm/arch-mxc/system.h
new file mode 100644
index 000000000000..109956b41aca
--- /dev/null
+++ b/include/asm-arm/arch-mxc/system.h
@@ -0,0 +1,50 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_SYSTEM_H__
+#define __ASM_ARCH_MXC_SYSTEM_H__
+/*!
+ * @file system.h
+ * @brief This file contains idle and reset functions.
+ *
+ * @ingroup System
+ */
+/*!
+ * This function puts the CPU into idle mode. It is called by default_idle()
+ * in process.c file.
+ */
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+/*
+ * This function resets the system. It is called by machine_restart().
+ *
+ * @param  mode         indicates different kinds of resets
+ */
+static inline void arch_reset(char mode)
+{
+        cpu_reset(0);
+}
+#endif                          /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/include/asm-arm/arch-mxc/timex.h b/include/asm-arm/arch-mxc/timex.h
new file mode 100644
index 000000000000..59019fa58f82
--- /dev/null
+++ b/include/asm-arm/arch-mxc/timex.h
@@ -0,0 +1,25 @@
+/*
+ *  Copyright (C) 1999 ARM Limited
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_TIMEX_H__
+#define __ASM_ARCH_MXC_TIMEX_H__
+#include <asm/hardware.h>       /* for CLOCK_TICK_RATE */
+#endif                          /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/include/asm-arm/arch-mxc/uncompress.h b/include/asm-arm/arch-mxc/uncompress.h
new file mode 100644
index 000000000000..ec5787d0e78c
--- /dev/null
+++ b/include/asm-arm/arch-mxc/uncompress.h
@@ -0,0 +1,79 @@
+/*
+ *  include/asm-arm/arch-mxc/uncompress.h
+ *
+ *
+ *
+ *  Copyright (C) 1999 ARM Limited
+ *  Copyright (C) Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_UNCOMPRESS_H__
+#define __ASM_ARCH_MXC_UNCOMPRESS_H__
+#define __MXC_BOOT_UNCOMPRESS
+#include <asm/hardware.h>
+#include <asm/processor.h>
+#define UART(x) (*(volatile unsigned long *)(serial_port + (x)))
+#define USR2 0x98
+#define USR2_TXFE (1<<14)
+#define TXR  0x40
+#define UCR1 0x80
+#define UCR1_UARTEN 1
+/*
+ * The following code assumes the serial port has already been
+ * initialized by the bootloader.  We search for the first enabled
+ * port in the most probable order.  If you didn't setup a port in
+ * your bootloader then nothing will appear (which might be desired).
+ *
+ * This does not append a newline
+ */
+static void putc(int ch)
+{
+        static unsigned long serial_port = 0;
+        if (unlikely(serial_port == 0)) {
+                do {
+                        serial_port = UART1_BASE_ADDR;
+                        if (UART(UCR1) & UCR1_UARTEN)
+                                break;
+                        serial_port = UART2_BASE_ADDR;
+                        if (UART(UCR1) & UCR1_UARTEN)
+                                break;
+                        return;
+                } while (0);
+        }
+        while (!(UART(USR2) & USR2_TXFE))
+                cpu_relax();
+        UART(TXR) = ch;
+}
+#define flush() do { } while (0)
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
+#endif                          /* __ASM_ARCH_MXC_UNCOMPRESS_H__ */
diff --git a/include/asm-arm/arch-mxc/vmalloc.h b/include/asm-arm/arch-mxc/vmalloc.h
new file mode 100644
index 000000000000..83a73da895eb
--- /dev/null
+++ b/include/asm-arm/arch-mxc/vmalloc.h
@@ -0,0 +1,36 @@
+/*
+ *  Copyright (C) 2000 Russell King.
+ *  Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __ASM_ARCH_MXC_VMALLOC_H__
+#define __ASM_ARCH_MXC_VMALLOC_H__
+/*!
+ * @file vmalloc.h
+ *
+ * @brief This file contains platform specific macros for vmalloc.
+ *
+ * @ingroup System
+ */
+/*!
+ * vmalloc ending address
+ */
+#define VMALLOC_END       0xF4000000
+#endif                          /* __ASM_ARCH_MXC_VMALLOC_H__ */
diff --git a/include/asm-arm/arch-ns9xxx/regs-bbu.h b/include/asm-arm/arch-ns9xxx/regs-bbu.h
index e26269546240..7ee194dc6354 100644
--- a/include/asm-arm/arch-ns9xxx/regs-bbu.h
+++ b/include/asm-arm/arch-ns9xxx/regs-bbu.h
@@ -15,7 +15,31 @@
 /* BBus Utility */
-/* GPIO Configuration Register */
+/* GPIO Configuration Registers block 1 */
-#define BBU_GC(x)       __REG2(0x9060000c, (x))
+/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
+ * at 0 for each block.  That is, BBU_GCONFb1(0) is GPIO Configuration Register
+ * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
+#define BBU_GCONFb1(x)  __REG2(0x90600010, (x))
+#define BBU_GCONFb2(x)  __REG2(0x90600100, (x))
+#define BBU_GCONFx_DIR(m)       __REGBIT(3 + (((m) & 7) << 2))
+#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
+#define BBU_GCONFx_DIR_OUTPUT(m)        __REGVAL(BBU_GCONFx_DIR(m), 1)
+#define BBU_GCONFx_INV(m)       __REGBIT(2 + (((m) & 7) << 2))
+#define BBU_GCONFx_INV_NO(m)            __REGVAL(BBU_GCONFx_INV(m), 0)
+#define BBU_GCONFx_INV_YES(m)           __REGVAL(BBU_GCONFx_INV(m), 1)
+#define BBU_GCONFx_FUNC(m)      __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
+#define BBU_GCONFx_FUNC_0(m)            __REGVAL(BBU_GCONFx_FUNC(m), 0)
+#define BBU_GCONFx_FUNC_1(m)            __REGVAL(BBU_GCONFx_FUNC(m), 1)
+#define BBU_GCONFx_FUNC_2(m)            __REGVAL(BBU_GCONFx_FUNC(m), 2)
+#define BBU_GCONFx_FUNC_3(m)            __REGVAL(BBU_GCONFx_FUNC(m), 3)
+#define BBU_GCTRL1      __REG(0x90600030)
+#define BBU_GCTRL2      __REG(0x90600034)
+#define BBU_GCTRL3      __REG(0x90600120)
+#define BBU_GSTAT1      __REG(0x90600040)
+#define BBU_GSTAT2      __REG(0x90600044)
+#define BBU_GSTAT3      __REG(0x90600130)
 #endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-mem.h b/include/asm-arm/arch-ns9xxx/regs-mem.h
index 8ed8448767b9..fb455a0ed845 100644
--- a/include/asm-arm/arch-ns9xxx/regs-mem.h
+++ b/include/asm-arm/arch-ns9xxx/regs-mem.h
@@ -79,9 +79,9 @@
 #define MEM_SMC(x)      __REG2(0xa0700200, (x) << 3)
 /* Static Memory Configuration Register x: Write protect */
-#define MEM_SMC_WSMC            __REGBIT(20)
+#define MEM_SMC_PSMC            __REGBIT(20)
-#define MEM_SMC_WSMC_OFF                __REGVAL(MEM_SMC_WSMC, 0)
+#define MEM_SMC_PSMC_OFF                __REGVAL(MEM_SMC_PSMC, 0)
-#define MEM_SMC_WSMC_ON                 __REGVAL(MEM_SMC_WSMC, 1)
+#define MEM_SMC_PSMC_ON                 __REGVAL(MEM_SMC_PSMC, 1)
 /* Static Memory Configuration Register x: Buffer enable */
 #define MEM_SMC_BSMC            __REGBIT(19)
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys.h
index a42546aeb92a..749262f86204 100644
--- a/include/asm-arm/arch-ns9xxx/regs-sys.h
+++ b/include/asm-arm/arch-ns9xxx/regs-sys.h
@@ -64,7 +64,7 @@
 /* Timer x Control register: Timer enable */
 #define SYS_TCx_TEN             __REGBIT(15)
-#define SYS_TCx_TEN_DIS                 __REGVAL(SYS_TCx_TEN, 1)
+#define SYS_TCx_TEN_DIS                 __REGVAL(SYS_TCx_TEN, 0)
 #define SYS_TCx_TEN_EN                  __REGVAL(SYS_TCx_TEN, 1)
 /* Timer x Control register: CPU debug mode */
diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h
index bed042d71d68..3280ee2ddfa5 100644
--- a/include/asm-arm/arch-pxa/dma.h
+++ b/include/asm-arm/arch-pxa/dma.h
@@ -30,30 +30,12 @@ typedef enum {
        DMA_PRIO_LOW = 2
 } pxa_dma_prio;
-#if defined(CONFIG_PXA27x)
-#define PXA_DMA_CHANNELS        32
-#define pxa_for_each_dma_prio(ch, prio)                                 \
-for (                                                                   \
-        ch = prio * 4;                                                  \
-        ch != (4 << prio) + 16;                                         \
-        ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1)       \
-)
-#elif defined(CONFIG_PXA25x)
-#define PXA_DMA_CHANNELS        16
-#define pxa_for_each_dma_prio(ch, prio)                                 \
-        for (ch = prio * 4; ch != (4 << prio); ch++)
-#endif
 /*
 * DMA registration
 */
+int __init pxa_init_dma(int num_ch);
 int pxa_request_dma (char *name,
                         pxa_dma_prio prio,
                         void (*irq_handler)(int, void *),
diff --git a/include/asm-arm/arch-pxa/entry-macro.S b/include/asm-arm/arch-pxa/entry-macro.S
index 1d5fbb9b379a..b7e730851461 100644
--- a/include/asm-arm/arch-pxa/entry-macro.S
+++ b/include/asm-arm/arch-pxa/entry-macro.S
@@ -20,20 +20,38 @@
                .endm
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-#ifdef CONFIG_PXA27x
+                mrc     p15, 0, \tmp, c0, c0, 0         @ CPUID
-                mrc     p6, 0, \irqstat, c0, c0, 0              @ ICIP
+                mov     \tmp, \tmp, lsr #13
-                mrc     p6, 0, \irqnr, c1, c0, 0                @ ICMR
+                and     \tmp, \tmp, #0x7                @ Core G
-#else
+                cmp     \tmp, #1
+                bhi     1004f
                mov     \base, #io_p2v(0x40000000)      @ IIR Ctl = 0x40d00000
                add     \base, \base, #0x00d00000
                ldr     \irqstat, [\base, #0]           @ ICIP
                ldr     \irqnr, [\base, #4]             @ ICMR
-#endif
+                b       1002f
+1004:
+                mrc     p6, 0, \irqstat, c6, c0, 0      @ ICIP2
+                mrc     p6, 0, \irqnr, c7, c0, 0        @ ICMR2
+                ands    \irqstat, \irqstat, \irqnr
+                beq     1003f
+                rsb     \irqstat, \irqnr, #0
+                and     \irqstat, \irqstat, \irqnr
+                clz     \irqnr, \irqstat
+                rsb     \irqnr, \irqnr, #31
+                add     \irqnr, \irqnr, #32
+                b       1001f
+1003:
+                mrc     p6, 0, \irqstat, c0, c0, 0      @ ICIP
+                mrc     p6, 0, \irqnr, c1, c0, 0        @ ICMR
+1002:
                ands    \irqnr, \irqstat, \irqnr
                beq     1001f
                rsb     \irqstat, \irqnr, #0
                and     \irqstat, \irqstat, \irqnr
                clz     \irqnr, \irqstat
-                rsb     \irqnr, \irqnr, #(31 - PXA_IRQ_SKIP)
+                rsb     \irqnr, \irqnr, #31
 1001:
                .endm
diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h
index e2bdc2fbede1..386121746417 100644
--- a/include/asm-arm/arch-pxa/hardware.h
+++ b/include/asm-arm/arch-pxa/hardware.h
@@ -62,6 +62,42 @@
 #ifndef __ASSEMBLY__
+#define __cpu_is_pxa21x(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xf3f;   \
+                _id == 0x212;                           \
+        })
+#define __cpu_is_pxa25x(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x2d0 || _id == 0x290;           \
+        })
+#define __cpu_is_pxa27x(id)                             \
+        ({                                              \
+                unsigned int _id = (id) >> 4 & 0xfff;   \
+                _id == 0x411;                           \
+        })
+#define cpu_is_pxa21x()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa21x(id);                    \
+        })
+#define cpu_is_pxa25x()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa25x(id);                    \
+        })
+#define cpu_is_pxa27x()                                 \
+        ({                                              \
+                unsigned int id = read_cpuid(CPUID_ID); \
+                __cpu_is_pxa27x(id);                    \
+        })
 /*
 * Handy routine to set GPIO alternate functions
 */
diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index 67ed43674c63..a07fe0f928cd 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -11,14 +11,9 @@
 */
-#ifdef CONFIG_PXA27x
+#define PXA_IRQ(x)      (x)
-#define PXA_IRQ_SKIP    0
-#else
-#define PXA_IRQ_SKIP    7
-#endif
-#define PXA_IRQ(x)      ((x) - PXA_IRQ_SKIP)
+#ifdef CONFIG_PXA27x
 #define IRQ_SSP3        PXA_IRQ(0)      /* SSP3 service request */
 #define IRQ_MSL         PXA_IRQ(1)      /* MSL Interface interrupt */
 #define IRQ_USBH2       PXA_IRQ(2)      /* USB Host interrupt 1 (OHCI) */
@@ -26,6 +21,8 @@
 #define IRQ_KEYPAD      PXA_IRQ(4)      /* Key pad controller */
 #define IRQ_MEMSTK      PXA_IRQ(5)      /* Memory Stick interrupt */
 #define IRQ_PWRI2C      PXA_IRQ(6)      /* Power I2C interrupt */
+#endif
 #define IRQ_HWUART      PXA_IRQ(7)      /* HWUART Transmit/Receive/Error (PXA26x) */
 #define IRQ_OST_4_11    PXA_IRQ(7)      /* OS timer 4-11 matches (PXA27x) */
 #define IRQ_GPIO0       PXA_IRQ(8)      /* GPIO0 Edge Detect */
@@ -58,18 +55,15 @@
 #ifdef CONFIG_PXA27x
 #define IRQ_TPM         PXA_IRQ(32)     /* TPM interrupt */
 #define IRQ_CAMERA      PXA_IRQ(33)     /* Camera Interface */
-#define PXA_INTERNAL_IRQS 34
-#else
-#define PXA_INTERNAL_IRQS 32
 #endif
-#define GPIO_2_x_TO_IRQ(x)      \
+#define PXA_GPIO_IRQ_BASE       (64)
-                        PXA_IRQ((x) - 2 + PXA_INTERNAL_IRQS)
+#define PXA_GPIO_IRQ_NUM        (128)
+#define GPIO_2_x_TO_IRQ(x)      (PXA_GPIO_IRQ_BASE + (x))
 #define IRQ_GPIO(x)     (((x) < 2) ? (IRQ_GPIO0 + (x)) : GPIO_2_x_TO_IRQ(x))
-#define IRQ_TO_GPIO_2_x(i)      \
+#define IRQ_TO_GPIO_2_x(i)      ((i) - PXA_GPIO_IRQ_BASE)
-                        ((i) - IRQ_GPIO(2) + 2)
 #define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
 #if defined(CONFIG_PXA25x)
@@ -84,7 +78,7 @@
 * these.  If you need more, increase IRQ_BOARD_END, but keep it
 * within sensible limits.
 */
-#define IRQ_BOARD_START         (IRQ_GPIO(PXA_LAST_GPIO) + 1)
+#define IRQ_BOARD_START         (PXA_GPIO_IRQ_BASE + PXA_GPIO_IRQ_NUM)
 #define IRQ_BOARD_END           (IRQ_BOARD_START + 16)
 #define IRQ_SA1111_START        (IRQ_BOARD_END)
diff --git a/include/asm-arm/arch-pxa/pm.h b/include/asm-arm/arch-pxa/pm.h
index 7a8a1cdf430d..6903db7fae15 100644
--- a/include/asm-arm/arch-pxa/pm.h
+++ b/include/asm-arm/arch-pxa/pm.h
@@ -7,6 +7,19 @@
 *
 */
-extern int pxa_pm_prepare(suspend_state_t state);
+struct pxa_cpu_pm_fns {
+        int     save_size;
+        void    (*save)(unsigned long *);
+        void    (*restore)(unsigned long *);
+        int     (*valid)(suspend_state_t state);
+        void    (*enter)(suspend_state_t state);
+};
+extern struct pxa_cpu_pm_fns *pxa_cpu_pm_fns;
+/* sleep.S */
+extern void pxa25x_cpu_suspend(unsigned int);
+extern void pxa27x_cpu_suspend(unsigned int);
+extern void pxa_cpu_resume(void);
 extern int pxa_pm_enter(suspend_state_t state);
-extern int pxa_pm_finish(suspend_state_t state);
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index dbcc9298b0c8..e68b593d69da 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1765,29 +1765,9 @@
 #define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
 /*
- * MultiMediaCard (MMC) controller
+ * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h
 */
-#define MMC_STRPCL      __REG(0x41100000)  /* Control to start and stop MMC clock */
-#define MMC_STAT        __REG(0x41100004)  /* MMC Status Register (read only) */
-#define MMC_CLKRT       __REG(0x41100008)  /* MMC clock rate */
-#define MMC_SPI         __REG(0x4110000c)  /* SPI mode control bits */
-#define MMC_CMDAT       __REG(0x41100010)  /* Command/response/data sequence control */
-#define MMC_RESTO       __REG(0x41100014)  /* Expected response time out */
-#define MMC_RDTO        __REG(0x41100018)  /* Expected data read time out */
-#define MMC_BLKLEN      __REG(0x4110001c)  /* Block length of data transaction */
-#define MMC_NOB         __REG(0x41100020)  /* Number of blocks, for block mode */
-#define MMC_PRTBUF      __REG(0x41100024)  /* Partial MMC_TXFIFO FIFO written */
-#define MMC_I_MASK      __REG(0x41100028)  /* Interrupt Mask */
-#define MMC_I_REG       __REG(0x4110002c)  /* Interrupt Register (read only) */
-#define MMC_CMD         __REG(0x41100030)  /* Index of current command */
-#define MMC_ARGH        __REG(0x41100034)  /* MSW part of the current command argument */
-#define MMC_ARGL        __REG(0x41100038)  /* LSW part of the current command argument */
-#define MMC_RES         __REG(0x4110003c)  /* Response FIFO (read only) */
-#define MMC_RXFIFO      __REG(0x41100040)  /* Receive FIFO (read only) */
-#define MMC_TXFIFO      __REG(0x41100044)  /* Transmit FIFO (write only) */
 /*
 * Core Clock
 */
diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h
index 8bc6f9c3e3ea..27aa3a91012f 100644
--- a/include/asm-arm/arch-pxa/udc.h
+++ b/include/asm-arm/arch-pxa/udc.h
@@ -1,41 +1,8 @@
 /*
 * linux/include/asm-arm/arch-pxa/udc.h
 *
- * This supports machine-specific differences in how the PXA2xx
- * USB Device Controller (UDC) is wired.
- *
 */
 #include <asm/mach/udc_pxa2xx.h>
 extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);
-static inline int udc_gpio_to_irq(unsigned gpio)
-{
-        return IRQ_GPIO(gpio & GPIO_MD_MASK_NR);
-}
-static inline void udc_gpio_init_vbus(unsigned gpio)
-{
-        pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_IN);
-}
-static inline void udc_gpio_init_pullup(unsigned gpio)
-{
-        pxa_gpio_mode((gpio & GPIO_MD_MASK_NR) | GPIO_OUT | GPIO_DFLT_LOW);
-}
-static inline int udc_gpio_get(unsigned gpio)
-{
-        return (GPLR(gpio) & GPIO_bit(gpio)) != 0;
-}
-static inline void udc_gpio_set(unsigned gpio, int is_on)
-{
-        int mask = GPIO_bit(gpio);
-        if (is_on)
-                GPSR(gpio) = mask;
-        else
-                GPCR(gpio) = mask;
-}
diff --git a/include/asm-arm/arch-s3c2400/map.h b/include/asm-arm/arch-s3c2400/map.h
new file mode 100644
index 000000000000..1184d907b31e
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/map.h
@@ -0,0 +1,66 @@
+/* linux/include/asm-arm/arch-s3c2400/map.h
+ *
+ * Copyright 2003,2007  Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * Copyright 2003, Lucas Correia Villa Real
+ *
+ * S3C2400 - Memory map definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#define S3C2400_PA_MEMCTRL      (0x14000000)
+#define S3C2400_PA_USBHOST      (0x14200000)
+#define S3C2400_PA_IRQ          (0x14400000)
+#define S3C2400_PA_DMA          (0x14600000)
+#define S3C2400_PA_CLKPWR       (0x14800000)
+#define S3C2400_PA_LCD          (0x14A00000)
+#define S3C2400_PA_UART         (0x15000000)
+#define S3C2400_PA_TIMER        (0x15100000)
+#define S3C2400_PA_USBDEV       (0x15200140)
+#define S3C2400_PA_WATCHDOG     (0x15300000)
+#define S3C2400_PA_IIC          (0x15400000)
+#define S3C2400_PA_IIS          (0x15508000)
+#define S3C2400_PA_GPIO         (0x15600000)
+#define S3C2400_PA_RTC          (0x15700040)
+#define S3C2400_PA_ADC          (0x15800000)
+#define S3C2400_PA_SPI          (0x15900000)
+#define S3C2400_PA_MMC          (0x15A00000)
+#define S3C2400_SZ_MMC          SZ_1M
+/* physical addresses of all the chip-select areas */
+#define S3C2400_CS0     (0x00000000)
+#define S3C2400_CS1     (0x02000000)
+#define S3C2400_CS2     (0x04000000)
+#define S3C2400_CS3     (0x06000000)
+#define S3C2400_CS4     (0x08000000)
+#define S3C2400_CS5     (0x0A000000)
+#define S3C2400_CS6     (0x0C000000)
+#define S3C2400_CS7     (0x0E000000)
+#define S3C2400_SDRAM_PA    (S3C2400_CS6)
+/* Use a single interface for common resources between S3C24XX cpus */
+#define S3C24XX_PA_IRQ          S3C2400_PA_IRQ
+#define S3C24XX_PA_MEMCTRL      S3C2400_PA_MEMCTRL
+#define S3C24XX_PA_USBHOST      S3C2400_PA_USBHOST
+#define S3C24XX_PA_DMA          S3C2400_PA_DMA
+#define S3C24XX_PA_CLKPWR       S3C2400_PA_CLKPWR
+#define S3C24XX_PA_LCD          S3C2400_PA_LCD
+#define S3C24XX_PA_UART         S3C2400_PA_UART
+#define S3C24XX_PA_TIMER        S3C2400_PA_TIMER
+#define S3C24XX_PA_USBDEV       S3C2400_PA_USBDEV
+#define S3C24XX_PA_WATCHDOG     S3C2400_PA_WATCHDOG
+#define S3C24XX_PA_IIC          S3C2400_PA_IIC
+#define S3C24XX_PA_IIS          S3C2400_PA_IIS
+#define S3C24XX_PA_GPIO         S3C2400_PA_GPIO
+#define S3C24XX_PA_RTC          S3C2400_PA_RTC
+#define S3C24XX_PA_ADC          S3C2400_PA_ADC
+#define S3C24XX_PA_SPI          S3C2400_PA_SPI
diff --git a/include/asm-arm/arch-s3c2400/memory.h b/include/asm-arm/arch-s3c2400/memory.h
new file mode 100644
index 000000000000..fb0381dde704
--- /dev/null
+++ b/include/asm-arm/arch-s3c2400/memory.h
@@ -0,0 +1,23 @@
+/* linux/include/asm-arm/arch-s3c2400/memory.h
+ *  from linux/include/asm-arm/arch-rpc/memory.h
+ *
+ *  Copyright 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+#define PHYS_OFFSET     UL(0x0C000000)
+#define __virt_to_bus(x) __virt_to_phys(x)
+#define __bus_to_virt(x) __phys_to_virt(x)
+#endif
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 93064860e0e5..9c8cd9abb82b 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -13,32 +13,23 @@
 */
 #include <asm/arch/map.h>
-#include <asm/arch/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
+#include <asm/plat-s3c/regs-serial.h>
 #define S3C2410_UART1_OFF (0x4000)
 #define SHIFT_2440TXF (14-9)
-                .macro addruart, rx
+        .macro addruart, rx
                mrc     p15, 0, \rx, c1, c0
                tst     \rx, #1
                ldreq   \rx, = S3C24XX_PA_UART
                ldrne   \rx, = S3C24XX_VA_UART
-#if CONFIG_DEBUG_S3C2410_UART != 0
+#if CONFIG_DEBUG_S3C_UART != 0
-                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART)
+                add     \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
 #endif
-                .endm
+        .endm
-                .macro  senduart,rd,rx
+        .macro fifo_full_s3c24xx rd, rx
-                strb    \rd, [\rx, # S3C2410_UTXH ]
-                .endm
-                .macro  busyuart, rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
-                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
-                beq     1001f                           @
-                @ FIFO enabled...
-1003:
                @ check for arm920 vs arm926. currently assume all arm926
                @ devices have an 64 byte FIFO identical to the s3c2440
                mrc     p15, 0, \rd, c0, c0
@@ -57,25 +48,22 @@
                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
                moveq   \rd, \rd, lsr #SHIFT_2440TXF
                tst     \rd, #S3C2410_UFSTAT_TXFULL
-                bne     1003b
+        .endm
-                b       1002f
-1001:
-                @ busy waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
-                tst     \rd, #S3C2410_UTRSTAT_TXFE
-                beq     1001b
-1002:           @ exit busyuart
+        .macro  fifo_full_s3c2410 rd, rx
-                .endm
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S3C2410_UFSTAT_TXFULL
+        .endm
-                .macro  waituart,rd,rx
+/* fifo level reading */
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+        .macro fifo_level_s3c24xx rd, rx
-                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                @ check for arm920 vs arm926. currently assume all arm926
-                beq     1001f                           @
+                @ devices have an 64 byte FIFO identical to the s3c2440
-                @ FIFO enabled...
+                mrc     p15, 0, \rd, c0, c0
-1003:
+                and     \rd, \rd, #0xff0
+                teq     \rd, #0x260
+                beq     10000f
                mrc     p15, 0, \rd, c1, c0
                tst     \rd, #1
                addeq   \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
@@ -85,18 +73,32 @@
                and     \rd, \rd, #0x00ff0000
                teq     \rd, #0x00440000                @ is it 2440?
+10000:
                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
                andne   \rd, \rd, #S3C2410_UFSTAT_TXMASK
                andeq   \rd, \rd, #S3C2440_UFSTAT_TXMASK
-                teq     \rd, #0
+        .endm
-                bne     1003b
-                b       1002f
+        .macro fifo_level_s3c2410 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S3C2410_UFSTAT_TXMASK
+        .endm
+/* Select the correct implementation depending on the configuration. The
+ * S3C2440 will get selected by default, as these are the most widely
+ * used variants of these
+*/
+#if defined(CONFIG_CPU_LLSERIAL_S3C2410_ONLY)
+#define fifo_full  fifo_full_s3c2410
+#define fifo_level fifo_level_s3c2410
+#warning 2410only
+#elif !defined(CONFIG_CPU_LLSERIAL_S3C2440_ONLY)
+#define fifo_full  fifo_full_s3c24xx
+#define fifo_level fifo_level_s3c24xx
+#warning generic
+#endif
-1001:
+/* include the reset of the code which will do the work */
-                @ idle waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
-                tst     \rd, #S3C2410_UTRSTAT_TXFE
-                beq     1001b
-1002:           @ exit busyuart
+#include <asm/plat-s3c/debug-macro.S>
-                .endm
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index 19e77f038042..b33ed3b05ef5 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -13,58 +13,36 @@
 #ifndef __ASM_ARCH_MAP_H
 #define __ASM_ARCH_MAP_H
-/* we have a bit of a tight squeeze to fit all our registers from
+#include <asm/plat-s3c/map.h>
- * 0xF00000000 upwards, since we use all of the nGCS space in some
- * capacity, and also need to fit the S3C2410 registers in as well...
- *
- * we try to ensure stuff like the IRQ registers are available for
- * an single MOVS instruction (ie, only 8 bits of set data)
- *
- * Note, we are trying to remove some of these from the implementation
- * as they are only useful to certain drivers...
- */
-#ifndef __ASSEMBLY__
-#define S3C2410_ADDR(x)   ((void __iomem __force *)0xF0000000 + (x))
-#else
-#define S3C2410_ADDR(x)   (0xF0000000 + (x))
-#endif
-#define S3C2400_ADDR(x)   S3C2410_ADDR(x)
+#define S3C2410_ADDR(x)         S3C_ADDR(x)
 /* interrupt controller is the first thing we put in, to make
 * the assembly code for the irq detection easier
 */
-#define S3C24XX_VA_IRQ     S3C2410_ADDR(0x00000000)
+#define S3C24XX_VA_IRQ     S3C_VA_IRQ
-#define S3C2400_PA_IRQ     (0x14400000)
 #define S3C2410_PA_IRQ     (0x4A000000)
 #define S3C24XX_SZ_IRQ     SZ_1M
 /* memory controller registers */
-#define S3C24XX_VA_MEMCTRL S3C2410_ADDR(0x00100000)
+#define S3C24XX_VA_MEMCTRL S3C_VA_MEM
-#define S3C2400_PA_MEMCTRL (0x14000000)
 #define S3C2410_PA_MEMCTRL (0x48000000)
 #define S3C24XX_SZ_MEMCTRL SZ_1M
 /* USB host controller */
-#define S3C2400_PA_USBHOST (0x14200000)
 #define S3C2410_PA_USBHOST (0x49000000)
 #define S3C24XX_SZ_USBHOST SZ_1M
 /* DMA controller */
-#define S3C2400_PA_DMA     (0x14600000)
 #define S3C2410_PA_DMA     (0x4B000000)
 #define S3C24XX_SZ_DMA     SZ_1M
 /* Clock and Power management */
-#define S3C24XX_VA_CLKPWR  S3C2410_ADDR(0x00200000)
+#define S3C24XX_VA_CLKPWR  S3C_VA_SYS
-#define S3C2400_PA_CLKPWR  (0x14800000)
 #define S3C2410_PA_CLKPWR  (0x4C000000)
 #define S3C24XX_SZ_CLKPWR  SZ_1M
 /* LCD controller */
-#define S3C24XX_VA_LCD     S3C2410_ADDR(0x00300000)
-#define S3C2400_PA_LCD     (0x14A00000)
 #define S3C2410_PA_LCD     (0x4D000000)
 #define S3C24XX_SZ_LCD     SZ_1M
@@ -72,41 +50,30 @@
 #define S3C2410_PA_NAND    (0x4E000000)
 #define S3C24XX_SZ_NAND    SZ_1M
-/* MMC controller - available on the S3C2400 */
-#define S3C2400_PA_MMC     (0x15A00000)
-#define S3C2400_SZ_MMC     SZ_1M
 /* UARTs */
-#define S3C24XX_VA_UART    S3C2410_ADDR(0x00400000)
+#define S3C24XX_VA_UART    S3C_VA_UART
-#define S3C2400_PA_UART    (0x15000000)
 #define S3C2410_PA_UART    (0x50000000)
 #define S3C24XX_SZ_UART    SZ_1M
 /* Timers */
-#define S3C24XX_VA_TIMER   S3C2410_ADDR(0x00500000)
+#define S3C24XX_VA_TIMER   S3C_VA_TIMER
-#define S3C2400_PA_TIMER   (0x15100000)
 #define S3C2410_PA_TIMER   (0x51000000)
 #define S3C24XX_SZ_TIMER   SZ_1M
 /* USB Device port */
-#define S3C24XX_VA_USBDEV  S3C2410_ADDR(0x00600000)
-#define S3C2400_PA_USBDEV  (0x15200140)
 #define S3C2410_PA_USBDEV  (0x52000000)
 #define S3C24XX_SZ_USBDEV  SZ_1M
 /* Watchdog */
-#define S3C24XX_VA_WATCHDOG S3C2410_ADDR(0x00700000)
+#define S3C24XX_VA_WATCHDOG S3C_VA_WATCHDOG
-#define S3C2400_PA_WATCHDOG (0x15300000)
 #define S3C2410_PA_WATCHDOG (0x53000000)
 #define S3C24XX_SZ_WATCHDOG SZ_1M
 /* IIC hardware controller */
-#define S3C2400_PA_IIC     (0x15400000)
 #define S3C2410_PA_IIC     (0x54000000)
 #define S3C24XX_SZ_IIC     SZ_1M
 /* IIS controller */
-#define S3C2400_PA_IIS     (0x15508000)
 #define S3C2410_PA_IIS     (0x55000000)
 #define S3C24XX_SZ_IIS     SZ_1M
@@ -116,27 +83,23 @@
 * it is the same distance apart from the UART in the
 * phsyical address space, as the initial mapping for the IO
 * is done as a 1:1 maping. This puts it (currently) at
- * 0xF6800000, which is not in the way of any current mapping
+ * 0xFA800000, which is not in the way of any current mapping
 * by the base system.
 */
-#define S3C2400_PA_GPIO    (0x15600000)
 #define S3C2410_PA_GPIO    (0x56000000)
 #define S3C24XX_VA_GPIO    ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
 #define S3C24XX_SZ_GPIO    SZ_1M
 /* RTC */
-#define S3C2400_PA_RTC     (0x15700040)
 #define S3C2410_PA_RTC     (0x57000000)
 #define S3C24XX_SZ_RTC     SZ_1M
 /* ADC */
-#define S3C2400_PA_ADC     (0x15800000)
 #define S3C2410_PA_ADC     (0x58000000)
 #define S3C24XX_SZ_ADC     SZ_1M
 /* SPI */
-#define S3C2400_PA_SPI     (0x15900000)
 #define S3C2410_PA_SPI     (0x59000000)
 #define S3C24XX_SZ_SPI     SZ_1M
@@ -177,37 +140,8 @@
 #define S3C2410_SDRAM_PA    (S3C2410_CS6)
-#define S3C2400_CS0 (0x00000000)
-#define S3C2400_CS1 (0x02000000)
-#define S3C2400_CS2 (0x04000000)
-#define S3C2400_CS3 (0x06000000)
-#define S3C2400_CS4 (0x08000000)
-#define S3C2400_CS5 (0x0A000000)
-#define S3C2400_CS6 (0x0C000000)
-#define S3C2400_CS7 (0x0E000000)
-#define S3C2400_SDRAM_PA    (S3C2400_CS6)
 /* Use a single interface for common resources between S3C24XX cpus */
-#ifdef CONFIG_CPU_S3C2400
-#define S3C24XX_PA_IRQ      S3C2400_PA_IRQ
-#define S3C24XX_PA_MEMCTRL  S3C2400_PA_MEMCTRL
-#define S3C24XX_PA_USBHOST  S3C2400_PA_USBHOST
-#define S3C24XX_PA_DMA      S3C2400_PA_DMA
-#define S3C24XX_PA_CLKPWR   S3C2400_PA_CLKPWR
-#define S3C24XX_PA_LCD      S3C2400_PA_LCD
-#define S3C24XX_PA_UART     S3C2400_PA_UART
-#define S3C24XX_PA_TIMER    S3C2400_PA_TIMER
-#define S3C24XX_PA_USBDEV   S3C2400_PA_USBDEV
-#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
-#define S3C24XX_PA_IIC      S3C2400_PA_IIC
-#define S3C24XX_PA_IIS      S3C2400_PA_IIS
-#define S3C24XX_PA_GPIO     S3C2400_PA_GPIO
-#define S3C24XX_PA_RTC      S3C2400_PA_RTC
-#define S3C24XX_PA_ADC      S3C2400_PA_ADC
-#define S3C24XX_PA_SPI      S3C2400_PA_SPI
-#else
 #define S3C24XX_PA_IRQ      S3C2410_PA_IRQ
 #define S3C24XX_PA_MEMCTRL  S3C2410_PA_MEMCTRL
 #define S3C24XX_PA_USBHOST  S3C2410_PA_USBHOST
@@ -224,7 +158,6 @@
 #define S3C24XX_PA_RTC      S3C2410_PA_RTC
 #define S3C24XX_PA_ADC      S3C2410_PA_ADC
 #define S3C24XX_PA_SPI      S3C2410_PA_SPI
-#endif
 /* deal with the registers that move under the 2412/2413 */
diff --git a/include/asm-arm/arch-s3c2410/memory.h b/include/asm-arm/arch-s3c2410/memory.h
index 4be6a74c4303..533e2436e707 100644
--- a/include/asm-arm/arch-s3c2410/memory.h
+++ b/include/asm-arm/arch-s3c2410/memory.h
@@ -11,20 +11,7 @@
 #ifndef __ASM_ARCH_MEMORY_H
 #define __ASM_ARCH_MEMORY_H
-/*
- * DRAM starts at 0x30000000 for S3C2410/S3C2440
- * and at 0x0C000000 for S3C2400
- */
-#ifdef CONFIG_CPU_S3C2400
-#define PHYS_OFFSET     UL(0x0C000000)
-#else
 #define PHYS_OFFSET     UL(0x30000000)
-#endif
-/*
- * These are exactly the same on the S3C2410 as the
- * physical memory view.
-*/
 #define __virt_to_bus(x) __virt_to_phys(x)
 #define __bus_to_virt(x) __phys_to_virt(x)
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index b7faeb04c0ff..76fe5f693426 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -12,7 +12,7 @@
 #ifndef ___ASM_ARCH_REGS_LCD_H
 #define ___ASM_ARCH_REGS_LCD_H "$Id: lcd.h,v 1.3 2003/06/26 13:25:06 ben Exp $"
-#define S3C2410_LCDREG(x) ((x) + S3C24XX_VA_LCD)
+#define S3C2410_LCDREG(x)       (x)
 /* LCD control registers */
 #define S3C2410_LCDCON1     S3C2410_LCDREG(0x00)
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 1c74ef17da33..63891786dfa0 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -17,7 +17,7 @@
 #include <asm/arch/idle.h>
 #include <asm/arch/reset.h>
-#include <asm/arch/regs-watchdog.h>
+#include <asm/plat-s3c/regs-watchdog.h>
 #include <asm/arch/regs-clock.h>
 void (*s3c24xx_idle)(void);
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index dcb2cef38f50..48a5731ee988 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -1,6 +1,7 @@
 /* linux/include/asm-arm/arch-s3c2410/uncompress.h
 *
- * Copyright (c) 2003 Simtec Electronics
+ * Copyright (c) 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
 *      Ben Dooks <ben@simtec.co.uk>
 *
 * S3C2410 - uncompress code
@@ -13,153 +14,39 @@
 #ifndef __ASM_ARCH_UNCOMPRESS_H
 #define __ASM_ARCH_UNCOMPRESS_H
-typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
+#include <asm/arch/regs-gpio.h>
-/* defines for UART registers */
-#include "asm/arch/regs-serial.h"
-#include "asm/arch/regs-gpio.h"
-#include "asm/arch/regs-watchdog.h"
 #include <asm/arch/map.h>
 /* working in physical space... */
 #undef S3C2410_GPIOREG
-#undef S3C2410_WDOGREG
 #define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#include <asm/plat-s3c/uncompress.h>
-#define FIFO_MAX         (14)
-#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
+static inline int is_arm926(void)
-static __inline__ void
-uart_wr(unsigned int reg, unsigned int val)
 {
-        volatile unsigned int *ptr;
+        unsigned int cpuid;
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        *ptr = val;
-}
-static __inline__ unsigned int
+        asm volatile ("mrc p15, 0, %0, c1, c0, 0" : "=r" (cpuid));
-uart_rd(unsigned int reg)
-{
-        volatile unsigned int *ptr;
-        ptr = (volatile unsigned int *)(reg + uart_base);
+        return ((cpuid & 0xff0) == 0x260);
-        return *ptr;
 }
+static void arch_detect_cpu(void)
-/* we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
-*/
-static void putc(int ch)
 {
-        int cpuid = S3C2410_GSTATUS1_2410;
+        unsigned int cpuid;
-#ifndef CONFIG_CPU_S3C2400
        cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
        cpuid &= S3C2410_GSTATUS1_IDMASK;
-#endif
-        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-                int level;
-                while (1) {
-                        level = uart_rd(S3C2410_UFSTAT);
-                        if (cpuid == S3C2410_GSTATUS1_2440 ||
-                            cpuid == S3C2410_GSTATUS1_2442) {
-                                level &= S3C2440_UFSTAT_TXMASK;
-                                level >>= S3C2440_UFSTAT_TXSHIFT;
-                        } else {
-                                level &= S3C2410_UFSTAT_TXMASK;
-                                level >>= S3C2410_UFSTAT_TXSHIFT;
-                        }
-                        if (level < FIFO_MAX)
-                                break;
-                }
+        if (is_arm926() || cpuid == S3C2410_GSTATUS1_2440 ||
+            cpuid == S3C2410_GSTATUS1_2442) {
+                fifo_mask = S3C2440_UFSTAT_TXMASK;
+                fifo_max = 63 << S3C2440_UFSTAT_TXSHIFT;
        } else {
-                /* not using fifos */
+                fifo_mask = S3C2410_UFSTAT_TXMASK;
+                fifo_max = 15 << S3C2410_UFSTAT_TXSHIFT;
-                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-                        barrier();
        }
-        /* write byte to transmission register */
-        uart_wr(S3C2410_UTXH, ch);
 }
-static inline void flush(void)
-{
-}
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
-/* CONFIG_S3C2410_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
-*/
-#ifdef CONFIG_S3C2410_BOOT_WATCHDOG
-#define WDOG_COUNT (0xff00)
-static inline void arch_decomp_wdog(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-static void arch_decomp_wdog_start(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
-#ifdef CONFIG_S3C2410_BOOT_ERROR_RESET
-static void arch_decomp_error(const char *x)
-{
-        putstr("\n\n");
-        putstr(x);
-        putstr("\n\n -- System resetting\n");
-        __raw_writel(0x4000, S3C2410_WTDAT);
-        __raw_writel(0x4000, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-        while(1);
-}
-#define arch_error arch_decomp_error
-#endif
-static void error(char *err);
-static void
-arch_decomp_setup(void)
-{
-        /* we may need to setup the uart(s) here if we are not running
-         * on an BAST... the BAST will have left the uarts configured
-         * after calling linux.
-         */
-        arch_decomp_wdog_start();
-}
 #endif /* __ASM_ARCH_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-sa1100/jornada720.h b/include/asm-arm/arch-sa1100/jornada720.h
new file mode 100644
index 000000000000..45d2bb59f9d0
--- /dev/null
+++ b/include/asm-arm/arch-sa1100/jornada720.h
@@ -0,0 +1,27 @@
+/*
+ * include/asm-arm/arch-sa1100/jornada720.h
+ *
+ * This file contains SSP/MCU communication definitions for HP Jornada 710/720/728
+ *
+ * Copyright (C) 2007 Kristoffer Ericson <Kristoffer.Ericson@gmail.com>
+ *  Copyright (C) 2000 John Ankcorn <jca@lcs.mit.edu>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+ /* HP Jornada 7xx microprocessor commands */
+#define GETBATTERYDATA          0xc0
+#define GETSCANKEYCODE          0x90
+#define GETTOUCHSAMPLES         0xa0
+#define GETCONTRAST             0xD0
+#define SETCONTRAST             0xD1
+#define GETBRIGHTNESS           0xD2
+#define SETBRIGHTNESS           0xD3
+#define CONTRASTOFF             0xD8
+#define BRIGHTNESSOFF           0xD9
+#define PWMOFF                  0xDF
+#define TXDUMMY                 0x11
+#define ERRORCODE               0x00
diff --git a/include/asm-arm/elf.h b/include/asm-arm/elf.h
index 3679a8a8922e..ec1c685562ce 100644
--- a/include/asm-arm/elf.h
+++ b/include/asm-arm/elf.h
@@ -1,6 +1,8 @@
 #ifndef __ASMARM_ELF_H
 #define __ASMARM_ELF_H
+#include <asm/hwcap.h>
 #ifndef __ASSEMBLY__
 /*
 * ELF register definitions..
@@ -39,31 +41,9 @@ typedef struct user_fp elf_fpregset_t;
 #endif
 #define ELF_ARCH        EM_ARM
-/*
- * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
- */
-#define HWCAP_SWP       1
-#define HWCAP_HALF      2
-#define HWCAP_THUMB     4
-#define HWCAP_26BIT     8       /* Play it safe */
-#define HWCAP_FAST_MULT 16
-#define HWCAP_FPA       32
-#define HWCAP_VFP       64
-#define HWCAP_EDSP      128
-#define HWCAP_JAVA      256
-#define HWCAP_IWMMXT    512
-#define HWCAP_CRUNCH    1024
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 /*
- * This yields a mask that user programs can use to figure out what
- * instruction set this cpu supports.
- */
-#define ELF_HWCAP       (elf_hwcap)
-extern unsigned int elf_hwcap;
-/*
 * This yields a string that ld.so will use to load implementation
 * specific libraries for optimization.  This is more specific in
 * intent than poking at uname or /proc/cpuinfo.
diff --git a/include/asm-arm/fb.h b/include/asm-arm/fb.h
new file mode 100644
index 000000000000..d92e99cd8c8a
--- /dev/null
+++ b/include/asm-arm/fb.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_FB_H_
+#define _ASM_FB_H_
+#include <linux/fb.h>
+#include <linux/fs.h>
+#include <asm/page.h>
+static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
+                                unsigned long off)
+{
+        vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
+}
+static inline int fb_is_primary_device(struct fb_info *info)
+{
+        return 0;
+}
+#endif /* _ASM_FB_H_ */
diff --git a/include/asm-arm/floppy.h b/include/asm-arm/floppy.h
index 54b5ae44ed94..d595c15166a4 100644
--- a/include/asm-arm/floppy.h
+++ b/include/asm-arm/floppy.h
@@ -30,15 +30,21 @@
 #define fd_disable_irq()        disable_irq(IRQ_FLOPPYDISK)
 #define fd_enable_irq()         enable_irq(IRQ_FLOPPYDISK)
+static inline int fd_dma_setup(void *data, unsigned int length,
+                               unsigned int mode, unsigned long addr)
+{
+        set_dma_mode(DMA_FLOPPY, mode);
+        __set_dma_addr(DMA_FLOPPY, data);
+        set_dma_count(DMA_FLOPPY, length);
+        virtual_dma_port = addr;
+        enable_dma(DMA_FLOPPY);
+        return 0;
+}
+#define fd_dma_setup            fd_dma_setup
 #define fd_request_dma()        request_dma(DMA_FLOPPY,"floppy")
 #define fd_free_dma()           free_dma(DMA_FLOPPY)
 #define fd_disable_dma()        disable_dma(DMA_FLOPPY)
-#define fd_enable_dma()         enable_dma(DMA_FLOPPY)
-#define fd_clear_dma_ff()       clear_dma_ff(DMA_FLOPPY)
-#define fd_set_dma_mode(mode)   set_dma_mode(DMA_FLOPPY, (mode))
-#define fd_set_dma_addr(addr)   set_dma_addr(DMA_FLOPPY, virt_to_bus((addr)))
-#define fd_set_dma_count(len)   set_dma_count(DMA_FLOPPY, (len))
-#define fd_cacheflush(addr,sz)
 /* need to clean up dma.h */
 #define DMA_FLOPPYDISK          DMA_FLOPPY
diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h
new file mode 100644
index 000000000000..10834b54f681
--- /dev/null
+++ b/include/asm-arm/hardware/iop3xx-adma.h
@@ -0,0 +1,892 @@
+/*
+ * Copyright © 2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#ifndef _ADMA_H
+#define _ADMA_H
+#include <linux/types.h>
+#include <linux/io.h>
+#include <asm/hardware.h>
+#include <asm/hardware/iop_adma.h>
+/* Memory copy units */
+#define DMA_CCR(chan)           (chan->mmr_base + 0x0)
+#define DMA_CSR(chan)           (chan->mmr_base + 0x4)
+#define DMA_DAR(chan)           (chan->mmr_base + 0xc)
+#define DMA_NDAR(chan)          (chan->mmr_base + 0x10)
+#define DMA_PADR(chan)          (chan->mmr_base + 0x14)
+#define DMA_PUADR(chan) (chan->mmr_base + 0x18)
+#define DMA_LADR(chan)          (chan->mmr_base + 0x1c)
+#define DMA_BCR(chan)           (chan->mmr_base + 0x20)
+#define DMA_DCR(chan)           (chan->mmr_base + 0x24)
+/* Application accelerator unit  */
+#define AAU_ACR(chan)           (chan->mmr_base + 0x0)
+#define AAU_ASR(chan)           (chan->mmr_base + 0x4)
+#define AAU_ADAR(chan)          (chan->mmr_base + 0x8)
+#define AAU_ANDAR(chan) (chan->mmr_base + 0xc)
+#define AAU_SAR(src, chan)      (chan->mmr_base + (0x10 + ((src) << 2)))
+#define AAU_DAR(chan)           (chan->mmr_base + 0x20)
+#define AAU_ABCR(chan)          (chan->mmr_base + 0x24)
+#define AAU_ADCR(chan)          (chan->mmr_base + 0x28)
+#define AAU_SAR_EDCR(src_edc)   (chan->mmr_base + (0x02c + ((src_edc-4) << 2)))
+#define AAU_EDCR0_IDX   8
+#define AAU_EDCR1_IDX   17
+#define AAU_EDCR2_IDX   26
+#define DMA0_ID 0
+#define DMA1_ID 1
+#define AAU_ID 2
+struct iop3xx_aau_desc_ctrl {
+        unsigned int int_en:1;
+        unsigned int blk1_cmd_ctrl:3;
+        unsigned int blk2_cmd_ctrl:3;
+        unsigned int blk3_cmd_ctrl:3;
+        unsigned int blk4_cmd_ctrl:3;
+        unsigned int blk5_cmd_ctrl:3;
+        unsigned int blk6_cmd_ctrl:3;
+        unsigned int blk7_cmd_ctrl:3;
+        unsigned int blk8_cmd_ctrl:3;
+        unsigned int blk_ctrl:2;
+        unsigned int dual_xor_en:1;
+        unsigned int tx_complete:1;
+        unsigned int zero_result_err:1;
+        unsigned int zero_result_en:1;
+        unsigned int dest_write_en:1;
+};
+struct iop3xx_aau_e_desc_ctrl {
+        unsigned int reserved:1;
+        unsigned int blk1_cmd_ctrl:3;
+        unsigned int blk2_cmd_ctrl:3;
+        unsigned int blk3_cmd_ctrl:3;
+        unsigned int blk4_cmd_ctrl:3;
+        unsigned int blk5_cmd_ctrl:3;
+        unsigned int blk6_cmd_ctrl:3;
+        unsigned int blk7_cmd_ctrl:3;
+        unsigned int blk8_cmd_ctrl:3;
+        unsigned int reserved2:7;
+};
+struct iop3xx_dma_desc_ctrl {
+        unsigned int pci_transaction:4;
+        unsigned int int_en:1;
+        unsigned int dac_cycle_en:1;
+        unsigned int mem_to_mem_en:1;
+        unsigned int crc_data_tx_en:1;
+        unsigned int crc_gen_en:1;
+        unsigned int crc_seed_dis:1;
+        unsigned int reserved:21;
+        unsigned int crc_tx_complete:1;
+};
+struct iop3xx_desc_dma {
+        u32 next_desc;
+        union {
+                u32 pci_src_addr;
+                u32 pci_dest_addr;
+                u32 src_addr;
+        };
+        union {
+                u32 upper_pci_src_addr;
+                u32 upper_pci_dest_addr;
+        };
+        union {
+                u32 local_pci_src_addr;
+                u32 local_pci_dest_addr;
+                u32 dest_addr;
+        };
+        u32 byte_count;
+        union {
+                u32 desc_ctrl;
+                struct iop3xx_dma_desc_ctrl desc_ctrl_field;
+        };
+        u32 crc_addr;
+};
+struct iop3xx_desc_aau {
+        u32 next_desc;
+        u32 src[4];
+        u32 dest_addr;
+        u32 byte_count;
+        union {
+                u32 desc_ctrl;
+                struct iop3xx_aau_desc_ctrl desc_ctrl_field;
+        };
+        union {
+                u32 src_addr;
+                u32 e_desc_ctrl;
+                struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
+        } src_edc[31];
+};
+struct iop3xx_aau_gfmr {
+        unsigned int gfmr1:8;
+        unsigned int gfmr2:8;
+        unsigned int gfmr3:8;
+        unsigned int gfmr4:8;
+};
+struct iop3xx_desc_pq_xor {
+        u32 next_desc;
+        u32 src[3];
+        union {
+                u32 data_mult1;
+                struct iop3xx_aau_gfmr data_mult1_field;
+        };
+        u32 dest_addr;
+        u32 byte_count;
+        union {
+                u32 desc_ctrl;
+                struct iop3xx_aau_desc_ctrl desc_ctrl_field;
+        };
+        union {
+                u32 src_addr;
+                u32 e_desc_ctrl;
+                struct iop3xx_aau_e_desc_ctrl e_desc_ctrl_field;
+                u32 data_multiplier;
+                struct iop3xx_aau_gfmr data_mult_field;
+                u32 reserved;
+        } src_edc_gfmr[19];
+};
+struct iop3xx_desc_dual_xor {
+        u32 next_desc;
+        u32 src0_addr;
+        u32 src1_addr;
+        u32 h_src_addr;
+        u32 d_src_addr;
+        u32 h_dest_addr;
+        u32 byte_count;
+        union {
+                u32 desc_ctrl;
+                struct iop3xx_aau_desc_ctrl desc_ctrl_field;
+        };
+        u32 d_dest_addr;
+};
+union iop3xx_desc {
+        struct iop3xx_desc_aau *aau;
+        struct iop3xx_desc_dma *dma;
+        struct iop3xx_desc_pq_xor *pq_xor;
+        struct iop3xx_desc_dual_xor *dual_xor;
+        void *ptr;
+};
+static inline int iop_adma_get_max_xor(void)
+{
+        return 32;
+}
+static inline u32 iop_chan_get_current_descriptor(struct iop_adma_chan *chan)
+{
+        int id = chan->device->id;
+        switch (id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                return __raw_readl(DMA_DAR(chan));
+        case AAU_ID:
+                return __raw_readl(AAU_ADAR(chan));
+        default:
+                BUG();
+        }
+        return 0;
+}
+static inline void iop_chan_set_next_descriptor(struct iop_adma_chan *chan,
+                                                u32 next_desc_addr)
+{
+        int id = chan->device->id;
+        switch (id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                __raw_writel(next_desc_addr, DMA_NDAR(chan));
+                break;
+        case AAU_ID:
+                __raw_writel(next_desc_addr, AAU_ANDAR(chan));
+                break;
+        }
+}
+#define IOP_ADMA_STATUS_BUSY (1 << 10)
+#define IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT (1024)
+#define IOP_ADMA_XOR_MAX_BYTE_COUNT (16 * 1024 * 1024)
+#define IOP_ADMA_MAX_BYTE_COUNT (16 * 1024 * 1024)
+static inline int iop_chan_is_busy(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(DMA_CSR(chan));
+        return (status & IOP_ADMA_STATUS_BUSY) ? 1 : 0;
+}
+static inline int iop_desc_is_aligned(struct iop_adma_desc_slot *desc,
+                                        int num_slots)
+{
+        /* num_slots will only ever be 1, 2, 4, or 8 */
+        return (desc->idx & (num_slots - 1)) ? 0 : 1;
+}
+/* to do: support large (i.e. > hw max) buffer sizes */
+static inline int iop_chan_memcpy_slot_count(size_t len, int *slots_per_op)
+{
+        *slots_per_op = 1;
+        return 1;
+}
+/* to do: support large (i.e. > hw max) buffer sizes */
+static inline int iop_chan_memset_slot_count(size_t len, int *slots_per_op)
+{
+        *slots_per_op = 1;
+        return 1;
+}
+static inline int iop3xx_aau_xor_slot_count(size_t len, int src_cnt,
+                                        int *slots_per_op)
+{
+        const static int slot_count_table[] = { 0,
+                                                1, 1, 1, 1, /* 01 - 04 */
+                                                2, 2, 2, 2, /* 05 - 08 */
+                                                4, 4, 4, 4, /* 09 - 12 */
+                                                4, 4, 4, 4, /* 13 - 16 */
+                                                8, 8, 8, 8, /* 17 - 20 */
+                                                8, 8, 8, 8, /* 21 - 24 */
+                                                8, 8, 8, 8, /* 25 - 28 */
+                                                8, 8, 8, 8, /* 29 - 32 */
+                                              };
+        *slots_per_op = slot_count_table[src_cnt];
+        return *slots_per_op;
+}
+static inline int
+iop_chan_interrupt_slot_count(int *slots_per_op, struct iop_adma_chan *chan)
+{
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                return iop_chan_memcpy_slot_count(0, slots_per_op);
+        case AAU_ID:
+                return iop3xx_aau_xor_slot_count(0, 2, slots_per_op);
+        default:
+                BUG();
+        }
+        return 0;
+}
+static inline int iop_chan_xor_slot_count(size_t len, int src_cnt,
+                                                int *slots_per_op)
+{
+        int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
+        if (len <= IOP_ADMA_XOR_MAX_BYTE_COUNT)
+                return slot_cnt;
+        len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
+        while (len > IOP_ADMA_XOR_MAX_BYTE_COUNT) {
+                len -= IOP_ADMA_XOR_MAX_BYTE_COUNT;
+                slot_cnt += *slots_per_op;
+        }
+        if (len)
+                slot_cnt += *slots_per_op;
+        return slot_cnt;
+}
+/* zero sum on iop3xx is limited to 1k at a time so it requires multiple
+ * descriptors
+ */
+static inline int iop_chan_zero_sum_slot_count(size_t len, int src_cnt,
+                                                int *slots_per_op)
+{
+        int slot_cnt = iop3xx_aau_xor_slot_count(len, src_cnt, slots_per_op);
+        if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT)
+                return slot_cnt;
+        len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
+        while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
+                len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
+                slot_cnt += *slots_per_op;
+        }
+        if (len)
+                slot_cnt += *slots_per_op;
+        return slot_cnt;
+}
+static inline u32 iop_desc_get_dest_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan)
+{
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                return hw_desc.dma->dest_addr;
+        case AAU_ID:
+                return hw_desc.aau->dest_addr;
+        default:
+                BUG();
+        }
+        return 0;
+}
+static inline u32 iop_desc_get_byte_count(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan)
+{
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                return hw_desc.dma->byte_count;
+        case AAU_ID:
+                return hw_desc.aau->byte_count;
+        default:
+                BUG();
+        }
+        return 0;
+}
+/* translate the src_idx to a descriptor word index */
+static inline int __desc_idx(int src_idx)
+{
+        const static int desc_idx_table[] = { 0, 0, 0, 0,
+                                              0, 1, 2, 3,
+                                              5, 6, 7, 8,
+                                              9, 10, 11, 12,
+                                              14, 15, 16, 17,
+                                              18, 19, 20, 21,
+                                              23, 24, 25, 26,
+                                              27, 28, 29, 30,
+                                            };
+        return desc_idx_table[src_idx];
+}
+static inline u32 iop_desc_get_src_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        int src_idx)
+{
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                return hw_desc.dma->src_addr;
+        case AAU_ID:
+                break;
+        default:
+                BUG();
+        }
+        if (src_idx < 4)
+                return hw_desc.aau->src[src_idx];
+        else
+                return hw_desc.aau->src_edc[__desc_idx(src_idx)].src_addr;
+}
+static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc,
+                                        int src_idx, dma_addr_t addr)
+{
+        if (src_idx < 4)
+                hw_desc->src[src_idx] = addr;
+        else
+                hw_desc->src_edc[__desc_idx(src_idx)].src_addr = addr;
+}
+static inline void
+iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en)
+{
+        struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop3xx_dma_desc_ctrl field;
+        } u_desc_ctrl;
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.mem_to_mem_en = 1;
+        u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */
+        u_desc_ctrl.field.int_en = int_en;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        hw_desc->upper_pci_src_addr = 0;
+        hw_desc->crc_addr = 0;
+}
+static inline void
+iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en)
+{
+        struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop3xx_aau_desc_ctrl field;
+        } u_desc_ctrl;
+        u_desc_ctrl.value = 0;
+        u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */
+        u_desc_ctrl.field.dest_write_en = 1;
+        u_desc_ctrl.field.int_en = int_en;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+}
+static inline u32
+iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en)
+{
+        int i, shift;
+        u32 edcr;
+        union {
+                u32 value;
+                struct iop3xx_aau_desc_ctrl field;
+        } u_desc_ctrl;
+        u_desc_ctrl.value = 0;
+        switch (src_cnt) {
+        case 25 ... 32:
+                u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
+                edcr = 0;
+                shift = 1;
+                for (i = 24; i < src_cnt; i++) {
+                        edcr |= (1 << shift);
+                        shift += 3;
+                }
+                hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = edcr;
+                src_cnt = 24;
+                /* fall through */
+        case 17 ... 24:
+                if (!u_desc_ctrl.field.blk_ctrl) {
+                        hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
+                        u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
+                }
+                edcr = 0;
+                shift = 1;
+                for (i = 16; i < src_cnt; i++) {
+                        edcr |= (1 << shift);
+                        shift += 3;
+                }
+                hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = edcr;
+                src_cnt = 16;
+                /* fall through */
+        case 9 ... 16:
+                if (!u_desc_ctrl.field.blk_ctrl)
+                        u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
+                edcr = 0;
+                shift = 1;
+                for (i = 8; i < src_cnt; i++) {
+                        edcr |= (1 << shift);
+                        shift += 3;
+                }
+                hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = edcr;
+                src_cnt = 8;
+                /* fall through */
+        case 2 ... 8:
+                shift = 1;
+                for (i = 0; i < src_cnt; i++) {
+                        u_desc_ctrl.value |= (1 << shift);
+                        shift += 3;
+                }
+                if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
+                        u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
+        }
+        u_desc_ctrl.field.dest_write_en = 1;
+        u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */
+        u_desc_ctrl.field.int_en = int_en;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+        return u_desc_ctrl.value;
+}
+static inline void
+iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
+{
+        iop3xx_desc_init_xor(desc->hw_desc, src_cnt, int_en);
+}
+/* return the number of operations */
+static inline int
+iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
+{
+        int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
+        struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter;
+        union {
+                u32 value;
+                struct iop3xx_aau_desc_ctrl field;
+        } u_desc_ctrl;
+        int i, j;
+        hw_desc = desc->hw_desc;
+        for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0;
+                i += slots_per_op, j++) {
+                iter = iop_hw_desc_slot_idx(hw_desc, i);
+                u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, int_en);
+                u_desc_ctrl.field.dest_write_en = 0;
+                u_desc_ctrl.field.zero_result_en = 1;
+                u_desc_ctrl.field.int_en = int_en;
+                iter->desc_ctrl = u_desc_ctrl.value;
+                /* for the subsequent descriptors preserve the store queue
+                 * and chain them together
+                 */
+                if (i) {
+                        prev_hw_desc =
+                                iop_hw_desc_slot_idx(hw_desc, i - slots_per_op);
+                        prev_hw_desc->next_desc =
+                                (u32) (desc->async_tx.phys + (i << 5));
+                }
+        }
+        return j;
+}
+static inline void
+iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
+{
+        struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
+        union {
+                u32 value;
+                struct iop3xx_aau_desc_ctrl field;
+        } u_desc_ctrl;
+        u_desc_ctrl.value = 0;
+        switch (src_cnt) {
+        case 25 ... 32:
+                u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
+                hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
+                /* fall through */
+        case 17 ... 24:
+                if (!u_desc_ctrl.field.blk_ctrl) {
+                        hw_desc->src_edc[AAU_EDCR2_IDX].e_desc_ctrl = 0;
+                        u_desc_ctrl.field.blk_ctrl = 0x3; /* use EDCR[2:0] */
+                }
+                hw_desc->src_edc[AAU_EDCR1_IDX].e_desc_ctrl = 0;
+                /* fall through */
+        case 9 ... 16:
+                if (!u_desc_ctrl.field.blk_ctrl)
+                        u_desc_ctrl.field.blk_ctrl = 0x2; /* use EDCR0 */
+                hw_desc->src_edc[AAU_EDCR0_IDX].e_desc_ctrl = 0;
+                /* fall through */
+        case 1 ... 8:
+                if (!u_desc_ctrl.field.blk_ctrl && src_cnt > 4)
+                        u_desc_ctrl.field.blk_ctrl = 0x1; /* use mini-desc */
+        }
+        u_desc_ctrl.field.dest_write_en = 0;
+        u_desc_ctrl.field.int_en = int_en;
+        hw_desc->desc_ctrl = u_desc_ctrl.value;
+}
+static inline void iop_desc_set_byte_count(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        u32 byte_count)
+{
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                hw_desc.dma->byte_count = byte_count;
+                break;
+        case AAU_ID:
+                hw_desc.aau->byte_count = byte_count;
+                break;
+        default:
+                BUG();
+        }
+}
+static inline void
+iop_desc_init_interrupt(struct iop_adma_desc_slot *desc,
+                        struct iop_adma_chan *chan)
+{
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                iop_desc_init_memcpy(desc, 1);
+                hw_desc.dma->byte_count = 0;
+                hw_desc.dma->dest_addr = 0;
+                hw_desc.dma->src_addr = 0;
+                break;
+        case AAU_ID:
+                iop_desc_init_null_xor(desc, 2, 1);
+                hw_desc.aau->byte_count = 0;
+                hw_desc.aau->dest_addr = 0;
+                hw_desc.aau->src[0] = 0;
+                hw_desc.aau->src[1] = 0;
+                break;
+        default:
+                BUG();
+        }
+}
+static inline void
+iop_desc_set_zero_sum_byte_count(struct iop_adma_desc_slot *desc, u32 len)
+{
+        int slots_per_op = desc->slots_per_op;
+        struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
+        int i = 0;
+        if (len <= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
+                hw_desc->byte_count = len;
+        } else {
+                do {
+                        iter = iop_hw_desc_slot_idx(hw_desc, i);
+                        iter->byte_count = IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
+                        len -= IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT;
+                        i += slots_per_op;
+                } while (len > IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT);
+                if (len) {
+                        iter = iop_hw_desc_slot_idx(hw_desc, i);
+                        iter->byte_count = len;
+                }
+        }
+}
+static inline void iop_desc_set_dest_addr(struct iop_adma_desc_slot *desc,
+                                        struct iop_adma_chan *chan,
+                                        dma_addr_t addr)
+{
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                hw_desc.dma->dest_addr = addr;
+                break;
+        case AAU_ID:
+                hw_desc.aau->dest_addr = addr;
+                break;
+        default:
+                BUG();
+        }
+}
+static inline void iop_desc_set_memcpy_src_addr(struct iop_adma_desc_slot *desc,
+                                        dma_addr_t addr)
+{
+        struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
+        hw_desc->src_addr = addr;
+}
+static inline void
+iop_desc_set_zero_sum_src_addr(struct iop_adma_desc_slot *desc, int src_idx,
+                                dma_addr_t addr)
+{
+        struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
+        int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
+        int i;
+        for (i = 0; (slot_cnt -= slots_per_op) >= 0;
+                i += slots_per_op, addr += IOP_ADMA_ZERO_SUM_MAX_BYTE_COUNT) {
+                iter = iop_hw_desc_slot_idx(hw_desc, i);
+                iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
+        }
+}
+static inline void iop_desc_set_xor_src_addr(struct iop_adma_desc_slot *desc,
+                                        int src_idx, dma_addr_t addr)
+{
+        struct iop3xx_desc_aau *hw_desc = desc->hw_desc, *iter;
+        int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
+        int i;
+        for (i = 0; (slot_cnt -= slots_per_op) >= 0;
+                i += slots_per_op, addr += IOP_ADMA_XOR_MAX_BYTE_COUNT) {
+                iter = iop_hw_desc_slot_idx(hw_desc, i);
+                iop3xx_aau_desc_set_src_addr(iter, src_idx, addr);
+        }
+}
+static inline void iop_desc_set_next_desc(struct iop_adma_desc_slot *desc,
+                                        u32 next_desc_addr)
+{
+        /* hw_desc->next_desc is the same location for all channels */
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        BUG_ON(hw_desc.dma->next_desc);
+        hw_desc.dma->next_desc = next_desc_addr;
+}
+static inline u32 iop_desc_get_next_desc(struct iop_adma_desc_slot *desc)
+{
+        /* hw_desc->next_desc is the same location for all channels */
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        return hw_desc.dma->next_desc;
+}
+static inline void iop_desc_clear_next_desc(struct iop_adma_desc_slot *desc)
+{
+        /* hw_desc->next_desc is the same location for all channels */
+        union iop3xx_desc hw_desc = { .ptr = desc->hw_desc, };
+        hw_desc.dma->next_desc = 0;
+}
+static inline void iop_desc_set_block_fill_val(struct iop_adma_desc_slot *desc,
+                                                u32 val)
+{
+        struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
+        hw_desc->src[0] = val;
+}
+static inline int iop_desc_get_zero_result(struct iop_adma_desc_slot *desc)
+{
+        struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
+        struct iop3xx_aau_desc_ctrl desc_ctrl = hw_desc->desc_ctrl_field;
+        BUG_ON(!(desc_ctrl.tx_complete && desc_ctrl.zero_result_en));
+        return desc_ctrl.zero_result_err;
+}
+static inline void iop_chan_append(struct iop_adma_chan *chan)
+{
+        u32 dma_chan_ctrl;
+        /* workaround dropped interrupts on 3xx */
+        mod_timer(&chan->cleanup_watchdog, jiffies + msecs_to_jiffies(3));
+        dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
+        dma_chan_ctrl |= 0x2;
+        __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
+}
+static inline void iop_chan_idle(int busy, struct iop_adma_chan *chan)
+{
+        if (!busy)
+                del_timer(&chan->cleanup_watchdog);
+}
+static inline u32 iop_chan_get_status(struct iop_adma_chan *chan)
+{
+        return __raw_readl(DMA_CSR(chan));
+}
+static inline void iop_chan_disable(struct iop_adma_chan *chan)
+{
+        u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
+        dma_chan_ctrl &= ~1;
+        __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
+}
+static inline void iop_chan_enable(struct iop_adma_chan *chan)
+{
+        u32 dma_chan_ctrl = __raw_readl(DMA_CCR(chan));
+        dma_chan_ctrl |= 1;
+        __raw_writel(dma_chan_ctrl, DMA_CCR(chan));
+}
+static inline void iop_adma_device_clear_eot_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(DMA_CSR(chan));
+        status &= (1 << 9);
+        __raw_writel(status, DMA_CSR(chan));
+}
+static inline void iop_adma_device_clear_eoc_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(DMA_CSR(chan));
+        status &= (1 << 8);
+        __raw_writel(status, DMA_CSR(chan));
+}
+static inline void iop_adma_device_clear_err_status(struct iop_adma_chan *chan)
+{
+        u32 status = __raw_readl(DMA_CSR(chan));
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                status &= (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1);
+                break;
+        case AAU_ID:
+                status &= (1 << 5);
+                break;
+        default:
+                BUG();
+        }
+        __raw_writel(status, DMA_CSR(chan));
+}
+static inline int
+iop_is_err_int_parity(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+static inline int
+iop_is_err_mcu_abort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+static inline int
+iop_is_err_int_tabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return 0;
+}
+static inline int
+iop_is_err_int_mabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        return test_bit(5, &status);
+}
+static inline int
+iop_is_err_pci_tabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                return test_bit(2, &status);
+        default:
+                return 0;
+        }
+}
+static inline int
+iop_is_err_pci_mabort(unsigned long status, struct iop_adma_chan *chan)
+{
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                return test_bit(3, &status);
+        default:
+                return 0;
+        }
+}
+static inline int
+iop_is_err_split_tx(unsigned long status, struct iop_adma_chan *chan)
+{
+        switch (chan->device->id) {
+        case DMA0_ID:
+        case DMA1_ID:
+                return test_bit(1, &status);
+        default:
+                return 0;
+        }
+}
+#endif /* _ADMA_H */
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index 63feceb7ede5..fb90b421f31c 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -144,24 +144,9 @@ extern int init_atu;
 #define IOP3XX_IAR              (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
 /* DMA Controller  */
-#define IOP3XX_DMA0_CCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0400)
+#define IOP3XX_DMA_PHYS_BASE(chan) (IOP3XX_PERIPHERAL_PHYS_BASE + \
-#define IOP3XX_DMA0_CSR         (volatile u32 *)IOP3XX_REG_ADDR(0x0404)
+                                        (0x400 + (chan << 6)))
-#define IOP3XX_DMA0_DAR         (volatile u32 *)IOP3XX_REG_ADDR(0x040c)
+#define IOP3XX_DMA_UPPER_PA(chan)  (IOP3XX_DMA_PHYS_BASE(chan) + 0x27)
-#define IOP3XX_DMA0_NDAR        (volatile u32 *)IOP3XX_REG_ADDR(0x0410)
-#define IOP3XX_DMA0_PADR        (volatile u32 *)IOP3XX_REG_ADDR(0x0414)
-#define IOP3XX_DMA0_PUADR       (volatile u32 *)IOP3XX_REG_ADDR(0x0418)
-#define IOP3XX_DMA0_LADR        (volatile u32 *)IOP3XX_REG_ADDR(0x041c)
-#define IOP3XX_DMA0_BCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0420)
-#define IOP3XX_DMA0_DCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0424)
-#define IOP3XX_DMA1_CCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0440)
-#define IOP3XX_DMA1_CSR         (volatile u32 *)IOP3XX_REG_ADDR(0x0444)
-#define IOP3XX_DMA1_DAR         (volatile u32 *)IOP3XX_REG_ADDR(0x044c)
-#define IOP3XX_DMA1_NDAR        (volatile u32 *)IOP3XX_REG_ADDR(0x0450)
-#define IOP3XX_DMA1_PADR        (volatile u32 *)IOP3XX_REG_ADDR(0x0454)
-#define IOP3XX_DMA1_PUADR       (volatile u32 *)IOP3XX_REG_ADDR(0x0458)
-#define IOP3XX_DMA1_LADR        (volatile u32 *)IOP3XX_REG_ADDR(0x045c)
-#define IOP3XX_DMA1_BCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0460)
-#define IOP3XX_DMA1_DCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0464)
 /* Peripheral bus interface  */
 #define IOP3XX_PBCR             (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
@@ -209,49 +194,16 @@ extern int init_atu;
 #define IOP_TMR_PRIVILEGED 0x08
 #define IOP_TMR_RATIO_1_1  0x00
+/* Watchdog timer definitions */
+#define IOP_WDTCR_EN_ARM        0x1e1e1e1e
+#define IOP_WDTCR_EN            0xe1e1e1e1
+/* iop3xx does not support stopping the watchdog, so we just re-arm */
+#define IOP_WDTCR_DIS_ARM       (IOP_WDTCR_EN_ARM)
+#define IOP_WDTCR_DIS           (IOP_WDTCR_EN)
 /* Application accelerator unit  */
-#define IOP3XX_AAU_ACR          (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
+#define IOP3XX_AAU_PHYS_BASE (IOP3XX_PERIPHERAL_PHYS_BASE + 0x800)
-#define IOP3XX_AAU_ASR          (volatile u32 *)IOP3XX_REG_ADDR(0x0804)
+#define IOP3XX_AAU_UPPER_PA (IOP3XX_AAU_PHYS_BASE + 0xa7)
-#define IOP3XX_AAU_ADAR         (volatile u32 *)IOP3XX_REG_ADDR(0x0808)
-#define IOP3XX_AAU_ANDAR        (volatile u32 *)IOP3XX_REG_ADDR(0x080c)
-#define IOP3XX_AAU_SAR1         (volatile u32 *)IOP3XX_REG_ADDR(0x0810)
-#define IOP3XX_AAU_SAR2         (volatile u32 *)IOP3XX_REG_ADDR(0x0814)
-#define IOP3XX_AAU_SAR3         (volatile u32 *)IOP3XX_REG_ADDR(0x0818)
-#define IOP3XX_AAU_SAR4         (volatile u32 *)IOP3XX_REG_ADDR(0x081c)
-#define IOP3XX_AAU_DAR          (volatile u32 *)IOP3XX_REG_ADDR(0x0820)
-#define IOP3XX_AAU_ABCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0824)
-#define IOP3XX_AAU_ADCR         (volatile u32 *)IOP3XX_REG_ADDR(0x0828)
-#define IOP3XX_AAU_SAR5         (volatile u32 *)IOP3XX_REG_ADDR(0x082c)
-#define IOP3XX_AAU_SAR6         (volatile u32 *)IOP3XX_REG_ADDR(0x0830)
-#define IOP3XX_AAU_SAR7         (volatile u32 *)IOP3XX_REG_ADDR(0x0834)
-#define IOP3XX_AAU_SAR8         (volatile u32 *)IOP3XX_REG_ADDR(0x0838)
-#define IOP3XX_AAU_EDCR0        (volatile u32 *)IOP3XX_REG_ADDR(0x083c)
-#define IOP3XX_AAU_SAR9         (volatile u32 *)IOP3XX_REG_ADDR(0x0840)
-#define IOP3XX_AAU_SAR10        (volatile u32 *)IOP3XX_REG_ADDR(0x0844)
-#define IOP3XX_AAU_SAR11        (volatile u32 *)IOP3XX_REG_ADDR(0x0848)
-#define IOP3XX_AAU_SAR12        (volatile u32 *)IOP3XX_REG_ADDR(0x084c)
-#define IOP3XX_AAU_SAR13        (volatile u32 *)IOP3XX_REG_ADDR(0x0850)
-#define IOP3XX_AAU_SAR14        (volatile u32 *)IOP3XX_REG_ADDR(0x0854)
-#define IOP3XX_AAU_SAR15        (volatile u32 *)IOP3XX_REG_ADDR(0x0858)
-#define IOP3XX_AAU_SAR16        (volatile u32 *)IOP3XX_REG_ADDR(0x085c)
-#define IOP3XX_AAU_EDCR1        (volatile u32 *)IOP3XX_REG_ADDR(0x0860)
-#define IOP3XX_AAU_SAR17        (volatile u32 *)IOP3XX_REG_ADDR(0x0864)
-#define IOP3XX_AAU_SAR18        (volatile u32 *)IOP3XX_REG_ADDR(0x0868)
-#define IOP3XX_AAU_SAR19        (volatile u32 *)IOP3XX_REG_ADDR(0x086c)
-#define IOP3XX_AAU_SAR20        (volatile u32 *)IOP3XX_REG_ADDR(0x0870)
-#define IOP3XX_AAU_SAR21        (volatile u32 *)IOP3XX_REG_ADDR(0x0874)
-#define IOP3XX_AAU_SAR22        (volatile u32 *)IOP3XX_REG_ADDR(0x0878)
-#define IOP3XX_AAU_SAR23        (volatile u32 *)IOP3XX_REG_ADDR(0x087c)
-#define IOP3XX_AAU_SAR24        (volatile u32 *)IOP3XX_REG_ADDR(0x0880)
-#define IOP3XX_AAU_EDCR2        (volatile u32 *)IOP3XX_REG_ADDR(0x0884)
-#define IOP3XX_AAU_SAR25        (volatile u32 *)IOP3XX_REG_ADDR(0x0888)
-#define IOP3XX_AAU_SAR26        (volatile u32 *)IOP3XX_REG_ADDR(0x088c)
-#define IOP3XX_AAU_SAR27        (volatile u32 *)IOP3XX_REG_ADDR(0x0890)
-#define IOP3XX_AAU_SAR28        (volatile u32 *)IOP3XX_REG_ADDR(0x0894)
-#define IOP3XX_AAU_SAR29        (volatile u32 *)IOP3XX_REG_ADDR(0x0898)
-#define IOP3XX_AAU_SAR30        (volatile u32 *)IOP3XX_REG_ADDR(0x089c)
-#define IOP3XX_AAU_SAR31        (volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
-#define IOP3XX_AAU_SAR32        (volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
 /* I2C bus interface unit  */
 #define IOP3XX_ICR0             (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
@@ -329,6 +281,35 @@ static inline void write_tisr(u32 val)
        asm volatile("mcr p6, 0, %0, c6, c1, 0" : : "r" (val));
 }
+static inline u32 read_wdtcr(void)
+{
+        u32 val;
+        asm volatile("mrc p6, 0, %0, c7, c1, 0":"=r" (val));
+        return val;
+}
+static inline void write_wdtcr(u32 val)
+{
+        asm volatile("mcr p6, 0, %0, c7, c1, 0"::"r" (val));
+}
+extern unsigned long get_iop_tick_rate(void);
+/* only iop13xx has these registers, we define these to present a
+ * common register interface for the iop_wdt driver.
+ */
+#define IOP_RCSR_WDT    (0)
+static inline u32 read_rcsr(void)
+{
+        return 0;
+}
+static inline void write_wdtsr(u32 val)
+{
+        do { } while (0);
+}
+extern struct platform_device iop3xx_dma_0_channel;
+extern struct platform_device iop3xx_dma_1_channel;
+extern struct platform_device iop3xx_aau_channel;
 extern struct platform_device iop3xx_i2c0_device;
 extern struct platform_device iop3xx_i2c1_device;
diff --git a/include/asm-arm/hardware/iop_adma.h b/include/asm-arm/hardware/iop_adma.h
new file mode 100644
index 000000000000..ca8e71f44346
--- /dev/null
+++ b/include/asm-arm/hardware/iop_adma.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright © 2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#ifndef IOP_ADMA_H
+#define IOP_ADMA_H
+#include <linux/types.h>
+#include <linux/dmaengine.h>
+#include <linux/interrupt.h>
+#define IOP_ADMA_SLOT_SIZE 32
+#define IOP_ADMA_THRESHOLD 4
+/**
+ * struct iop_adma_device - internal representation of an ADMA device
+ * @pdev: Platform device
+ * @id: HW ADMA Device selector
+ * @dma_desc_pool: base of DMA descriptor region (DMA address)
+ * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
+ * @common: embedded struct dma_device
+ */
+struct iop_adma_device {
+        struct platform_device *pdev;
+        int id;
+        dma_addr_t dma_desc_pool;
+        void *dma_desc_pool_virt;
+        struct dma_device common;
+};
+/**
+ * struct iop_adma_chan - internal representation of an ADMA device
+ * @pending: allows batching of hardware operations
+ * @completed_cookie: identifier for the most recently completed operation
+ * @lock: serializes enqueue/dequeue operations to the slot pool
+ * @mmr_base: memory mapped register base
+ * @chain: device chain view of the descriptors
+ * @device: parent device
+ * @common: common dmaengine channel object members
+ * @last_used: place holder for allocation to continue from where it left off
+ * @all_slots: complete domain of slots usable by the channel
+ * @cleanup_watchdog: workaround missed interrupts on iop3xx
+ * @slots_allocated: records the actual size of the descriptor slot pool
+ * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
+ */
+struct iop_adma_chan {
+        int pending;
+        dma_cookie_t completed_cookie;
+        spinlock_t lock; /* protects the descriptor slot pool */
+        void __iomem *mmr_base;
+        struct list_head chain;
+        struct iop_adma_device *device;
+        struct dma_chan common;
+        struct iop_adma_desc_slot *last_used;
+        struct list_head all_slots;
+        struct timer_list cleanup_watchdog;
+        int slots_allocated;
+        struct tasklet_struct irq_tasklet;
+};
+/**
+ * struct iop_adma_desc_slot - IOP-ADMA software descriptor
+ * @slot_node: node on the iop_adma_chan.all_slots list
+ * @chain_node: node on the op_adma_chan.chain list
+ * @hw_desc: virtual address of the hardware descriptor chain
+ * @phys: hardware address of the hardware descriptor chain
+ * @group_head: first operation in a transaction
+ * @slot_cnt: total slots used in an transaction (group of operations)
+ * @slots_per_op: number of slots per operation
+ * @idx: pool index
+ * @unmap_src_cnt: number of xor sources
+ * @unmap_len: transaction bytecount
+ * @async_tx: support for the async_tx api
+ * @group_list: list of slots that make up a multi-descriptor transaction
+ *      for example transfer lengths larger than the supported hw max
+ * @xor_check_result: result of zero sum
+ * @crc32_result: result crc calculation
+ */
+struct iop_adma_desc_slot {
+        struct list_head slot_node;
+        struct list_head chain_node;
+        void *hw_desc;
+        struct iop_adma_desc_slot *group_head;
+        u16 slot_cnt;
+        u16 slots_per_op;
+        u16 idx;
+        u16 unmap_src_cnt;
+        size_t unmap_len;
+        struct dma_async_tx_descriptor async_tx;
+        union {
+                u32 *xor_check_result;
+                u32 *crc32_result;
+        };
+};
+struct iop_adma_platform_data {
+        int hw_id;
+        dma_cap_mask_t cap_mask;
+        size_t pool_size;
+};
+#define to_iop_sw_desc(addr_hw_desc) \
+        container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
+#define iop_hw_desc_slot_idx(hw_desc, idx) \
+        ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
+#endif
diff --git a/include/asm-arm/hwcap.h b/include/asm-arm/hwcap.h
new file mode 100644
index 000000000000..01a1391d3014
--- /dev/null
+++ b/include/asm-arm/hwcap.h
@@ -0,0 +1,28 @@
+#ifndef __ASMARM_HWCAP_H
+#define __ASMARM_HWCAP_H
+/*
+ * HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
+ */
+#define HWCAP_SWP       1
+#define HWCAP_HALF      2
+#define HWCAP_THUMB     4
+#define HWCAP_26BIT     8       /* Play it safe */
+#define HWCAP_FAST_MULT 16
+#define HWCAP_FPA       32
+#define HWCAP_VFP       64
+#define HWCAP_EDSP      128
+#define HWCAP_JAVA      256
+#define HWCAP_IWMMXT    512
+#define HWCAP_CRUNCH    1024
+#if defined(__KERNEL__) && !defined(__ASSEMBLY__)
+/*
+ * This yields a mask that user programs can use to figure out what
+ * instruction set this cpu supports.
+ */
+#define ELF_HWCAP       (elf_hwcap)
+extern unsigned int elf_hwcap;
+#endif
+#endif
diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h
index f21abd4ddac6..ed3f898191f4 100644
--- a/include/asm-arm/pci.h
+++ b/include/asm-arm/pci.h
@@ -26,11 +26,6 @@ static inline void pcibios_penalize_isa_irq(int irq, int active)
 #define PCI_DMA_BUS_IS_PHYS     (0)
 /*
- * We don't support DAC DMA cycles.
- */
-#define pci_dac_dma_supported(pci_dev, mask)    (0)
-/*
 * Whether pci_unmap_{single,page} is a nop depends upon the
 * configuration.
 */
@@ -76,10 +71,6 @@ pcibios_select_root(struct pci_dev *pdev, struct resource *res)
        return root;
 }
-static inline void pcibios_add_platform_entries(struct pci_dev *dev)
-{
-}
 #endif /* __KERNEL__ */
 
 #endif
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index 0c8be19fd66b..b186bc820e30 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -102,7 +102,8 @@ extern int is_in_rom(unsigned long);
 #define v4_tlb_fns      (0)
 #define v4wb_tlb_fns    (0)
 #define v4wbi_tlb_fns   (0)
-#define v6_tlb_fns      (0)
+#define v6wbi_tlb_fns   (0)
+#define v7wbi_tlb_fns   (0)
 #define v3_user_fns     (0)
 #define v4_user_fns     (0)
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 21dec9f258d8..d2e8171d1d4e 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -83,14 +83,14 @@
 * means that a write to a clean page will cause a permission fault, and
 * the Linux MM layer will mark the page dirty via handle_pte_fault().
 * For the hardware to notice the permission change, the TLB entry must
- * be flushed, and ptep_establish() does that for us.
+ * be flushed, and ptep_set_access_flags() does that for us.
 *
 * The "accessed" or "young" bit is emulated by a similar method; we only
 * allow accesses to the page if the "young" bit is set.  Accesses to the
 * page will cause a fault, and handle_pte_fault() will set the young bit
 * for us as long as the page is marked present in the corresponding Linux
- * PTE entry.  Again, ptep_establish() will ensure that the TLB is up to
+ * PTE entry.  Again, ptep_set_access_flags() will ensure that the TLB is
- * date.
+ * up to date.
 *
 * However, when the "young" bit is cleared, we deny access to the page
 * by clearing the hardware PTE.  Currently Linux does not flush the TLB
@@ -257,9 +257,7 @@ extern struct page *empty_zero_page;
 * Undefined behaviour if not..
 */
 #define pte_present(pte)        (pte_val(pte) & L_PTE_PRESENT)
-#define pte_read(pte)           (pte_val(pte) & L_PTE_USER)
 #define pte_write(pte)          (pte_val(pte) & L_PTE_WRITE)
-#define pte_exec(pte)           (pte_val(pte) & L_PTE_EXEC)
 #define pte_dirty(pte)          (pte_val(pte) & L_PTE_DIRTY)
 #define pte_young(pte)          (pte_val(pte) & L_PTE_YOUNG)
@@ -275,12 +273,8 @@ extern struct page *empty_zero_page;
 #define PTE_BIT_FUNC(fn,op) \
 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
-/*PTE_BIT_FUNC(rdprotect, &= ~L_PTE_USER);*/
-/*PTE_BIT_FUNC(mkread,    |= L_PTE_USER);*/
 PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
 PTE_BIT_FUNC(mkwrite,   |= L_PTE_WRITE);
-PTE_BIT_FUNC(exprotect, &= ~L_PTE_EXEC);
-PTE_BIT_FUNC(mkexec,    |= L_PTE_EXEC);
 PTE_BIT_FUNC(mkclean,   &= ~L_PTE_DIRTY);
 PTE_BIT_FUNC(mkdirty,   |= L_PTE_DIRTY);
 PTE_BIT_FUNC(mkold,     &= ~L_PTE_YOUNG);
diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/include/asm-arm/plat-s3c/debug-macro.S
new file mode 100644
index 000000000000..84c40b847da8
--- /dev/null
+++ b/include/asm-arm/plat-s3c/debug-macro.S
@@ -0,0 +1,75 @@
+/* linux/include/asm-arm/plat-s3c/debug-macro.S
+ *
+ * Copyright 2005, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#include <asm/plat-s3c/regs-serial.h>
+/* The S3C2440 implementations are used by default as they are the
+ * most widely re-used */
+        .macro fifo_level_s3c2440 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                and     \rd, \rd, #S3C2440_UFSTAT_TXMASK
+        .endm
+#ifndef fifo_level
+#define fifo_level fifo_level_s3c2410
+#endif
+        .macro  fifo_full_s3c2440 rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
+                tst     \rd, #S3C2440_UFSTAT_TXFULL
+        .endm
+#ifndef fifo_full
+#define fifo_full fifo_full_s3c2440
+#endif
+        .macro  senduart,rd,rx
+                strb    \rd, [\rx, # S3C2410_UTXH ]
+        .endm
+        .macro  busyuart, rd, rx
+                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                beq     1001f                           @
+                @ FIFO enabled...
+1003:
+                fifo_full \rd, \rx
+                bne     1003b
+                b       1002f
+1001:
+                @ busy waiting for non fifo
+                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                tst     \rd, #S3C2410_UTRSTAT_TXFE
+                beq     1001b
+1002:           @ exit busyuart
+        .endm
+        .macro  waituart,rd,rx
+                ldr     \rd, [ \rx, # S3C2410_UFCON ]
+                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
+                beq     1001f                           @
+                @ FIFO enabled...
+1003:
+                fifo_level \rd, \rx
+                teq     \rd, #0
+                bne     1003b
+                b       1002f
+1001:
+                @ idle waiting for non fifo
+                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
+                tst     \rd, #S3C2410_UTRSTAT_TXFE
+                beq     1001b
+1002:           @ exit busyuart
+        .endm
diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/plat-s3c/iic.h
index 71211c8b5384..71211c8b5384 100644
--- a/include/asm-arm/arch-s3c2410/iic.h
+++ b/include/asm-arm/plat-s3c/iic.h
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
new file mode 100644
index 000000000000..95a82b0e84a1
--- /dev/null
+++ b/include/asm-arm/plat-s3c/map.h
@@ -0,0 +1,40 @@
+/* linux/include/asm-arm/plat-s3c/map.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - Memory map definitions (virtual addresses)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_PLAT_MAP_H
+#define __ASM_PLAT_MAP_H __FILE__
+/* Fit all our registers in at 0xF4000000 upwards, trying to use as
+ * little of the VA space as possible so vmalloc and friends have a
+ * better chance of getting memory.
+ *
+ * we try to ensure stuff like the IRQ registers are available for
+ * an single MOVS instruction (ie, only 8 bits of set data)
+ */
+#define S3C_ADDR_BASE   (0xF4000000)
+#ifndef __ASSEMBLY__
+#define S3C_ADDR(x)     ((void __iomem __force *)S3C_ADDR_BASE + (x))
+#else
+#define S3C_ADDR(x)     (S3C_ADDR_BASE + (x))
+#endif
+#define S3C_VA_IRQ      S3C_ADDR(0x000000000)   /* irq controller(s) */
+#define S3C_VA_SYS      S3C_ADDR(0x001000000)   /* system control */
+#define S3C_VA_MEM      S3C_ADDR(0x002000000)   /* system control */
+#define S3C_VA_TIMER    S3C_ADDR(0x003000000)   /* timer block */
+#define S3C_VA_WATCHDOG S3C_ADDR(0x004000000)   /* watchdog */
+#define S3C_VA_UART     S3C_ADDR(0x010000000)   /* UART */
+#endif /* __ASM_PLAT_MAP_H */
diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/plat-s3c/nand.h
index 8816f7f9cee1..8816f7f9cee1 100644
--- a/include/asm-arm/arch-s3c2410/nand.h
+++ b/include/asm-arm/plat-s3c/nand.h
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/plat-s3c/regs-ac97.h
index b004dee6bcaf..b004dee6bcaf 100644
--- a/include/asm-arm/arch-s3c2410/regs-ac97.h
+++ b/include/asm-arm/plat-s3c/regs-ac97.h
diff --git a/include/asm-arm/arch-s3c2410/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
index c7f231963e76..c7f231963e76 100644
--- a/include/asm-arm/arch-s3c2410/regs-adc.h
+++ b/include/asm-arm/plat-s3c/regs-adc.h
diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h
index 2ae29522f253..2ae29522f253 100644
--- a/include/asm-arm/arch-s3c2410/regs-iic.h
+++ b/include/asm-arm/plat-s3c/regs-iic.h
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
index b824d371ae0b..b824d371ae0b 100644
--- a/include/asm-arm/arch-s3c2410/regs-nand.h
+++ b/include/asm-arm/plat-s3c/regs-nand.h
diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h
index 93b03c49710a..93b03c49710a 100644
--- a/include/asm-arm/arch-s3c2410/regs-rtc.h
+++ b/include/asm-arm/plat-s3c/regs-rtc.h
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
index 8946702a87f5..923e114db663 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/plat-s3c/regs-serial.h
@@ -32,10 +32,10 @@
 #ifndef __ASM_ARM_REGS_SERIAL_H
 #define __ASM_ARM_REGS_SERIAL_H
-#define S3C24XX_VA_UART0      (S3C24XX_VA_UART)
+#define S3C24XX_VA_UART0      (S3C_VA_UART)
-#define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )
+#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )
+#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C24XX_VA_UART + 0xC000 )
+#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
 #define S3C2410_PA_UART0      (S3C24XX_PA_UART)
 #define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
index 6f8fe432fe3a..8b0d594397b1 100644
--- a/include/asm-arm/arch-s3c2410/regs-timer.h
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -14,12 +14,12 @@
 #ifndef __ASM_ARCH_REGS_TIMER_H
 #define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
-#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
+#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
-#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
+#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
-#define S3C2410_TCFG0         S3C2410_TIMERREG(0x00)
+#define S3C2410_TCFG0         S3C_TIMERREG(0x00)
-#define S3C2410_TCFG1         S3C2410_TIMERREG(0x04)
+#define S3C2410_TCFG1         S3C_TIMERREG(0x04)
-#define S3C2410_TCON          S3C2410_TIMERREG(0x08)
+#define S3C2410_TCON          S3C_TIMERREG(0x08)
 #define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
 #define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
@@ -71,9 +71,9 @@
 /* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
-#define S3C2410_TCNTB(tmr)    S3C2410_TIMERREG2(tmr, 0x00)
+#define S3C2410_TCNTB(tmr)    S3C_TIMERREG2(tmr, 0x00)
-#define S3C2410_TCMPB(tmr)    S3C2410_TIMERREG2(tmr, 0x04)
+#define S3C2410_TCMPB(tmr)    S3C_TIMERREG2(tmr, 0x04)
-#define S3C2410_TCNTO(tmr)    S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
+#define S3C2410_TCNTO(tmr)    S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
 #define S3C2410_TCON_T4RELOAD     (1<<22)
 #define S3C2410_TCON_T4MANUALUPD  (1<<21)
diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h
index a9c5d491bdb6..56c4193b7a46 100644
--- a/include/asm-arm/arch-s3c2410/regs-watchdog.h
+++ b/include/asm-arm/plat-s3c/regs-watchdog.h
@@ -14,11 +14,11 @@
 #ifndef __ASM_ARCH_REGS_WATCHDOG_H
 #define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
-#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
+#define S3C_WDOGREG(x) ((x) + S3C_VA_WATCHDOG)
-#define S3C2410_WTCON      S3C2410_WDOGREG(0x00)
+#define S3C2410_WTCON      S3C_WDOGREG(0x00)
-#define S3C2410_WTDAT      S3C2410_WDOGREG(0x04)
+#define S3C2410_WTDAT      S3C_WDOGREG(0x04)
-#define S3C2410_WTCNT      S3C2410_WDOGREG(0x08)
+#define S3C2410_WTCNT      S3C_WDOGREG(0x08)
 /* the watchdog can either generate a reset pulse, or an
 * interrupt.
diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h
new file mode 100644
index 000000000000..b5e6208175d1
--- /dev/null
+++ b/include/asm-arm/plat-s3c/uncompress.h
@@ -0,0 +1,155 @@
+/* linux/include/asm-arm/plat-s3c/uncompress.h
+ *
+ * Copyright 2003, 2007 Simtec Electronics
+ *      http://armlinux.simtec.co.uk/
+ *      Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C - uncompress code
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+#ifndef __ASM_PLAT_UNCOMPRESS_H
+#define __ASM_PLAT_UNCOMPRESS_H
+typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
+/* uart setup */
+static unsigned int fifo_mask;
+static unsigned int fifo_max;
+/* forward declerations */
+static void arch_detect_cpu(void);
+/* defines for UART registers */
+#include "asm/plat-s3c/regs-serial.h"
+#include "asm/plat-s3c/regs-watchdog.h"
+/* working in physical space... */
+#undef S3C2410_WDOGREG
+#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
+/* how many bytes we allow into the FIFO at a time in FIFO mode */
+#define FIFO_MAX         (14)
+#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
+static __inline__ void
+uart_wr(unsigned int reg, unsigned int val)
+{
+        volatile unsigned int *ptr;
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        *ptr = val;
+}
+static __inline__ unsigned int
+uart_rd(unsigned int reg)
+{
+        volatile unsigned int *ptr;
+        ptr = (volatile unsigned int *)(reg + uart_base);
+        return *ptr;
+}
+/* we can deal with the case the UARTs are being run
+ * in FIFO mode, so that we don't hold up our execution
+ * waiting for tx to happen...
+*/
+static void putc(int ch)
+{
+        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
+                int level;
+                while (1) {
+                        level = uart_rd(S3C2410_UFSTAT);
+                        level &= fifo_mask;
+                        if (level < fifo_max)
+                                break;
+                }
+        } else {
+                /* not using fifos */
+                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
+                        barrier();
+        }
+        /* write byte to transmission register */
+        uart_wr(S3C2410_UTXH, ch);
+}
+static inline void flush(void)
+{
+}
+#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
+/* CONFIG_S3C_BOOT_WATCHDOG
+ *
+ * Simple boot-time watchdog setup, to reboot the system if there is
+ * any problem with the boot process
+*/
+#ifdef CONFIG_S3C_BOOT_WATCHDOG
+#define WDOG_COUNT (0xff00)
+static inline void arch_decomp_wdog(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+}
+static void arch_decomp_wdog_start(void)
+{
+        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
+        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
+}
+#else
+#define arch_decomp_wdog_start()
+#define arch_decomp_wdog()
+#endif
+#ifdef CONFIG_S3C_BOOT_ERROR_RESET
+static void arch_decomp_error(const char *x)
+{
+        putstr("\n\n");
+        putstr(x);
+        putstr("\n\n -- System resetting\n");
+        __raw_writel(0x4000, S3C2410_WTDAT);
+        __raw_writel(0x4000, S3C2410_WTCNT);
+        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
+        while(1);
+}
+#define arch_error arch_decomp_error
+#endif
+static void error(char *err);
+static void
+arch_decomp_setup(void)
+{
+        /* we may need to setup the uart(s) here if we are not running
+         * on an BAST... the BAST will have left the uarts configured
+         * after calling linux.
+         */
+        arch_detect_cpu();
+        arch_decomp_wdog_start();
+}
+#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-iis.h b/include/asm-arm/plat-s3c24xx/regs-iis.h
index eaf77916a602..eaf77916a602 100644
--- a/include/asm-arm/arch-s3c2410/regs-iis.h
+++ b/include/asm-arm/plat-s3c24xx/regs-iis.h
diff --git a/include/asm-arm/arch-s3c2410/regs-spi.h b/include/asm-arm/plat-s3c24xx/regs-spi.h
index 4a499a138256..4a499a138256 100644
--- a/include/asm-arm/arch-s3c2410/regs-spi.h
+++ b/include/asm-arm/plat-s3c24xx/regs-spi.h
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/plat-s3c24xx/regs-udc.h
index e1e9805d2d9a..e1e9805d2d9a 100644
--- a/include/asm-arm/arch-s3c2410/regs-udc.h
+++ b/include/asm-arm/plat-s3c24xx/regs-udc.h
diff --git a/include/asm-arm/arch-s3c2410/udc.h b/include/asm-arm/plat-s3c24xx/udc.h
index b8aa6cb69b58..b8aa6cb69b58 100644
--- a/include/asm-arm/arch-s3c2410/udc.h
+++ b/include/asm-arm/plat-s3c24xx/udc.h
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index ee3d93c281d8..7aaa206cb54e 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -10,6 +10,8 @@
 #ifndef __ASM_ARM_PTRACE_H
 #define __ASM_ARM_PTRACE_H
+#include <asm/hwcap.h>
 #define PTRACE_GETREGS          12
 #define PTRACE_SETREGS          13
 #define PTRACE_GETFPREGS        14
@@ -45,6 +47,7 @@
 #define PSR_T_BIT       0x00000020
 #define PSR_F_BIT       0x00000040
 #define PSR_I_BIT       0x00000080
+#define PSR_A_BIT       0x00000100
 #define PSR_J_BIT       0x01000000
 #define PSR_Q_BIT       0x08000000
 #define PSR_V_BIT       0x10000000
@@ -103,6 +106,10 @@ struct pt_regs {
 #define thumb_mode(regs) (0)
 #endif
+#define isa_mode(regs) \
+        ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
+         (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
 #define processor_mode(regs) \
        ((regs)->ARM_cpsr & MODE_MASK)
@@ -117,14 +124,17 @@ struct pt_regs {
 */
 static inline int valid_user_regs(struct pt_regs *regs)
 {
-        if (user_mode(regs) &&
+        if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
-            (regs->ARM_cpsr & (PSR_F_BIT|PSR_I_BIT)) == 0)
+                regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
                return 1;
+        }
        /*
         * Force CPSR to something logical...
         */
-        regs->ARM_cpsr &= PSR_f | PSR_s | PSR_x | PSR_T_BIT | MODE32_BIT;
+        regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
+        if (!(elf_hwcap & HWCAP_26BIT))
+                regs->ARM_cpsr |= USR_MODE;
        return 0;
 }
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 6f8e6a69dc5f..94ea8c6dc1a4 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -254,16 +254,6 @@ do {									\
        last = __switch_to(prev,task_thread_info(prev), task_thread_info(next));        \
 } while (0)
-/*
- * On SMP systems, when the scheduler does migration-cost autodetection,
- * it needs a way to flush as much of the CPU's caches as possible.
- *
- * TODO: fill this in!
- */
-static inline void sched_cacheflush(void)
-{
-}
 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
 /*
 * On the StrongARM, "swp" is terminally broken since it bypasses the
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index eae85b09db2e..69c65d56a6ac 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -24,7 +24,6 @@
 struct task_struct;
 struct exec_domain;
-#include <asm/ptrace.h>
 #include <asm/types.h>
 #include <asm/domain.h>
diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h
index bfdbebebdc1b..d327b25c986c 100644
--- a/include/asm-arm/unistd.h
+++ b/include/asm-arm/unistd.h
@@ -441,7 +441,6 @@
 /*
 * Unimplemented (or alternatively implemented) syscalls
 */
-#define __IGNORE_sync_file_range        1
 #define __IGNORE_fadvise64_64           1
 #endif /* __KERNEL__ */
diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index 14c5e0946c47..bd6be9d7f772 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -26,8 +26,8 @@
 #define FPSID_REV_MASK          (0xF  << FPSID_REV_BIT)
 /* FPEXC bits */
-#define FPEXC_EXCEPTION         (1<<31)
+#define FPEXC_EX                (1 << 31)
-#define FPEXC_ENABLE            (1<<30)
+#define FPEXC_EN                (1 << 30)
 /* FPSCR bits */
 #define FPSCR_DEFAULT_NAN       (1<<25)
author	David Woodhouse <dwmw2@infradead.org>	2007-07-23 05:20:10 -0400
committer	David Woodhouse <dwmw2@infradead.org>	2007-07-23 05:20:10 -0400
commit	39fe5434cb9de5da40510028b17b96bc4eb312b3 (patch)
tree	7a02a317b9ad57da51ca99887c119e779ccf3f13 /include/asm-arm
parent	0fc72b81d3111d114ab378935b1cf07680ca1289 (diff)
parent	f695baf2df9e0413d3521661070103711545207a (diff)