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authorAndrew Victor <andrew@sanpeople.com>2007-05-08 02:51:23 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-05-08 15:45:21 -0400
commitb85fe92766dfc0c4e803cb0cead4c780cd0c02f9 (patch)
tree1a1a829bf16eae2d7803eb739618db2e5eb43766 /include/asm-arm
parent8eef3896b352a8760ab04293174444da4e8c8127 (diff)
[ARM] 4363/1: AT91: Remove legacy PIO definitions
Remove the legacy PIO pin definitions for the AT91 processors. The standard (and portable between the different AT91 processors) method is to use the AT91_PIN_* defines and the GPIO API. Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-at91/at91rm9200.h181
-rw-r--r--include/asm-arm/arch-at91/at91sam9260.h9
-rw-r--r--include/asm-arm/arch-at91/at91sam9261.h191
-rw-r--r--include/asm-arm/arch-at91/at91sam9263.h8
4 files changed, 0 insertions, 389 deletions
diff --git a/include/asm-arm/arch-at91/at91rm9200.h b/include/asm-arm/arch-at91/at91rm9200.h
index a12ac8ab2ad0..802891a9cd81 100644
--- a/include/asm-arm/arch-at91/at91rm9200.h
+++ b/include/asm-arm/arch-at91/at91rm9200.h
@@ -107,185 +107,4 @@
107#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */ 107#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
108 108
109 109
110#if 0
111/*
112 * PIO pin definitions (peripheral A/B multiplexing).
113 */
114#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */
115#define AT91_PA0_PCK3 (1 << 0) /* B: PMC Programmable Clock Output 3 */
116#define AT91_PA1_MOSI (1 << 1) /* A: SPI Master-Out Slave-In */
117#define AT91_PA1_PCK0 (1 << 1) /* B: PMC Programmable Clock Output 0 */
118#define AT91_PA2_SPCK (1 << 2) /* A: SPI Serial Clock */
119#define AT91_PA2_IRQ4 (1 << 2) /* B: External Interrupt 4 */
120#define AT91_PA3_NPCS0 (1 << 3) /* A: SPI Peripheral Chip Select 0 */
121#define AT91_PA3_IRQ5 (1 << 3) /* B: External Interrupt 5 */
122#define AT91_PA4_NPCS1 (1 << 4) /* A: SPI Peripheral Chip Select 1 */
123#define AT91_PA4_PCK1 (1 << 4) /* B: PMC Programmable Clock Output 1 */
124#define AT91_PA5_NPCS2 (1 << 5) /* A: SPI Peripheral Chip Select 2 */
125#define AT91_PA5_TXD3 (1 << 5) /* B: USART Transmit Data 3 */
126#define AT91_PA6_NPCS3 (1 << 6) /* A: SPI Peripheral Chip Select 3 */
127#define AT91_PA6_RXD3 (1 << 6) /* B: USART Receive Data 3 */
128#define AT91_PA7_ETXCK_EREFCK (1 << 7) /* A: Ethernet Reference Clock / Transmit Clock */
129#define AT91_PA7_PCK2 (1 << 7) /* B: PMC Programmable Clock Output 2 */
130#define AT91_PA8_ETXEN (1 << 8) /* A: Ethernet Transmit Enable */
131#define AT91_PA8_MCCDB (1 << 8) /* B: MMC Multimedia Card B Command */
132#define AT91_PA9_ETX0 (1 << 9) /* A: Ethernet Transmit Data 0 */
133#define AT91_PA9_MCDB0 (1 << 9) /* B: MMC Multimedia Card B Data 0 */
134#define AT91_PA10_ETX1 (1 << 10) /* A: Ethernet Transmit Data 1 */
135#define AT91_PA10_MCDB1 (1 << 10) /* B: MMC Multimedia Card B Data 1 */
136#define AT91_PA11_ECRS_ECRSDV (1 << 11) /* A: Ethernet Carrier Sense / Data Valid */
137#define AT91_PA11_MCDB2 (1 << 11) /* B: MMC Multimedia Card B Data 2 */
138#define AT91_PA12_ERX0 (1 << 12) /* A: Ethernet Receive Data 0 */
139#define AT91_PA12_MCDB3 (1 << 12) /* B: MMC Multimedia Card B Data 3 */
140#define AT91_PA13_ERX1 (1 << 13) /* A: Ethernet Receive Data 1 */
141#define AT91_PA13_TCLK0 (1 << 13) /* B: TC External Clock Input 0 */
142#define AT91_PA14_ERXER (1 << 14) /* A: Ethernet Receive Error */
143#define AT91_PA14_TCLK1 (1 << 14) /* B: TC External Clock Input 1 */
144#define AT91_PA15_EMDC (1 << 15) /* A: Ethernet Management Data Clock */
145#define AT91_PA15_TCLK2 (1 << 15) /* B: TC External Clock Input 2 */
146#define AT91_PA16_EMDIO (1 << 16) /* A: Ethernet Management Data I/O */
147#define AT91_PA16_IRQ6 (1 << 16) /* B: External Interrupt 6 */
148#define AT91_PA17_TXD0 (1 << 17) /* A: USART Transmit Data 0 */
149#define AT91_PA17_TIOA0 (1 << 17) /* B: TC I/O Line A 0 */
150#define AT91_PA18_RXD0 (1 << 18) /* A: USART Receive Data 0 */
151#define AT91_PA18_TIOB0 (1 << 18) /* B: TC I/O Line B 0 */
152#define AT91_PA19_SCK0 (1 << 19) /* A: USART Serial Clock 0 */
153#define AT91_PA19_TIOA1 (1 << 19) /* B: TC I/O Line A 1 */
154#define AT91_PA20_CTS0 (1 << 20) /* A: USART Clear To Send 0 */
155#define AT91_PA20_TIOB1 (1 << 20) /* B: TC I/O Line B 1 */
156#define AT91_PA21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
157#define AT91_PA21_TIOA2 (1 << 21) /* B: TC I/O Line A 2 */
158#define AT91_PA22_RXD2 (1 << 22) /* A: USART Receive Data 2 */
159#define AT91_PA22_TIOB2 (1 << 22) /* B: TC I/O Line B 2 */
160#define AT91_PA23_TXD2 (1 << 23) /* A: USART Transmit Data 2 */
161#define AT91_PA23_IRQ3 (1 << 23) /* B: External Interrupt 3 */
162#define AT91_PA24_SCK2 (1 << 24) /* A: USART Serial Clock 2 */
163#define AT91_PA24_PCK1 (1 << 24) /* B: PMC Programmable Clock Output 1 */
164#define AT91_PA25_TWD (1 << 25) /* A: TWI Two-wire Serial Data */
165#define AT91_PA25_IRQ2 (1 << 25) /* B: External Interrupt 2 */
166#define AT91_PA26_TWCK (1 << 26) /* A: TWI Two-wire Serial Clock */
167#define AT91_PA26_IRQ1 (1 << 26) /* B: External Interrupt 1 */
168#define AT91_PA27_MCCK (1 << 27) /* A: MMC Multimedia Card Clock */
169#define AT91_PA27_TCLK3 (1 << 27) /* B: TC External Clock Input 3 */
170#define AT91_PA28_MCCDA (1 << 28) /* A: MMC Multimedia Card A Command */
171#define AT91_PA28_TCLK4 (1 << 28) /* B: TC External Clock Input 4 */
172#define AT91_PA29_MCDA0 (1 << 29) /* A: MMC Multimedia Card A Data 0 */
173#define AT91_PA29_TCLK5 (1 << 29) /* B: TC External Clock Input 5 */
174#define AT91_PA30_DRXD (1 << 30) /* A: DBGU Receive Data */
175#define AT91_PA30_CTS2 (1 << 30) /* B: USART Clear To Send 2 */
176#define AT91_PA31_DTXD (1 << 31) /* A: DBGU Transmit Data */
177#define AT91_PA31_RTS2 (1 << 31) /* B: USART Ready To Send 2 */
178
179#define AT91_PB0_TF0 (1 << 0) /* A: SSC Transmit Frame Sync 0 */
180#define AT91_PB0_RTS3 (1 << 0) /* B: USART Ready To Send 3 */
181#define AT91_PB1_TK0 (1 << 1) /* A: SSC Transmit Clock 0 */
182#define AT91_PB1_CTS3 (1 << 1) /* B: USART Clear To Send 3 */
183#define AT91_PB2_TD0 (1 << 2) /* A: SSC Transmit Data 0 */
184#define AT91_PB2_SCK3 (1 << 2) /* B: USART Serial Clock 3 */
185#define AT91_PB3_RD0 (1 << 3) /* A: SSC Receive Data 0 */
186#define AT91_PB3_MCDA1 (1 << 3) /* B: MMC Multimedia Card A Data 1 */
187#define AT91_PB4_RK0 (1 << 4) /* A: SSC Receive Clock 0 */
188#define AT91_PB4_MCDA2 (1 << 4) /* B: MMC Multimedia Card A Data 2 */
189#define AT91_PB5_RF0 (1 << 5) /* A: SSC Receive Frame Sync 0 */
190#define AT91_PB5_MCDA3 (1 << 5) /* B: MMC Multimedia Card A Data 3 */
191#define AT91_PB6_TF1 (1 << 6) /* A: SSC Transmit Frame Sync 1 */
192#define AT91_PB6_TIOA3 (1 << 6) /* B: TC I/O Line A 3 */
193#define AT91_PB7_TK1 (1 << 7) /* A: SSC Transmit Clock 1 */
194#define AT91_PB7_TIOB3 (1 << 7) /* B: TC I/O Line B 3 */
195#define AT91_PB8_TD1 (1 << 8) /* A: SSC Transmit Data 1 */
196#define AT91_PB8_TIOA4 (1 << 8) /* B: TC I/O Line A 4 */
197#define AT91_PB9_RD1 (1 << 9) /* A: SSC Receive Data 1 */
198#define AT91_PB9_TIOB4 (1 << 9) /* B: TC I/O Line B 4 */
199#define AT91_PB10_RK1 (1 << 10) /* A: SSC Receive Clock 1 */
200#define AT91_PB10_TIOA5 (1 << 10) /* B: TC I/O Line A 5 */
201#define AT91_PB11_RF1 (1 << 11) /* A: SSC Receive Frame Sync 1 */
202#define AT91_PB11_TIOB5 (1 << 11) /* B: TC I/O Line B 5 */
203#define AT91_PB12_TF2 (1 << 12) /* A: SSC Transmit Frame Sync 2 */
204#define AT91_PB12_ETX2 (1 << 12) /* B: Ethernet Transmit Data 2 */
205#define AT91_PB13_TK2 (1 << 13) /* A: SSC Transmit Clock 3 */
206#define AT91_PB13_ETX3 (1 << 13) /* B: Ethernet Transmit Data 3 */
207#define AT91_PB14_TD2 (1 << 14) /* A: SSC Transmit Data 2 */
208#define AT91_PB14_ETXER (1 << 14) /* B: Ethernet Transmit Coding Error */
209#define AT91_PB15_RD2 (1 << 15) /* A: SSC Receive Data 2 */
210#define AT91_PB15_ERX2 (1 << 15) /* B: Ethernet Receive Data 2 */
211#define AT91_PB16_RK2 (1 << 16) /* A: SSC Receive Clock 2 */
212#define AT91_PB16_ERX3 (1 << 16) /* B: Ethernet Receive Data 3 */
213#define AT91_PB17_RF2 (1 << 17) /* A: SSC Receive Frame Sync 2 */
214#define AT91_PB17_ERXDV (1 << 17) /* B: Ethernet Receive Data Valid */
215#define AT91_PB18_RI1 (1 << 18) /* A: USART Ring Indicator 1 */
216#define AT91_PB18_ECOL (1 << 18) /* B: Ethernet Collision Detected */
217#define AT91_PB19_DTR1 (1 << 19) /* A: USART Data Terminal Ready 1 */
218#define AT91_PB19_ERXCK (1 << 19) /* B: Ethernet Receive Clock */
219#define AT91_PB20_TXD1 (1 << 20) /* A: USART Transmit Data 1 */
220#define AT91_PB21_RXD1 (1 << 21) /* A: USART Receive Data 1 */
221#define AT91_PB22_SCK1 (1 << 22) /* A: USART Serial Clock 1 */
222#define AT91_PB23_DCD1 (1 << 23) /* A: USART Data Carrier Detect 1 */
223#define AT91_PB24_CTS1 (1 << 24) /* A: USART Clear To Send 1 */
224#define AT91_PB25_DSR1 (1 << 25) /* A: USART Data Set Ready 1 */
225#define AT91_PB25_EF100 (1 << 25) /* B: Ethernet Force 100 Mbit */
226#define AT91_PB26_RTS1 (1 << 26) /* A: USART Ready To Send 1 */
227#define AT91_PB27_PCK0 (1 << 27) /* B: PMC Programmable Clock Output 0 */
228#define AT91_PB28_FIQ (1 << 28) /* A: Fast Interrupt */
229#define AT91_PB29_IRQ0 (1 << 29) /* A: External Interrupt 0 */
230
231#define AT91_PC0_BFCK (1 << 0) /* A: Burst Flash Clock */
232#define AT91_PC1_BFRDY_SMOE (1 << 1) /* A: Burst Flash Ready / SmartMedia Output Enable */
233#define AT91_PC2_BFAVD (1 << 2) /* A: Burst Flash Address Valid */
234#define AT91_PC3_BFBAA_SMWE (1 << 3) /* A: Burst Flash Address Advance / SmartMedia Write Enable */
235#define AT91_PC4_BFOE (1 << 4) /* A: Burst Flash Output Enable */
236#define AT91_PC5_BFWE (1 << 5) /* A: Burst Flash Write Enable */
237#define AT91_PC6_NWAIT (1 << 6) /* A: SMC Wait Signal */
238#define AT91_PC7_A23 (1 << 7) /* A: Address Bus 23 */
239#define AT91_PC8_A24 (1 << 8) /* A: Address Bus 24 */
240#define AT91_PC9_A25_CFRNW (1 << 9) /* A: Address Bus 25 / Compact Flash Read Not Write */
241#define AT91_PC10_NCS4_CFCS (1 << 10) /* A: SMC Chip Select 4 / Compact Flash Chip Select */
242#define AT91_PC11_NCS5_CFCE1 (1 << 11) /* A: SMC Chip Select 5 / Compact Flash Chip Enable 1 */
243#define AT91_PC12_NCS6_CFCE2 (1 << 12) /* A: SMC Chip Select 6 / Compact Flash Chip Enable 2 */
244#define AT91_PC13_NCS7 (1 << 13) /* A: Chip Select 7 */
245
246#define AT91_PD0_ETX0 (1 << 0) /* A: Ethernet Transmit Data 0 */
247#define AT91_PD1_ETX1 (1 << 1) /* A: Ethernet Transmit Data 1 */
248#define AT91_PD2_ETX2 (1 << 2) /* A: Ethernet Transmit Data 2 */
249#define AT91_PD3_ETX3 (1 << 3) /* A: Ethernet Transmit Data 3 */
250#define AT91_PD4_ETXEN (1 << 4) /* A: Ethernet Transmit Enable */
251#define AT91_PD5_ETXER (1 << 5) /* A: Ethernet Transmit Coding Error */
252#define AT91_PD6_DTXD (1 << 6) /* A: DBGU Transmit Data */
253#define AT91_PD7_PCK0 (1 << 7) /* A: PMC Programmable Clock Output 0 */
254#define AT91_PD7_TSYNC (1 << 7) /* B: ETM Trace Synchronization Signal */
255#define AT91_PD8_PCK1 (1 << 8) /* A: PMC Programmable Clock Output 1 */
256#define AT91_PD8_TCLK (1 << 8) /* B: ETM Trace Clock */
257#define AT91_PD9_PCK2 (1 << 9) /* A: PMC Programmable Clock Output 2 */
258#define AT91_PD9_TPS0 (1 << 9) /* B: ETM Trace ARM Pipeline Status 0 */
259#define AT91_PD10_PCK3 (1 << 10) /* A: PMC Programmable Clock Output 3 */
260#define AT91_PD10_TPS1 (1 << 10) /* B: ETM Trace ARM Pipeline Status 1 */
261#define AT91_PD11_TPS2 (1 << 11) /* B: ETM Trace ARM Pipeline Status 2 */
262#define AT91_PD12_TPK0 (1 << 12) /* B: ETM Trace Packet Port 0 */
263#define AT91_PD13_TPK1 (1 << 13) /* B: ETM Trace Packet Port 1 */
264#define AT91_PD14_TPK2 (1 << 14) /* B: ETM Trace Packet Port 2 */
265#define AT91_PD15_TD0 (1 << 15) /* A: SSC Transmit Data 0 */
266#define AT91_PD15_TPK3 (1 << 15) /* B: ETM Trace Packet Port 3 */
267#define AT91_PD16_TD1 (1 << 16) /* A: SSC Transmit Data 1 */
268#define AT91_PD16_TPK4 (1 << 16) /* B: ETM Trace Packet Port 4 */
269#define AT91_PD17_TD2 (1 << 17) /* A: SSC Transmit Data 2 */
270#define AT91_PD17_TPK5 (1 << 17) /* B: ETM Trace Packet Port 5 */
271#define AT91_PD18_NPCS1 (1 << 18) /* A: SPI Peripheral Chip Select 1 */
272#define AT91_PD18_TPK6 (1 << 18) /* B: ETM Trace Packet Port 6 */
273#define AT91_PD19_NPCS2 (1 << 19) /* A: SPI Peripheral Chip Select 2 */
274#define AT91_PD19_TPK7 (1 << 19) /* B: ETM Trace Packet Port 7 */
275#define AT91_PD20_NPCS3 (1 << 20) /* A: SPI Peripheral Chip Select 3 */
276#define AT91_PD20_TPK8 (1 << 20) /* B: ETM Trace Packet Port 8 */
277#define AT91_PD21_RTS0 (1 << 21) /* A: USART Ready To Send 0 */
278#define AT91_PD21_TPK9 (1 << 21) /* B: ETM Trace Packet Port 9 */
279#define AT91_PD22_RTS1 (1 << 22) /* A: USART Ready To Send 1 */
280#define AT91_PD22_TPK10 (1 << 22) /* B: ETM Trace Packet Port 10 */
281#define AT91_PD23_RTS2 (1 << 23) /* A: USART Ready To Send 2 */
282#define AT91_PD23_TPK11 (1 << 23) /* B: ETM Trace Packet Port 11 */
283#define AT91_PD24_RTS3 (1 << 24) /* A: USART Ready To Send 3 */
284#define AT91_PD24_TPK12 (1 << 24) /* B: ETM Trace Packet Port 12 */
285#define AT91_PD25_DTR1 (1 << 25) /* A: USART Data Terminal Ready 1 */
286#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
287#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
288#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
289#endif
290
291#endif 110#endif
diff --git a/include/asm-arm/arch-at91/at91sam9260.h b/include/asm-arm/arch-at91/at91sam9260.h
index 2cadebc36af7..0427f8698c07 100644
--- a/include/asm-arm/arch-at91/at91sam9260.h
+++ b/include/asm-arm/arch-at91/at91sam9260.h
@@ -117,13 +117,4 @@
117#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 117#define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
118 118
119 119
120#if 0
121/*
122 * PIO pin definitions (peripheral A/B multiplexing).
123 */
124
125// TODO: Add
126
127#endif
128
129#endif 120#endif
diff --git a/include/asm-arm/arch-at91/at91sam9261.h b/include/asm-arm/arch-at91/at91sam9261.h
index 01b58ffe2e27..9eb459570330 100644
--- a/include/asm-arm/arch-at91/at91sam9261.h
+++ b/include/asm-arm/arch-at91/at91sam9261.h
@@ -98,195 +98,4 @@
98#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */ 98#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
99 99
100 100
101#if 0
102/*
103 * PIO pin definitions (peripheral A/B multiplexing).
104 */
105#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */
106#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */
107#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */
108#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */
109#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */
110#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */
111#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */
112#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */
113#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */
114#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */
115#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */
116#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */
117#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */
118#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */
119#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */
120#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */
121#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */
122#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */
123#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */
124#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */
125#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */
126#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */
127#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */
128#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */
129#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */
130#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */
131#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */
132#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */
133#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */
134#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */
135#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */
136#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */
137#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */
138#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */
139#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */
140#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */
141#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */
142#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */
143#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */
144#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */
145#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */
146#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */
147#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */
148#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */
149#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */
150#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */
151#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */
152#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */
153#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */
154#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */
155#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */
156#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */
157#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */
158#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */
159#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */
160#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */
161#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */
162#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */
163#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */
164#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */
165#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */
166#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */
167#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */
168
169#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */
170#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */
171#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */
172#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */
173#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */
174#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */
175#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */
176#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */
177#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */
178#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */
179#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */
180#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */
181#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */
182#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */
183#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */
184#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */
185#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */
186#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */
187#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */
188#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */
189#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */
190#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */
191#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */
192#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */
193#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */
194#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */
195#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */
196#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */
197#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */
198#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */
199#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */
200#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */
201#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */
202#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */
203#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */
204#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */
205#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */
206#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */
207#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */
208#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */
209#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */
210#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */
211#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */
212#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */
213#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */
214#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */
215#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */
216#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */
217#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */
218#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */
219#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */
220#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */
221#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */
222#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */
223#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */
224#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */
225#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */
226#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */
227#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */
228#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */
229#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */
230
231#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */
232#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */
233#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */
234#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */
235#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */
236#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */
237#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */
238#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */
239#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */
240#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */
241#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */
242#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */
243#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */
244#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */
245#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */
246#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */
247#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */
248#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */
249#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */
250#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */
251#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */
252#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */
253#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */
254#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */
255#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */
256#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */
257#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */
258#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */
259#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */
260#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */
261#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */
262#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */
263#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */
264#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */
265#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
266#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */
267#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
268#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */
269#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
270#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */
271#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
272#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */
273#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
274#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */
275#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
276#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */
277#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */
278#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */
279#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */
280#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */
281#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */
282#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */
283#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */
284#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */
285#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */
286#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */
287#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */
288#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */
289#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */
290#endif
291
292#endif 101#endif
diff --git a/include/asm-arm/arch-at91/at91sam9263.h b/include/asm-arm/arch-at91/at91sam9263.h
index f4af68ae0ea9..115c47ac7ebb 100644
--- a/include/asm-arm/arch-at91/at91sam9263.h
+++ b/include/asm-arm/arch-at91/at91sam9263.h
@@ -119,13 +119,5 @@
119#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */ 119#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
120#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */ 120#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
121 121
122#if 0
123/*
124 * PIO pin definitions (peripheral A/B multiplexing).
125 */
126
127// TODO: Add
128
129#endif
130 122
131#endif 123#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-06 09:34:46 -0500