diff options
author | Kenneth Tan <chong.yin.tan@intel.com> | 2005-10-18 02:53:35 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2005-10-18 02:53:35 -0400 |
commit | 251b928cdff5f12e7da8f56e8933e2b58ba08456 (patch) | |
tree | dc978d9a44e865063b1cfb4606c03bae1b6e4eab /include/asm-arm | |
parent | ad1b472bea1bbcd8dc7fd92f6952d8b2d8355edb (diff) |
[ARM] 3021/1: Interrupt 0 bug fix for ixp4xx
Patch from Kenneth Tan
The get_irqnr_and_base subroutine of ixp4xx does not take interrupt 0 condition into account properly. We should not perform "subs" here. The Z flag will be set when interrupt 0 occur, which resulting "movne r1, sp" in the caller routine (irq_handler) not being executed.
When interrupt 0 occur:
o if CONFIG_CPU_IXP46X is not set, "subs" will set the Z flag and return
o if CONFIG_CPU_IXP46X is set, codes in upper interrupt handling will be trigerred. But since this is not supper interrupt, the "cmp" in the upper interrupt handling portion will set the Z flag and return
Signed-off-by: Kenneth Tan <chong.yin.tan@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r-- | include/asm-arm/arch-ixp4xx/entry-macro.S | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S index 455da64832de..323b0bc4a39c 100644 --- a/include/asm-arm/arch-ixp4xx/entry-macro.S +++ b/include/asm-arm/arch-ixp4xx/entry-macro.S | |||
@@ -15,25 +15,26 @@ | |||
15 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) | 15 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET) |
16 | ldr \irqstat, [\irqstat] @ get interrupts | 16 | ldr \irqstat, [\irqstat] @ get interrupts |
17 | cmp \irqstat, #0 | 17 | cmp \irqstat, #0 |
18 | beq 1001f | 18 | beq 1001f @ upper IRQ? |
19 | clz \irqnr, \irqstat | 19 | clz \irqnr, \irqstat |
20 | mov \base, #31 | 20 | mov \base, #31 |
21 | subs \irqnr, \base, \irqnr | 21 | sub \irqnr, \base, \irqnr |
22 | b 1002f @ lower IRQ being | ||
23 | @ handled | ||
22 | 24 | ||
23 | 1001: | 25 | 1001: |
24 | /* | 26 | /* |
25 | * IXP465 has an upper IRQ status register | 27 | * IXP465 has an upper IRQ status register |
26 | */ | 28 | */ |
27 | #if defined(CONFIG_CPU_IXP46X) | 29 | #if defined(CONFIG_CPU_IXP46X) |
28 | bne 1002f | ||
29 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET) | 30 | ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET) |
30 | ldr \irqstat, [\irqstat] @ get upper interrupts | 31 | ldr \irqstat, [\irqstat] @ get upper interrupts |
31 | mov \irqnr, #63 | 32 | mov \irqnr, #63 |
32 | clz \irqstat, \irqstat | 33 | clz \irqstat, \irqstat |
33 | cmp \irqstat, #32 | 34 | cmp \irqstat, #32 |
34 | subne \irqnr, \irqnr, \irqstat | 35 | subne \irqnr, \irqnr, \irqstat |
35 | 1002: | ||
36 | #endif | 36 | #endif |
37 | 1002: | ||
37 | .endm | 38 | .endm |
38 | 39 | ||
39 | 40 | ||