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authorAdrian Bunk <bunk@stusta.de>2006-06-30 12:23:39 -0400
committerAdrian Bunk <bunk@stusta.de>2006-06-30 12:23:39 -0400
commitfd245f00695cbcf0f8430f35841c216559d243df (patch)
tree20d1a5a98e5d626ce8215316b16c8cdf392995a7 /include/asm-arm
parent0418726bb5c7b5a70c7e7e82e860d5979d0c78cf (diff)
typo fixes: disadvantadge -> disadvantage
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index b59520e56fc7..0d517267fb63 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -38,7 +38,7 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
38 * 2) If > 64MB of memory space is required, the IXP4xx can be configured 38 * 2) If > 64MB of memory space is required, the IXP4xx can be configured
39 * to use indirect registers to access PCI (as we do below for I/O 39 * to use indirect registers to access PCI (as we do below for I/O
40 * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff) 40 * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
41 * of memory on the bus. The disadvantadge of this is that every 41 * of memory on the bus. The disadvantage of this is that every
42 * PCI access requires three local register accesses plus a spinlock, 42 * PCI access requires three local register accesses plus a spinlock,
43 * but in some cases the performance hit is acceptable. In addition, 43 * but in some cases the performance hit is acceptable. In addition,
44 * you cannot mmap() PCI devices in this case. 44 * you cannot mmap() PCI devices in this case.