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authorPavel Pisa <ppisa@pikron.com>2007-05-12 09:31:17 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-12 06:11:39 -0400
commitb3e6a508ed920698d367e5993ed056d70364d91f (patch)
tree4097af7112f18f4e610d16d46c95746f6d1621a6 /include/asm-arm
parent7dcca30a32aadb0520417521b0c44f42d09fe05c (diff)
[ARM] 4373/1: i.MX/MX1 GPIO support implementation
Support for generic input output for MX1 family. The implementation prevents allocation of one pin by two users, but does not store pointer to the user description permanently, because this solution would have bigger memory overhead. The simple way to integrate code with per BSP pins setup and allocation is required else all GPIO registration checking is useless. The function imx_gpio_setup_multiple_pins() can be used for this purpose in future. Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-imx/gpio.h102
-rw-r--r--include/asm-arm/arch-imx/imx-regs.h2
2 files changed, 104 insertions, 0 deletions
diff --git a/include/asm-arm/arch-imx/gpio.h b/include/asm-arm/arch-imx/gpio.h
new file mode 100644
index 000000000000..486023263f32
--- /dev/null
+++ b/include/asm-arm/arch-imx/gpio.h
@@ -0,0 +1,102 @@
1#ifndef _IMX_GPIO_H
2
3#include <asm/arch/imx-regs.h>
4
5#define IMX_GPIO_ALLOC_MODE_NORMAL 0
6#define IMX_GPIO_ALLOC_MODE_NO_ALLOC 1
7#define IMX_GPIO_ALLOC_MODE_TRY_ALLOC 2
8#define IMX_GPIO_ALLOC_MODE_ALLOC_ONLY 4
9#define IMX_GPIO_ALLOC_MODE_RELEASE 8
10
11extern int imx_gpio_request(unsigned gpio, const char *label);
12
13extern void imx_gpio_free(unsigned gpio);
14
15extern int imx_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
16 int alloc_mode, const char *label);
17
18extern int imx_gpio_direction_input(unsigned gpio);
19
20extern int imx_gpio_direction_output(unsigned gpio, int value);
21
22extern void __imx_gpio_set_value(unsigned gpio, int value);
23
24static inline int imx_gpio_get_value(unsigned gpio)
25{
26 return SSR(gpio >> GPIO_PORT_SHIFT) & (1 << (gpio & GPIO_PIN_MASK));
27}
28
29static inline void imx_gpio_set_value_inline(unsigned gpio, int value)
30{
31 unsigned long flags;
32
33 raw_local_irq_save(flags);
34 if(value)
35 DR(gpio >> GPIO_PORT_SHIFT) |= (1 << (gpio & GPIO_PIN_MASK));
36 else
37 DR(gpio >> GPIO_PORT_SHIFT) &= ~(1 << (gpio & GPIO_PIN_MASK));
38 raw_local_irq_restore(flags);
39}
40
41static inline void imx_gpio_set_value(unsigned gpio, int value)
42{
43 if(__builtin_constant_p(gpio))
44 imx_gpio_set_value_inline(gpio, value);
45 else
46 __imx_gpio_set_value(gpio, value);
47}
48
49extern int imx_gpio_to_irq(unsigned gpio);
50
51extern int imx_irq_to_gpio(unsigned irq);
52
53/*-------------------------------------------------------------------------*/
54
55/* Wrappers for "new style" GPIO calls. These calls i.MX specific versions
56 * to allow future extension of GPIO logic.
57 */
58
59static inline int gpio_request(unsigned gpio, const char *label)
60{
61 return imx_gpio_request(gpio, label);
62}
63
64static inline void gpio_free(unsigned gpio)
65{
66 imx_gpio_free(gpio);
67}
68
69static inline int gpio_direction_input(unsigned gpio)
70{
71 return imx_gpio_direction_input(gpio);
72}
73
74static inline int gpio_direction_output(unsigned gpio, int value)
75{
76 return imx_gpio_direction_output(gpio, value);
77}
78
79static inline int gpio_get_value(unsigned gpio)
80{
81 return imx_gpio_get_value(gpio);
82}
83
84static inline void gpio_set_value(unsigned gpio, int value)
85{
86 imx_gpio_set_value(gpio, value);
87}
88
89#include <asm-generic/gpio.h> /* cansleep wrappers */
90
91static inline int gpio_to_irq(unsigned gpio)
92{
93 return imx_gpio_to_irq(gpio);
94}
95
96static inline int irq_to_gpio(unsigned irq)
97{
98 return imx_irq_to_gpio(irq);
99}
100
101
102#endif
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index 30de404c61f5..fb9de2733879 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -77,6 +77,8 @@
77#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) 77#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
78#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) 78#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
79 79
80#define GPIO_PORT_MAX 3
81
80#define GPIO_PIN_MASK 0x1f 82#define GPIO_PIN_MASK 0x1f
81#define GPIO_PORT_MASK (0x3 << 5) 83#define GPIO_PORT_MASK (0x3 << 5)
82 84