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authorDan Williams <dan.j.williams@intel.com>2006-12-06 20:59:39 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-12-07 12:20:21 -0500
commit285f5fa7e9a35e75d9022f9b036ed709721c5cdf (patch)
treed977aecd1a350e2c14086005b873141d8d829e12 /include/asm-arm
parent4dbda6a50ae34d853353f15d30a166c87143408f (diff)
[ARM] 3995/1: iop13xx: add iop13xx support
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz PCI-X interface, a x8 PCI-Express interface, and other peripherals to form a system-on-a-chip RAID subsystem engine. The iop342 processor replaces the SAS controller with a second Xscale core for dual core embedded applications. The iop341 processor is the single core version of iop342. This patch supports the two Intel customer reference platforms iq81340mc for external storage and iq81340sc for direct attach (HBA) development. The developer's manual is available here: ftp://download.intel.com/design/iio/docs/31503701.pdf Changelog: * removed virtual addresses from resource definitions * cleaned up some unnecessary #include's Signed-off-by: Dan Williams <dan.j.williams@intel.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm')
-rw-r--r--include/asm-arm/arch-iop13xx/debug-macro.S26
-rw-r--r--include/asm-arm/arch-iop13xx/dma.h3
-rw-r--r--include/asm-arm/arch-iop13xx/entry-macro.S39
-rw-r--r--include/asm-arm/arch-iop13xx/hardware.h28
-rw-r--r--include/asm-arm/arch-iop13xx/io.h41
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h492
-rw-r--r--include/asm-arm/arch-iop13xx/iq81340.h31
-rw-r--r--include/asm-arm/arch-iop13xx/irqs.h207
-rw-r--r--include/asm-arm/arch-iop13xx/memory.h64
-rw-r--r--include/asm-arm/arch-iop13xx/pci.h57
-rw-r--r--include/asm-arm/arch-iop13xx/system.h59
-rw-r--r--include/asm-arm/arch-iop13xx/timex.h3
-rw-r--r--include/asm-arm/arch-iop13xx/uncompress.h24
-rw-r--r--include/asm-arm/arch-iop13xx/vmalloc.h4
14 files changed, 1078 insertions, 0 deletions
diff --git a/include/asm-arm/arch-iop13xx/debug-macro.S b/include/asm-arm/arch-iop13xx/debug-macro.S
new file mode 100644
index 000000000000..788b4e386c16
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/debug-macro.S
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-iop13xx/debug-macro.S
3 *
4 * Debugging macro include header
5 *
6 * Copyright (C) 1994-1999 Russell King
7 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 .macro addruart, rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ mmu enabled?
17 moveq \rx, #0xff000000 @ physical
18 orreq \rx, \rx, #0x00d80000
19 movne \rx, #0xfe000000 @ virtual
20 orrne \rx, \rx, #0x00e80000
21 orr \rx, \rx, #0x00002300
22 orr \rx, \rx, #0x00000040
23 .endm
24
25#define UART_SHIFT 2
26#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-iop13xx/dma.h b/include/asm-arm/arch-iop13xx/dma.h
new file mode 100644
index 000000000000..2e15da53ff79
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/dma.h
@@ -0,0 +1,3 @@
1#ifndef _IOP13XX_DMA_H
2#define _IOP13XX_DMA_H_
3#endif
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
new file mode 100644
index 000000000000..94c50283dc56
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * iop13xx low level irq macros
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 .macro disable_fiq
20 .endm
21
22 /*
23 * Note: a 1-cycle window exists where iintvec will return the value
24 * of iintbase, so we explicitly check for "bad zeros"
25 */
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mrc p15, 0, \tmp, c15, c1, 0
28 orr \tmp, \tmp, #(1 << 6)
29 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
30
31 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
32 cmp \irqnr, #0
33 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
34 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
35 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
36
37 biceq \tmp, \tmp, #(1 << 6)
38 mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts
39 .endm
diff --git a/include/asm-arm/arch-iop13xx/hardware.h b/include/asm-arm/arch-iop13xx/hardware.h
new file mode 100644
index 000000000000..8e1d56289846
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/hardware.h
@@ -0,0 +1,28 @@
1#ifndef __ASM_ARCH_HARDWARE_H
2#define __ASM_ARCH_HARDWARE_H
3#include <asm/types.h>
4
5#define pcibios_assign_all_busses() 1
6
7#ifndef __ASSEMBLY__
8extern unsigned long iop13xx_pcibios_min_io;
9extern unsigned long iop13xx_pcibios_min_mem;
10extern u16 iop13xx_dev_id(void);
11extern void iop13xx_set_atu_mmr_bases(void);
12#endif
13
14#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
15#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
16
17/*
18 * Generic chipset bits
19 *
20 */
21#include "iop13xx.h"
22
23/*
24 * Board specific bits
25 */
26#include "iq81340.h"
27
28#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h
new file mode 100644
index 000000000000..db6de2480a24
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/io.h
@@ -0,0 +1,41 @@
1/*
2 * iop13xx custom ioremap implementation
3 * Copyright (c) 2005-2006, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19#ifndef __ASM_ARM_ARCH_IO_H
20#define __ASM_ARM_ARCH_IO_H
21
22#define IO_SPACE_LIMIT 0xffffffff
23
24#define __io(a) (a)
25#define __mem_pci(a) (a)
26#define __mem_isa(a) (a)
27
28extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
29extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
30 unsigned long flags);
31extern void __iop13xx_iounmap(void __iomem *addr);
32
33extern u32 iop13xx_atue_mem_base;
34extern u32 iop13xx_atux_mem_base;
35extern size_t iop13xx_atue_mem_size;
36extern size_t iop13xx_atux_mem_size;
37
38#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
39#define __arch_iounmap(a) __iop13xx_iounmap(a)
40
41#endif
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
new file mode 100644
index 000000000000..a88522a0ff8e
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -0,0 +1,492 @@
1#ifndef _IOP13XX_HW_H_
2#define _IOP13XX_HW_H_
3
4#ifndef __ASSEMBLY__
5/* The ATU offsets can change based on the strapping */
6extern u32 iop13xx_atux_pmmr_offset;
7extern u32 iop13xx_atue_pmmr_offset;
8void iop13xx_init_irq(void);
9void iop13xx_map_io(void);
10void iop13xx_platform_init(void);
11void iop13xx_init_irq(void);
12void iop13xx_init_time(unsigned long tickrate);
13unsigned long iop13xx_gettimeoffset(void);
14
15/* handle cp6 access
16 * to do: handle access in entry-armv5.S and unify with
17 * the iop3xx implementation
18 * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
19 * when interrupts are enabled
20 */
21static inline unsigned long iop13xx_cp6_save(void)
22{
23 u32 temp, cp_flags;
24
25 asm volatile (
26 "mrc p15, 0, %1, c15, c1, 0\n\t"
27 "orr %0, %1, #(1 << 6)\n\t"
28 "mcr p15, 0, %0, c15, c1, 0\n\t"
29 : "=r" (temp), "=r"(cp_flags));
30
31 return cp_flags;
32}
33
34static inline void iop13xx_cp6_restore(unsigned long cp_flags)
35{
36 asm volatile (
37 "mcr p15, 0, %0, c15, c1, 0\n\t"
38 : : "r" (cp_flags) );
39}
40
41/* CPUID CP6 R0 Page 0 */
42static inline int iop13xx_cpu_id(void)
43{
44 int id;
45 asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
46 return id;
47}
48
49#endif
50
51/*
52 * IOP13XX I/O and Mem space regions for PCI autoconfiguration
53 */
54#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
55#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
56
57/* PCI MAP
58 * 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
59 * 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
60*/
61#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
62#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
63#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
64#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
65#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
66 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
67#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
68 IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
69#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
70 IOP13XX_PCIX_LOWER_IO_BA)
71#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
72 (IOP13XX_PCIX_LOWER_IO_PA\
73 - IOP13XX_PCIX_LOWER_IO_VA))
74
75#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
76#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
77#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
78#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
79 IOP13XX_PCIX_LOWER_MEM_BA)
80#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
81 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
82#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
83 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
84
85#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
86#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
87#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
88 IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
89#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
90 IOP13XX_PCIX_LOWER_MEM_BA)
91
92/* PCI-E ranges */
93#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
94#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
95#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
96#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
97#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
98 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
99#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
100 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
101#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
102 IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
103#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
104 IOP13XX_PCIE_LOWER_IO_BA)
105#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
106 (IOP13XX_PCIE_LOWER_IO_PA\
107 - IOP13XX_PCIE_LOWER_IO_VA))
108
109#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
110#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
111#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
112#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
113 IOP13XX_PCIE_LOWER_MEM_BA)
114#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
115 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
116#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
117 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
118
119/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
120#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
121#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
122#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
123 IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
124#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
125 IOP13XX_PCIE_LOWER_MEM_BA)
126
127/* PBI Ranges */
128#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
129#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
130#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
131#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
132#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
133 IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
134
135/*
136 * IOP13XX chipset registers
137 */
138#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
139#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
140#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
141#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
142 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
143#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
144 IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
145#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
146 (IOP13XX_PMMR_PHYS_MEM_BASE\
147 - IOP13XX_PMMR_VIRT_MEM_BASE))
148#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
149 (IOP13XX_PMMR_PHYS_MEM_BASE\
150 - IOP13XX_PMMR_VIRT_MEM_BASE))
151#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
152#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
153#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
154#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
155#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
156#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
157#define IOP13XX_PMMR_SIZE 0x00080000
158
159/*=================== Defines for Platform Devices =====================*/
160#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
161#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
162#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
163#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
164
165#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
166#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
167#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
168#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
169#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
170#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
171
172/* ATU selection flags */
173/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
174#define IOP13XX_INIT_ATU_DEFAULT (0)
175#define IOP13XX_INIT_ATU_ATUX (1 << 0)
176#define IOP13XX_INIT_ATU_ATUE (1 << 1)
177#define IOP13XX_INIT_ATU_NONE (1 << 2)
178
179/* UART selection flags */
180/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
181#define IOP13XX_INIT_UART_DEFAULT (0)
182#define IOP13XX_INIT_UART_0 (1 << 0)
183#define IOP13XX_INIT_UART_1 (1 << 1)
184
185/* I2C selection flags */
186/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
187#define IOP13XX_INIT_I2C_DEFAULT (0)
188#define IOP13XX_INIT_I2C_0 (1 << 0)
189#define IOP13XX_INIT_I2C_1 (1 << 1)
190#define IOP13XX_INIT_I2C_2 (1 << 2)
191
192#define IQ81340_NUM_UART 2
193#define IQ81340_NUM_I2C 3
194#define IQ81340_NUM_PHYS_MAP_FLASH 1
195#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
196 IQ81340_NUM_I2C +\
197 IQ81340_NUM_PHYS_MAP_FLASH)
198
199/*========================== PMMR offsets for key registers ============*/
200#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
201#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
202#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
203#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
204#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
205#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
206#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
207#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
208#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
209
210#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
211#define IOP13XX_CONTROLLER_ONLY (1 << 14)
212#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
213
214#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
215#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
216 IOP13XX_PMON_PMMR_OFFSET)
217#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
218 IOP13XX_PMON_PMMR_OFFSET)
219
220#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
221#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
222#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
223#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
224
225#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
226#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
227#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
228#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
229
230#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
231#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
232#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
233#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
234
235#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
236#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
237
238/*================================ATU===================================*/
239#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
240 iop13xx_atux_pmmr_offset + (ofs))
241
242#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
243 iop13xx_atux_pmmr_offset + 0x2)
244
245#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
246 iop13xx_atux_pmmr_offset + 0x4)
247#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
248 iop13xx_atux_pmmr_offset + 0x6)
249
250#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
251#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
252#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
253#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
254#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
255#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
256#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
257#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
258#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
259#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
260#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
261#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
262#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
263#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
264#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
265#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
266#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
267#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
268#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
269#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
270#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
271#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
272#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
273#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
274
275#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
276#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
277#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
278#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
279#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
280#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
281#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
282#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
283#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
284#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
285#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
286#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
287#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
288#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
289
290#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
291#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
292#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
293#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
294#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
295#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
296
297#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
298#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
299#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
300#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
301#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
302#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
303#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
304#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
305#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
306#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
307#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
308#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
309#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
310#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
311#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
312#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
313#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
314
315#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
316#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
317#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
318
319#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
320#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
321
322#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
323 iop13xx_atue_pmmr_offset + (ofs))
324
325#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
326 iop13xx_atue_pmmr_offset + 0x2)
327#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
328 iop13xx_atue_pmmr_offset + 0x4)
329#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
330 iop13xx_atue_pmmr_offset + 0x6)
331
332#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
333#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
334#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
335#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
336#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
337#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
338#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
339#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
340#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
341#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
342#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
343#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
344#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
345#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
346#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
347#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
348 iop13xx_atue_pmmr_offset + 0xe2)
349#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
350#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
351#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
352#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
353#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
354#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
355#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
356#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
357#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
358
359#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
360#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
361#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
362#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
363#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
364#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
365
366#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
367#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
368
369#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
370#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
371#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
372#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
373#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
374#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
375#define IOP13XX_ATUE_OCCAR_REG (2)
376
377#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
378#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
379#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
380#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
381#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
382#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
383#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
384
385#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
386#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
387#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
388
389#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
390#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
391
392#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
393#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
394#define IOP13XX_ATUE_STAT_PME (1 << 27)
395#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
396#define IOP13XX_ATUE_STAT_IVM (1 << 25)
397#define IOP13XX_ATUE_STAT_BIST (1 << 24)
398#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
399#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
400#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
401#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
402#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
403#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
404#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
405#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
406#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
407#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
408#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
409#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
410#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
411#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
412#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
413#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
414#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
415
416#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
417#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
418#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
419#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
420#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
421#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
422#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
423#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
424#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
425#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
426#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
427#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
428#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
429#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
430#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
431
432#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
433#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
434#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
435#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
436/*=======================================================================*/
437
438/*==============================ADMA UNITS===============================*/
439#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
440#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
441#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs))
442
443#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0)
444#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4)
445#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8)
446#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18)
447#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c)
448#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20)
449#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24)
450#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28)
451#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c)
452#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30)
453#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34)
454#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38)
455#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
456#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
457
458/*==============================XSI BRIDGE===============================*/
459#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
460#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
461#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
462#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
463 IOP13XX_PMMR_VIRT_TO_PHYS(\
464 IOP13XX_ATUE_OCCDR))\
465 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
466#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
467 IOP13XX_PMMR_VIRT_TO_PHYS(\
468 IOP13XX_ATUX_OCCDR))\
469 && (__raw_readl(IOP13XX_XBG_BECSR) & 1))
470/*=======================================================================*/
471
472#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
473 (ofs))
474
475#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
476#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
477#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
478#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
479#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
480#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
481
482#define IOP13XX_TMR_TC 0x01
483#define IOP13XX_TMR_EN 0x02
484#define IOP13XX_TMR_RELOAD 0x04
485#define IOP13XX_TMR_PRIVILEGED 0x08
486
487#define IOP13XX_TMR_RATIO_1_1 0x00
488#define IOP13XX_TMR_RATIO_4_1 0x10
489#define IOP13XX_TMR_RATIO_8_1 0x20
490#define IOP13XX_TMR_RATIO_16_1 0x30
491
492#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/iq81340.h b/include/asm-arm/arch-iop13xx/iq81340.h
new file mode 100644
index 000000000000..b98f8f109c22
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/iq81340.h
@@ -0,0 +1,31 @@
1#ifndef _IQ81340_H_
2#define _IQ81340_H_
3
4#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
5#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
6
7#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
8
9#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
10
11#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
12#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
13#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
14#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
15#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
16#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
17#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
18#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
19#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
20#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
21#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
22#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
23
24#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
25#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
26
27/* These are the values used in the Machine description */
28#define PHYS_IO 0xfeffff00
29#define IO_PG_OFFSET 0xffffff00
30#define BOOT_PARAM_OFFSET 0x00000100
31#endif /* _IQ81340_H_ */
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
new file mode 100644
index 000000000000..442e35a40359
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -0,0 +1,207 @@
1#ifndef _IOP13XX_IRQS_H_
2#define _IOP13XX_IRQS_H_
3
4#ifndef __ASSEMBLER__
5#include <linux/types.h>
6#include <asm/system.h> /* local_irq_save */
7#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
8
9/* INTPND0 CP6 R0 Page 3
10 */
11static inline u32 read_intpnd_0(void)
12{
13 u32 val;
14 asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
15 return val;
16}
17
18/* INTPND1 CP6 R1 Page 3
19 */
20static inline u32 read_intpnd_1(void)
21{
22 u32 val;
23 asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
24 return val;
25}
26
27/* INTPND2 CP6 R2 Page 3
28 */
29static inline u32 read_intpnd_2(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
33 return val;
34}
35
36/* INTPND3 CP6 R3 Page 3
37 */
38static inline u32 read_intpnd_3(void)
39{
40 u32 val;
41 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
42 return val;
43}
44
45static inline void
46iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
47{
48 local_irq_save(*irq_flags);
49 *cp_flags = iop13xx_cp6_save();
50}
51
52static inline void
53iop13xx_cp6_irq_restore(unsigned long *cp_flags,
54 unsigned long *irq_flags)
55{
56 iop13xx_cp6_restore(*cp_flags);
57 local_irq_restore(*irq_flags);
58}
59#endif
60
61#define INTBASE 0
62#define INTSIZE_4 1
63
64/*
65 * iop34x chipset interrupts
66 */
67#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
68
69/*
70 * On IRQ or FIQ register
71 */
72#define IRQ_IOP13XX_ADMA0_EOT (0)
73#define IRQ_IOP13XX_ADMA0_EOC (1)
74#define IRQ_IOP13XX_ADMA1_EOT (2)
75#define IRQ_IOP13XX_ADMA1_EOC (3)
76#define IRQ_IOP13XX_ADMA2_EOT (4)
77#define IRQ_IOP13XX_ADMA2_EOC (5)
78#define IRQ_IOP134_WATCHDOG (6)
79#define IRQ_IOP13XX_RSVD_7 (7)
80#define IRQ_IOP13XX_TIMER0 (8)
81#define IRQ_IOP13XX_TIMER1 (9)
82#define IRQ_IOP13XX_I2C_0 (10)
83#define IRQ_IOP13XX_I2C_1 (11)
84#define IRQ_IOP13XX_MSG (12)
85#define IRQ_IOP13XX_MSGIBQ (13)
86#define IRQ_IOP13XX_ATU_IM (14)
87#define IRQ_IOP13XX_ATU_BIST (15)
88#define IRQ_IOP13XX_PPMU (16)
89#define IRQ_IOP13XX_COREPMU (17)
90#define IRQ_IOP13XX_CORECACHE (18)
91#define IRQ_IOP13XX_RSVD_19 (19)
92#define IRQ_IOP13XX_RSVD_20 (20)
93#define IRQ_IOP13XX_RSVD_21 (21)
94#define IRQ_IOP13XX_RSVD_22 (22)
95#define IRQ_IOP13XX_RSVD_23 (23)
96#define IRQ_IOP13XX_XINT0 (24)
97#define IRQ_IOP13XX_XINT1 (25)
98#define IRQ_IOP13XX_XINT2 (26)
99#define IRQ_IOP13XX_XINT3 (27)
100#define IRQ_IOP13XX_XINT4 (28)
101#define IRQ_IOP13XX_XINT5 (29)
102#define IRQ_IOP13XX_XINT6 (30)
103#define IRQ_IOP13XX_XINT7 (31)
104 /* IINTSRC1 bit */
105#define IRQ_IOP13XX_XINT8 (32) /* 0 */
106#define IRQ_IOP13XX_XINT9 (33) /* 1 */
107#define IRQ_IOP13XX_XINT10 (34) /* 2 */
108#define IRQ_IOP13XX_XINT11 (35) /* 3 */
109#define IRQ_IOP13XX_XINT12 (36) /* 4 */
110#define IRQ_IOP13XX_XINT13 (37) /* 5 */
111#define IRQ_IOP13XX_XINT14 (38) /* 6 */
112#define IRQ_IOP13XX_XINT15 (39) /* 7 */
113#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
114#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
115#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
116#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
117#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
118#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
119#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
120#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
121#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
122#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
123#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
124#define IRQ_IOP13XX_UART0 (51) /* 19 */
125#define IRQ_IOP13XX_UART1 (52) /* 20 */
126#define IRQ_IOP13XX_PBIE (53) /* 21 */
127#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
128#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
129#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
130#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
131#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
132#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
133#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
134#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
135#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
136#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
137 /* IINTSRC2 bit */
138#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
139#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
140#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
141#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
142#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
143#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
144#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
145#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
146#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
147#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
148#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
149#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
150#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
151#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
152#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
153#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
154#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
155#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
156#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
157#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
158#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
159#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
160#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
161#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
162#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
163#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
164#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
165#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
166#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
167#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
168#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
169#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
170 /* IINTSRC3 bit */
171#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
172#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
173#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
174#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
175#define IRQ_IOP13XX_IMU (100) /* 4 */
176#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
177#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
178#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
179#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
180#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
181#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
182#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
183#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
184#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
185#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
186#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
187#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
188#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */
189#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
190#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
191#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
192#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
193#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
194#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
195#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
196#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
197#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
198#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
199#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
200#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
201#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
202#define IRQ_IOP13XX_HPI (127) /* 31 */
203
204#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
205#define NR_IRQS NR_IOP13XX_IRQS
206
207#endif /* _IOP13XX_IRQ_H_ */
diff --git a/include/asm-arm/arch-iop13xx/memory.h b/include/asm-arm/arch-iop13xx/memory.h
new file mode 100644
index 000000000000..031a0fa78eff
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/memory.h
@@ -0,0 +1,64 @@
1#ifndef __ASM_ARCH_MEMORY_H
2#define __ASM_ARCH_MEMORY_H
3
4#include <asm/arch/hardware.h>
5
6/*
7 * Physical DRAM offset.
8 */
9#define PHYS_OFFSET UL(0x00000000)
10#define TASK_SIZE UL(0x3f000000)
11#define PAGE_OFFSET UL(0x40000000)
12#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
13
14#ifndef __ASSEMBLY__
15
16#if defined(CONFIG_ARCH_IOP13XX)
17#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
18#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
19#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
20#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
21
22/*
23 * Virtual view <-> PCI DMA view memory address translations
24 * virt_to_bus: Used to translate the virtual address to an
25 * address suitable to be passed to set_dma_addr
26 * bus_to_virt: Used to convert an address for DMA operations
27 * to an address that the kernel can use.
28 */
29
30/* RAM has 1:1 mapping on the PCIe/x Busses */
31#define __virt_to_bus(x) (__virt_to_phys(x))
32#define __bus_to_virt(x) (__phys_to_virt(x))
33
34#define virt_to_lbus(x) \
35(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \
36((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \
37((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
38((x) - PAGE_OFFSET + PHYS_OFFSET))
39
40#define lbus_to_virt(x) \
41(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
42((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
43((x) - PHYS_OFFSET + PAGE_OFFSET))
44
45/* Device is an lbus device if it is on the platform bus of the IOP13XX */
46#define is_lbus_device(dev) (dev &&\
47 (strncmp(dev->bus->name, "platform", 8) == 0))
48
49#define __arch_page_to_dma(dev, page) \
50({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
51(dma_addr_t)__virt_to_bus(page_address(page));})
52
53#define __arch_dma_to_virt(dev, addr) \
54({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
55
56#define __arch_virt_to_dma(dev, addr) \
57({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
58
59#endif /* CONFIG_ARCH_IOP13XX */
60#endif /* !ASSEMBLY */
61
62#define PFN_TO_NID(addr) (0)
63
64#endif
diff --git a/include/asm-arm/arch-iop13xx/pci.h b/include/asm-arm/arch-iop13xx/pci.h
new file mode 100644
index 000000000000..4041f30d4cd3
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/pci.h
@@ -0,0 +1,57 @@
1#ifndef _IOP13XX_PCI_H_
2#define _IOP13XX_PCI_H_
3#include <asm/arch/irqs.h>
4#include <asm/io.h>
5
6struct pci_sys_data;
7struct hw_pci;
8int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
9struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
10void iop13xx_atu_select(struct hw_pci *plat_pci);
11void iop13xx_pci_init(void);
12void iop13xx_map_pci_memory(void);
13
14#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
15 PCI_STATUS_SIG_TARGET_ABORT | \
16 PCI_STATUS_REC_TARGET_ABORT | \
17 PCI_STATUS_REC_TARGET_ABORT | \
18 PCI_STATUS_REC_MASTER_ABORT | \
19 PCI_STATUS_SIG_SYSTEM_ERROR | \
20 PCI_STATUS_DETECTED_PARITY)
21
22#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
23 IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
24 IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
25 IOP13XX_ATUE_STAT_ERR_COR | \
26 IOP13XX_ATUE_STAT_ERR_UNCOR | \
27 IOP13XX_ATUE_STAT_CRS | \
28 IOP13XX_ATUE_STAT_DET_PAR_ERR | \
29 IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
30 IOP13XX_ATUE_STAT_SIG_TABORT | \
31 IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
32 IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
33
34#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
35 IOP13XX_ATUX_STAT_REC_SCEM | \
36 IOP13XX_ATUX_STAT_TX_SERR | \
37 IOP13XX_ATUX_STAT_DET_PAR_ERR | \
38 IOP13XX_ATUX_STAT_INT_REC_MABORT | \
39 IOP13XX_ATUX_STAT_REC_SERR | \
40 IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
41 IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
42 IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
43 IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
44
45/* PCI interrupts
46 */
47#define ATUX_INTA IRQ_IOP13XX_XINT0
48#define ATUX_INTB IRQ_IOP13XX_XINT1
49#define ATUX_INTC IRQ_IOP13XX_XINT2
50#define ATUX_INTD IRQ_IOP13XX_XINT3
51
52#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
53#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
54#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
55#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
56
57#endif /* _IOP13XX_PCI_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
new file mode 100644
index 000000000000..ee3a62530af2
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -0,0 +1,59 @@
1/*
2 * linux/include/asm-arm/arch-iop13xx/system.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <asm/arch/iop13xx.h>
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16/* WDTCR CP6 R7 Page 9 */
17static inline u32 read_wdtcr(void)
18{
19 u32 val;
20 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
21 return val;
22}
23static inline void write_wdtcr(u32 val)
24{
25 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
26}
27
28/* WDTSR CP6 R8 Page 9 */
29static inline u32 read_wdtsr(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
33 return val;
34}
35static inline void write_wdtsr(u32 val)
36{
37 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
38}
39
40#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
41#define IOP13XX_WDTCR_EN 0xe1e1e1e1
42#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
43#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
44#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
45#define IOP13XX_WDTCR_IB_RESET (1 << 0)
46static inline void arch_reset(char mode)
47{
48 /*
49 * Reset the internal bus (warning both cores are reset)
50 */
51 u32 cp_flags = iop13xx_cp6_save();
52 write_wdtcr(IOP13XX_WDTCR_EN_ARM);
53 write_wdtcr(IOP13XX_WDTCR_EN);
54 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
55 write_wdtcr(0x1000);
56 iop13xx_cp6_restore(cp_flags);
57
58 for(;;);
59}
diff --git a/include/asm-arm/arch-iop13xx/timex.h b/include/asm-arm/arch-iop13xx/timex.h
new file mode 100644
index 000000000000..f0c51dd97ed8
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/timex.h
@@ -0,0 +1,3 @@
1#include <asm/hardware.h>
2
3#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-iop13xx/uncompress.h b/include/asm-arm/arch-iop13xx/uncompress.h
new file mode 100644
index 000000000000..b9525d59b7ad
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/uncompress.h
@@ -0,0 +1,24 @@
1#include <asm/types.h>
2#include <linux/serial_reg.h>
3#include <asm/hardware.h>
4#include <asm/processor.h>
5
6#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
7#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
8
9static inline void putc(char c)
10{
11 while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
12 cpu_relax();
13 UART_BASE[UART_TX] = c;
14}
15
16static inline void flush(void)
17{
18}
19
20/*
21 * nothing to do
22 */
23#define arch_decomp_setup()
24#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop13xx/vmalloc.h b/include/asm-arm/arch-iop13xx/vmalloc.h
new file mode 100644
index 000000000000..c53456740345
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/vmalloc.h
@@ -0,0 +1,4 @@
1#ifndef _VMALLOC_H_
2#define _VMALLOC_H_
3#define VMALLOC_END 0xfa000000UL
4#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-23 11:34:36 -0400