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authorLen Brown <len.brown@intel.com>2006-01-27 17:18:29 -0500
committerLen Brown <len.brown@intel.com>2006-01-27 17:18:29 -0500
commit292dd876ee765c478b27c93cc51e93a558ed58bf (patch)
tree5b740e93253295baee2a9c414a6c66d03d44a9ef /include/asm-arm26/system.h
parentd4ec6c7cc9a15a7a529719bc3b84f46812f9842e (diff)
parent9fdb62af92c741addbea15545f214a6e89460865 (diff)
Pull release into acpica branch
Diffstat (limited to 'include/asm-arm26/system.h')
-rw-r--r--include/asm-arm26/system.h12
1 files changed, 11 insertions, 1 deletions
diff --git a/include/asm-arm26/system.h b/include/asm-arm26/system.h
index f23fac1938f3..ca4ccfc4b578 100644
--- a/include/asm-arm26/system.h
+++ b/include/asm-arm26/system.h
@@ -111,10 +111,20 @@ extern struct task_struct *__switch_to(struct task_struct *, struct thread_info
111 111
112#define switch_to(prev,next,last) \ 112#define switch_to(prev,next,last) \
113do { \ 113do { \
114 last = __switch_to(prev,prev->thread_info,next->thread_info); \ 114 last = __switch_to(prev,task_thread_info(prev),task_thread_info(next)); \
115} while (0) 115} while (0)
116 116
117/* 117/*
118 * On SMP systems, when the scheduler does migration-cost autodetection,
119 * it needs a way to flush as much of the CPU's caches as possible.
120 *
121 * TODO: fill this in!
122 */
123static inline void sched_cacheflush(void)
124{
125}
126
127/*
118 * Save the current interrupt enable state & disable IRQs 128 * Save the current interrupt enable state & disable IRQs
119 */ 129 */
120#define local_irq_save(x) \ 130#define local_irq_save(x) \