[ARM] 4582/2: Add support for the common VFP subarchitecture

This patch allows the VFP support code to run correctly on CPUs
compatible with the common VFP subarchitecture specification (Appendix
B in the ARM ARM v7-A and v7-R edition). It implements support for VFP
subarchitecture 2 while being backwards compatible with
subarchitecture 1.

On VFP subarchitecture 1, the arithmetic exceptions are asynchronous
(or imprecise as described in the old ARM ARM) unless the FPSCR.IXE
bit is 1. The exceptional instructions can be read from FPINST and
FPINST2 registers. With VFP subarchitecture 2, the arithmetic
exceptions can also be synchronous and marked by the FPEXC.DEX bit
(the FPEXC.EX bit is cleared). CPUs implementing the synchronous
arithmetic exceptions don't have the FPINST and FPINST2 registers and
accessing them would trigger and undefined exception.

Note that FPEXC.EX bit has an additional meaning on subarchitecture 1
- if it isn't set, there is no additional information in FPINST and
FPINST2 that needs to be saved at context switch or when lazy-loading
the VFP state of a different thread.

The patch also removes the clearing of the cumulative exception flags in
FPSCR when additional exceptions were raised. It is up to the user
application to clear these bits.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 15 insertions, 15 deletions

diff --git a/include/asm-arm/vfp.h b/include/asm-arm/vfp.h
index bd6be9d7f772..9d474d47b266 100644
--- a/include/asm-arm/vfp.h
+++ b/include/asm-arm/vfp.h
@@ -8,6 +8,8 @@
 #define FPSID                   cr0
 #define FPSCR                   cr1
 #define FPEXC                   cr8
+#define FPINST                  cr9
+#define FPINST2                 cr10
 
 /* FPSID bits */
 #define FPSID_IMPLEMENTER_BIT   (24)
@@ -28,6 +30,19 @@
 /* FPEXC bits */
 #define FPEXC_EX                (1 << 31)
 #define FPEXC_EN                (1 << 30)
+#define FPEXC_DEX               (1 << 29)
+#define FPEXC_FP2V              (1 << 28)
+#define FPEXC_VV                (1 << 27)
+#define FPEXC_TFV               (1 << 26)
+#define FPEXC_LENGTH_BIT        (8)
+#define FPEXC_LENGTH_MASK       (7 << FPEXC_LENGTH_BIT)
+#define FPEXC_IDF               (1 << 7)
+#define FPEXC_IXF               (1 << 4)
+#define FPEXC_UFF               (1 << 3)
+#define FPEXC_OFF               (1 << 2)
+#define FPEXC_DZF               (1 << 1)
+#define FPEXC_IOF               (1 << 0)
+#define FPEXC_TRAP_MASK         (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
 
 /* FPSCR bits */
 #define FPSCR_DEFAULT_NAN       (1<<25)
@@ -55,21 +70,6 @@
 #define FPSCR_IXC               (1<<4)
 #define FPSCR_IDC               (1<<7)
 
-/*
- * VFP9-S specific.
- */
-#define FPINST                  cr9
-#define FPINST2                 cr10
-
-/* FPEXC bits */
-#define FPEXC_FPV2              (1<<28)
-#define FPEXC_LENGTH_BIT        (8)
-#define FPEXC_LENGTH_MASK       (7 << FPEXC_LENGTH_BIT)
-#define FPEXC_INV               (1 << 7)
-#define FPEXC_UFC               (1 << 3)
-#define FPEXC_OFC               (1 << 2)
-#define FPEXC_IOC               (1 << 0)
-
 /* Bit patterns for decoding the packaged operation descriptors */
 #define VFPOPDESC_LENGTH_BIT    (9)
 #define VFPOPDESC_LENGTH_MASK   (0x07 << VFPOPDESC_LENGTH_BIT)