diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-19 16:18:39 -0500 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-02-19 16:18:39 -0500 |
commit | 59b8175c771040afcd4ad67022b0cc80c216b866 (patch) | |
tree | 4ef5935bee1e342716d49b9d4b99e3fa835526e6 /include/asm-arm/tlbflush.h | |
parent | 920841d8d1d61bc12b43f95a579a5374f6d98f81 (diff) | |
parent | 3b0eb4a195a124567cd0dd6f700f8388def542c6 (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits)
[ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports
[ARM] 4140/1: AACI stability add ac97 timeout and retries
[ARM] 4139/1: AACI record support
[ARM] 4138/1: AACI: multiple channel support for IRQ handling
[ARM] 4211/1: Provide a defconfig for ns9xxx
[ARM] 4210/1: base for new machine type "NetSilicon NS9360"
[ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM
[ARM] 4221/1: S3C2443: DMA support
[ARM] 4220/1: S3C24XX: DMA system initialised from sysdev
[ARM] 4219/1: S3C2443: DMA source definitions
[ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443
[ARM] 4217/1: S3C24XX: remove the dma channel show at startup
[ARM] 4090/2: avoid clash between PXA and SA1111 defines
[ARM] 4216/1: add .gitignore entries for ARM specific files
[ARM] 4214/2: S3C2410: Add Armzone QT2410
[ARM] 4215/1: s3c2410 usb device: per-platform vbus_draw
[ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST
[ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos
[ARM] 4137/1: Add kexec support
[ARM] 4201/1: SMP barriers pair needed for the secondary boot process
...
Fix up conflict due to typedef removal in sound/arm/aaci.h
Diffstat (limited to 'include/asm-arm/tlbflush.h')
-rw-r--r-- | include/asm-arm/tlbflush.h | 50 |
1 files changed, 38 insertions, 12 deletions
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h index cd10a0b5f8ae..08c6991dc9c9 100644 --- a/include/asm-arm/tlbflush.h +++ b/include/asm-arm/tlbflush.h | |||
@@ -247,7 +247,7 @@ static inline void local_flush_tlb_all(void) | |||
247 | const unsigned int __tlb_flag = __cpu_tlb_flags; | 247 | const unsigned int __tlb_flag = __cpu_tlb_flags; |
248 | 248 | ||
249 | if (tlb_flag(TLB_WB)) | 249 | if (tlb_flag(TLB_WB)) |
250 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); | 250 | dsb(); |
251 | 251 | ||
252 | if (tlb_flag(TLB_V3_FULL)) | 252 | if (tlb_flag(TLB_V3_FULL)) |
253 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); | 253 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc"); |
@@ -257,6 +257,15 @@ static inline void local_flush_tlb_all(void) | |||
257 | asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); | 257 | asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc"); |
258 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) | 258 | if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL)) |
259 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); | 259 | asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc"); |
260 | |||
261 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | ||
262 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
263 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
264 | /* flush the branch target cache */ | ||
265 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | ||
266 | dsb(); | ||
267 | isb(); | ||
268 | } | ||
260 | } | 269 | } |
261 | 270 | ||
262 | static inline void local_flush_tlb_mm(struct mm_struct *mm) | 271 | static inline void local_flush_tlb_mm(struct mm_struct *mm) |
@@ -266,7 +275,7 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) | |||
266 | const unsigned int __tlb_flag = __cpu_tlb_flags; | 275 | const unsigned int __tlb_flag = __cpu_tlb_flags; |
267 | 276 | ||
268 | if (tlb_flag(TLB_WB)) | 277 | if (tlb_flag(TLB_WB)) |
269 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); | 278 | dsb(); |
270 | 279 | ||
271 | if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) { | 280 | if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) { |
272 | if (tlb_flag(TLB_V3_FULL)) | 281 | if (tlb_flag(TLB_V3_FULL)) |
@@ -285,6 +294,14 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) | |||
285 | asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); | 294 | asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc"); |
286 | if (tlb_flag(TLB_V6_I_ASID)) | 295 | if (tlb_flag(TLB_V6_I_ASID)) |
287 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); | 296 | asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc"); |
297 | |||
298 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | ||
299 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
300 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
301 | /* flush the branch target cache */ | ||
302 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | ||
303 | dsb(); | ||
304 | } | ||
288 | } | 305 | } |
289 | 306 | ||
290 | static inline void | 307 | static inline void |
@@ -296,7 +313,7 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | |||
296 | uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); | 313 | uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm); |
297 | 314 | ||
298 | if (tlb_flag(TLB_WB)) | 315 | if (tlb_flag(TLB_WB)) |
299 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero)); | 316 | dsb(); |
300 | 317 | ||
301 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { | 318 | if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) { |
302 | if (tlb_flag(TLB_V3_PAGE)) | 319 | if (tlb_flag(TLB_V3_PAGE)) |
@@ -317,6 +334,14 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr) | |||
317 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); | 334 | asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc"); |
318 | if (tlb_flag(TLB_V6_I_PAGE)) | 335 | if (tlb_flag(TLB_V6_I_PAGE)) |
319 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); | 336 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc"); |
337 | |||
338 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | | ||
339 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | | ||
340 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { | ||
341 | /* flush the branch target cache */ | ||
342 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); | ||
343 | dsb(); | ||
344 | } | ||
320 | } | 345 | } |
321 | 346 | ||
322 | static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | 347 | static inline void local_flush_tlb_kernel_page(unsigned long kaddr) |
@@ -327,7 +352,7 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
327 | kaddr &= PAGE_MASK; | 352 | kaddr &= PAGE_MASK; |
328 | 353 | ||
329 | if (tlb_flag(TLB_WB)) | 354 | if (tlb_flag(TLB_WB)) |
330 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); | 355 | dsb(); |
331 | 356 | ||
332 | if (tlb_flag(TLB_V3_PAGE)) | 357 | if (tlb_flag(TLB_V3_PAGE)) |
333 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc"); | 358 | asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc"); |
@@ -347,11 +372,14 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
347 | if (tlb_flag(TLB_V6_I_PAGE)) | 372 | if (tlb_flag(TLB_V6_I_PAGE)) |
348 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); | 373 | asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc"); |
349 | 374 | ||
350 | /* The ARM ARM states that the completion of a TLB maintenance | 375 | if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL | |
351 | * operation is only guaranteed by a DSB instruction | 376 | TLB_V6_I_PAGE | TLB_V6_D_PAGE | |
352 | */ | 377 | TLB_V6_I_ASID | TLB_V6_D_ASID)) { |
353 | if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE)) | 378 | /* flush the branch target cache */ |
354 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc"); | 379 | asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc"); |
380 | dsb(); | ||
381 | isb(); | ||
382 | } | ||
355 | } | 383 | } |
356 | 384 | ||
357 | /* | 385 | /* |
@@ -369,15 +397,13 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr) | |||
369 | */ | 397 | */ |
370 | static inline void flush_pmd_entry(pmd_t *pmd) | 398 | static inline void flush_pmd_entry(pmd_t *pmd) |
371 | { | 399 | { |
372 | const unsigned int zero = 0; | ||
373 | const unsigned int __tlb_flag = __cpu_tlb_flags; | 400 | const unsigned int __tlb_flag = __cpu_tlb_flags; |
374 | 401 | ||
375 | if (tlb_flag(TLB_DCLEAN)) | 402 | if (tlb_flag(TLB_DCLEAN)) |
376 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" | 403 | asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd" |
377 | : : "r" (pmd) : "cc"); | 404 | : : "r" (pmd) : "cc"); |
378 | if (tlb_flag(TLB_WB)) | 405 | if (tlb_flag(TLB_WB)) |
379 | asm("mcr p15, 0, %0, c7, c10, 4 @ flush_pmd" | 406 | dsb(); |
380 | : : "r" (zero) : "cc"); | ||
381 | } | 407 | } |
382 | 408 | ||
383 | static inline void clean_pmd_entry(pmd_t *pmd) | 409 | static inline void clean_pmd_entry(pmd_t *pmd) |