[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation

Patch from Catalin Marinas

Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
the completion of a TLB maintenance operation is only guaranteed by
the execution of a DSB (Data Syncronization Barrier, formerly Data
Write Barrier or Drain Write Buffer).

Note that a DSB is only needed in the flush_tlb_kernel_* functions
since the completion is guaranteed by a mode change (i.e. switching
back to user mode) for the flush_tlb_user_* functions.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 6 insertions, 0 deletions

diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 9387a5e1ffe0..0c2acc944a0a 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -340,6 +340,12 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
                 asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
         if (tlb_flag(TLB_V6_I_PAGE))
                 asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
+
+        /* The ARM ARM states that the completion of a TLB maintenance
+         * operation is only guaranteed by a DSB instruction
+         */
+        if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
+                asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
 }
 
 /*