[ARM] Set bit 4 on section mappings correctly depending on CPU

On some CPUs, bit 4 of section mappings means "update the
cache when written to".  On others, this bit is required to
be one, and others it's required to be zero.  Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.

With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 2 insertions, 1 deletions

diff --git a/include/asm-arm/procinfo.h b/include/asm-arm/procinfo.h
index 842526055225..edb7b6502fcf 100644
--- a/include/asm-arm/procinfo.h
+++ b/include/asm-arm/procinfo.h
@@ -29,7 +29,8 @@ struct processor;
 struct proc_info_list {
         unsigned int            cpu_val;
         unsigned int            cpu_mask;
-        unsigned long           __cpu_mmu_flags;        /* used by head.S */
+        unsigned long           __cpu_mm_mmu_flags;     /* used by head.S */
+        unsigned long           __cpu_io_mmu_flags;     /* used by head.S */
         unsigned long           __cpu_flush;            /* used by head.S */
         const char              *arch_name;
         const char              *elf_name;