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author | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-14 19:06:58 -0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2008-07-14 19:06:58 -0400 |
commit | 85082fd7cbe3173198aac0eb5e85ab1edcc6352c (patch) | |
tree | edbc09b7945994f78668d218fa02e991c3b3b365 /include/asm-arm/plat-s3c/regs-timer.h | |
parent | 666484f0250db2e016948d63b3ef33e202e3b8d0 (diff) | |
parent | 53ffe3b440aa85af6fc4eda09b2d44bcdd312d4d (diff) |
Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (241 commits)
[ARM] 5171/1: ep93xx: fix compilation of modules using clocks
[ARM] 5133/2: at91sam9g20 defconfig file
[ARM] 5130/4: Support for the at91sam9g20
[ARM] 5160/1: IOP3XX: gpio/gpiolib support
[ARM] at91: Fix NAND FLASH timings for at91sam9x evaluation kits.
[ARM] 5084/1: zylonite: Register AC97 device
[ARM] 5085/2: PXA: Move AC97 over to the new central device declaration model
[ARM] 5120/1: pxa: correct platform driver names for PXA25x and PXA27x UDC drivers
[ARM] 5147/1: pxaficp_ir: drop pxa_gpio_mode calls, as pin setting
[ARM] 5145/1: PXA2xx: provide api to control IrDA pins state
[ARM] 5144/1: pxaficp_ir: cleanup includes
[ARM] pxa: remove pxa_set_cken()
[ARM] pxa: allow clk aliases
[ARM] Feroceon: don't disable BPU on boot
[ARM] Orion: LED support for HP mv2120
[ARM] Orion: add RD88F5181L-FXO support
[ARM] Orion: add RD88F5181L-GE support
[ARM] Orion: add Netgear WNR854T support
[ARM] s3c2410_defconfig: update for current build
[ARM] Acer n30: Minor style and indentation fixes.
...
Diffstat (limited to 'include/asm-arm/plat-s3c/regs-timer.h')
-rw-r--r-- | include/asm-arm/plat-s3c/regs-timer.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h index 8b0d594397b1..b5bc692f3489 100644 --- a/include/asm-arm/plat-s3c/regs-timer.h +++ b/include/asm-arm/plat-s3c/regs-timer.h | |||
@@ -65,6 +65,15 @@ | |||
65 | #define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) | 65 | #define S3C2410_TCFG1_MUX0_TCLK0 (4<<0) |
66 | #define S3C2410_TCFG1_MUX0_MASK (15<<0) | 66 | #define S3C2410_TCFG1_MUX0_MASK (15<<0) |
67 | 67 | ||
68 | #define S3C2410_TCFG1_MUX_DIV2 (0<<0) | ||
69 | #define S3C2410_TCFG1_MUX_DIV4 (1<<0) | ||
70 | #define S3C2410_TCFG1_MUX_DIV8 (2<<0) | ||
71 | #define S3C2410_TCFG1_MUX_DIV16 (3<<0) | ||
72 | #define S3C2410_TCFG1_MUX_TCLK (4<<0) | ||
73 | #define S3C2410_TCFG1_MUX_MASK (15<<0) | ||
74 | |||
75 | #define S3C2410_TCFG1_SHIFT(x) ((x) * 4) | ||
76 | |||
68 | /* for each timer, we have an count buffer, an compare buffer and | 77 | /* for each timer, we have an count buffer, an compare buffer and |
69 | * an observation buffer | 78 | * an observation buffer |
70 | */ | 79 | */ |