[ARM] Set bit 4 on section mappings correctly depending on CPU

On some CPUs, bit 4 of section mappings means "update the
cache when written to".  On others, this bit is required to
be one, and others it's required to be zero.  Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.

With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 1 insertions, 0 deletions

diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h
index 1bc1f997bda2..f3b5120c99fe 100644
--- a/include/asm-arm/pgtable-hwdef.h
+++ b/include/asm-arm/pgtable-hwdef.h
@@ -28,6 +28,7 @@
  */
 #define PMD_SECT_BUFFERABLE     (1 << 2)
 #define PMD_SECT_CACHEABLE      (1 << 3)
+#define PMD_SECT_XN             (1 << 4)        /* v6 */
 #define PMD_SECT_AP_WRITE       (1 << 10)
 #define PMD_SECT_AP_READ        (1 << 11)
 #define PMD_SECT_TEX(x)         ((x) << 12)     /* v5 */