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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/hardware
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-arm/hardware')
-rw-r--r--include/asm-arm/hardware/amba.h55
-rw-r--r--include/asm-arm/hardware/amba_clcd.h264
-rw-r--r--include/asm-arm/hardware/amba_kmi.h92
-rw-r--r--include/asm-arm/hardware/amba_serial.h156
-rw-r--r--include/asm-arm/hardware/clock.h121
-rw-r--r--include/asm-arm/hardware/clps7111.h184
-rw-r--r--include/asm-arm/hardware/cs89712.h49
-rw-r--r--include/asm-arm/hardware/dec21285.h148
-rw-r--r--include/asm-arm/hardware/entry-macro-iomd.S145
-rw-r--r--include/asm-arm/hardware/ep7211.h40
-rw-r--r--include/asm-arm/hardware/ep7212.h83
-rw-r--r--include/asm-arm/hardware/icst307.h38
-rw-r--r--include/asm-arm/hardware/icst525.h36
-rw-r--r--include/asm-arm/hardware/ioc.h72
-rw-r--r--include/asm-arm/hardware/iomd.h227
-rw-r--r--include/asm-arm/hardware/linkup-l1110.h48
-rw-r--r--include/asm-arm/hardware/locomo.h206
-rw-r--r--include/asm-arm/hardware/memc.h26
-rw-r--r--include/asm-arm/hardware/pci_v3.h186
-rw-r--r--include/asm-arm/hardware/sa1111.h602
-rw-r--r--include/asm-arm/hardware/scoop.h47
-rw-r--r--include/asm-arm/hardware/ssp.h28
22 files changed, 2853 insertions, 0 deletions
diff --git a/include/asm-arm/hardware/amba.h b/include/asm-arm/hardware/amba.h
new file mode 100644
index 000000000000..51e6e54b2aa1
--- /dev/null
+++ b/include/asm-arm/hardware/amba.h
@@ -0,0 +1,55 @@
1/*
2 * linux/include/asm-arm/hardware/amba.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef ASMARM_AMBA_H
11#define ASMARM_AMBA_H
12
13#define AMBA_NR_IRQS 2
14
15struct amba_device {
16 struct device dev;
17 struct resource res;
18 u64 dma_mask;
19 unsigned int periphid;
20 unsigned int irq[AMBA_NR_IRQS];
21};
22
23struct amba_id {
24 unsigned int id;
25 unsigned int mask;
26 void *data;
27};
28
29struct amba_driver {
30 struct device_driver drv;
31 int (*probe)(struct amba_device *, void *);
32 int (*remove)(struct amba_device *);
33 void (*shutdown)(struct amba_device *);
34 int (*suspend)(struct amba_device *, pm_message_t);
35 int (*resume)(struct amba_device *);
36 struct amba_id *id_table;
37};
38
39#define amba_get_drvdata(d) dev_get_drvdata(&d->dev)
40#define amba_set_drvdata(d,p) dev_set_drvdata(&d->dev, p)
41
42int amba_driver_register(struct amba_driver *);
43void amba_driver_unregister(struct amba_driver *);
44int amba_device_register(struct amba_device *, struct resource *);
45void amba_device_unregister(struct amba_device *);
46struct amba_device *amba_find_device(const char *, struct device *, unsigned int, unsigned int);
47int amba_request_regions(struct amba_device *, const char *);
48void amba_release_regions(struct amba_device *);
49
50#define amba_config(d) (((d)->periphid >> 24) & 0xff)
51#define amba_rev(d) (((d)->periphid >> 20) & 0x0f)
52#define amba_manf(d) (((d)->periphid >> 12) & 0xff)
53#define amba_part(d) ((d)->periphid & 0xfff)
54
55#endif
diff --git a/include/asm-arm/hardware/amba_clcd.h b/include/asm-arm/hardware/amba_clcd.h
new file mode 100644
index 000000000000..2149be7c7023
--- /dev/null
+++ b/include/asm-arm/hardware/amba_clcd.h
@@ -0,0 +1,264 @@
1/*
2 * linux/include/asm-arm/hardware/amba_clcd.h -- Integrator LCD panel.
3 *
4 * David A Rusling
5 *
6 * Copyright (C) 2001 ARM Limited
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file COPYING in the main directory of this archive
10 * for more details.
11 */
12#include <linux/config.h>
13#include <linux/fb.h>
14
15/*
16 * CLCD Controller Internal Register addresses
17 */
18#define CLCD_TIM0 0x00000000
19#define CLCD_TIM1 0x00000004
20#define CLCD_TIM2 0x00000008
21#define CLCD_TIM3 0x0000000c
22#define CLCD_UBAS 0x00000010
23#define CLCD_LBAS 0x00000014
24
25#ifndef CONFIG_ARCH_VERSATILE
26#define CLCD_IENB 0x00000018
27#define CLCD_CNTL 0x0000001c
28#else
29/*
30 * Someone rearranged these two registers on the Versatile
31 * platform...
32 */
33#define CLCD_IENB 0x0000001c
34#define CLCD_CNTL 0x00000018
35#endif
36
37#define CLCD_STAT 0x00000020
38#define CLCD_INTR 0x00000024
39#define CLCD_UCUR 0x00000028
40#define CLCD_LCUR 0x0000002C
41#define CLCD_PALL 0x00000200
42#define CLCD_PALETTE 0x00000200
43
44#define TIM2_CLKSEL (1 << 5)
45#define TIM2_IVS (1 << 11)
46#define TIM2_IHS (1 << 12)
47#define TIM2_IPC (1 << 13)
48#define TIM2_IOE (1 << 14)
49#define TIM2_BCD (1 << 26)
50
51#define CNTL_LCDEN (1 << 0)
52#define CNTL_LCDBPP1 (0 << 1)
53#define CNTL_LCDBPP2 (1 << 1)
54#define CNTL_LCDBPP4 (2 << 1)
55#define CNTL_LCDBPP8 (3 << 1)
56#define CNTL_LCDBPP16 (4 << 1)
57#define CNTL_LCDBPP24 (5 << 1)
58#define CNTL_LCDBW (1 << 4)
59#define CNTL_LCDTFT (1 << 5)
60#define CNTL_LCDMONO8 (1 << 6)
61#define CNTL_LCDDUAL (1 << 7)
62#define CNTL_BGR (1 << 8)
63#define CNTL_BEBO (1 << 9)
64#define CNTL_BEPO (1 << 10)
65#define CNTL_LCDPWR (1 << 11)
66#define CNTL_LCDVCOMP(x) ((x) << 12)
67#define CNTL_LDMAFIFOTIME (1 << 15)
68#define CNTL_WATERMARK (1 << 16)
69
70struct clcd_panel {
71 struct fb_videomode mode;
72 signed short width; /* width in mm */
73 signed short height; /* height in mm */
74 u32 tim2;
75 u32 tim3;
76 u32 cntl;
77 unsigned int bpp:8,
78 fixedtimings:1,
79 grayscale:1;
80 unsigned int connector;
81};
82
83struct clcd_regs {
84 u32 tim0;
85 u32 tim1;
86 u32 tim2;
87 u32 tim3;
88 u32 cntl;
89 unsigned long pixclock;
90};
91
92struct clcd_fb;
93
94/*
95 * the board-type specific routines
96 */
97struct clcd_board {
98 const char *name;
99
100 /*
101 * Optional. Check whether the var structure is acceptable
102 * for this display.
103 */
104 int (*check)(struct clcd_fb *fb, struct fb_var_screeninfo *var);
105
106 /*
107 * Compulsary. Decode fb->fb.var into regs->*. In the case of
108 * fixed timing, set regs->* to the register values required.
109 */
110 void (*decode)(struct clcd_fb *fb, struct clcd_regs *regs);
111
112 /*
113 * Optional. Disable any extra display hardware.
114 */
115 void (*disable)(struct clcd_fb *);
116
117 /*
118 * Optional. Enable any extra display hardware.
119 */
120 void (*enable)(struct clcd_fb *);
121
122 /*
123 * Setup platform specific parts of CLCD driver
124 */
125 int (*setup)(struct clcd_fb *);
126
127 /*
128 * mmap the framebuffer memory
129 */
130 int (*mmap)(struct clcd_fb *, struct vm_area_struct *);
131
132 /*
133 * Remove platform specific parts of CLCD driver
134 */
135 void (*remove)(struct clcd_fb *);
136};
137
138struct amba_device;
139struct clk;
140
141/* this data structure describes each frame buffer device we find */
142struct clcd_fb {
143 struct fb_info fb;
144 struct amba_device *dev;
145 struct clk *clk;
146 struct clcd_panel *panel;
147 struct clcd_board *board;
148 void *board_data;
149 void __iomem *regs;
150 u32 clcd_cntl;
151 u32 cmap[16];
152};
153
154static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
155{
156 u32 val;
157
158 /*
159 * Program the CLCD controller registers and start the CLCD
160 */
161 val = ((fb->fb.var.xres / 16) - 1) << 2;
162 val |= (fb->fb.var.hsync_len - 1) << 8;
163 val |= (fb->fb.var.right_margin - 1) << 16;
164 val |= (fb->fb.var.left_margin - 1) << 24;
165 regs->tim0 = val;
166
167 val = fb->fb.var.yres - 1;
168 val |= (fb->fb.var.vsync_len - 1) << 10;
169 val |= fb->fb.var.lower_margin << 16;
170 val |= fb->fb.var.upper_margin << 24;
171 regs->tim1 = val;
172
173 val = fb->panel->tim2;
174 val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
175 val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
176
177 if (fb->panel->cntl & CNTL_LCDTFT)
178 val |= (fb->fb.var.xres_virtual - 1) << 16;
179 else if (fb->panel->cntl & CNTL_LCDBW)
180 printk("what value for CPL for stnmono panels?");
181 else
182 val |= ((fb->fb.var.xres_virtual * 8 / 3) - 1) << 16;
183 regs->tim2 = val;
184
185 regs->tim3 = fb->panel->tim3;
186
187 val = fb->panel->cntl;
188 if (fb->fb.var.grayscale)
189 val |= CNTL_LCDBW;
190
191 switch (fb->fb.var.bits_per_pixel) {
192 case 1:
193 val |= CNTL_LCDBPP1;
194 break;
195 case 2:
196 val |= CNTL_LCDBPP2;
197 break;
198 case 4:
199 val |= CNTL_LCDBPP4;
200 break;
201 case 8:
202 val |= CNTL_LCDBPP8;
203 break;
204 case 16:
205 val |= CNTL_LCDBPP16;
206 break;
207 case 24:
208 val |= CNTL_LCDBPP24;
209 break;
210 }
211
212 regs->cntl = val;
213 regs->pixclock = fb->fb.var.pixclock;
214}
215
216static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
217{
218 var->xres_virtual = var->xres = (var->xres + 7) & ~7;
219 var->yres_virtual = var->yres;
220
221#define CHECK(e,l,h) (var->e < l || var->e > h)
222 if (CHECK(right_margin, (5+1), 256) || /* back porch */
223 CHECK(left_margin, (5+1), 256) || /* front porch */
224 CHECK(hsync_len, (5+1), 256) ||
225 var->xres > 4096 ||
226 var->lower_margin > 255 || /* back porch */
227 var->upper_margin > 255 || /* front porch */
228 var->vsync_len > 32 ||
229 var->yres > 1024)
230 return -EINVAL;
231#undef CHECK
232
233 /* single panel mode: PCD = max(PCD, 1) */
234 /* dual panel mode: PCD = max(PCD, 5) */
235
236 /*
237 * You can't change the grayscale setting, and
238 * we can only do non-interlaced video.
239 */
240 if (var->grayscale != fb->fb.var.grayscale ||
241 (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
242 return -EINVAL;
243
244#define CHECK(e) (var->e != fb->fb.var.e)
245 if (fb->panel->fixedtimings &&
246 (CHECK(xres) ||
247 CHECK(yres) ||
248 CHECK(bits_per_pixel) ||
249 CHECK(pixclock) ||
250 CHECK(left_margin) ||
251 CHECK(right_margin) ||
252 CHECK(upper_margin) ||
253 CHECK(lower_margin) ||
254 CHECK(hsync_len) ||
255 CHECK(vsync_len) ||
256 CHECK(sync)))
257 return -EINVAL;
258#undef CHECK
259
260 var->nonstd = 0;
261 var->accel_flags = 0;
262
263 return 0;
264}
diff --git a/include/asm-arm/hardware/amba_kmi.h b/include/asm-arm/hardware/amba_kmi.h
new file mode 100644
index 000000000000..a39e5be751b3
--- /dev/null
+++ b/include/asm-arm/hardware/amba_kmi.h
@@ -0,0 +1,92 @@
1/*
2 * linux/include/asm-arm/hardware/amba_kmi.h
3 *
4 * Internal header file for AMBA KMI ports
5 *
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 *
23 * ---------------------------------------------------------------------------
24 * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical
25 * Reference Manual - ARM DDI 0143B - see http://www.arm.com/
26 * ---------------------------------------------------------------------------
27 */
28#ifndef ASM_ARM_HARDWARE_AMBA_KMI_H
29#define ASM_ARM_HARDWARE_AMBA_KMI_H
30
31/*
32 * KMI control register:
33 * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode
34 * KMICR_RXINTREN 1 = enable RX interrupts
35 * KMICR_TXINTREN 1 = enable TX interrupts
36 * KMICR_EN 1 = enable KMI
37 * KMICR_FD 1 = force KMI data low
38 * KMICR_FC 1 = force KMI clock low
39 */
40#define KMICR (KMI_BASE + 0x00)
41#define KMICR_TYPE (1 << 5)
42#define KMICR_RXINTREN (1 << 4)
43#define KMICR_TXINTREN (1 << 3)
44#define KMICR_EN (1 << 2)
45#define KMICR_FD (1 << 1)
46#define KMICR_FC (1 << 0)
47
48/*
49 * KMI status register:
50 * KMISTAT_TXEMPTY 1 = transmitter register empty
51 * KMISTAT_TXBUSY 1 = currently sending data
52 * KMISTAT_RXFULL 1 = receiver register ready to be read
53 * KMISTAT_RXBUSY 1 = currently receiving data
54 * KMISTAT_RXPARITY parity of last databyte received
55 * KMISTAT_IC current level of KMI clock input
56 * KMISTAT_ID current level of KMI data input
57 */
58#define KMISTAT (KMI_BASE + 0x04)
59#define KMISTAT_TXEMPTY (1 << 6)
60#define KMISTAT_TXBUSY (1 << 5)
61#define KMISTAT_RXFULL (1 << 4)
62#define KMISTAT_RXBUSY (1 << 3)
63#define KMISTAT_RXPARITY (1 << 2)
64#define KMISTAT_IC (1 << 1)
65#define KMISTAT_ID (1 << 0)
66
67/*
68 * KMI data register
69 */
70#define KMIDATA (KMI_BASE + 0x08)
71
72/*
73 * KMI clock divisor: to generate 8MHz internal clock
74 * div = (ref / 8MHz) - 1; 0 <= div <= 15
75 */
76#define KMICLKDIV (KMI_BASE + 0x0c)
77
78/*
79 * KMI interrupt register:
80 * KMIIR_TXINTR 1 = transmit interrupt asserted
81 * KMIIR_RXINTR 1 = receive interrupt asserted
82 */
83#define KMIIR (KMI_BASE + 0x10)
84#define KMIIR_TXINTR (1 << 1)
85#define KMIIR_RXINTR (1 << 0)
86
87/*
88 * The size of the KMI primecell
89 */
90#define KMI_SIZE (0x100)
91
92#endif
diff --git a/include/asm-arm/hardware/amba_serial.h b/include/asm-arm/hardware/amba_serial.h
new file mode 100644
index 000000000000..71770aa6389f
--- /dev/null
+++ b/include/asm-arm/hardware/amba_serial.h
@@ -0,0 +1,156 @@
1/*
2 * linux/include/asm-arm/hardware/serial_amba.h
3 *
4 * Internal header file for AMBA serial ports
5 *
6 * Copyright (C) ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
24#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
25
26/* -------------------------------------------------------------------------------
27 * From AMBA UART (PL010) Block Specification
28 * -------------------------------------------------------------------------------
29 * UART Register Offsets.
30 */
31#define UART01x_DR 0x00 /* Data read or written from the interface. */
32#define UART01x_RSR 0x04 /* Receive status register (Read). */
33#define UART01x_ECR 0x04 /* Error clear register (Write). */
34#define UART010_LCRH 0x08 /* Line control register, high byte. */
35#define UART010_LCRM 0x0C /* Line control register, middle byte. */
36#define UART010_LCRL 0x10 /* Line control register, low byte. */
37#define UART010_CR 0x14 /* Control register. */
38#define UART01x_FR 0x18 /* Flag register (Read only). */
39#define UART010_IIR 0x1C /* Interrupt indentification register (Read). */
40#define UART010_ICR 0x1C /* Interrupt clear register (Write). */
41#define UART01x_ILPR 0x20 /* IrDA low power counter register. */
42#define UART011_IBRD 0x24 /* Integer baud rate divisor register. */
43#define UART011_FBRD 0x28 /* Fractional baud rate divisor register. */
44#define UART011_LCRH 0x2c /* Line control register. */
45#define UART011_CR 0x30 /* Control register. */
46#define UART011_IFLS 0x34 /* Interrupt fifo level select. */
47#define UART011_IMSC 0x38 /* Interrupt mask. */
48#define UART011_RIS 0x3c /* Raw interrupt status. */
49#define UART011_MIS 0x40 /* Masked interrupt status. */
50#define UART011_ICR 0x44 /* Interrupt clear register. */
51#define UART011_DMACR 0x48 /* DMA control register. */
52
53#define UART01x_RSR_OE 0x08
54#define UART01x_RSR_BE 0x04
55#define UART01x_RSR_PE 0x02
56#define UART01x_RSR_FE 0x01
57
58#define UART011_FR_RI 0x100
59#define UART011_FR_TXFE 0x080
60#define UART011_FR_RXFF 0x040
61#define UART01x_FR_TXFF 0x020
62#define UART01x_FR_RXFE 0x010
63#define UART01x_FR_BUSY 0x008
64#define UART01x_FR_DCD 0x004
65#define UART01x_FR_DSR 0x002
66#define UART01x_FR_CTS 0x001
67#define UART01x_FR_TMSK (UART01x_FR_TXFF + UART01x_FR_BUSY)
68
69#define UART011_CR_CTSEN 0x8000 /* CTS hardware flow control */
70#define UART011_CR_RTSEN 0x4000 /* RTS hardware flow control */
71#define UART011_CR_OUT2 0x2000 /* OUT2 */
72#define UART011_CR_OUT1 0x1000 /* OUT1 */
73#define UART011_CR_RTS 0x0800 /* RTS */
74#define UART011_CR_DTR 0x0400 /* DTR */
75#define UART011_CR_RXE 0x0200 /* receive enable */
76#define UART011_CR_TXE 0x0100 /* transmit enable */
77#define UART011_CR_LBE 0x0080 /* loopback enable */
78#define UART010_CR_RTIE 0x0040
79#define UART010_CR_TIE 0x0020
80#define UART010_CR_RIE 0x0010
81#define UART010_CR_MSIE 0x0008
82#define UART01x_CR_IIRLP 0x0004 /* SIR low power mode */
83#define UART01x_CR_SIREN 0x0002 /* SIR enable */
84#define UART01x_CR_UARTEN 0x0001 /* UART enable */
85
86#define UART011_LCRH_SPS 0x80
87#define UART01x_LCRH_WLEN_8 0x60
88#define UART01x_LCRH_WLEN_7 0x40
89#define UART01x_LCRH_WLEN_6 0x20
90#define UART01x_LCRH_WLEN_5 0x00
91#define UART01x_LCRH_FEN 0x10
92#define UART01x_LCRH_STP2 0x08
93#define UART01x_LCRH_EPS 0x04
94#define UART01x_LCRH_PEN 0x02
95#define UART01x_LCRH_BRK 0x01
96
97#define UART010_IIR_RTIS 0x08
98#define UART010_IIR_TIS 0x04
99#define UART010_IIR_RIS 0x02
100#define UART010_IIR_MIS 0x01
101
102#define UART011_IFLS_RX1_8 (0 << 3)
103#define UART011_IFLS_RX2_8 (1 << 3)
104#define UART011_IFLS_RX4_8 (2 << 3)
105#define UART011_IFLS_RX6_8 (3 << 3)
106#define UART011_IFLS_RX7_8 (4 << 3)
107#define UART011_IFLS_TX1_8 (0 << 0)
108#define UART011_IFLS_TX2_8 (1 << 0)
109#define UART011_IFLS_TX4_8 (2 << 0)
110#define UART011_IFLS_TX6_8 (3 << 0)
111#define UART011_IFLS_TX7_8 (4 << 0)
112
113#define UART011_OEIM (1 << 10) /* overrun error interrupt mask */
114#define UART011_BEIM (1 << 9) /* break error interrupt mask */
115#define UART011_PEIM (1 << 8) /* parity error interrupt mask */
116#define UART011_FEIM (1 << 7) /* framing error interrupt mask */
117#define UART011_RTIM (1 << 6) /* receive timeout interrupt mask */
118#define UART011_TXIM (1 << 5) /* transmit interrupt mask */
119#define UART011_RXIM (1 << 4) /* receive interrupt mask */
120#define UART011_DSRMIM (1 << 3) /* DSR interrupt mask */
121#define UART011_DCDMIM (1 << 2) /* DCD interrupt mask */
122#define UART011_CTSMIM (1 << 1) /* CTS interrupt mask */
123#define UART011_RIMIM (1 << 0) /* RI interrupt mask */
124
125#define UART011_OEIS (1 << 10) /* overrun error interrupt status */
126#define UART011_BEIS (1 << 9) /* break error interrupt status */
127#define UART011_PEIS (1 << 8) /* parity error interrupt status */
128#define UART011_FEIS (1 << 7) /* framing error interrupt status */
129#define UART011_RTIS (1 << 6) /* receive timeout interrupt status */
130#define UART011_TXIS (1 << 5) /* transmit interrupt status */
131#define UART011_RXIS (1 << 4) /* receive interrupt status */
132#define UART011_DSRMIS (1 << 3) /* DSR interrupt status */
133#define UART011_DCDMIS (1 << 2) /* DCD interrupt status */
134#define UART011_CTSMIS (1 << 1) /* CTS interrupt status */
135#define UART011_RIMIS (1 << 0) /* RI interrupt status */
136
137#define UART011_OEIC (1 << 10) /* overrun error interrupt clear */
138#define UART011_BEIC (1 << 9) /* break error interrupt clear */
139#define UART011_PEIC (1 << 8) /* parity error interrupt clear */
140#define UART011_FEIC (1 << 7) /* framing error interrupt clear */
141#define UART011_RTIC (1 << 6) /* receive timeout interrupt clear */
142#define UART011_TXIC (1 << 5) /* transmit interrupt clear */
143#define UART011_RXIC (1 << 4) /* receive interrupt clear */
144#define UART011_DSRMIC (1 << 3) /* DSR interrupt clear */
145#define UART011_DCDMIC (1 << 2) /* DCD interrupt clear */
146#define UART011_CTSMIC (1 << 1) /* CTS interrupt clear */
147#define UART011_RIMIC (1 << 0) /* RI interrupt clear */
148
149#define UART011_DMAONERR (1 << 2) /* disable dma on error */
150#define UART011_TXDMAE (1 << 1) /* enable transmit dma */
151#define UART011_RXDMAE (1 << 0) /* enable receive dma */
152
153#define UART01x_RSR_ANY (UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
154#define UART01x_FR_MODEM_ANY (UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
155
156#endif
diff --git a/include/asm-arm/hardware/clock.h b/include/asm-arm/hardware/clock.h
new file mode 100644
index 000000000000..4983449ff2c7
--- /dev/null
+++ b/include/asm-arm/hardware/clock.h
@@ -0,0 +1,121 @@
1/*
2 * linux/include/asm-arm/hardware/clock.h
3 *
4 * Copyright (C) 2004 ARM Limited.
5 * Written by Deep Blue Solutions Limited.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef ASMARM_CLOCK_H
12#define ASMARM_CLOCK_H
13
14struct device;
15
16/*
17 * The base API.
18 */
19
20
21/*
22 * struct clk - an machine class defined object / cookie.
23 */
24struct clk;
25
26/**
27 * clk_get - lookup and obtain a reference to a clock producer.
28 * @dev: device for clock "consumer"
29 * @id: device ID
30 *
31 * Returns a struct clk corresponding to the clock producer, or
32 * valid IS_ERR() condition containing errno.
33 */
34struct clk *clk_get(struct device *dev, const char *id);
35
36/**
37 * clk_enable - inform the system when the clock source should be running.
38 * @clk: clock source
39 *
40 * If the clock can not be enabled/disabled, this should return success.
41 *
42 * Returns success (0) or negative errno.
43 */
44int clk_enable(struct clk *clk);
45
46/**
47 * clk_disable - inform the system when the clock source is no longer required.
48 * @clk: clock source
49 */
50void clk_disable(struct clk *clk);
51
52/**
53 * clk_use - increment the use count
54 * @clk: clock source
55 *
56 * Returns success (0) or negative errno.
57 */
58int clk_use(struct clk *clk);
59
60/**
61 * clk_unuse - decrement the use count
62 * @clk: clock source
63 */
64void clk_unuse(struct clk *clk);
65
66/**
67 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source.
68 * This is only valid once the clock source has been enabled.
69 * @clk: clock source
70 */
71unsigned long clk_get_rate(struct clk *clk);
72
73/**
74 * clk_put - "free" the clock source
75 * @clk: clock source
76 */
77void clk_put(struct clk *clk);
78
79
80/*
81 * The remaining APIs are optional for machine class support.
82 */
83
84
85/**
86 * clk_round_rate - adjust a rate to the exact rate a clock can provide
87 * @clk: clock source
88 * @rate: desired clock rate in Hz
89 *
90 * Returns rounded clock rate in Hz, or negative errno.
91 */
92long clk_round_rate(struct clk *clk, unsigned long rate);
93
94/**
95 * clk_set_rate - set the clock rate for a clock source
96 * @clk: clock source
97 * @rate: desired clock rate in Hz
98 *
99 * Returns success (0) or negative errno.
100 */
101int clk_set_rate(struct clk *clk, unsigned long rate);
102
103/**
104 * clk_set_parent - set the parent clock source for this clock
105 * @clk: clock source
106 * @parent: parent clock source
107 *
108 * Returns success (0) or negative errno.
109 */
110int clk_set_parent(struct clk *clk, struct clk *parent);
111
112/**
113 * clk_get_parent - get the parent clock source for this clock
114 * @clk: clock source
115 *
116 * Returns struct clk corresponding to parent clock source, or
117 * valid IS_ERR() condition containing errno.
118 */
119struct clk *clk_get_parent(struct clk *clk);
120
121#endif
diff --git a/include/asm-arm/hardware/clps7111.h b/include/asm-arm/hardware/clps7111.h
new file mode 100644
index 000000000000..8d3228dc1778
--- /dev/null
+++ b/include/asm-arm/hardware/clps7111.h
@@ -0,0 +1,184 @@
1/*
2 * linux/include/asm-arm/hardware/clps7111.h
3 *
4 * This file contains the hardware definitions of the CLPS7111 internal
5 * registers.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_CLPS7111_H
24#define __ASM_HARDWARE_CLPS7111_H
25
26#define CLPS7111_PHYS_BASE (0x80000000)
27
28#ifndef __ASSEMBLY__
29#define clps_readb(off) __raw_readb(CLPS7111_BASE + (off))
30#define clps_readw(off) __raw_readw(CLPS7111_BASE + (off))
31#define clps_readl(off) __raw_readl(CLPS7111_BASE + (off))
32#define clps_writeb(val,off) __raw_writeb(val, CLPS7111_BASE + (off))
33#define clps_writew(val,off) __raw_writew(val, CLPS7111_BASE + (off))
34#define clps_writel(val,off) __raw_writel(val, CLPS7111_BASE + (off))
35#endif
36
37#define PADR (0x0000)
38#define PBDR (0x0001)
39#define PDDR (0x0003)
40#define PADDR (0x0040)
41#define PBDDR (0x0041)
42#define PDDDR (0x0043)
43#define PEDR (0x0080)
44#define PEDDR (0x00c0)
45#define SYSCON1 (0x0100)
46#define SYSFLG1 (0x0140)
47#define MEMCFG1 (0x0180)
48#define MEMCFG2 (0x01c0)
49#define DRFPR (0x0200)
50#define INTSR1 (0x0240)
51#define INTMR1 (0x0280)
52#define LCDCON (0x02c0)
53#define TC1D (0x0300)
54#define TC2D (0x0340)
55#define RTCDR (0x0380)
56#define RTCMR (0x03c0)
57#define PMPCON (0x0400)
58#define CODR (0x0440)
59#define UARTDR1 (0x0480)
60#define UBRLCR1 (0x04c0)
61#define SYNCIO (0x0500)
62#define PALLSW (0x0540)
63#define PALMSW (0x0580)
64#define STFCLR (0x05c0)
65#define BLEOI (0x0600)
66#define MCEOI (0x0640)
67#define TEOI (0x0680)
68#define TC1EOI (0x06c0)
69#define TC2EOI (0x0700)
70#define RTCEOI (0x0740)
71#define UMSEOI (0x0780)
72#define COEOI (0x07c0)
73#define HALT (0x0800)
74#define STDBY (0x0840)
75
76#define FBADDR (0x1000)
77#define SYSCON2 (0x1100)
78#define SYSFLG2 (0x1140)
79#define INTSR2 (0x1240)
80#define INTMR2 (0x1280)
81#define UARTDR2 (0x1480)
82#define UBRLCR2 (0x14c0)
83#define SS2DR (0x1500)
84#define SRXEOF (0x1600)
85#define SS2POP (0x16c0)
86#define KBDEOI (0x1700)
87
88/* common bits: SYSCON1 / SYSCON2 */
89#define SYSCON_UARTEN (1 << 8)
90
91#define SYSCON1_KBDSCAN(x) ((x) & 15)
92#define SYSCON1_KBDSCANMASK (15)
93#define SYSCON1_TC1M (1 << 4)
94#define SYSCON1_TC1S (1 << 5)
95#define SYSCON1_TC2M (1 << 6)
96#define SYSCON1_TC2S (1 << 7)
97#define SYSCON1_UART1EN SYSCON_UARTEN
98#define SYSCON1_BZTOG (1 << 9)
99#define SYSCON1_BZMOD (1 << 10)
100#define SYSCON1_DBGEN (1 << 11)
101#define SYSCON1_LCDEN (1 << 12)
102#define SYSCON1_CDENTX (1 << 13)
103#define SYSCON1_CDENRX (1 << 14)
104#define SYSCON1_SIREN (1 << 15)
105#define SYSCON1_ADCKSEL(x) (((x) & 3) << 16)
106#define SYSCON1_ADCKSEL_MASK (3 << 16)
107#define SYSCON1_EXCKEN (1 << 18)
108#define SYSCON1_WAKEDIS (1 << 19)
109#define SYSCON1_IRTXM (1 << 20)
110
111/* common bits: SYSFLG1 / SYSFLG2 */
112#define SYSFLG_UBUSY (1 << 11)
113#define SYSFLG_URXFE (1 << 22)
114#define SYSFLG_UTXFF (1 << 23)
115
116#define SYSFLG1_MCDR (1 << 0)
117#define SYSFLG1_DCDET (1 << 1)
118#define SYSFLG1_WUDR (1 << 2)
119#define SYSFLG1_WUON (1 << 3)
120#define SYSFLG1_CTS (1 << 8)
121#define SYSFLG1_DSR (1 << 9)
122#define SYSFLG1_DCD (1 << 10)
123#define SYSFLG1_UBUSY SYSFLG_UBUSY
124#define SYSFLG1_NBFLG (1 << 12)
125#define SYSFLG1_RSTFLG (1 << 13)
126#define SYSFLG1_PFFLG (1 << 14)
127#define SYSFLG1_CLDFLG (1 << 15)
128#define SYSFLG1_URXFE SYSFLG_URXFE
129#define SYSFLG1_UTXFF SYSFLG_UTXFF
130#define SYSFLG1_CRXFE (1 << 24)
131#define SYSFLG1_CTXFF (1 << 25)
132#define SYSFLG1_SSIBUSY (1 << 26)
133#define SYSFLG1_ID (1 << 29)
134
135#define SYSFLG2_SSRXOF (1 << 0)
136#define SYSFLG2_RESVAL (1 << 1)
137#define SYSFLG2_RESFRM (1 << 2)
138#define SYSFLG2_SS2RXFE (1 << 3)
139#define SYSFLG2_SS2TXFF (1 << 4)
140#define SYSFLG2_SS2TXUF (1 << 5)
141#define SYSFLG2_CKMODE (1 << 6)
142#define SYSFLG2_UBUSY SYSFLG_UBUSY
143#define SYSFLG2_URXFE SYSFLG_URXFE
144#define SYSFLG2_UTXFF SYSFLG_UTXFF
145
146#define LCDCON_GSEN (1 << 30)
147#define LCDCON_GSMD (1 << 31)
148
149#define SYSCON2_SERSEL (1 << 0)
150#define SYSCON2_KBD6 (1 << 1)
151#define SYSCON2_DRAMZ (1 << 2)
152#define SYSCON2_KBWEN (1 << 3)
153#define SYSCON2_SS2TXEN (1 << 4)
154#define SYSCON2_PCCARD1 (1 << 5)
155#define SYSCON2_PCCARD2 (1 << 6)
156#define SYSCON2_SS2RXEN (1 << 7)
157#define SYSCON2_UART2EN SYSCON_UARTEN
158#define SYSCON2_SS2MAEN (1 << 9)
159#define SYSCON2_OSTB (1 << 12)
160#define SYSCON2_CLKENSL (1 << 13)
161#define SYSCON2_BUZFREQ (1 << 14)
162
163/* common bits: UARTDR1 / UARTDR2 */
164#define UARTDR_FRMERR (1 << 8)
165#define UARTDR_PARERR (1 << 9)
166#define UARTDR_OVERR (1 << 10)
167
168/* common bits: UBRLCR1 / UBRLCR2 */
169#define UBRLCR_BAUD_MASK ((1 << 12) - 1)
170#define UBRLCR_BREAK (1 << 12)
171#define UBRLCR_PRTEN (1 << 13)
172#define UBRLCR_EVENPRT (1 << 14)
173#define UBRLCR_XSTOP (1 << 15)
174#define UBRLCR_FIFOEN (1 << 16)
175#define UBRLCR_WRDLEN5 (0 << 17)
176#define UBRLCR_WRDLEN6 (1 << 17)
177#define UBRLCR_WRDLEN7 (2 << 17)
178#define UBRLCR_WRDLEN8 (3 << 17)
179#define UBRLCR_WRDLEN_MASK (3 << 17)
180
181#define SYNCIO_SMCKEN (1 << 13)
182#define SYNCIO_TXFRMEN (1 << 14)
183
184#endif /* __ASM_HARDWARE_CLPS7111_H */
diff --git a/include/asm-arm/hardware/cs89712.h b/include/asm-arm/hardware/cs89712.h
new file mode 100644
index 000000000000..ad99a3e1b802
--- /dev/null
+++ b/include/asm-arm/hardware/cs89712.h
@@ -0,0 +1,49 @@
1/*
2 * linux/include/asm-arm/hardware/cs89712.h
3 *
4 * This file contains the hardware definitions of the CS89712
5 * additional internal registers.
6 *
7 * Copyright (C) 2001 Thomas Gleixner autronix automation <gleixner@autronix.de>
8 *
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 */
24#ifndef __ASM_HARDWARE_CS89712_H
25#define __ASM_HARDWARE_CS89712_H
26
27/*
28* CS89712 additional registers
29*/
30
31#define PCDR 0x0002 /* Port C Data register ---------------------------- */
32#define PCDDR 0x0042 /* Port C Data Direction register ------------------ */
33#define SDCONF 0x2300 /* SDRAM Configuration register ---------------------*/
34#define SDRFPR 0x2340 /* SDRAM Refresh period register --------------------*/
35
36#define SDCONF_ACTIVE (1 << 10)
37#define SDCONF_CLKCTL (1 << 9)
38#define SDCONF_WIDTH_4 (0 << 7)
39#define SDCONF_WIDTH_8 (1 << 7)
40#define SDCONF_WIDTH_16 (2 << 7)
41#define SDCONF_WIDTH_32 (3 << 7)
42#define SDCONF_SIZE_16 (0 << 5)
43#define SDCONF_SIZE_64 (1 << 5)
44#define SDCONF_SIZE_128 (2 << 5)
45#define SDCONF_SIZE_256 (3 << 5)
46#define SDCONF_CASLAT_2 (2)
47#define SDCONF_CASLAT_3 (3)
48
49#endif /* __ASM_HARDWARE_CS89712_H */
diff --git a/include/asm-arm/hardware/dec21285.h b/include/asm-arm/hardware/dec21285.h
new file mode 100644
index 000000000000..9049f0ddaecf
--- /dev/null
+++ b/include/asm-arm/hardware/dec21285.h
@@ -0,0 +1,148 @@
1/*
2 * linux/include/asm-arm/hardware/dec21285.h
3 *
4 * Copyright (C) 1998 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * DC21285 registers
11 */
12#define DC21285_PCI_IACK 0x79000000
13#define DC21285_ARMCSR_BASE 0x42000000
14#define DC21285_PCI_TYPE_0_CONFIG 0x7b000000
15#define DC21285_PCI_TYPE_1_CONFIG 0x7a000000
16#define DC21285_OUTBOUND_WRITE_FLUSH 0x78000000
17#define DC21285_FLASH 0x41000000
18#define DC21285_PCI_IO 0x7c000000
19#define DC21285_PCI_MEM 0x80000000
20
21#include <linux/config.h>
22#ifndef __ASSEMBLY__
23#include <asm/arch/hardware.h>
24#define DC21285_IO(x) ((volatile unsigned long *)(ARMCSR_BASE+(x)))
25#else
26#define DC21285_IO(x) (x)
27#endif
28
29#define CSR_PCICMD DC21285_IO(0x0004)
30#define CSR_CLASSREV DC21285_IO(0x0008)
31#define CSR_PCICACHELINESIZE DC21285_IO(0x000c)
32#define CSR_PCICSRBASE DC21285_IO(0x0010)
33#define CSR_PCICSRIOBASE DC21285_IO(0x0014)
34#define CSR_PCISDRAMBASE DC21285_IO(0x0018)
35#define CSR_PCIROMBASE DC21285_IO(0x0030)
36#define CSR_MBOX0 DC21285_IO(0x0050)
37#define CSR_MBOX1 DC21285_IO(0x0054)
38#define CSR_MBOX2 DC21285_IO(0x0058)
39#define CSR_MBOX3 DC21285_IO(0x005c)
40#define CSR_DOORBELL DC21285_IO(0x0060)
41#define CSR_DOORBELL_SETUP DC21285_IO(0x0064)
42#define CSR_ROMWRITEREG DC21285_IO(0x0068)
43#define CSR_CSRBASEMASK DC21285_IO(0x00f8)
44#define CSR_CSRBASEOFFSET DC21285_IO(0x00fc)
45#define CSR_SDRAMBASEMASK DC21285_IO(0x0100)
46#define CSR_SDRAMBASEOFFSET DC21285_IO(0x0104)
47#define CSR_ROMBASEMASK DC21285_IO(0x0108)
48#define CSR_SDRAMTIMING DC21285_IO(0x010c)
49#define CSR_SDRAMADDRSIZE0 DC21285_IO(0x0110)
50#define CSR_SDRAMADDRSIZE1 DC21285_IO(0x0114)
51#define CSR_SDRAMADDRSIZE2 DC21285_IO(0x0118)
52#define CSR_SDRAMADDRSIZE3 DC21285_IO(0x011c)
53#define CSR_I2O_INFREEHEAD DC21285_IO(0x0120)
54#define CSR_I2O_INPOSTTAIL DC21285_IO(0x0124)
55#define CSR_I2O_OUTPOSTHEAD DC21285_IO(0x0128)
56#define CSR_I2O_OUTFREETAIL DC21285_IO(0x012c)
57#define CSR_I2O_INFREECOUNT DC21285_IO(0x0130)
58#define CSR_I2O_OUTPOSTCOUNT DC21285_IO(0x0134)
59#define CSR_I2O_INPOSTCOUNT DC21285_IO(0x0138)
60#define CSR_SA110_CNTL DC21285_IO(0x013c)
61#define SA110_CNTL_INITCMPLETE (1 << 0)
62#define SA110_CNTL_ASSERTSERR (1 << 1)
63#define SA110_CNTL_RXSERR (1 << 3)
64#define SA110_CNTL_SA110DRAMPARITY (1 << 4)
65#define SA110_CNTL_PCISDRAMPARITY (1 << 5)
66#define SA110_CNTL_DMASDRAMPARITY (1 << 6)
67#define SA110_CNTL_DISCARDTIMER (1 << 8)
68#define SA110_CNTL_PCINRESET (1 << 9)
69#define SA110_CNTL_I2O_256 (0 << 10)
70#define SA110_CNTL_I20_512 (1 << 10)
71#define SA110_CNTL_I2O_1024 (2 << 10)
72#define SA110_CNTL_I2O_2048 (3 << 10)
73#define SA110_CNTL_I2O_4096 (4 << 10)
74#define SA110_CNTL_I2O_8192 (5 << 10)
75#define SA110_CNTL_I2O_16384 (6 << 10)
76#define SA110_CNTL_I2O_32768 (7 << 10)
77#define SA110_CNTL_WATCHDOG (1 << 13)
78#define SA110_CNTL_ROMWIDTH_UNDEF (0 << 14)
79#define SA110_CNTL_ROMWIDTH_16 (1 << 14)
80#define SA110_CNTL_ROMWIDTH_32 (2 << 14)
81#define SA110_CNTL_ROMWIDTH_8 (3 << 14)
82#define SA110_CNTL_ROMACCESSTIME(x) ((x)<<16)
83#define SA110_CNTL_ROMBURSTTIME(x) ((x)<<20)
84#define SA110_CNTL_ROMTRISTATETIME(x) ((x)<<24)
85#define SA110_CNTL_XCSDIR(x) ((x)<<28)
86#define SA110_CNTL_PCICFN (1 << 31)
87
88/*
89 * footbridge_cfn_mode() is used when we want
90 * to check whether we are the central function
91 */
92#define __footbridge_cfn_mode() (*CSR_SA110_CNTL & SA110_CNTL_PCICFN)
93#if defined(CONFIG_FOOTBRIDGE_HOST) && defined(CONFIG_FOOTBRIDGE_ADDIN)
94#define footbridge_cfn_mode() __footbridge_cfn_mode()
95#elif defined(CONFIG_FOOTBRIDGE_HOST)
96#define footbridge_cfn_mode() (1)
97#else
98#define footbridge_cfn_mode() (0)
99#endif
100
101#define CSR_PCIADDR_EXTN DC21285_IO(0x0140)
102#define CSR_PREFETCHMEMRANGE DC21285_IO(0x0144)
103#define CSR_XBUS_CYCLE DC21285_IO(0x0148)
104#define CSR_XBUS_IOSTROBE DC21285_IO(0x014c)
105#define CSR_DOORBELL_PCI DC21285_IO(0x0150)
106#define CSR_DOORBELL_SA110 DC21285_IO(0x0154)
107#define CSR_UARTDR DC21285_IO(0x0160)
108#define CSR_RXSTAT DC21285_IO(0x0164)
109#define CSR_H_UBRLCR DC21285_IO(0x0168)
110#define CSR_M_UBRLCR DC21285_IO(0x016c)
111#define CSR_L_UBRLCR DC21285_IO(0x0170)
112#define CSR_UARTCON DC21285_IO(0x0174)
113#define CSR_UARTFLG DC21285_IO(0x0178)
114#define CSR_IRQ_STATUS DC21285_IO(0x0180)
115#define CSR_IRQ_RAWSTATUS DC21285_IO(0x0184)
116#define CSR_IRQ_ENABLE DC21285_IO(0x0188)
117#define CSR_IRQ_DISABLE DC21285_IO(0x018c)
118#define CSR_IRQ_SOFT DC21285_IO(0x0190)
119#define CSR_FIQ_STATUS DC21285_IO(0x0280)
120#define CSR_FIQ_RAWSTATUS DC21285_IO(0x0284)
121#define CSR_FIQ_ENABLE DC21285_IO(0x0288)
122#define CSR_FIQ_DISABLE DC21285_IO(0x028c)
123#define CSR_FIQ_SOFT DC21285_IO(0x0290)
124#define CSR_TIMER1_LOAD DC21285_IO(0x0300)
125#define CSR_TIMER1_VALUE DC21285_IO(0x0304)
126#define CSR_TIMER1_CNTL DC21285_IO(0x0308)
127#define CSR_TIMER1_CLR DC21285_IO(0x030c)
128#define CSR_TIMER2_LOAD DC21285_IO(0x0320)
129#define CSR_TIMER2_VALUE DC21285_IO(0x0324)
130#define CSR_TIMER2_CNTL DC21285_IO(0x0328)
131#define CSR_TIMER2_CLR DC21285_IO(0x032c)
132#define CSR_TIMER3_LOAD DC21285_IO(0x0340)
133#define CSR_TIMER3_VALUE DC21285_IO(0x0344)
134#define CSR_TIMER3_CNTL DC21285_IO(0x0348)
135#define CSR_TIMER3_CLR DC21285_IO(0x034c)
136#define CSR_TIMER4_LOAD DC21285_IO(0x0360)
137#define CSR_TIMER4_VALUE DC21285_IO(0x0364)
138#define CSR_TIMER4_CNTL DC21285_IO(0x0368)
139#define CSR_TIMER4_CLR DC21285_IO(0x036c)
140
141#define TIMER_CNTL_ENABLE (1 << 7)
142#define TIMER_CNTL_AUTORELOAD (1 << 6)
143#define TIMER_CNTL_DIV1 (0)
144#define TIMER_CNTL_DIV16 (1 << 2)
145#define TIMER_CNTL_DIV256 (2 << 2)
146#define TIMER_CNTL_CNTEXT (3 << 2)
147
148
diff --git a/include/asm-arm/hardware/entry-macro-iomd.S b/include/asm-arm/hardware/entry-macro-iomd.S
new file mode 100644
index 000000000000..30c7b92c2416
--- /dev/null
+++ b/include/asm-arm/hardware/entry-macro-iomd.S
@@ -0,0 +1,145 @@
1/*
2 * arch/arm/commond/entry-macro-iomd.S
3 *
4 * Low-level IRQ helper macros for IOC/IOMD based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11/* IOC / IOMD based hardware */
12#include <asm/hardware/iomd.h>
13
14 .equ ioc_base_high, IOC_BASE & 0xff000000
15 .equ ioc_base_low, IOC_BASE & 0x00ff0000
16 .macro disable_fiq
17 mov r12, #ioc_base_high
18 .if ioc_base_low
19 orr r12, r12, #ioc_base_low
20 .endif
21 strb r12, [r12, #0x38] @ Disable FIQ register
22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 mov r4, #ioc_base_high @ point at IOC
26 .if ioc_base_low
27 orr r4, r4, #ioc_base_low
28 .endif
29 ldrb \irqstat, [r4, #IOMD_IRQREQB] @ get high priority first
30 ldr \base, =irq_prio_h
31 teq \irqstat, #0
32#ifdef IOMD_BASE
33 ldreqb \irqstat, [r4, #IOMD_DMAREQ] @ get dma
34 addeq \base, \base, #256 @ irq_prio_h table size
35 teqeq \irqstat, #0
36 bne 2406f
37#endif
38 ldreqb \irqstat, [r4, #IOMD_IRQREQA] @ get low priority
39 addeq \base, \base, #256 @ irq_prio_d table size
40 teqeq \irqstat, #0
41#ifdef IOMD_IRQREQC
42 ldreqb \irqstat, [r4, #IOMD_IRQREQC]
43 addeq \base, \base, #256 @ irq_prio_l table size
44 teqeq \irqstat, #0
45#endif
46#ifdef IOMD_IRQREQD
47 ldreqb \irqstat, [r4, #IOMD_IRQREQD]
48 addeq \base, \base, #256 @ irq_prio_lc table size
49 teqeq \irqstat, #0
50#endif
512406: ldrneb \irqnr, [\base, \irqstat] @ get IRQ number
52 .endm
53
54/*
55 * Interrupt table (incorporates priority). Please note that we
56 * rely on the order of these tables (see above code).
57 */
58 .align 5
59irq_prio_h: .byte 0, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
60 .byte 12, 8, 9, 8,10,10,10,10,11,11,11,11,10,10,10,10
61 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
62 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
63 .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
64 .byte 14,14,14,14,10,10,10,10,11,11,11,11,10,10,10,10
65 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
66 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
67 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
68 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
69 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
70 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
71 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
72 .byte 15,15,15,15,10,10,10,10,11,11,11,11,10,10,10,10
73 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
74 .byte 13,13,13,13,10,10,10,10,11,11,11,11,10,10,10,10
75#ifdef IOMD_BASE
76irq_prio_d: .byte 0,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
77 .byte 20,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
78 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
79 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
80 .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
81 .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
82 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
83 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
84 .byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
85 .byte 23,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
86 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
87 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
88 .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
89 .byte 22,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
90 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
91 .byte 21,16,17,16,18,16,17,16,19,16,17,16,18,16,17,16
92#endif
93irq_prio_l: .byte 0, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
94 .byte 4, 0, 1, 0, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3
95 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
96 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
97 .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
98 .byte 6, 6, 6, 6, 6, 6, 6, 6, 3, 3, 3, 3, 3, 3, 3, 3
99 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
100 .byte 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5
101 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
102 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
103 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
104 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
105 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
106 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
107 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
108 .byte 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7
109#ifdef IOMD_IRQREQC
110irq_prio_lc: .byte 24,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
111 .byte 28,24,25,24,26,26,26,26,27,27,27,27,27,27,27,27
112 .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
113 .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
114 .byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
115 .byte 30,30,30,30,30,30,30,30,27,27,27,27,27,27,27,27
116 .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
117 .byte 29,29,29,29,29,29,29,29,29,29,29,29,29,29,29,29
118 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
119 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
120 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
121 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
122 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
123 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
124 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
125 .byte 31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31
126#endif
127#ifdef IOMD_IRQREQD
128irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
129 .byte 44,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
130 .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
131 .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
132 .byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
133 .byte 46,46,46,46,46,46,46,46,43,43,43,43,43,43,43,43
134 .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
135 .byte 45,45,45,45,45,45,45,45,45,45,45,45,45,45,45,45
136 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
137 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
138 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
139 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
140 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
141 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
142 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
143 .byte 47,47,47,47,47,47,47,47,47,47,47,47,47,47,47,47
144#endif
145
diff --git a/include/asm-arm/hardware/ep7211.h b/include/asm-arm/hardware/ep7211.h
new file mode 100644
index 000000000000..017aa68f612d
--- /dev/null
+++ b/include/asm-arm/hardware/ep7211.h
@@ -0,0 +1,40 @@
1/*
2 * linux/include/asm-arm/hardware/ep7211.h
3 *
4 * This file contains the hardware definitions of the EP7211 internal
5 * registers.
6 *
7 * Copyright (C) 2001 Blue Mug, Inc. All Rights Reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_EP7211_H
24#define __ASM_HARDWARE_EP7211_H
25
26#include <asm/hardware/clps7111.h>
27
28/*
29 * define EP7211_BASE to be the base address of the region
30 * you want to access.
31 */
32
33#define EP7211_PHYS_BASE (0x80000000)
34
35/*
36 * XXX miket@bluemug.com: need to introduce EP7211 registers (those not
37 * present in 7212) here.
38 */
39
40#endif /* __ASM_HARDWARE_EP7211_H */
diff --git a/include/asm-arm/hardware/ep7212.h b/include/asm-arm/hardware/ep7212.h
new file mode 100644
index 000000000000..0e952e747073
--- /dev/null
+++ b/include/asm-arm/hardware/ep7212.h
@@ -0,0 +1,83 @@
1/*
2 * linux/include/asm-arm/hardware/ep7212.h
3 *
4 * This file contains the hardware definitions of the EP7212 internal
5 * registers.
6 *
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef __ASM_HARDWARE_EP7212_H
24#define __ASM_HARDWARE_EP7212_H
25
26/*
27 * define EP7212_BASE to be the base address of the region
28 * you want to access.
29 */
30
31#define EP7212_PHYS_BASE (0x80000000)
32
33#ifndef __ASSEMBLY__
34#define ep_readl(off) __raw_readl(EP7212_BASE + (off))
35#define ep_writel(val,off) __raw_writel(val, EP7212_BASE + (off))
36#endif
37
38/*
39 * These registers are specific to the EP7212 only
40 */
41#define DAIR 0x2000
42#define DAIR0 0x2040
43#define DAIDR1 0x2080
44#define DAIDR2 0x20c0
45#define DAISR 0x2100
46#define SYSCON3 0x2200
47#define INTSR3 0x2240
48#define INTMR3 0x2280
49#define LEDFLSH 0x22c0
50
51#define DAIR_DAIEN (1 << 16)
52#define DAIR_ECS (1 << 17)
53#define DAIR_LCTM (1 << 19)
54#define DAIR_LCRM (1 << 20)
55#define DAIR_RCTM (1 << 21)
56#define DAIR_RCRM (1 << 22)
57#define DAIR_LBM (1 << 23)
58
59#define DAIDR2_FIFOEN (1 << 15)
60#define DAIDR2_FIFOLEFT (0x0d << 16)
61#define DAIDR2_FIFORIGHT (0x11 << 16)
62
63#define DAISR_RCTS (1 << 0)
64#define DAISR_RCRS (1 << 1)
65#define DAISR_LCTS (1 << 2)
66#define DAISR_LCRS (1 << 3)
67#define DAISR_RCTU (1 << 4)
68#define DAISR_RCRO (1 << 5)
69#define DAISR_LCTU (1 << 6)
70#define DAISR_LCRO (1 << 7)
71#define DAISR_RCNF (1 << 8)
72#define DAISR_RCNE (1 << 9)
73#define DAISR_LCNF (1 << 10)
74#define DAISR_LCNE (1 << 11)
75#define DAISR_FIFO (1 << 12)
76
77#define SYSCON3_ADCCON (1 << 0)
78#define SYSCON3_DAISEL (1 << 3)
79#define SYSCON3_ADCCKNSEN (1 << 4)
80#define SYSCON3_FASTWAKE (1 << 8)
81#define SYSCON3_DAIEN (1 << 9)
82
83#endif /* __ASM_HARDWARE_EP7212_H */
diff --git a/include/asm-arm/hardware/icst307.h b/include/asm-arm/hardware/icst307.h
new file mode 100644
index 000000000000..ff8618a441c0
--- /dev/null
+++ b/include/asm-arm/hardware/icst307.h
@@ -0,0 +1,38 @@
1/*
2 * linux/include/asm-arm/hardware/icst307.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Support functions for calculating clocks/divisors for the ICS307
11 * clock generators. See http://www.icst.com/ for more information
12 * on these devices.
13 *
14 * This file is similar to the icst525.h file
15 */
16#ifndef ASMARM_HARDWARE_ICST307_H
17#define ASMARM_HARDWARE_ICST307_H
18
19struct icst307_params {
20 unsigned long ref;
21 unsigned long vco_max; /* inclusive */
22 unsigned short vd_min; /* inclusive */
23 unsigned short vd_max; /* inclusive */
24 unsigned char rd_min; /* inclusive */
25 unsigned char rd_max; /* inclusive */
26};
27
28struct icst307_vco {
29 unsigned short v;
30 unsigned char r;
31 unsigned char s;
32};
33
34unsigned long icst307_khz(const struct icst307_params *p, struct icst307_vco vco);
35struct icst307_vco icst307_khz_to_vco(const struct icst307_params *p, unsigned long freq);
36struct icst307_vco icst307_ps_to_vco(const struct icst307_params *p, unsigned long period);
37
38#endif
diff --git a/include/asm-arm/hardware/icst525.h b/include/asm-arm/hardware/icst525.h
new file mode 100644
index 000000000000..edd5a5704406
--- /dev/null
+++ b/include/asm-arm/hardware/icst525.h
@@ -0,0 +1,36 @@
1/*
2 * linux/include/asm-arm/hardware/icst525.h
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Support functions for calculating clocks/divisors for the ICST525
11 * clock generators. See http://www.icst.com/ for more information
12 * on these devices.
13 */
14#ifndef ASMARM_HARDWARE_ICST525_H
15#define ASMARM_HARDWARE_ICST525_H
16
17struct icst525_params {
18 unsigned long ref;
19 unsigned long vco_max; /* inclusive */
20 unsigned short vd_min; /* inclusive */
21 unsigned short vd_max; /* inclusive */
22 unsigned char rd_min; /* inclusive */
23 unsigned char rd_max; /* inclusive */
24};
25
26struct icst525_vco {
27 unsigned short v;
28 unsigned char r;
29 unsigned char s;
30};
31
32unsigned long icst525_khz(const struct icst525_params *p, struct icst525_vco vco);
33struct icst525_vco icst525_khz_to_vco(const struct icst525_params *p, unsigned long freq);
34struct icst525_vco icst525_ps_to_vco(const struct icst525_params *p, unsigned long period);
35
36#endif
diff --git a/include/asm-arm/hardware/ioc.h b/include/asm-arm/hardware/ioc.h
new file mode 100644
index 000000000000..b3b46ef65943
--- /dev/null
+++ b/include/asm-arm/hardware/ioc.h
@@ -0,0 +1,72 @@
1/*
2 * linux/include/asm-arm/hardware/ioc.h
3 *
4 * Copyright (C) Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Use these macros to read/write the IOC. All it does is perform the actual
11 * read/write.
12 */
13#ifndef __ASMARM_HARDWARE_IOC_H
14#define __ASMARM_HARDWARE_IOC_H
15
16#ifndef __ASSEMBLY__
17
18/*
19 * We use __raw_base variants here so that we give the compiler the
20 * chance to keep IOC_BASE in a register.
21 */
22#define ioc_readb(off) __raw_readb(IOC_BASE + (off))
23#define ioc_writeb(val,off) __raw_writeb(val, IOC_BASE + (off))
24
25#endif
26
27#define IOC_CONTROL (0x00)
28#define IOC_KARTTX (0x04)
29#define IOC_KARTRX (0x04)
30
31#define IOC_IRQSTATA (0x10)
32#define IOC_IRQREQA (0x14)
33#define IOC_IRQCLRA (0x14)
34#define IOC_IRQMASKA (0x18)
35
36#define IOC_IRQSTATB (0x20)
37#define IOC_IRQREQB (0x24)
38#define IOC_IRQMASKB (0x28)
39
40#define IOC_FIQSTAT (0x30)
41#define IOC_FIQREQ (0x34)
42#define IOC_FIQMASK (0x38)
43
44#define IOC_T0CNTL (0x40)
45#define IOC_T0LTCHL (0x40)
46#define IOC_T0CNTH (0x44)
47#define IOC_T0LTCHH (0x44)
48#define IOC_T0GO (0x48)
49#define IOC_T0LATCH (0x4c)
50
51#define IOC_T1CNTL (0x50)
52#define IOC_T1LTCHL (0x50)
53#define IOC_T1CNTH (0x54)
54#define IOC_T1LTCHH (0x54)
55#define IOC_T1GO (0x58)
56#define IOC_T1LATCH (0x5c)
57
58#define IOC_T2CNTL (0x60)
59#define IOC_T2LTCHL (0x60)
60#define IOC_T2CNTH (0x64)
61#define IOC_T2LTCHH (0x64)
62#define IOC_T2GO (0x68)
63#define IOC_T2LATCH (0x6c)
64
65#define IOC_T3CNTL (0x70)
66#define IOC_T3LTCHL (0x70)
67#define IOC_T3CNTH (0x74)
68#define IOC_T3LTCHH (0x74)
69#define IOC_T3GO (0x78)
70#define IOC_T3LATCH (0x7c)
71
72#endif
diff --git a/include/asm-arm/hardware/iomd.h b/include/asm-arm/hardware/iomd.h
new file mode 100644
index 000000000000..82fa2c279a18
--- /dev/null
+++ b/include/asm-arm/hardware/iomd.h
@@ -0,0 +1,227 @@
1/*
2 * linux/include/asm-arm/hardware/iomd.h
3 *
4 * Copyright (C) 1999 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This file contains information out the IOMD ASIC used in the
11 * Acorn RiscPC and subsequently integrated into the CLPS7500 chips.
12 */
13#ifndef __ASMARM_HARDWARE_IOMD_H
14#define __ASMARM_HARDWARE_IOMD_H
15
16#include <linux/config.h>
17
18#ifndef __ASSEMBLY__
19
20/*
21 * We use __raw_base variants here so that we give the compiler the
22 * chance to keep IOC_BASE in a register.
23 */
24#define iomd_readb(off) __raw_readb(IOMD_BASE + (off))
25#define iomd_readl(off) __raw_readl(IOMD_BASE + (off))
26#define iomd_writeb(val,off) __raw_writeb(val, IOMD_BASE + (off))
27#define iomd_writel(val,off) __raw_writel(val, IOMD_BASE + (off))
28
29#endif
30
31#define IOMD_CONTROL (0x000)
32#define IOMD_KARTTX (0x004)
33#define IOMD_KARTRX (0x004)
34#define IOMD_KCTRL (0x008)
35
36#ifdef CONFIG_ARCH_CLPS7500
37#define IOMD_IOLINES (0x00C)
38#endif
39
40#define IOMD_IRQSTATA (0x010)
41#define IOMD_IRQREQA (0x014)
42#define IOMD_IRQCLRA (0x014)
43#define IOMD_IRQMASKA (0x018)
44
45#ifdef CONFIG_ARCH_CLPS7500
46#define IOMD_SUSMODE (0x01C)
47#endif
48
49#define IOMD_IRQSTATB (0x020)
50#define IOMD_IRQREQB (0x024)
51#define IOMD_IRQMASKB (0x028)
52
53#define IOMD_FIQSTAT (0x030)
54#define IOMD_FIQREQ (0x034)
55#define IOMD_FIQMASK (0x038)
56
57#ifdef CONFIG_ARCH_CLPS7500
58#define IOMD_CLKCTL (0x03C)
59#endif
60
61#define IOMD_T0CNTL (0x040)
62#define IOMD_T0LTCHL (0x040)
63#define IOMD_T0CNTH (0x044)
64#define IOMD_T0LTCHH (0x044)
65#define IOMD_T0GO (0x048)
66#define IOMD_T0LATCH (0x04c)
67
68#define IOMD_T1CNTL (0x050)
69#define IOMD_T1LTCHL (0x050)
70#define IOMD_T1CNTH (0x054)
71#define IOMD_T1LTCHH (0x054)
72#define IOMD_T1GO (0x058)
73#define IOMD_T1LATCH (0x05c)
74
75#ifdef CONFIG_ARCH_CLPS7500
76#define IOMD_IRQSTATC (0x060)
77#define IOMD_IRQREQC (0x064)
78#define IOMD_IRQMASKC (0x068)
79
80#define IOMD_VIDMUX (0x06c)
81
82#define IOMD_IRQSTATD (0x070)
83#define IOMD_IRQREQD (0x074)
84#define IOMD_IRQMASKD (0x078)
85#endif
86
87#define IOMD_ROMCR0 (0x080)
88#define IOMD_ROMCR1 (0x084)
89#ifdef CONFIG_ARCH_RPC
90#define IOMD_DRAMCR (0x088)
91#endif
92#define IOMD_REFCR (0x08C)
93
94#define IOMD_FSIZE (0x090)
95#define IOMD_ID0 (0x094)
96#define IOMD_ID1 (0x098)
97#define IOMD_VERSION (0x09C)
98
99#ifdef CONFIG_ARCH_RPC
100#define IOMD_MOUSEX (0x0A0)
101#define IOMD_MOUSEY (0x0A4)
102#endif
103
104#ifdef CONFIG_ARCH_CLPS7500
105#define IOMD_MSEDAT (0x0A8)
106#define IOMD_MSECTL (0x0Ac)
107#endif
108
109#ifdef CONFIG_ARCH_RPC
110#define IOMD_DMATCR (0x0C0)
111#endif
112#define IOMD_IOTCR (0x0C4)
113#define IOMD_ECTCR (0x0C8)
114#ifdef CONFIG_ARCH_RPC
115#define IOMD_DMAEXT (0x0CC)
116#endif
117#ifdef CONFIG_ARCH_CLPS7500
118#define IOMD_ASTCR (0x0CC)
119#define IOMD_DRAMCR (0x0D0)
120#define IOMD_SELFREF (0x0D4)
121#define IOMD_ATODICR (0x0E0)
122#define IOMD_ATODSR (0x0E4)
123#define IOMD_ATODCC (0x0E8)
124#define IOMD_ATODCNT1 (0x0EC)
125#define IOMD_ATODCNT2 (0x0F0)
126#define IOMD_ATODCNT3 (0x0F4)
127#define IOMD_ATODCNT4 (0x0F8)
128#endif
129
130#ifdef CONFIG_ARCH_RPC
131#define DMA_EXT_IO0 1
132#define DMA_EXT_IO1 2
133#define DMA_EXT_IO2 4
134#define DMA_EXT_IO3 8
135
136#define IOMD_IO0CURA (0x100)
137#define IOMD_IO0ENDA (0x104)
138#define IOMD_IO0CURB (0x108)
139#define IOMD_IO0ENDB (0x10C)
140#define IOMD_IO0CR (0x110)
141#define IOMD_IO0ST (0x114)
142
143#define IOMD_IO1CURA (0x120)
144#define IOMD_IO1ENDA (0x124)
145#define IOMD_IO1CURB (0x128)
146#define IOMD_IO1ENDB (0x12C)
147#define IOMD_IO1CR (0x130)
148#define IOMD_IO1ST (0x134)
149
150#define IOMD_IO2CURA (0x140)
151#define IOMD_IO2ENDA (0x144)
152#define IOMD_IO2CURB (0x148)
153#define IOMD_IO2ENDB (0x14C)
154#define IOMD_IO2CR (0x150)
155#define IOMD_IO2ST (0x154)
156
157#define IOMD_IO3CURA (0x160)
158#define IOMD_IO3ENDA (0x164)
159#define IOMD_IO3CURB (0x168)
160#define IOMD_IO3ENDB (0x16C)
161#define IOMD_IO3CR (0x170)
162#define IOMD_IO3ST (0x174)
163#endif
164
165#define IOMD_SD0CURA (0x180)
166#define IOMD_SD0ENDA (0x184)
167#define IOMD_SD0CURB (0x188)
168#define IOMD_SD0ENDB (0x18C)
169#define IOMD_SD0CR (0x190)
170#define IOMD_SD0ST (0x194)
171
172#ifdef CONFIG_ARCH_RPC
173#define IOMD_SD1CURA (0x1A0)
174#define IOMD_SD1ENDA (0x1A4)
175#define IOMD_SD1CURB (0x1A8)
176#define IOMD_SD1ENDB (0x1AC)
177#define IOMD_SD1CR (0x1B0)
178#define IOMD_SD1ST (0x1B4)
179#endif
180
181#define IOMD_CURSCUR (0x1C0)
182#define IOMD_CURSINIT (0x1C4)
183
184#define IOMD_VIDCUR (0x1D0)
185#define IOMD_VIDEND (0x1D4)
186#define IOMD_VIDSTART (0x1D8)
187#define IOMD_VIDINIT (0x1DC)
188#define IOMD_VIDCR (0x1E0)
189
190#define IOMD_DMASTAT (0x1F0)
191#define IOMD_DMAREQ (0x1F4)
192#define IOMD_DMAMASK (0x1F8)
193
194#define DMA_END_S (1 << 31)
195#define DMA_END_L (1 << 30)
196
197#define DMA_CR_C 0x80
198#define DMA_CR_D 0x40
199#define DMA_CR_E 0x20
200
201#define DMA_ST_OFL 4
202#define DMA_ST_INT 2
203#define DMA_ST_AB 1
204
205/*
206 * DMA (MEMC) compatibility
207 */
208#define HALF_SAM vram_half_sam
209#define VDMA_ALIGNMENT (HALF_SAM * 2)
210#define VDMA_XFERSIZE (HALF_SAM)
211#define VDMA_INIT IOMD_VIDINIT
212#define VDMA_START IOMD_VIDSTART
213#define VDMA_END IOMD_VIDEND
214
215#ifndef __ASSEMBLY__
216extern unsigned int vram_half_sam;
217#define video_set_dma(start,end,offset) \
218do { \
219 outl (SCREEN_START + start, VDMA_START); \
220 outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
221 if (offset >= end - VDMA_XFERSIZE) \
222 offset |= 0x40000000; \
223 outl (SCREEN_START + offset, VDMA_INIT); \
224} while (0)
225#endif
226
227#endif
diff --git a/include/asm-arm/hardware/linkup-l1110.h b/include/asm-arm/hardware/linkup-l1110.h
new file mode 100644
index 000000000000..7ec91168a576
--- /dev/null
+++ b/include/asm-arm/hardware/linkup-l1110.h
@@ -0,0 +1,48 @@
1/*
2*
3* Definitions for H3600 Handheld Computer
4*
5* Copyright 2001 Compaq Computer Corporation.
6*
7* Use consistent with the GNU GPL is permitted,
8* provided that this copyright notice is
9* preserved in its entirety in all copies and derived works.
10*
11* COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
12* AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
13* FITNESS FOR ANY PARTICULAR PURPOSE.
14*
15* Author: Jamey Hicks.
16*
17*/
18
19/* LinkUp Systems PCCard/CompactFlash Interface for SA-1100 */
20
21/* PC Card Status Register */
22#define LINKUP_PRS_S1 (1 << 0) /* voltage control bits S1-S4 */
23#define LINKUP_PRS_S2 (1 << 1)
24#define LINKUP_PRS_S3 (1 << 2)
25#define LINKUP_PRS_S4 (1 << 3)
26#define LINKUP_PRS_BVD1 (1 << 4)
27#define LINKUP_PRS_BVD2 (1 << 5)
28#define LINKUP_PRS_VS1 (1 << 6)
29#define LINKUP_PRS_VS2 (1 << 7)
30#define LINKUP_PRS_RDY (1 << 8)
31#define LINKUP_PRS_CD1 (1 << 9)
32#define LINKUP_PRS_CD2 (1 << 10)
33
34/* PC Card Command Register */
35#define LINKUP_PRC_S1 (1 << 0)
36#define LINKUP_PRC_S2 (1 << 1)
37#define LINKUP_PRC_S3 (1 << 2)
38#define LINKUP_PRC_S4 (1 << 3)
39#define LINKUP_PRC_RESET (1 << 4)
40#define LINKUP_PRC_APOE (1 << 5) /* Auto Power Off Enable: clears S1-S4 when either nCD goes high */
41#define LINKUP_PRC_CFE (1 << 6) /* CompactFlash mode Enable: addresses A[10:0] only, A[25:11] high */
42#define LINKUP_PRC_SOE (1 << 7) /* signal output driver enable */
43#define LINKUP_PRC_SSP (1 << 8) /* sock select polarity: 0 for socket 0, 1 for socket 1 */
44#define LINKUP_PRC_MBZ (1 << 15) /* must be zero */
45
46struct linkup_l1110 {
47 volatile short prc;
48};
diff --git a/include/asm-arm/hardware/locomo.h b/include/asm-arm/hardware/locomo.h
new file mode 100644
index 000000000000..5f10048ec54e
--- /dev/null
+++ b/include/asm-arm/hardware/locomo.h
@@ -0,0 +1,206 @@
1/*
2 * linux/include/asm-arm/hardware/locomo.h
3 *
4 * This file contains the definitions for the LoCoMo G/A Chip
5 *
6 * (C) Copyright 2004 John Lenz
7 *
8 * May be copied or modified under the terms of the GNU General Public
9 * License. See linux/COPYING for more information.
10 *
11 * Based on sa1111.h
12 */
13#ifndef _ASM_ARCH_LOCOMO
14#define _ASM_ARCH_LOCOMO
15
16#define locomo_writel(val,addr) ({ *(volatile u16 *)(addr) = (val); })
17#define locomo_readl(addr) (*(volatile u16 *)(addr))
18
19/* LOCOMO version */
20#define LOCOMO_VER 0x00
21
22/* Pin status */
23#define LOCOMO_ST 0x04
24
25/* Pin status */
26#define LOCOMO_C32K 0x08
27
28/* Interrupt controller */
29#define LOCOMO_ICR 0x0C
30
31/* MCS decoder for boot selecting */
32#define LOCOMO_MCSX0 0x10
33#define LOCOMO_MCSX1 0x14
34#define LOCOMO_MCSX2 0x18
35#define LOCOMO_MCSX3 0x1c
36
37/* Touch panel controller */
38#define LOCOMO_ASD 0x20 /* AD start delay */
39#define LOCOMO_HSD 0x28 /* HSYS delay */
40#define LOCOMO_HSC 0x2c /* HSYS period */
41#define LOCOMO_TADC 0x30 /* tablet ADC clock */
42
43
44/* Long time timer */
45#define LOCOMO_LTC 0xd8 /* LTC interrupt setting */
46#define LOCOMO_LTINT 0xdc /* LTC interrupt */
47
48/* DAC control signal for LCD (COMADJ ) */
49#define LOCOMO_DAC 0xe0
50/* DAC control */
51#define LOCOMO_DAC_SCLOEB 0x08 /* SCL pin output data */
52#define LOCOMO_DAC_TEST 0x04 /* Test bit */
53#define LOCOMO_DAC_SDA 0x02 /* SDA pin level (read-only) */
54#define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */
55
56/* SPI interface */
57#define LOCOMO_SPIMD 0x60 /* SPI mode setting */
58#define LOCOMO_SPICT 0x64 /* SPI mode control */
59#define LOCOMO_SPIST 0x68 /* SPI status */
60#define LOCOMO_SPIIS 0x70 /* SPI interrupt status */
61#define LOCOMO_SPIWE 0x74 /* SPI interrupt status write enable */
62#define LOCOMO_SPIIE 0x78 /* SPI interrupt enable */
63#define LOCOMO_SPIIR 0x7c /* SPI interrupt request */
64#define LOCOMO_SPITD 0x80 /* SPI transfer data write */
65#define LOCOMO_SPIRD 0x84 /* SPI receive data read */
66#define LOCOMO_SPITS 0x88 /* SPI transfer data shift */
67#define LOCOMO_SPIRS 0x8C /* SPI receive data shift */
68#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
69#define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */
70#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
71#define LOCOMO_SPI_RFR (1) /* read buffer bit */
72
73/* GPIO */
74#define LOCOMO_GPD 0x90 /* GPIO direction */
75#define LOCOMO_GPE 0x94 /* GPIO input enable */
76#define LOCOMO_GPL 0x98 /* GPIO level */
77#define LOCOMO_GPO 0x9c /* GPIO out data setteing */
78#define LOCOMO_GRIE 0xa0 /* GPIO rise detection */
79#define LOCOMO_GFIE 0xa4 /* GPIO fall detection */
80#define LOCOMO_GIS 0xa8 /* GPIO edge detection status */
81#define LOCOMO_GWE 0xac /* GPIO status write enable */
82#define LOCOMO_GIE 0xb0 /* GPIO interrupt enable */
83#define LOCOMO_GIR 0xb4 /* GPIO interrupt request */
84#define LOCOMO_GPIO(Nb) (0x01 << (Nb))
85#define LOCOMO_GPIO_RTS LOCOMO_GPIO(0)
86#define LOCOMO_GPIO_CTS LOCOMO_GPIO(1)
87#define LOCOMO_GPIO_DSR LOCOMO_GPIO(2)
88#define LOCOMO_GPIO_DTR LOCOMO_GPIO(3)
89#define LOCOMO_GPIO_LCD_VSHA_ON LOCOMO_GPIO(4)
90#define LOCOMO_GPIO_LCD_VSHD_ON LOCOMO_GPIO(5)
91#define LOCOMO_GPIO_LCD_VEE_ON LOCOMO_GPIO(6)
92#define LOCOMO_GPIO_LCD_MOD LOCOMO_GPIO(7)
93#define LOCOMO_GPIO_DAC_ON LOCOMO_GPIO(8)
94#define LOCOMO_GPIO_FL_VR LOCOMO_GPIO(9)
95#define LOCOMO_GPIO_DAC_SDATA LOCOMO_GPIO(10)
96#define LOCOMO_GPIO_DAC_SCK LOCOMO_GPIO(11)
97#define LOCOMO_GPIO_DAC_SLOAD LOCOMO_GPIO(12)
98
99/* Start the definitions of the devices. Each device has an initial
100 * base address and a series of offsets from that base address. */
101
102/* Keyboard controller */
103#define LOCOMO_KEYBOARD 0x40
104#define LOCOMO_KIB 0x00 /* KIB level */
105#define LOCOMO_KSC 0x04 /* KSTRB control */
106#define LOCOMO_KCMD 0x08 /* KSTRB command */
107#define LOCOMO_KIC 0x0c /* Key interrupt */
108
109/* Front light adjustment controller */
110#define LOCOMO_FRONTLIGHT 0xc8
111#define LOCOMO_ALS 0x00 /* Adjust light cycle */
112#define LOCOMO_ALD 0x04 /* Adjust light duty */
113
114/* Backlight controller: TFT signal */
115#define LOCOMO_BACKLIGHT 0x38
116#define LOCOMO_TC 0x00 /* TFT control signal */
117#define LOCOMO_CPSD 0x04 /* CPS delay */
118
119/* Audio controller */
120#define LOCOMO_AUDIO 0x54
121#define LOCOMO_ACC 0x00 /* Audio clock */
122#define LOCOMO_PAIF 0x7C /* PCM audio interface */
123/* Audio clock */
124#define LOCOMO_ACC_XON 0x80
125#define LOCOMO_ACC_XEN 0x40
126#define LOCOMO_ACC_XSEL0 0x00
127#define LOCOMO_ACC_XSEL1 0x20
128#define LOCOMO_ACC_MCLKEN 0x10
129#define LOCOMO_ACC_64FSEN 0x08
130#define LOCOMO_ACC_CLKSEL000 0x00 /* mclk 2 */
131#define LOCOMO_ACC_CLKSEL001 0x01 /* mclk 3 */
132#define LOCOMO_ACC_CLKSEL010 0x02 /* mclk 4 */
133#define LOCOMO_ACC_CLKSEL011 0x03 /* mclk 6 */
134#define LOCOMO_ACC_CLKSEL100 0x04 /* mclk 8 */
135#define LOCOMO_ACC_CLKSEL101 0x05 /* mclk 12 */
136/* PCM audio interface */
137#define LOCOMO_PAIF_SCINV 0x20
138#define LOCOMO_PAIF_SCEN 0x10
139#define LOCOMO_PAIF_LRCRST 0x08
140#define LOCOMO_PAIF_LRCEVE 0x04
141#define LOCOMO_PAIF_LRCINV 0x02
142#define LOCOMO_PAIF_LRCEN 0x01
143
144/* LED controller */
145#define LOCOMO_LED 0xe8
146#define LOCOMO_LPT0 0x00
147#define LOCOMO_LPT1 0x04
148/* LED control */
149#define LOCOMO_LPT_TOFH 0x80
150#define LOCOMO_LPT_TOFL 0x08
151#define LOCOMO_LPT_TOH(TOH) ((TOH & 0x7) << 4)
152#define LOCOMO_LPT_TOL(TOL) ((TOL & 0x7))
153
154extern struct bus_type locomo_bus_type;
155
156#define LOCOMO_DEVID_KEYBOARD 0
157#define LOCOMO_DEVID_FRONTLIGHT 1
158#define LOCOMO_DEVID_BACKLIGHT 2
159#define LOCOMO_DEVID_AUDIO 3
160#define LOCOMO_DEVID_LED 4
161#define LOCOMO_DEVID_UART 5
162
163struct locomo_dev {
164 struct device dev;
165 unsigned int devid;
166 unsigned int irq[1];
167
168 void *mapbase;
169 unsigned long length;
170
171 u64 dma_mask;
172};
173
174#define LOCOMO_DEV(_d) container_of((_d), struct locomo_dev, dev)
175
176#define locomo_get_drvdata(d) dev_get_drvdata(&(d)->dev)
177#define locomo_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
178
179struct locomo_driver {
180 struct device_driver drv;
181 unsigned int devid;
182 int (*probe)(struct locomo_dev *);
183 int (*remove)(struct locomo_dev *);
184 int (*suspend)(struct locomo_dev *, pm_message_t);
185 int (*resume)(struct locomo_dev *);
186};
187
188#define LOCOMO_DRV(_d) container_of((_d), struct locomo_driver, drv)
189
190#define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name)
191
192void locomo_lcd_power(struct locomo_dev *, int, unsigned int);
193
194int locomo_driver_register(struct locomo_driver *);
195void locomo_driver_unregister(struct locomo_driver *);
196
197/* GPIO control functions */
198void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned int dir);
199unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits);
200unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits);
201void locomo_gpio_write(struct locomo_dev *ldev, unsigned int bits, unsigned int set);
202
203/* M62332 control function */
204void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
205
206#endif
diff --git a/include/asm-arm/hardware/memc.h b/include/asm-arm/hardware/memc.h
new file mode 100644
index 000000000000..8aef5aa0e01b
--- /dev/null
+++ b/include/asm-arm/hardware/memc.h
@@ -0,0 +1,26 @@
1/*
2 * linux/include/asm-arm/hardware/memc.h
3 *
4 * Copyright (C) Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#define VDMA_ALIGNMENT PAGE_SIZE
11#define VDMA_XFERSIZE 16
12#define VDMA_INIT 0
13#define VDMA_START 1
14#define VDMA_END 2
15
16#ifndef __ASSEMBLY__
17extern void memc_write(unsigned int reg, unsigned long val);
18
19#define video_set_dma(start,end,offset) \
20do { \
21 memc_write (VDMA_START, (start >> 2)); \
22 memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \
23 memc_write (VDMA_INIT, (offset >> 2)); \
24} while (0)
25
26#endif
diff --git a/include/asm-arm/hardware/pci_v3.h b/include/asm-arm/hardware/pci_v3.h
new file mode 100644
index 000000000000..4d497bdb9a97
--- /dev/null
+++ b/include/asm-arm/hardware/pci_v3.h
@@ -0,0 +1,186 @@
1/*
2 * linux/include/asm-arm/hardware/pci_v3.h
3 *
4 * Internal header file PCI V3 chip
5 *
6 * Copyright (C) ARM Limited
7 * Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23#ifndef ASM_ARM_HARDWARE_PCI_V3_H
24#define ASM_ARM_HARDWARE_PCI_V3_H
25
26/* -------------------------------------------------------------------------------
27 * V3 Local Bus to PCI Bridge definitions
28 * -------------------------------------------------------------------------------
29 * Registers (these are taken from page 129 of the EPC User's Manual Rev 1.04
30 * All V3 register names are prefaced by V3_ to avoid clashing with any other
31 * PCI definitions. Their names match the user's manual.
32 *
33 * I'm assuming that I20 is disabled.
34 *
35 */
36#define V3_PCI_VENDOR 0x00000000
37#define V3_PCI_DEVICE 0x00000002
38#define V3_PCI_CMD 0x00000004
39#define V3_PCI_STAT 0x00000006
40#define V3_PCI_CC_REV 0x00000008
41#define V3_PCI_HDR_CFG 0x0000000C
42#define V3_PCI_IO_BASE 0x00000010
43#define V3_PCI_BASE0 0x00000014
44#define V3_PCI_BASE1 0x00000018
45#define V3_PCI_SUB_VENDOR 0x0000002C
46#define V3_PCI_SUB_ID 0x0000002E
47#define V3_PCI_ROM 0x00000030
48#define V3_PCI_BPARAM 0x0000003C
49#define V3_PCI_MAP0 0x00000040
50#define V3_PCI_MAP1 0x00000044
51#define V3_PCI_INT_STAT 0x00000048
52#define V3_PCI_INT_CFG 0x0000004C
53#define V3_LB_BASE0 0x00000054
54#define V3_LB_BASE1 0x00000058
55#define V3_LB_MAP0 0x0000005E
56#define V3_LB_MAP1 0x00000062
57#define V3_LB_BASE2 0x00000064
58#define V3_LB_MAP2 0x00000066
59#define V3_LB_SIZE 0x00000068
60#define V3_LB_IO_BASE 0x0000006E
61#define V3_FIFO_CFG 0x00000070
62#define V3_FIFO_PRIORITY 0x00000072
63#define V3_FIFO_STAT 0x00000074
64#define V3_LB_ISTAT 0x00000076
65#define V3_LB_IMASK 0x00000077
66#define V3_SYSTEM 0x00000078
67#define V3_LB_CFG 0x0000007A
68#define V3_PCI_CFG 0x0000007C
69#define V3_DMA_PCI_ADR0 0x00000080
70#define V3_DMA_PCI_ADR1 0x00000090
71#define V3_DMA_LOCAL_ADR0 0x00000084
72#define V3_DMA_LOCAL_ADR1 0x00000094
73#define V3_DMA_LENGTH0 0x00000088
74#define V3_DMA_LENGTH1 0x00000098
75#define V3_DMA_CSR0 0x0000008B
76#define V3_DMA_CSR1 0x0000009B
77#define V3_DMA_CTLB_ADR0 0x0000008C
78#define V3_DMA_CTLB_ADR1 0x0000009C
79#define V3_DMA_DELAY 0x000000E0
80#define V3_MAIL_DATA 0x000000C0
81#define V3_PCI_MAIL_IEWR 0x000000D0
82#define V3_PCI_MAIL_IERD 0x000000D2
83#define V3_LB_MAIL_IEWR 0x000000D4
84#define V3_LB_MAIL_IERD 0x000000D6
85#define V3_MAIL_WR_STAT 0x000000D8
86#define V3_MAIL_RD_STAT 0x000000DA
87#define V3_QBA_MAP 0x000000DC
88
89/* PCI COMMAND REGISTER bits
90 */
91#define V3_COMMAND_M_FBB_EN (1 << 9)
92#define V3_COMMAND_M_SERR_EN (1 << 8)
93#define V3_COMMAND_M_PAR_EN (1 << 6)
94#define V3_COMMAND_M_MASTER_EN (1 << 2)
95#define V3_COMMAND_M_MEM_EN (1 << 1)
96#define V3_COMMAND_M_IO_EN (1 << 0)
97
98/* SYSTEM REGISTER bits
99 */
100#define V3_SYSTEM_M_RST_OUT (1 << 15)
101#define V3_SYSTEM_M_LOCK (1 << 14)
102
103/* PCI_CFG bits
104 */
105#define V3_PCI_CFG_M_I2O_EN (1 << 15)
106#define V3_PCI_CFG_M_IO_REG_DIS (1 << 14)
107#define V3_PCI_CFG_M_IO_DIS (1 << 13)
108#define V3_PCI_CFG_M_EN3V (1 << 12)
109#define V3_PCI_CFG_M_RETRY_EN (1 << 10)
110#define V3_PCI_CFG_M_AD_LOW1 (1 << 9)
111#define V3_PCI_CFG_M_AD_LOW0 (1 << 8)
112
113/* PCI_BASE register bits (PCI -> Local Bus)
114 */
115#define V3_PCI_BASE_M_ADR_BASE 0xFFF00000
116#define V3_PCI_BASE_M_ADR_BASEL 0x000FFF00
117#define V3_PCI_BASE_M_PREFETCH (1 << 3)
118#define V3_PCI_BASE_M_TYPE (3 << 1)
119#define V3_PCI_BASE_M_IO (1 << 0)
120
121/* PCI MAP register bits (PCI -> Local bus)
122 */
123#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000
124#define V3_PCI_MAP_M_RD_POST_INH (1 << 15)
125#define V3_PCI_MAP_M_ROM_SIZE (3 << 10)
126#define V3_PCI_MAP_M_SWAP (3 << 8)
127#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0
128#define V3_PCI_MAP_M_REG_EN (1 << 1)
129#define V3_PCI_MAP_M_ENABLE (1 << 0)
130
131/*
132 * LB_BASE0,1 register bits (Local bus -> PCI)
133 */
134#define V3_LB_BASE_ADR_BASE 0xfff00000
135#define V3_LB_BASE_SWAP (3 << 8)
136#define V3_LB_BASE_ADR_SIZE (15 << 4)
137#define V3_LB_BASE_PREFETCH (1 << 3)
138#define V3_LB_BASE_ENABLE (1 << 0)
139
140#define V3_LB_BASE_ADR_SIZE_1MB (0 << 4)
141#define V3_LB_BASE_ADR_SIZE_2MB (1 << 4)
142#define V3_LB_BASE_ADR_SIZE_4MB (2 << 4)
143#define V3_LB_BASE_ADR_SIZE_8MB (3 << 4)
144#define V3_LB_BASE_ADR_SIZE_16MB (4 << 4)
145#define V3_LB_BASE_ADR_SIZE_32MB (5 << 4)
146#define V3_LB_BASE_ADR_SIZE_64MB (6 << 4)
147#define V3_LB_BASE_ADR_SIZE_128MB (7 << 4)
148#define V3_LB_BASE_ADR_SIZE_256MB (8 << 4)
149#define V3_LB_BASE_ADR_SIZE_512MB (9 << 4)
150#define V3_LB_BASE_ADR_SIZE_1GB (10 << 4)
151#define V3_LB_BASE_ADR_SIZE_2GB (11 << 4)
152
153#define v3_addr_to_lb_base(a) ((a) & V3_LB_BASE_ADR_BASE)
154
155/*
156 * LB_MAP0,1 register bits (Local bus -> PCI)
157 */
158#define V3_LB_MAP_MAP_ADR 0xfff0
159#define V3_LB_MAP_TYPE (7 << 1)
160#define V3_LB_MAP_AD_LOW_EN (1 << 0)
161
162#define V3_LB_MAP_TYPE_IACK (0 << 1)
163#define V3_LB_MAP_TYPE_IO (1 << 1)
164#define V3_LB_MAP_TYPE_MEM (3 << 1)
165#define V3_LB_MAP_TYPE_CONFIG (5 << 1)
166#define V3_LB_MAP_TYPE_MEM_MULTIPLE (6 << 1)
167
168#define v3_addr_to_lb_map(a) (((a) >> 16) & V3_LB_MAP_MAP_ADR)
169
170/*
171 * LB_BASE2 register bits (Local bus -> PCI IO)
172 */
173#define V3_LB_BASE2_ADR_BASE 0xff00
174#define V3_LB_BASE2_SWAP (3 << 6)
175#define V3_LB_BASE2_ENABLE (1 << 0)
176
177#define v3_addr_to_lb_base2(a) (((a) >> 16) & V3_LB_BASE2_ADR_BASE)
178
179/*
180 * LB_MAP2 register bits (Local bus -> PCI IO)
181 */
182#define V3_LB_MAP2_MAP_ADR 0xff00
183
184#define v3_addr_to_lb_map2(a) (((a) >> 16) & V3_LB_MAP2_MAP_ADR)
185
186#endif
diff --git a/include/asm-arm/hardware/sa1111.h b/include/asm-arm/hardware/sa1111.h
new file mode 100644
index 000000000000..319aea064c36
--- /dev/null
+++ b/include/asm-arm/hardware/sa1111.h
@@ -0,0 +1,602 @@
1/*
2 * linux/include/asm-arm/hardware/SA-1111.h
3 *
4 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
5 *
6 * This file contains definitions for the SA-1111 Companion Chip.
7 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
8 *
9 * Macro that calculates real address for registers in the SA-1111
10 */
11
12#ifndef _ASM_ARCH_SA1111
13#define _ASM_ARCH_SA1111
14
15#include <asm/arch/bitfield.h>
16
17/*
18 * The SA1111 is always located at virtual 0xf4000000, and is always
19 * "native" endian.
20 */
21
22#define SA1111_VBASE 0xf4000000
23
24/* Don't use these! */
25#define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE)
26#define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE)
27
28#ifndef __ASSEMBLY__
29#define _SA1111(x) ((x) + sa1111->resource.start)
30#endif
31
32/*
33 * 26 bits of the SA-1110 address bus are available to the SA-1111.
34 * Use these when feeding target addresses to the DMA engines.
35 */
36
37#define SA1111_ADDR_WIDTH (26)
38#define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)
39#define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)
40
41/*
42 * Don't ask the (SAC) DMA engines to move less than this amount.
43 */
44
45#define SA1111_SAC_DMA_MIN_XFER (0x800)
46
47/*
48 * SA1111 register definitions.
49 */
50#define __CCREG(x) __REGP(SA1111_VBASE + (x))
51
52#define sa1111_writel(val,addr) __raw_writel(val, addr)
53#define sa1111_readl(addr) __raw_readl(addr)
54
55/*
56 * System Bus Interface (SBI)
57 *
58 * Registers
59 * SKCR Control Register
60 * SMCR Shared Memory Controller Register
61 * SKID ID Register
62 */
63#define SA1111_SKCR 0x0000
64#define SA1111_SMCR 0x0004
65#define SA1111_SKID 0x0008
66
67#define SKCR_PLL_BYPASS (1<<0)
68#define SKCR_RCLKEN (1<<1)
69#define SKCR_SLEEP (1<<2)
70#define SKCR_DOZE (1<<3)
71#define SKCR_VCO_OFF (1<<4)
72#define SKCR_SCANTSTEN (1<<5)
73#define SKCR_CLKTSTEN (1<<6)
74#define SKCR_RDYEN (1<<7)
75#define SKCR_SELAC (1<<8)
76#define SKCR_OPPC (1<<9)
77#define SKCR_PLLTSTEN (1<<10)
78#define SKCR_USBIOTSTEN (1<<11)
79/*
80 * Don't believe the specs! Take them, throw them outside. Leave them
81 * there for a week. Spit on them. Walk on them. Stamp on them.
82 * Pour gasoline over them and finally burn them. Now think about coding.
83 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
84 * - The Feb 2001 errata (278260-010) says that the previous errata
85 * (278260-009) is wrong, and its bit actually 12, fixed in spec
86 * 278242-003.
87 * - The SA1111 manual (278242) says bit 12, but 0 to enable.
88 * - Reality is bit 13, 1 to enable.
89 * -- rmk
90 */
91#define SKCR_OE_EN (1<<13)
92
93#define SMCR_DTIM (1<<0)
94#define SMCR_MBGE (1<<1)
95#define SMCR_DRAC_0 (1<<2)
96#define SMCR_DRAC_1 (1<<3)
97#define SMCR_DRAC_2 (1<<4)
98#define SMCR_DRAC Fld(3, 2)
99#define SMCR_CLAT (1<<5)
100
101#define SKID_SIREV_MASK (0x000000f0)
102#define SKID_MTREV_MASK (0x0000000f)
103#define SKID_ID_MASK (0xffffff00)
104#define SKID_SA1111_ID (0x690cc200)
105
106/*
107 * System Controller
108 *
109 * Registers
110 * SKPCR Power Control Register
111 * SKCDR Clock Divider Register
112 * SKAUD Audio Clock Divider Register
113 * SKPMC PS/2 Mouse Clock Divider Register
114 * SKPTC PS/2 Track Pad Clock Divider Register
115 * SKPEN0 PWM0 Enable Register
116 * SKPWM0 PWM0 Clock Register
117 * SKPEN1 PWM1 Enable Register
118 * SKPWM1 PWM1 Clock Register
119 */
120#define SA1111_SKPCR 0x0200
121#define SA1111_SKCDR 0x0204
122#define SA1111_SKAUD 0x0208
123#define SA1111_SKPMC 0x020c
124#define SA1111_SKPTC 0x0210
125#define SA1111_SKPEN0 0x0214
126#define SA1111_SKPWM0 0x0218
127#define SA1111_SKPEN1 0x021c
128#define SA1111_SKPWM1 0x0220
129
130#define SKPCR_UCLKEN (1<<0)
131#define SKPCR_ACCLKEN (1<<1)
132#define SKPCR_I2SCLKEN (1<<2)
133#define SKPCR_L3CLKEN (1<<3)
134#define SKPCR_SCLKEN (1<<4)
135#define SKPCR_PMCLKEN (1<<5)
136#define SKPCR_PTCLKEN (1<<6)
137#define SKPCR_DCLKEN (1<<7)
138#define SKPCR_PWMCLKEN (1<<8)
139
140/*
141 * USB Host controller
142 */
143#define SA1111_USB 0x0400
144
145/*
146 * Offsets from SA1111_USB_BASE
147 */
148#define SA1111_USB_STATUS 0x0118
149#define SA1111_USB_RESET 0x011c
150#define SA1111_USB_IRQTEST 0x0120
151
152#define USB_RESET_FORCEIFRESET (1 << 0)
153#define USB_RESET_FORCEHCRESET (1 << 1)
154#define USB_RESET_CLKGENRESET (1 << 2)
155#define USB_RESET_SIMSCALEDOWN (1 << 3)
156#define USB_RESET_USBINTTEST (1 << 4)
157#define USB_RESET_SLEEPSTBYEN (1 << 5)
158#define USB_RESET_PWRSENSELOW (1 << 6)
159#define USB_RESET_PWRCTRLLOW (1 << 7)
160
161#define USB_STATUS_IRQHCIRMTWKUP (1 << 7)
162#define USB_STATUS_IRQHCIBUFFACC (1 << 8)
163#define USB_STATUS_NIRQHCIM (1 << 9)
164#define USB_STATUS_NHCIMFCLR (1 << 10)
165#define USB_STATUS_USBPWRSENSE (1 << 11)
166
167/*
168 * Serial Audio Controller
169 *
170 * Registers
171 * SACR0 Serial Audio Common Control Register
172 * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
173 * SACR2 Serial Audio AC-link Control Register
174 * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
175 * SASR1 Serial Audio AC-link Interface & FIFO Status Register
176 * SASCR Serial Audio Status Clear Register
177 * L3_CAR L3 Control Bus Address Register
178 * L3_CDR L3 Control Bus Data Register
179 * ACCAR AC-link Command Address Register
180 * ACCDR AC-link Command Data Register
181 * ACSAR AC-link Status Address Register
182 * ACSDR AC-link Status Data Register
183 * SADTCS Serial Audio DMA Transmit Control/Status Register
184 * SADTSA Serial Audio DMA Transmit Buffer Start Address A
185 * SADTCA Serial Audio DMA Transmit Buffer Count Register A
186 * SADTSB Serial Audio DMA Transmit Buffer Start Address B
187 * SADTCB Serial Audio DMA Transmit Buffer Count Register B
188 * SADRCS Serial Audio DMA Receive Control/Status Register
189 * SADRSA Serial Audio DMA Receive Buffer Start Address A
190 * SADRCA Serial Audio DMA Receive Buffer Count Register A
191 * SADRSB Serial Audio DMA Receive Buffer Start Address B
192 * SADRCB Serial Audio DMA Receive Buffer Count Register B
193 * SAITR Serial Audio Interrupt Test Register
194 * SADR Serial Audio Data Register (16 x 32-bit)
195 */
196
197#define _SACR0 _SA1111( 0x0600 )
198#define _SACR1 _SA1111( 0x0604 )
199#define _SACR2 _SA1111( 0x0608 )
200#define _SASR0 _SA1111( 0x060c )
201#define _SASR1 _SA1111( 0x0610 )
202#define _SASCR _SA1111( 0x0618 )
203#define _L3_CAR _SA1111( 0x061c )
204#define _L3_CDR _SA1111( 0x0620 )
205#define _ACCAR _SA1111( 0x0624 )
206#define _ACCDR _SA1111( 0x0628 )
207#define _ACSAR _SA1111( 0x062c )
208#define _ACSDR _SA1111( 0x0630 )
209#define _SADTCS _SA1111( 0x0634 )
210#define _SADTSA _SA1111( 0x0638 )
211#define _SADTCA _SA1111( 0x063c )
212#define _SADTSB _SA1111( 0x0640 )
213#define _SADTCB _SA1111( 0x0644 )
214#define _SADRCS _SA1111( 0x0648 )
215#define _SADRSA _SA1111( 0x064c )
216#define _SADRCA _SA1111( 0x0650 )
217#define _SADRSB _SA1111( 0x0654 )
218#define _SADRCB _SA1111( 0x0658 )
219#define _SAITR _SA1111( 0x065c )
220#define _SADR _SA1111( 0x0680 )
221
222#define SACR0 __CCREG(0x0600)
223#define SACR1 __CCREG(0x0604)
224#define SACR2 __CCREG(0x0608)
225#define SASR0 __CCREG(0x060c)
226#define SASR1 __CCREG(0x0610)
227#define SASCR __CCREG(0x0618)
228#define L3_CAR __CCREG(0x061c)
229#define L3_CDR __CCREG(0x0620)
230#define ACCAR __CCREG(0x0624)
231#define ACCDR __CCREG(0x0628)
232#define ACSAR __CCREG(0x062c)
233#define ACSDR __CCREG(0x0630)
234#define SADTCS __CCREG(0x0634)
235#define SADTSA __CCREG(0x0638)
236#define SADTCA __CCREG(0x063c)
237#define SADTSB __CCREG(0x0640)
238#define SADTCB __CCREG(0x0644)
239#define SADRCS __CCREG(0x0648)
240#define SADRSA __CCREG(0x064c)
241#define SADRCA __CCREG(0x0650)
242#define SADRSB __CCREG(0x0654)
243#define SADRCB __CCREG(0x0658)
244#define SAITR __CCREG(0x065c)
245#define SADR __CCREG(0x0680)
246
247#define SACR0_ENB (1<<0)
248#define SACR0_BCKD (1<<2)
249#define SACR0_RST (1<<3)
250
251#define SACR1_AMSL (1<<0)
252#define SACR1_L3EN (1<<1)
253#define SACR1_L3MB (1<<2)
254#define SACR1_DREC (1<<3)
255#define SACR1_DRPL (1<<4)
256#define SACR1_ENLBF (1<<5)
257
258#define SACR2_TS3V (1<<0)
259#define SACR2_TS4V (1<<1)
260#define SACR2_WKUP (1<<2)
261#define SACR2_DREC (1<<3)
262#define SACR2_DRPL (1<<4)
263#define SACR2_ENLBF (1<<5)
264#define SACR2_RESET (1<<6)
265
266#define SASR0_TNF (1<<0)
267#define SASR0_RNE (1<<1)
268#define SASR0_BSY (1<<2)
269#define SASR0_TFS (1<<3)
270#define SASR0_RFS (1<<4)
271#define SASR0_TUR (1<<5)
272#define SASR0_ROR (1<<6)
273#define SASR0_L3WD (1<<16)
274#define SASR0_L3RD (1<<17)
275
276#define SASR1_TNF (1<<0)
277#define SASR1_RNE (1<<1)
278#define SASR1_BSY (1<<2)
279#define SASR1_TFS (1<<3)
280#define SASR1_RFS (1<<4)
281#define SASR1_TUR (1<<5)
282#define SASR1_ROR (1<<6)
283#define SASR1_CADT (1<<16)
284#define SASR1_SADR (1<<17)
285#define SASR1_RSTO (1<<18)
286#define SASR1_CLPM (1<<19)
287#define SASR1_CRDY (1<<20)
288#define SASR1_RS3V (1<<21)
289#define SASR1_RS4V (1<<22)
290
291#define SASCR_TUR (1<<5)
292#define SASCR_ROR (1<<6)
293#define SASCR_DTS (1<<16)
294#define SASCR_RDD (1<<17)
295#define SASCR_STO (1<<18)
296
297#define SADTCS_TDEN (1<<0)
298#define SADTCS_TDIE (1<<1)
299#define SADTCS_TDBDA (1<<3)
300#define SADTCS_TDSTA (1<<4)
301#define SADTCS_TDBDB (1<<5)
302#define SADTCS_TDSTB (1<<6)
303#define SADTCS_TBIU (1<<7)
304
305#define SADRCS_RDEN (1<<0)
306#define SADRCS_RDIE (1<<1)
307#define SADRCS_RDBDA (1<<3)
308#define SADRCS_RDSTA (1<<4)
309#define SADRCS_RDBDB (1<<5)
310#define SADRCS_RDSTB (1<<6)
311#define SADRCS_RBIU (1<<7)
312
313#define SAD_CS_DEN (1<<0)
314#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
315#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
316#define SAD_CS_DSTA (1<<4)
317#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
318#define SAD_CS_DSTB (1<<6)
319#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
320
321#define SAITR_TFS (1<<0)
322#define SAITR_RFS (1<<1)
323#define SAITR_TUR (1<<2)
324#define SAITR_ROR (1<<3)
325#define SAITR_CADT (1<<4)
326#define SAITR_SADR (1<<5)
327#define SAITR_RSTO (1<<6)
328#define SAITR_TDBDA (1<<8)
329#define SAITR_TDBDB (1<<9)
330#define SAITR_RDBDA (1<<10)
331#define SAITR_RDBDB (1<<11)
332
333/*
334 * General-Purpose I/O Interface
335 *
336 * Registers
337 * PA_DDR GPIO Block A Data Direction
338 * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
339 * PA_SDR GPIO Block A Sleep Direction
340 * PA_SSR GPIO Block A Sleep State
341 * PB_DDR GPIO Block B Data Direction
342 * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
343 * PB_SDR GPIO Block B Sleep Direction
344 * PB_SSR GPIO Block B Sleep State
345 * PC_DDR GPIO Block C Data Direction
346 * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
347 * PC_SDR GPIO Block C Sleep Direction
348 * PC_SSR GPIO Block C Sleep State
349 */
350
351#define _PA_DDR _SA1111( 0x1000 )
352#define _PA_DRR _SA1111( 0x1004 )
353#define _PA_DWR _SA1111( 0x1004 )
354#define _PA_SDR _SA1111( 0x1008 )
355#define _PA_SSR _SA1111( 0x100c )
356#define _PB_DDR _SA1111( 0x1010 )
357#define _PB_DRR _SA1111( 0x1014 )
358#define _PB_DWR _SA1111( 0x1014 )
359#define _PB_SDR _SA1111( 0x1018 )
360#define _PB_SSR _SA1111( 0x101c )
361#define _PC_DDR _SA1111( 0x1020 )
362#define _PC_DRR _SA1111( 0x1024 )
363#define _PC_DWR _SA1111( 0x1024 )
364#define _PC_SDR _SA1111( 0x1028 )
365#define _PC_SSR _SA1111( 0x102c )
366
367#define SA1111_GPIO 0x1000
368
369#define SA1111_GPIO_PADDR (0x000)
370#define SA1111_GPIO_PADRR (0x004)
371#define SA1111_GPIO_PADWR (0x004)
372#define SA1111_GPIO_PASDR (0x008)
373#define SA1111_GPIO_PASSR (0x00c)
374#define SA1111_GPIO_PBDDR (0x010)
375#define SA1111_GPIO_PBDRR (0x014)
376#define SA1111_GPIO_PBDWR (0x014)
377#define SA1111_GPIO_PBSDR (0x018)
378#define SA1111_GPIO_PBSSR (0x01c)
379#define SA1111_GPIO_PCDDR (0x020)
380#define SA1111_GPIO_PCDRR (0x024)
381#define SA1111_GPIO_PCDWR (0x024)
382#define SA1111_GPIO_PCSDR (0x028)
383#define SA1111_GPIO_PCSSR (0x02c)
384
385#define GPIO_A0 (1 << 0)
386#define GPIO_A1 (1 << 1)
387#define GPIO_A2 (1 << 2)
388#define GPIO_A3 (1 << 3)
389
390#define GPIO_B0 (1 << 8)
391#define GPIO_B1 (1 << 9)
392#define GPIO_B2 (1 << 10)
393#define GPIO_B3 (1 << 11)
394#define GPIO_B4 (1 << 12)
395#define GPIO_B5 (1 << 13)
396#define GPIO_B6 (1 << 14)
397#define GPIO_B7 (1 << 15)
398
399#define GPIO_C0 (1 << 16)
400#define GPIO_C1 (1 << 17)
401#define GPIO_C2 (1 << 18)
402#define GPIO_C3 (1 << 19)
403#define GPIO_C4 (1 << 20)
404#define GPIO_C5 (1 << 21)
405#define GPIO_C6 (1 << 22)
406#define GPIO_C7 (1 << 23)
407
408/*
409 * Interrupt Controller
410 *
411 * Registers
412 * INTTEST0 Test register 0
413 * INTTEST1 Test register 1
414 * INTEN0 Interrupt Enable register 0
415 * INTEN1 Interrupt Enable register 1
416 * INTPOL0 Interrupt Polarity selection 0
417 * INTPOL1 Interrupt Polarity selection 1
418 * INTTSTSEL Interrupt source selection
419 * INTSTATCLR0 Interrupt Status/Clear 0
420 * INTSTATCLR1 Interrupt Status/Clear 1
421 * INTSET0 Interrupt source set 0
422 * INTSET1 Interrupt source set 1
423 * WAKE_EN0 Wake-up source enable 0
424 * WAKE_EN1 Wake-up source enable 1
425 * WAKE_POL0 Wake-up polarity selection 0
426 * WAKE_POL1 Wake-up polarity selection 1
427 */
428#define SA1111_INTC 0x1600
429
430/*
431 * These are offsets from the above base.
432 */
433#define SA1111_INTTEST0 0x0000
434#define SA1111_INTTEST1 0x0004
435#define SA1111_INTEN0 0x0008
436#define SA1111_INTEN1 0x000c
437#define SA1111_INTPOL0 0x0010
438#define SA1111_INTPOL1 0x0014
439#define SA1111_INTTSTSEL 0x0018
440#define SA1111_INTSTATCLR0 0x001c
441#define SA1111_INTSTATCLR1 0x0020
442#define SA1111_INTSET0 0x0024
443#define SA1111_INTSET1 0x0028
444#define SA1111_WAKEEN0 0x002c
445#define SA1111_WAKEEN1 0x0030
446#define SA1111_WAKEPOL0 0x0034
447#define SA1111_WAKEPOL1 0x0038
448
449/*
450 * PS/2 Trackpad and Mouse Interfaces
451 *
452 * Registers
453 * PS2CR Control Register
454 * PS2STAT Status Register
455 * PS2DATA Transmit/Receive Data register
456 * PS2CLKDIV Clock Division Register
457 * PS2PRECNT Clock Precount Register
458 * PS2TEST1 Test register 1
459 * PS2TEST2 Test register 2
460 * PS2TEST3 Test register 3
461 * PS2TEST4 Test register 4
462 */
463
464#define SA1111_KBD 0x0a00
465#define SA1111_MSE 0x0c00
466
467/*
468 * These are offsets from the above bases.
469 */
470#define SA1111_PS2CR 0x0000
471#define SA1111_PS2STAT 0x0004
472#define SA1111_PS2DATA 0x0008
473#define SA1111_PS2CLKDIV 0x000c
474#define SA1111_PS2PRECNT 0x0010
475
476#define PS2CR_ENA 0x08
477#define PS2CR_FKD 0x02
478#define PS2CR_FKC 0x01
479
480#define PS2STAT_STP 0x0100
481#define PS2STAT_TXE 0x0080
482#define PS2STAT_TXB 0x0040
483#define PS2STAT_RXF 0x0020
484#define PS2STAT_RXB 0x0010
485#define PS2STAT_ENA 0x0008
486#define PS2STAT_RXP 0x0004
487#define PS2STAT_KBD 0x0002
488#define PS2STAT_KBC 0x0001
489
490/*
491 * PCMCIA Interface
492 *
493 * Registers
494 * PCSR Status Register
495 * PCCR Control Register
496 * PCSSR Sleep State Register
497 */
498
499#define SA1111_PCMCIA 0x1600
500
501/*
502 * These are offsets from the above base.
503 */
504#define SA1111_PCCR 0x0000
505#define SA1111_PCSSR 0x0004
506#define SA1111_PCSR 0x0008
507
508#define PCSR_S0_READY (1<<0)
509#define PCSR_S1_READY (1<<1)
510#define PCSR_S0_DETECT (1<<2)
511#define PCSR_S1_DETECT (1<<3)
512#define PCSR_S0_VS1 (1<<4)
513#define PCSR_S0_VS2 (1<<5)
514#define PCSR_S1_VS1 (1<<6)
515#define PCSR_S1_VS2 (1<<7)
516#define PCSR_S0_WP (1<<8)
517#define PCSR_S1_WP (1<<9)
518#define PCSR_S0_BVD1 (1<<10)
519#define PCSR_S0_BVD2 (1<<11)
520#define PCSR_S1_BVD1 (1<<12)
521#define PCSR_S1_BVD2 (1<<13)
522
523#define PCCR_S0_RST (1<<0)
524#define PCCR_S1_RST (1<<1)
525#define PCCR_S0_FLT (1<<2)
526#define PCCR_S1_FLT (1<<3)
527#define PCCR_S0_PWAITEN (1<<4)
528#define PCCR_S1_PWAITEN (1<<5)
529#define PCCR_S0_PSE (1<<6)
530#define PCCR_S1_PSE (1<<7)
531
532#define PCSSR_S0_SLEEP (1<<0)
533#define PCSSR_S1_SLEEP (1<<1)
534
535
536
537
538extern struct bus_type sa1111_bus_type;
539
540#define SA1111_DEVID_SBI 0
541#define SA1111_DEVID_SK 1
542#define SA1111_DEVID_USB 2
543#define SA1111_DEVID_SAC 3
544#define SA1111_DEVID_SSP 4
545#define SA1111_DEVID_PS2 5
546#define SA1111_DEVID_GPIO 6
547#define SA1111_DEVID_INT 7
548#define SA1111_DEVID_PCMCIA 8
549
550struct sa1111_dev {
551 struct device dev;
552 unsigned int devid;
553 struct resource res;
554 void __iomem *mapbase;
555 unsigned int skpcr_mask;
556 unsigned int irq[6];
557 u64 dma_mask;
558};
559
560#define SA1111_DEV(_d) container_of((_d), struct sa1111_dev, dev)
561
562#define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
563#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
564
565struct sa1111_driver {
566 struct device_driver drv;
567 unsigned int devid;
568 int (*probe)(struct sa1111_dev *);
569 int (*remove)(struct sa1111_dev *);
570 int (*suspend)(struct sa1111_dev *, pm_message_t);
571 int (*resume)(struct sa1111_dev *);
572};
573
574#define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv)
575
576#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
577
578/*
579 * These frob the SKPCR register.
580 */
581void sa1111_enable_device(struct sa1111_dev *);
582void sa1111_disable_device(struct sa1111_dev *);
583
584unsigned int sa1111_pll_clock(struct sa1111_dev *);
585
586#define SA1111_AUDIO_ACLINK 0
587#define SA1111_AUDIO_I2S 1
588
589void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
590int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
591int sa1111_get_audio_rate(struct sa1111_dev *sadev);
592
593int sa1111_check_dma_bug(dma_addr_t addr);
594
595int sa1111_driver_register(struct sa1111_driver *);
596void sa1111_driver_unregister(struct sa1111_driver *);
597
598void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir);
599void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
600void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
601
602#endif /* _ASM_ARCH_SA1111 */
diff --git a/include/asm-arm/hardware/scoop.h b/include/asm-arm/hardware/scoop.h
new file mode 100644
index 000000000000..7ea771ff6144
--- /dev/null
+++ b/include/asm-arm/hardware/scoop.h
@@ -0,0 +1,47 @@
1/*
2 * Definitions for the SCOOP interface found on various Sharp PDAs
3 *
4 * Copyright (c) 2004 Richard Purdie
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define SCOOP_MCR 0x00
13#define SCOOP_CDR 0x04
14#define SCOOP_CSR 0x08
15#define SCOOP_CPR 0x0C
16#define SCOOP_CCR 0x10
17#define SCOOP_IRR 0x14
18#define SCOOP_IRM 0x14
19#define SCOOP_IMR 0x18
20#define SCOOP_ISR 0x1C
21#define SCOOP_GPCR 0x20
22#define SCOOP_GPWR 0x24
23#define SCOOP_GPRR 0x28
24
25#define SCOOP_GPCR_PA22 ( 1 << 12 )
26#define SCOOP_GPCR_PA21 ( 1 << 11 )
27#define SCOOP_GPCR_PA20 ( 1 << 10 )
28#define SCOOP_GPCR_PA19 ( 1 << 9 )
29#define SCOOP_GPCR_PA18 ( 1 << 8 )
30#define SCOOP_GPCR_PA17 ( 1 << 7 )
31#define SCOOP_GPCR_PA16 ( 1 << 6 )
32#define SCOOP_GPCR_PA15 ( 1 << 5 )
33#define SCOOP_GPCR_PA14 ( 1 << 4 )
34#define SCOOP_GPCR_PA13 ( 1 << 3 )
35#define SCOOP_GPCR_PA12 ( 1 << 2 )
36#define SCOOP_GPCR_PA11 ( 1 << 1 )
37
38struct scoop_config {
39 unsigned short io_out;
40 unsigned short io_dir;
41};
42
43void reset_scoop(struct device *dev);
44unsigned short set_scoop_gpio(struct device *dev, unsigned short bit);
45unsigned short reset_scoop_gpio(struct device *dev, unsigned short bit);
46unsigned short read_scoop_reg(struct device *dev, unsigned short reg);
47void write_scoop_reg(struct device *dev, unsigned short reg, unsigned short data);
diff --git a/include/asm-arm/hardware/ssp.h b/include/asm-arm/hardware/ssp.h
new file mode 100644
index 000000000000..28aa11b769cd
--- /dev/null
+++ b/include/asm-arm/hardware/ssp.h
@@ -0,0 +1,28 @@
1/*
2 * ssp.h
3 *
4 * Copyright (C) 2003 Russell King, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef SSP_H
11#define SSP_H
12
13struct ssp_state {
14 unsigned int cr0;
15 unsigned int cr1;
16};
17
18int ssp_write_word(u16 data);
19int ssp_read_word(void);
20void ssp_flush(void);
21void ssp_enable(void);
22void ssp_disable(void);
23void ssp_save_state(struct ssp_state *ssp);
24void ssp_restore_state(struct ssp_state *ssp);
25int ssp_init(void);
26void ssp_exit(void);
27
28#endif
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