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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-02 05:55:55 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-02 16:32:35 -0400
commit4baa9922430662431231ac637adedddbb0cfb2d7 (patch)
treee8fb765ce3e41c01f33de34a0bc9494f0ae19818 /include/asm-arm/hardware/sa1111.h
parentff4db0a043a5dee7180bdffd178e61cd02812c68 (diff)
[ARM] move include/asm-arm to arch/arm/include/asm
Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/hardware/sa1111.h')
-rw-r--r--include/asm-arm/hardware/sa1111.h581
1 files changed, 0 insertions, 581 deletions
diff --git a/include/asm-arm/hardware/sa1111.h b/include/asm-arm/hardware/sa1111.h
deleted file mode 100644
index 61b1d05c7df7..000000000000
--- a/include/asm-arm/hardware/sa1111.h
+++ /dev/null
@@ -1,581 +0,0 @@
1/*
2 * linux/include/asm-arm/hardware/sa1111.h
3 *
4 * Copyright (C) 2000 John G Dorsey <john+@cs.cmu.edu>
5 *
6 * This file contains definitions for the SA-1111 Companion Chip.
7 * (Structure and naming borrowed from SA-1101.h, by Peter Danielsson.)
8 *
9 * Macro that calculates real address for registers in the SA-1111
10 */
11
12#ifndef _ASM_ARCH_SA1111
13#define _ASM_ARCH_SA1111
14
15#include <asm/arch/bitfield.h>
16
17/*
18 * The SA1111 is always located at virtual 0xf4000000, and is always
19 * "native" endian.
20 */
21
22#define SA1111_VBASE 0xf4000000
23
24/* Don't use these! */
25#define SA1111_p2v( x ) ((x) - SA1111_BASE + SA1111_VBASE)
26#define SA1111_v2p( x ) ((x) - SA1111_VBASE + SA1111_BASE)
27
28#ifndef __ASSEMBLY__
29#define _SA1111(x) ((x) + sa1111->resource.start)
30#endif
31
32#define sa1111_writel(val,addr) __raw_writel(val, addr)
33#define sa1111_readl(addr) __raw_readl(addr)
34
35/*
36 * 26 bits of the SA-1110 address bus are available to the SA-1111.
37 * Use these when feeding target addresses to the DMA engines.
38 */
39
40#define SA1111_ADDR_WIDTH (26)
41#define SA1111_ADDR_MASK ((1<<SA1111_ADDR_WIDTH)-1)
42#define SA1111_DMA_ADDR(x) ((x)&SA1111_ADDR_MASK)
43
44/*
45 * Don't ask the (SAC) DMA engines to move less than this amount.
46 */
47
48#define SA1111_SAC_DMA_MIN_XFER (0x800)
49
50/*
51 * System Bus Interface (SBI)
52 *
53 * Registers
54 * SKCR Control Register
55 * SMCR Shared Memory Controller Register
56 * SKID ID Register
57 */
58#define SA1111_SKCR 0x0000
59#define SA1111_SMCR 0x0004
60#define SA1111_SKID 0x0008
61
62#define SKCR_PLL_BYPASS (1<<0)
63#define SKCR_RCLKEN (1<<1)
64#define SKCR_SLEEP (1<<2)
65#define SKCR_DOZE (1<<3)
66#define SKCR_VCO_OFF (1<<4)
67#define SKCR_SCANTSTEN (1<<5)
68#define SKCR_CLKTSTEN (1<<6)
69#define SKCR_RDYEN (1<<7)
70#define SKCR_SELAC (1<<8)
71#define SKCR_OPPC (1<<9)
72#define SKCR_PLLTSTEN (1<<10)
73#define SKCR_USBIOTSTEN (1<<11)
74/*
75 * Don't believe the specs! Take them, throw them outside. Leave them
76 * there for a week. Spit on them. Walk on them. Stamp on them.
77 * Pour gasoline over them and finally burn them. Now think about coding.
78 * - The October 1999 errata (278260-007) says its bit 13, 1 to enable.
79 * - The Feb 2001 errata (278260-010) says that the previous errata
80 * (278260-009) is wrong, and its bit actually 12, fixed in spec
81 * 278242-003.
82 * - The SA1111 manual (278242) says bit 12, but 0 to enable.
83 * - Reality is bit 13, 1 to enable.
84 * -- rmk
85 */
86#define SKCR_OE_EN (1<<13)
87
88#define SMCR_DTIM (1<<0)
89#define SMCR_MBGE (1<<1)
90#define SMCR_DRAC_0 (1<<2)
91#define SMCR_DRAC_1 (1<<3)
92#define SMCR_DRAC_2 (1<<4)
93#define SMCR_DRAC Fld(3, 2)
94#define SMCR_CLAT (1<<5)
95
96#define SKID_SIREV_MASK (0x000000f0)
97#define SKID_MTREV_MASK (0x0000000f)
98#define SKID_ID_MASK (0xffffff00)
99#define SKID_SA1111_ID (0x690cc200)
100
101/*
102 * System Controller
103 *
104 * Registers
105 * SKPCR Power Control Register
106 * SKCDR Clock Divider Register
107 * SKAUD Audio Clock Divider Register
108 * SKPMC PS/2 Mouse Clock Divider Register
109 * SKPTC PS/2 Track Pad Clock Divider Register
110 * SKPEN0 PWM0 Enable Register
111 * SKPWM0 PWM0 Clock Register
112 * SKPEN1 PWM1 Enable Register
113 * SKPWM1 PWM1 Clock Register
114 */
115#define SA1111_SKPCR 0x0200
116#define SA1111_SKCDR 0x0204
117#define SA1111_SKAUD 0x0208
118#define SA1111_SKPMC 0x020c
119#define SA1111_SKPTC 0x0210
120#define SA1111_SKPEN0 0x0214
121#define SA1111_SKPWM0 0x0218
122#define SA1111_SKPEN1 0x021c
123#define SA1111_SKPWM1 0x0220
124
125#define SKPCR_UCLKEN (1<<0)
126#define SKPCR_ACCLKEN (1<<1)
127#define SKPCR_I2SCLKEN (1<<2)
128#define SKPCR_L3CLKEN (1<<3)
129#define SKPCR_SCLKEN (1<<4)
130#define SKPCR_PMCLKEN (1<<5)
131#define SKPCR_PTCLKEN (1<<6)
132#define SKPCR_DCLKEN (1<<7)
133#define SKPCR_PWMCLKEN (1<<8)
134
135/*
136 * USB Host controller
137 */
138#define SA1111_USB 0x0400
139
140/*
141 * Offsets from SA1111_USB_BASE
142 */
143#define SA1111_USB_STATUS 0x0118
144#define SA1111_USB_RESET 0x011c
145#define SA1111_USB_IRQTEST 0x0120
146
147#define USB_RESET_FORCEIFRESET (1 << 0)
148#define USB_RESET_FORCEHCRESET (1 << 1)
149#define USB_RESET_CLKGENRESET (1 << 2)
150#define USB_RESET_SIMSCALEDOWN (1 << 3)
151#define USB_RESET_USBINTTEST (1 << 4)
152#define USB_RESET_SLEEPSTBYEN (1 << 5)
153#define USB_RESET_PWRSENSELOW (1 << 6)
154#define USB_RESET_PWRCTRLLOW (1 << 7)
155
156#define USB_STATUS_IRQHCIRMTWKUP (1 << 7)
157#define USB_STATUS_IRQHCIBUFFACC (1 << 8)
158#define USB_STATUS_NIRQHCIM (1 << 9)
159#define USB_STATUS_NHCIMFCLR (1 << 10)
160#define USB_STATUS_USBPWRSENSE (1 << 11)
161
162/*
163 * Serial Audio Controller
164 *
165 * Registers
166 * SACR0 Serial Audio Common Control Register
167 * SACR1 Serial Audio Alternate Mode (I2C/MSB) Control Register
168 * SACR2 Serial Audio AC-link Control Register
169 * SASR0 Serial Audio I2S/MSB Interface & FIFO Status Register
170 * SASR1 Serial Audio AC-link Interface & FIFO Status Register
171 * SASCR Serial Audio Status Clear Register
172 * L3_CAR L3 Control Bus Address Register
173 * L3_CDR L3 Control Bus Data Register
174 * ACCAR AC-link Command Address Register
175 * ACCDR AC-link Command Data Register
176 * ACSAR AC-link Status Address Register
177 * ACSDR AC-link Status Data Register
178 * SADTCS Serial Audio DMA Transmit Control/Status Register
179 * SADTSA Serial Audio DMA Transmit Buffer Start Address A
180 * SADTCA Serial Audio DMA Transmit Buffer Count Register A
181 * SADTSB Serial Audio DMA Transmit Buffer Start Address B
182 * SADTCB Serial Audio DMA Transmit Buffer Count Register B
183 * SADRCS Serial Audio DMA Receive Control/Status Register
184 * SADRSA Serial Audio DMA Receive Buffer Start Address A
185 * SADRCA Serial Audio DMA Receive Buffer Count Register A
186 * SADRSB Serial Audio DMA Receive Buffer Start Address B
187 * SADRCB Serial Audio DMA Receive Buffer Count Register B
188 * SAITR Serial Audio Interrupt Test Register
189 * SADR Serial Audio Data Register (16 x 32-bit)
190 */
191
192#define SA1111_SERAUDIO 0x0600
193
194/*
195 * These are offsets from the above base.
196 */
197#define SA1111_SACR0 0x00
198#define SA1111_SACR1 0x04
199#define SA1111_SACR2 0x08
200#define SA1111_SASR0 0x0c
201#define SA1111_SASR1 0x10
202#define SA1111_SASCR 0x18
203#define SA1111_L3_CAR 0x1c
204#define SA1111_L3_CDR 0x20
205#define SA1111_ACCAR 0x24
206#define SA1111_ACCDR 0x28
207#define SA1111_ACSAR 0x2c
208#define SA1111_ACSDR 0x30
209#define SA1111_SADTCS 0x34
210#define SA1111_SADTSA 0x38
211#define SA1111_SADTCA 0x3c
212#define SA1111_SADTSB 0x40
213#define SA1111_SADTCB 0x44
214#define SA1111_SADRCS 0x48
215#define SA1111_SADRSA 0x4c
216#define SA1111_SADRCA 0x50
217#define SA1111_SADRSB 0x54
218#define SA1111_SADRCB 0x58
219#define SA1111_SAITR 0x5c
220#define SA1111_SADR 0x80
221
222#ifndef CONFIG_ARCH_PXA
223
224#define SACR0_ENB (1<<0)
225#define SACR0_BCKD (1<<2)
226#define SACR0_RST (1<<3)
227
228#define SACR1_AMSL (1<<0)
229#define SACR1_L3EN (1<<1)
230#define SACR1_L3MB (1<<2)
231#define SACR1_DREC (1<<3)
232#define SACR1_DRPL (1<<4)
233#define SACR1_ENLBF (1<<5)
234
235#define SACR2_TS3V (1<<0)
236#define SACR2_TS4V (1<<1)
237#define SACR2_WKUP (1<<2)
238#define SACR2_DREC (1<<3)
239#define SACR2_DRPL (1<<4)
240#define SACR2_ENLBF (1<<5)
241#define SACR2_RESET (1<<6)
242
243#define SASR0_TNF (1<<0)
244#define SASR0_RNE (1<<1)
245#define SASR0_BSY (1<<2)
246#define SASR0_TFS (1<<3)
247#define SASR0_RFS (1<<4)
248#define SASR0_TUR (1<<5)
249#define SASR0_ROR (1<<6)
250#define SASR0_L3WD (1<<16)
251#define SASR0_L3RD (1<<17)
252
253#define SASR1_TNF (1<<0)
254#define SASR1_RNE (1<<1)
255#define SASR1_BSY (1<<2)
256#define SASR1_TFS (1<<3)
257#define SASR1_RFS (1<<4)
258#define SASR1_TUR (1<<5)
259#define SASR1_ROR (1<<6)
260#define SASR1_CADT (1<<16)
261#define SASR1_SADR (1<<17)
262#define SASR1_RSTO (1<<18)
263#define SASR1_CLPM (1<<19)
264#define SASR1_CRDY (1<<20)
265#define SASR1_RS3V (1<<21)
266#define SASR1_RS4V (1<<22)
267
268#define SASCR_TUR (1<<5)
269#define SASCR_ROR (1<<6)
270#define SASCR_DTS (1<<16)
271#define SASCR_RDD (1<<17)
272#define SASCR_STO (1<<18)
273
274#define SADTCS_TDEN (1<<0)
275#define SADTCS_TDIE (1<<1)
276#define SADTCS_TDBDA (1<<3)
277#define SADTCS_TDSTA (1<<4)
278#define SADTCS_TDBDB (1<<5)
279#define SADTCS_TDSTB (1<<6)
280#define SADTCS_TBIU (1<<7)
281
282#define SADRCS_RDEN (1<<0)
283#define SADRCS_RDIE (1<<1)
284#define SADRCS_RDBDA (1<<3)
285#define SADRCS_RDSTA (1<<4)
286#define SADRCS_RDBDB (1<<5)
287#define SADRCS_RDSTB (1<<6)
288#define SADRCS_RBIU (1<<7)
289
290#define SAD_CS_DEN (1<<0)
291#define SAD_CS_DIE (1<<1) /* Not functional on metal 1 */
292#define SAD_CS_DBDA (1<<3) /* Not functional on metal 1 */
293#define SAD_CS_DSTA (1<<4)
294#define SAD_CS_DBDB (1<<5) /* Not functional on metal 1 */
295#define SAD_CS_DSTB (1<<6)
296#define SAD_CS_BIU (1<<7) /* Not functional on metal 1 */
297
298#define SAITR_TFS (1<<0)
299#define SAITR_RFS (1<<1)
300#define SAITR_TUR (1<<2)
301#define SAITR_ROR (1<<3)
302#define SAITR_CADT (1<<4)
303#define SAITR_SADR (1<<5)
304#define SAITR_RSTO (1<<6)
305#define SAITR_TDBDA (1<<8)
306#define SAITR_TDBDB (1<<9)
307#define SAITR_RDBDA (1<<10)
308#define SAITR_RDBDB (1<<11)
309
310#endif /* !CONFIG_ARCH_PXA */
311
312/*
313 * General-Purpose I/O Interface
314 *
315 * Registers
316 * PA_DDR GPIO Block A Data Direction
317 * PA_DRR/PA_DWR GPIO Block A Data Value Register (read/write)
318 * PA_SDR GPIO Block A Sleep Direction
319 * PA_SSR GPIO Block A Sleep State
320 * PB_DDR GPIO Block B Data Direction
321 * PB_DRR/PB_DWR GPIO Block B Data Value Register (read/write)
322 * PB_SDR GPIO Block B Sleep Direction
323 * PB_SSR GPIO Block B Sleep State
324 * PC_DDR GPIO Block C Data Direction
325 * PC_DRR/PC_DWR GPIO Block C Data Value Register (read/write)
326 * PC_SDR GPIO Block C Sleep Direction
327 * PC_SSR GPIO Block C Sleep State
328 */
329
330#define _PA_DDR _SA1111( 0x1000 )
331#define _PA_DRR _SA1111( 0x1004 )
332#define _PA_DWR _SA1111( 0x1004 )
333#define _PA_SDR _SA1111( 0x1008 )
334#define _PA_SSR _SA1111( 0x100c )
335#define _PB_DDR _SA1111( 0x1010 )
336#define _PB_DRR _SA1111( 0x1014 )
337#define _PB_DWR _SA1111( 0x1014 )
338#define _PB_SDR _SA1111( 0x1018 )
339#define _PB_SSR _SA1111( 0x101c )
340#define _PC_DDR _SA1111( 0x1020 )
341#define _PC_DRR _SA1111( 0x1024 )
342#define _PC_DWR _SA1111( 0x1024 )
343#define _PC_SDR _SA1111( 0x1028 )
344#define _PC_SSR _SA1111( 0x102c )
345
346#define SA1111_GPIO 0x1000
347
348#define SA1111_GPIO_PADDR (0x000)
349#define SA1111_GPIO_PADRR (0x004)
350#define SA1111_GPIO_PADWR (0x004)
351#define SA1111_GPIO_PASDR (0x008)
352#define SA1111_GPIO_PASSR (0x00c)
353#define SA1111_GPIO_PBDDR (0x010)
354#define SA1111_GPIO_PBDRR (0x014)
355#define SA1111_GPIO_PBDWR (0x014)
356#define SA1111_GPIO_PBSDR (0x018)
357#define SA1111_GPIO_PBSSR (0x01c)
358#define SA1111_GPIO_PCDDR (0x020)
359#define SA1111_GPIO_PCDRR (0x024)
360#define SA1111_GPIO_PCDWR (0x024)
361#define SA1111_GPIO_PCSDR (0x028)
362#define SA1111_GPIO_PCSSR (0x02c)
363
364#define GPIO_A0 (1 << 0)
365#define GPIO_A1 (1 << 1)
366#define GPIO_A2 (1 << 2)
367#define GPIO_A3 (1 << 3)
368
369#define GPIO_B0 (1 << 8)
370#define GPIO_B1 (1 << 9)
371#define GPIO_B2 (1 << 10)
372#define GPIO_B3 (1 << 11)
373#define GPIO_B4 (1 << 12)
374#define GPIO_B5 (1 << 13)
375#define GPIO_B6 (1 << 14)
376#define GPIO_B7 (1 << 15)
377
378#define GPIO_C0 (1 << 16)
379#define GPIO_C1 (1 << 17)
380#define GPIO_C2 (1 << 18)
381#define GPIO_C3 (1 << 19)
382#define GPIO_C4 (1 << 20)
383#define GPIO_C5 (1 << 21)
384#define GPIO_C6 (1 << 22)
385#define GPIO_C7 (1 << 23)
386
387/*
388 * Interrupt Controller
389 *
390 * Registers
391 * INTTEST0 Test register 0
392 * INTTEST1 Test register 1
393 * INTEN0 Interrupt Enable register 0
394 * INTEN1 Interrupt Enable register 1
395 * INTPOL0 Interrupt Polarity selection 0
396 * INTPOL1 Interrupt Polarity selection 1
397 * INTTSTSEL Interrupt source selection
398 * INTSTATCLR0 Interrupt Status/Clear 0
399 * INTSTATCLR1 Interrupt Status/Clear 1
400 * INTSET0 Interrupt source set 0
401 * INTSET1 Interrupt source set 1
402 * WAKE_EN0 Wake-up source enable 0
403 * WAKE_EN1 Wake-up source enable 1
404 * WAKE_POL0 Wake-up polarity selection 0
405 * WAKE_POL1 Wake-up polarity selection 1
406 */
407#define SA1111_INTC 0x1600
408
409/*
410 * These are offsets from the above base.
411 */
412#define SA1111_INTTEST0 0x0000
413#define SA1111_INTTEST1 0x0004
414#define SA1111_INTEN0 0x0008
415#define SA1111_INTEN1 0x000c
416#define SA1111_INTPOL0 0x0010
417#define SA1111_INTPOL1 0x0014
418#define SA1111_INTTSTSEL 0x0018
419#define SA1111_INTSTATCLR0 0x001c
420#define SA1111_INTSTATCLR1 0x0020
421#define SA1111_INTSET0 0x0024
422#define SA1111_INTSET1 0x0028
423#define SA1111_WAKEEN0 0x002c
424#define SA1111_WAKEEN1 0x0030
425#define SA1111_WAKEPOL0 0x0034
426#define SA1111_WAKEPOL1 0x0038
427
428/*
429 * PS/2 Trackpad and Mouse Interfaces
430 *
431 * Registers
432 * PS2CR Control Register
433 * PS2STAT Status Register
434 * PS2DATA Transmit/Receive Data register
435 * PS2CLKDIV Clock Division Register
436 * PS2PRECNT Clock Precount Register
437 * PS2TEST1 Test register 1
438 * PS2TEST2 Test register 2
439 * PS2TEST3 Test register 3
440 * PS2TEST4 Test register 4
441 */
442
443#define SA1111_KBD 0x0a00
444#define SA1111_MSE 0x0c00
445
446/*
447 * These are offsets from the above bases.
448 */
449#define SA1111_PS2CR 0x0000
450#define SA1111_PS2STAT 0x0004
451#define SA1111_PS2DATA 0x0008
452#define SA1111_PS2CLKDIV 0x000c
453#define SA1111_PS2PRECNT 0x0010
454
455#define PS2CR_ENA 0x08
456#define PS2CR_FKD 0x02
457#define PS2CR_FKC 0x01
458
459#define PS2STAT_STP 0x0100
460#define PS2STAT_TXE 0x0080
461#define PS2STAT_TXB 0x0040
462#define PS2STAT_RXF 0x0020
463#define PS2STAT_RXB 0x0010
464#define PS2STAT_ENA 0x0008
465#define PS2STAT_RXP 0x0004
466#define PS2STAT_KBD 0x0002
467#define PS2STAT_KBC 0x0001
468
469/*
470 * PCMCIA Interface
471 *
472 * Registers
473 * PCSR Status Register
474 * PCCR Control Register
475 * PCSSR Sleep State Register
476 */
477
478#define SA1111_PCMCIA 0x1600
479
480/*
481 * These are offsets from the above base.
482 */
483#define SA1111_PCCR 0x0000
484#define SA1111_PCSSR 0x0004
485#define SA1111_PCSR 0x0008
486
487#define PCSR_S0_READY (1<<0)
488#define PCSR_S1_READY (1<<1)
489#define PCSR_S0_DETECT (1<<2)
490#define PCSR_S1_DETECT (1<<3)
491#define PCSR_S0_VS1 (1<<4)
492#define PCSR_S0_VS2 (1<<5)
493#define PCSR_S1_VS1 (1<<6)
494#define PCSR_S1_VS2 (1<<7)
495#define PCSR_S0_WP (1<<8)
496#define PCSR_S1_WP (1<<9)
497#define PCSR_S0_BVD1 (1<<10)
498#define PCSR_S0_BVD2 (1<<11)
499#define PCSR_S1_BVD1 (1<<12)
500#define PCSR_S1_BVD2 (1<<13)
501
502#define PCCR_S0_RST (1<<0)
503#define PCCR_S1_RST (1<<1)
504#define PCCR_S0_FLT (1<<2)
505#define PCCR_S1_FLT (1<<3)
506#define PCCR_S0_PWAITEN (1<<4)
507#define PCCR_S1_PWAITEN (1<<5)
508#define PCCR_S0_PSE (1<<6)
509#define PCCR_S1_PSE (1<<7)
510
511#define PCSSR_S0_SLEEP (1<<0)
512#define PCSSR_S1_SLEEP (1<<1)
513
514
515
516
517extern struct bus_type sa1111_bus_type;
518
519#define SA1111_DEVID_SBI 0
520#define SA1111_DEVID_SK 1
521#define SA1111_DEVID_USB 2
522#define SA1111_DEVID_SAC 3
523#define SA1111_DEVID_SSP 4
524#define SA1111_DEVID_PS2 5
525#define SA1111_DEVID_GPIO 6
526#define SA1111_DEVID_INT 7
527#define SA1111_DEVID_PCMCIA 8
528
529struct sa1111_dev {
530 struct device dev;
531 unsigned int devid;
532 struct resource res;
533 void __iomem *mapbase;
534 unsigned int skpcr_mask;
535 unsigned int irq[6];
536 u64 dma_mask;
537};
538
539#define SA1111_DEV(_d) container_of((_d), struct sa1111_dev, dev)
540
541#define sa1111_get_drvdata(d) dev_get_drvdata(&(d)->dev)
542#define sa1111_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, p)
543
544struct sa1111_driver {
545 struct device_driver drv;
546 unsigned int devid;
547 int (*probe)(struct sa1111_dev *);
548 int (*remove)(struct sa1111_dev *);
549 int (*suspend)(struct sa1111_dev *, pm_message_t);
550 int (*resume)(struct sa1111_dev *);
551};
552
553#define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv)
554
555#define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name)
556
557/*
558 * These frob the SKPCR register.
559 */
560void sa1111_enable_device(struct sa1111_dev *);
561void sa1111_disable_device(struct sa1111_dev *);
562
563unsigned int sa1111_pll_clock(struct sa1111_dev *);
564
565#define SA1111_AUDIO_ACLINK 0
566#define SA1111_AUDIO_I2S 1
567
568void sa1111_select_audio_mode(struct sa1111_dev *sadev, int mode);
569int sa1111_set_audio_rate(struct sa1111_dev *sadev, int rate);
570int sa1111_get_audio_rate(struct sa1111_dev *sadev);
571
572int sa1111_check_dma_bug(dma_addr_t addr);
573
574int sa1111_driver_register(struct sa1111_driver *);
575void sa1111_driver_unregister(struct sa1111_driver *);
576
577void sa1111_set_io_dir(struct sa1111_dev *sadev, unsigned int bits, unsigned int dir, unsigned int sleep_dir);
578void sa1111_set_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
579void sa1111_set_sleep_io(struct sa1111_dev *sadev, unsigned int bits, unsigned int v);
580
581#endif /* _ASM_ARCH_SA1111 */
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