async_tx: replace 'int_en' with operation preparation flags

Pass a full set of flags to drivers' per-operation 'prep' routines.
Currently the only flag passed is DMA_PREP_INTERRUPT.  The expectation is
that arch-specific async_tx_find_channel() implementations can exploit this
capability to find the best channel for an operation.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Shannon Nelson <shannon.nelson@intel.com>
Reviewed-by: Haavard Skinnemoen <hskinnemoen@atmel.com>

1 files changed, 17 insertions, 13 deletions

diff --git a/include/asm-arm/hardware/iop3xx-adma.h b/include/asm-arm/hardware/iop3xx-adma.h
index 10834b54f681..5c529e6a5e3b 100644
--- a/include/asm-arm/hardware/iop3xx-adma.h
+++ b/include/asm-arm/hardware/iop3xx-adma.h
@@ -414,7 +414,7 @@ static inline void iop3xx_aau_desc_set_src_addr(struct iop3xx_desc_aau *hw_desc,
 }
 
 static inline void
-iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en)
+iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, unsigned long flags)
 {
         struct iop3xx_desc_dma *hw_desc = desc->hw_desc;
         union {
@@ -425,14 +425,14 @@ iop_desc_init_memcpy(struct iop_adma_desc_slot *desc, int int_en)
         u_desc_ctrl.value = 0;
         u_desc_ctrl.field.mem_to_mem_en = 1;
         u_desc_ctrl.field.pci_transaction = 0xe; /* memory read block */
-        u_desc_ctrl.field.int_en = int_en;
+        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
         hw_desc->desc_ctrl = u_desc_ctrl.value;
         hw_desc->upper_pci_src_addr = 0;
         hw_desc->crc_addr = 0;
 }
 
 static inline void
-iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en)
+iop_desc_init_memset(struct iop_adma_desc_slot *desc, unsigned long flags)
 {
         struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
         union {
@@ -443,12 +443,13 @@ iop_desc_init_memset(struct iop_adma_desc_slot *desc, int int_en)
         u_desc_ctrl.value = 0;
         u_desc_ctrl.field.blk1_cmd_ctrl = 0x2; /* memory block fill */
         u_desc_ctrl.field.dest_write_en = 1;
-        u_desc_ctrl.field.int_en = int_en;
+        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
         hw_desc->desc_ctrl = u_desc_ctrl.value;
 }
 
 static inline u32
-iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en)
+iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt,
+                     unsigned long flags)
 {
         int i, shift;
         u32 edcr;
@@ -509,21 +510,23 @@ iop3xx_desc_init_xor(struct iop3xx_desc_aau *hw_desc, int src_cnt, int int_en)
 
         u_desc_ctrl.field.dest_write_en = 1;
         u_desc_ctrl.field.blk1_cmd_ctrl = 0x7; /* direct fill */
-        u_desc_ctrl.field.int_en = int_en;
+        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
         hw_desc->desc_ctrl = u_desc_ctrl.value;
 
         return u_desc_ctrl.value;
 }
 
 static inline void
-iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
+iop_desc_init_xor(struct iop_adma_desc_slot *desc, int src_cnt,
+                  unsigned long flags)
 {
-        iop3xx_desc_init_xor(desc->hw_desc, src_cnt, int_en);
+        iop3xx_desc_init_xor(desc->hw_desc, src_cnt, flags);
 }
 
 /* return the number of operations */
 static inline int
-iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
+iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt,
+                       unsigned long flags)
 {
         int slot_cnt = desc->slot_cnt, slots_per_op = desc->slots_per_op;
         struct iop3xx_desc_aau *hw_desc, *prev_hw_desc, *iter;
@@ -538,10 +541,10 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
         for (i = 0, j = 0; (slot_cnt -= slots_per_op) >= 0;
                 i += slots_per_op, j++) {
                 iter = iop_hw_desc_slot_idx(hw_desc, i);
-                u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, int_en);
+                u_desc_ctrl.value = iop3xx_desc_init_xor(iter, src_cnt, flags);
                 u_desc_ctrl.field.dest_write_en = 0;
                 u_desc_ctrl.field.zero_result_en = 1;
-                u_desc_ctrl.field.int_en = int_en;
+                u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
                 iter->desc_ctrl = u_desc_ctrl.value;
 
                 /* for the subsequent descriptors preserve the store queue
@@ -559,7 +562,8 @@ iop_desc_init_zero_sum(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
 }
 
 static inline void
-iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
+iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt,
+                       unsigned long flags)
 {
         struct iop3xx_desc_aau *hw_desc = desc->hw_desc;
         union {
@@ -591,7 +595,7 @@ iop_desc_init_null_xor(struct iop_adma_desc_slot *desc, int src_cnt, int int_en)
         }
 
         u_desc_ctrl.field.dest_write_en = 0;
-        u_desc_ctrl.field.int_en = int_en;
+        u_desc_ctrl.field.int_en = flags & DMA_PREP_INTERRUPT;
         hw_desc->desc_ctrl = u_desc_ctrl.value;
 }