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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-02 05:55:55 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-02 16:32:35 -0400
commit4baa9922430662431231ac637adedddbb0cfb2d7 (patch)
treee8fb765ce3e41c01f33de34a0bc9494f0ae19818 /include/asm-arm/bitops.h
parentff4db0a043a5dee7180bdffd178e61cd02812c68 (diff)
[ARM] move include/asm-arm to arch/arm/include/asm
Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/bitops.h')
-rw-r--r--include/asm-arm/bitops.h340
1 files changed, 0 insertions, 340 deletions
diff --git a/include/asm-arm/bitops.h b/include/asm-arm/bitops.h
deleted file mode 100644
index 9a1db20e032a..000000000000
--- a/include/asm-arm/bitops.h
+++ /dev/null
@@ -1,340 +0,0 @@
1/*
2 * Copyright 1995, Russell King.
3 * Various bits and pieces copyrights include:
4 * Linus Torvalds (test_bit).
5 * Big endian support: Copyright 2001, Nicolas Pitre
6 * reworked by rmk.
7 *
8 * bit 0 is the LSB of an "unsigned long" quantity.
9 *
10 * Please note that the code in this file should never be included
11 * from user space. Many of these are not implemented in assembler
12 * since they would be too costly. Also, they require privileged
13 * instructions (which are not available from user mode) to ensure
14 * that they are atomic.
15 */
16
17#ifndef __ASM_ARM_BITOPS_H
18#define __ASM_ARM_BITOPS_H
19
20#ifdef __KERNEL__
21
22#ifndef _LINUX_BITOPS_H
23#error only <linux/bitops.h> can be included directly
24#endif
25
26#include <linux/compiler.h>
27#include <asm/system.h>
28
29#define smp_mb__before_clear_bit() mb()
30#define smp_mb__after_clear_bit() mb()
31
32/*
33 * These functions are the basis of our bit ops.
34 *
35 * First, the atomic bitops. These use native endian.
36 */
37static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
38{
39 unsigned long flags;
40 unsigned long mask = 1UL << (bit & 31);
41
42 p += bit >> 5;
43
44 raw_local_irq_save(flags);
45 *p |= mask;
46 raw_local_irq_restore(flags);
47}
48
49static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
50{
51 unsigned long flags;
52 unsigned long mask = 1UL << (bit & 31);
53
54 p += bit >> 5;
55
56 raw_local_irq_save(flags);
57 *p &= ~mask;
58 raw_local_irq_restore(flags);
59}
60
61static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
62{
63 unsigned long flags;
64 unsigned long mask = 1UL << (bit & 31);
65
66 p += bit >> 5;
67
68 raw_local_irq_save(flags);
69 *p ^= mask;
70 raw_local_irq_restore(flags);
71}
72
73static inline int
74____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
75{
76 unsigned long flags;
77 unsigned int res;
78 unsigned long mask = 1UL << (bit & 31);
79
80 p += bit >> 5;
81
82 raw_local_irq_save(flags);
83 res = *p;
84 *p = res | mask;
85 raw_local_irq_restore(flags);
86
87 return res & mask;
88}
89
90static inline int
91____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
92{
93 unsigned long flags;
94 unsigned int res;
95 unsigned long mask = 1UL << (bit & 31);
96
97 p += bit >> 5;
98
99 raw_local_irq_save(flags);
100 res = *p;
101 *p = res & ~mask;
102 raw_local_irq_restore(flags);
103
104 return res & mask;
105}
106
107static inline int
108____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
109{
110 unsigned long flags;
111 unsigned int res;
112 unsigned long mask = 1UL << (bit & 31);
113
114 p += bit >> 5;
115
116 raw_local_irq_save(flags);
117 res = *p;
118 *p = res ^ mask;
119 raw_local_irq_restore(flags);
120
121 return res & mask;
122}
123
124#include <asm-generic/bitops/non-atomic.h>
125
126/*
127 * A note about Endian-ness.
128 * -------------------------
129 *
130 * When the ARM is put into big endian mode via CR15, the processor
131 * merely swaps the order of bytes within words, thus:
132 *
133 * ------------ physical data bus bits -----------
134 * D31 ... D24 D23 ... D16 D15 ... D8 D7 ... D0
135 * little byte 3 byte 2 byte 1 byte 0
136 * big byte 0 byte 1 byte 2 byte 3
137 *
138 * This means that reading a 32-bit word at address 0 returns the same
139 * value irrespective of the endian mode bit.
140 *
141 * Peripheral devices should be connected with the data bus reversed in
142 * "Big Endian" mode. ARM Application Note 61 is applicable, and is
143 * available from http://www.arm.com/.
144 *
145 * The following assumes that the data bus connectivity for big endian
146 * mode has been followed.
147 *
148 * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
149 */
150
151/*
152 * Little endian assembly bitops. nr = 0 -> byte 0 bit 0.
153 */
154extern void _set_bit_le(int nr, volatile unsigned long * p);
155extern void _clear_bit_le(int nr, volatile unsigned long * p);
156extern void _change_bit_le(int nr, volatile unsigned long * p);
157extern int _test_and_set_bit_le(int nr, volatile unsigned long * p);
158extern int _test_and_clear_bit_le(int nr, volatile unsigned long * p);
159extern int _test_and_change_bit_le(int nr, volatile unsigned long * p);
160extern int _find_first_zero_bit_le(const void * p, unsigned size);
161extern int _find_next_zero_bit_le(const void * p, int size, int offset);
162extern int _find_first_bit_le(const unsigned long *p, unsigned size);
163extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
164
165/*
166 * Big endian assembly bitops. nr = 0 -> byte 3 bit 0.
167 */
168extern void _set_bit_be(int nr, volatile unsigned long * p);
169extern void _clear_bit_be(int nr, volatile unsigned long * p);
170extern void _change_bit_be(int nr, volatile unsigned long * p);
171extern int _test_and_set_bit_be(int nr, volatile unsigned long * p);
172extern int _test_and_clear_bit_be(int nr, volatile unsigned long * p);
173extern int _test_and_change_bit_be(int nr, volatile unsigned long * p);
174extern int _find_first_zero_bit_be(const void * p, unsigned size);
175extern int _find_next_zero_bit_be(const void * p, int size, int offset);
176extern int _find_first_bit_be(const unsigned long *p, unsigned size);
177extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
178
179#ifndef CONFIG_SMP
180/*
181 * The __* form of bitops are non-atomic and may be reordered.
182 */
183#define ATOMIC_BITOP_LE(name,nr,p) \
184 (__builtin_constant_p(nr) ? \
185 ____atomic_##name(nr, p) : \
186 _##name##_le(nr,p))
187
188#define ATOMIC_BITOP_BE(name,nr,p) \
189 (__builtin_constant_p(nr) ? \
190 ____atomic_##name(nr, p) : \
191 _##name##_be(nr,p))
192#else
193#define ATOMIC_BITOP_LE(name,nr,p) _##name##_le(nr,p)
194#define ATOMIC_BITOP_BE(name,nr,p) _##name##_be(nr,p)
195#endif
196
197#define NONATOMIC_BITOP(name,nr,p) \
198 (____nonatomic_##name(nr, p))
199
200#ifndef __ARMEB__
201/*
202 * These are the little endian, atomic definitions.
203 */
204#define set_bit(nr,p) ATOMIC_BITOP_LE(set_bit,nr,p)
205#define clear_bit(nr,p) ATOMIC_BITOP_LE(clear_bit,nr,p)
206#define change_bit(nr,p) ATOMIC_BITOP_LE(change_bit,nr,p)
207#define test_and_set_bit(nr,p) ATOMIC_BITOP_LE(test_and_set_bit,nr,p)
208#define test_and_clear_bit(nr,p) ATOMIC_BITOP_LE(test_and_clear_bit,nr,p)
209#define test_and_change_bit(nr,p) ATOMIC_BITOP_LE(test_and_change_bit,nr,p)
210#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz)
211#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off)
212#define find_first_bit(p,sz) _find_first_bit_le(p,sz)
213#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off)
214
215#define WORD_BITOFF_TO_LE(x) ((x))
216
217#else
218
219/*
220 * These are the big endian, atomic definitions.
221 */
222#define set_bit(nr,p) ATOMIC_BITOP_BE(set_bit,nr,p)
223#define clear_bit(nr,p) ATOMIC_BITOP_BE(clear_bit,nr,p)
224#define change_bit(nr,p) ATOMIC_BITOP_BE(change_bit,nr,p)
225#define test_and_set_bit(nr,p) ATOMIC_BITOP_BE(test_and_set_bit,nr,p)
226#define test_and_clear_bit(nr,p) ATOMIC_BITOP_BE(test_and_clear_bit,nr,p)
227#define test_and_change_bit(nr,p) ATOMIC_BITOP_BE(test_and_change_bit,nr,p)
228#define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz)
229#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off)
230#define find_first_bit(p,sz) _find_first_bit_be(p,sz)
231#define find_next_bit(p,sz,off) _find_next_bit_be(p,sz,off)
232
233#define WORD_BITOFF_TO_LE(x) ((x) ^ 0x18)
234
235#endif
236
237#if __LINUX_ARM_ARCH__ < 5
238
239#include <asm-generic/bitops/ffz.h>
240#include <asm-generic/bitops/__ffs.h>
241#include <asm-generic/bitops/fls.h>
242#include <asm-generic/bitops/ffs.h>
243
244#else
245
246static inline int constant_fls(int x)
247{
248 int r = 32;
249
250 if (!x)
251 return 0;
252 if (!(x & 0xffff0000u)) {
253 x <<= 16;
254 r -= 16;
255 }
256 if (!(x & 0xff000000u)) {
257 x <<= 8;
258 r -= 8;
259 }
260 if (!(x & 0xf0000000u)) {
261 x <<= 4;
262 r -= 4;
263 }
264 if (!(x & 0xc0000000u)) {
265 x <<= 2;
266 r -= 2;
267 }
268 if (!(x & 0x80000000u)) {
269 x <<= 1;
270 r -= 1;
271 }
272 return r;
273}
274
275/*
276 * On ARMv5 and above those functions can be implemented around
277 * the clz instruction for much better code efficiency.
278 */
279
280#define __fls(x) \
281 ( __builtin_constant_p(x) ? constant_fls(x) : \
282 ({ int __r; asm("clz\t%0, %1" : "=r"(__r) : "r"(x) : "cc"); 32-__r; }) )
283
284/* Implement fls() in C so that 64-bit args are suitably truncated */
285static inline int fls(int x)
286{
287 return __fls(x);
288}
289
290#define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
291#define __ffs(x) (ffs(x) - 1)
292#define ffz(x) __ffs( ~(x) )
293
294#endif
295
296#include <asm-generic/bitops/fls64.h>
297
298#include <asm-generic/bitops/sched.h>
299#include <asm-generic/bitops/hweight.h>
300#include <asm-generic/bitops/lock.h>
301
302/*
303 * Ext2 is defined to use little-endian byte ordering.
304 * These do not need to be atomic.
305 */
306#define ext2_set_bit(nr,p) \
307 __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
308#define ext2_set_bit_atomic(lock,nr,p) \
309 test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
310#define ext2_clear_bit(nr,p) \
311 __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
312#define ext2_clear_bit_atomic(lock,nr,p) \
313 test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
314#define ext2_test_bit(nr,p) \
315 test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
316#define ext2_find_first_zero_bit(p,sz) \
317 _find_first_zero_bit_le(p,sz)
318#define ext2_find_next_zero_bit(p,sz,off) \
319 _find_next_zero_bit_le(p,sz,off)
320#define ext2_find_next_bit(p, sz, off) \
321 _find_next_bit_le(p, sz, off)
322
323/*
324 * Minix is defined to use little-endian byte ordering.
325 * These do not need to be atomic.
326 */
327#define minix_set_bit(nr,p) \
328 __set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
329#define minix_test_bit(nr,p) \
330 test_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
331#define minix_test_and_set_bit(nr,p) \
332 __test_and_set_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
333#define minix_test_and_clear_bit(nr,p) \
334 __test_and_clear_bit(WORD_BITOFF_TO_LE(nr), (unsigned long *)(p))
335#define minix_find_first_zero_bit(p,sz) \
336 _find_first_zero_bit_le(p,sz)
337
338#endif /* __KERNEL__ */
339
340#endif /* _ARM_BITOPS_H */
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