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author | David Woodhouse <David.Woodhouse@intel.com> | 2008-07-25 10:40:14 -0400 |
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committer | David Woodhouse <David.Woodhouse@intel.com> | 2008-07-25 10:40:14 -0400 |
commit | ff877ea80efa2015b6263766f78ee42c2a1b32f9 (patch) | |
tree | 85205005c611ab774702148558321c6fb92f1ccd /include/asm-arm/assembler.h | |
parent | 30821fee4f0cb3e6d241d9f7ddc37742212e3eb7 (diff) | |
parent | d37e6bf68fc1eb34a4ad21d9ae8890ed37ea80e7 (diff) |
Merge branch 'linux-next' of git://git.infradead.org/~dedekind/ubi-2.6
Diffstat (limited to 'include/asm-arm/assembler.h')
-rw-r--r-- | include/asm-arm/assembler.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h index fce832820825..911393b2c6f0 100644 --- a/include/asm-arm/assembler.h +++ b/include/asm-arm/assembler.h | |||
@@ -56,6 +56,21 @@ | |||
56 | #endif | 56 | #endif |
57 | 57 | ||
58 | /* | 58 | /* |
59 | * This can be used to enable code to cacheline align the destination | ||
60 | * pointer when bulk writing to memory. Experiments on StrongARM and | ||
61 | * XScale didn't show this a worthwhile thing to do when the cache is not | ||
62 | * set to write-allocate (this would need further testing on XScale when WA | ||
63 | * is used). | ||
64 | * | ||
65 | * On Feroceon there is much to gain however, regardless of cache mode. | ||
66 | */ | ||
67 | #ifdef CONFIG_CPU_FEROCEON | ||
68 | #define CALGN(code...) code | ||
69 | #else | ||
70 | #define CALGN(code...) | ||
71 | #endif | ||
72 | |||
73 | /* | ||
59 | * Enable and disable interrupts | 74 | * Enable and disable interrupts |
60 | */ | 75 | */ |
61 | #if __LINUX_ARM_ARCH__ >= 6 | 76 | #if __LINUX_ARM_ARCH__ >= 6 |