diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2006-01-13 16:30:48 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-01-13 16:30:48 -0500 |
commit | fa0fe48fcca9ea7f8c13e21d2646bbaa1747d183 (patch) | |
tree | 803a155f42d989ad15d3dc74389dfa6277a78895 /include/asm-arm/arch-versatile | |
parent | 5ff3fd27161127cc464fc04548d58672a6a8272a (diff) |
[ARM] Separate VIC (vectored interrupt controller) support from Versatile
Other machines may wish to make use of the VIC support code, so
move it to arch/arm/common.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-versatile')
-rw-r--r-- | include/asm-arm/arch-versatile/entry-macro.S | 1 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/platform.h | 23 |
2 files changed, 2 insertions, 22 deletions
diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S index 58f0d71759f6..feff771c0a0a 100644 --- a/include/asm-arm/arch-versatile/entry-macro.S +++ b/include/asm-arm/arch-versatile/entry-macro.S | |||
@@ -8,6 +8,7 @@ | |||
8 | * warranty of any kind, whether express or implied. | 8 | * warranty of any kind, whether express or implied. |
9 | */ | 9 | */ |
10 | #include <asm/hardware.h> | 10 | #include <asm/hardware.h> |
11 | #include <asm/hardware/vic.h> | ||
11 | 12 | ||
12 | .macro disable_fiq | 13 | .macro disable_fiq |
13 | .endm | 14 | .endm |
diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h index cbdd9fb96332..72ef874567d5 100644 --- a/include/asm-arm/arch-versatile/platform.h +++ b/include/asm-arm/arch-versatile/platform.h | |||
@@ -293,26 +293,7 @@ | |||
293 | * VERSATILE_SYS_IC | 293 | * VERSATILE_SYS_IC |
294 | * | 294 | * |
295 | */ | 295 | */ |
296 | #define VIC_IRQ_STATUS 0 | 296 | /* VIC definitions in include/asm-arm/hardware/vic.h */ |
297 | #define VIC_FIQ_STATUS 0x04 | ||
298 | #define VIC_IRQ_RAW_STATUS 0x08 | ||
299 | #define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */ | ||
300 | #define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */ | ||
301 | #define VIC_IRQ_ENABLE_CLEAR 0x14 | ||
302 | #define VIC_IRQ_SOFT 0x18 | ||
303 | #define VIC_IRQ_SOFT_CLEAR 0x1C | ||
304 | #define VIC_PROTECT 0x20 | ||
305 | #define VIC_VECT_ADDR 0x30 | ||
306 | #define VIC_DEF_VECT_ADDR 0x34 | ||
307 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ | ||
308 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ | ||
309 | #define VIC_ITCR 0x300 /* VIC test control register */ | ||
310 | |||
311 | #define VIC_FIQ_RAW_STATUS 0x08 | ||
312 | #define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */ | ||
313 | #define VIC_FIQ_ENABLE_CLEAR 0x14 | ||
314 | #define VIC_FIQ_SOFT 0x18 | ||
315 | #define VIC_FIQ_SOFT_CLEAR 0x1C | ||
316 | 297 | ||
317 | #define SIC_IRQ_STATUS 0 | 298 | #define SIC_IRQ_STATUS 0 |
318 | #define SIC_IRQ_RAW_STATUS 0x04 | 299 | #define SIC_IRQ_RAW_STATUS 0x04 |
@@ -325,8 +306,6 @@ | |||
325 | #define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */ | 306 | #define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */ |
326 | #define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */ | 307 | #define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */ |
327 | 308 | ||
328 | #define VICVectCntl_Enable (1 << 5) | ||
329 | |||
330 | /* ------------------------------------------------------------------------ | 309 | /* ------------------------------------------------------------------------ |
331 | * Interrupts - bit assignment (primary) | 310 | * Interrupts - bit assignment (primary) |
332 | * ------------------------------------------------------------------------ | 311 | * ------------------------------------------------------------------------ |