diff options
author | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2005-04-16 18:20:36 -0400 |
commit | 1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch) | |
tree | 0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-versatile |
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
Diffstat (limited to 'include/asm-arm/arch-versatile')
-rw-r--r-- | include/asm-arm/arch-versatile/debug-macro.S | 39 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/dma.h | 27 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/entry-macro.S | 35 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/hardware.h | 45 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/io.h | 29 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/irqs.h | 211 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/memory.h | 38 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/param.h | 19 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/platform.h | 510 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/system.h | 51 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/timex.h | 23 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/uncompress.h | 52 | ||||
-rw-r--r-- | include/asm-arm/arch-versatile/vmalloc.h | 33 |
13 files changed, 1112 insertions, 0 deletions
diff --git a/include/asm-arm/arch-versatile/debug-macro.S b/include/asm-arm/arch-versatile/debug-macro.S new file mode 100644 index 000000000000..89e38ac1444e --- /dev/null +++ b/include/asm-arm/arch-versatile/debug-macro.S | |||
@@ -0,0 +1,39 @@ | |||
1 | /* linux/include/asm-arm/arch-versatile/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <asm/hardware/amba_serial.h> | ||
15 | |||
16 | .macro addruart,rx | ||
17 | mrc p15, 0, \rx, c1, c0 | ||
18 | tst \rx, #1 @ MMU enabled? | ||
19 | moveq \rx, #0x10000000 | ||
20 | movne \rx, #0xf1000000 @ virtual base | ||
21 | orr \rx, \rx, #0x001F0000 | ||
22 | orr \rx, \rx, #0x00001000 | ||
23 | .endm | ||
24 | |||
25 | .macro senduart,rd,rx | ||
26 | strb \rd, [\rx, #UART01x_DR] | ||
27 | .endm | ||
28 | |||
29 | .macro waituart,rd,rx | ||
30 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
31 | tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full | ||
32 | bne 1001b | ||
33 | .endm | ||
34 | |||
35 | .macro busyuart,rd,rx | ||
36 | 1001: ldr \rd, [\rx, #0x18] @ UARTFLG | ||
37 | tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy | ||
38 | bne 1001b | ||
39 | .endm | ||
diff --git a/include/asm-arm/arch-versatile/dma.h b/include/asm-arm/arch-versatile/dma.h new file mode 100644 index 000000000000..dcc8ac26eac0 --- /dev/null +++ b/include/asm-arm/arch-versatile/dma.h | |||
@@ -0,0 +1,27 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/dma.h | ||
3 | * | ||
4 | * Copyright (C) 2003 ARM Limited. | ||
5 | * Copyright (C) 1997,1998 Russell King | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | #ifndef __ASM_ARCH_DMA_H | ||
22 | #define __ASM_ARCH_DMA_H | ||
23 | |||
24 | #define MAX_DMA_ADDRESS 0xffffffff | ||
25 | #define MAX_DMA_CHANNELS 0 | ||
26 | |||
27 | #endif /* _ASM_ARCH_DMA_H */ | ||
diff --git a/include/asm-arm/arch-versatile/entry-macro.S b/include/asm-arm/arch-versatile/entry-macro.S new file mode 100644 index 000000000000..90e4e970d253 --- /dev/null +++ b/include/asm-arm/arch-versatile/entry-macro.S | |||
@@ -0,0 +1,35 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-versatile/entry-macro.S | ||
3 | * | ||
4 | * Low-level IRQ helper macros for Versatile platforms | ||
5 | * | ||
6 | * This file is licensed under the terms of the GNU General Public | ||
7 | * License version 2. This program is licensed "as is" without any | ||
8 | * warranty of any kind, whether express or implied. | ||
9 | */ | ||
10 | .macro disable_fiq | ||
11 | .endm | ||
12 | |||
13 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
14 | ldr \base, =IO_ADDRESS(VERSATILE_VIC_BASE) | ||
15 | ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get masked status | ||
16 | mov \irqnr, #0 | ||
17 | teq \irqstat, #0 | ||
18 | beq 1003f | ||
19 | |||
20 | 1001: tst \irqstat, #15 | ||
21 | bne 1002f | ||
22 | add \irqnr, \irqnr, #4 | ||
23 | movs \irqstat, \irqstat, lsr #4 | ||
24 | bne 1001b | ||
25 | 1002: tst \irqstat, #1 | ||
26 | bne 1003f | ||
27 | add \irqnr, \irqnr, #1 | ||
28 | movs \irqstat, \irqstat, lsr #1 | ||
29 | bne 1002b | ||
30 | 1003: /* EQ will be set if no irqs pending */ | ||
31 | |||
32 | @ clz \irqnr, \irqstat | ||
33 | @1003: /* EQ will be set if we reach MAXIRQNUM */ | ||
34 | .endm | ||
35 | |||
diff --git a/include/asm-arm/arch-versatile/hardware.h b/include/asm-arm/arch-versatile/hardware.h new file mode 100644 index 000000000000..d5fb4a251e7f --- /dev/null +++ b/include/asm-arm/arch-versatile/hardware.h | |||
@@ -0,0 +1,45 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/hardware.h | ||
3 | * | ||
4 | * This file contains the hardware definitions of the Versatile boards. | ||
5 | * | ||
6 | * Copyright (C) 2003 ARM Limited. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | */ | ||
22 | #ifndef __ASM_ARCH_HARDWARE_H | ||
23 | #define __ASM_ARCH_HARDWARE_H | ||
24 | |||
25 | #include <asm/sizes.h> | ||
26 | #include <asm/arch/platform.h> | ||
27 | |||
28 | // FIXME = PCI settings need to be fixed!!!!! | ||
29 | |||
30 | /* | ||
31 | * Similar to above, but for PCI addresses (memory, IO, Config and the | ||
32 | * V3 chip itself). WARNING: this has to mirror definitions in platform.h | ||
33 | */ | ||
34 | #define PCI_MEMORY_VADDR 0xe8000000 | ||
35 | #define PCI_CONFIG_VADDR 0xec000000 | ||
36 | #define PCI_V3_VADDR 0xed000000 | ||
37 | #define PCI_IO_VADDR 0xee000000 | ||
38 | |||
39 | #define PCIO_BASE PCI_IO_VADDR | ||
40 | #define PCIMEM_BASE PCI_MEMORY_VADDR | ||
41 | |||
42 | /* macro to get at IO space when running virtually */ | ||
43 | #define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000) | ||
44 | |||
45 | #endif | ||
diff --git a/include/asm-arm/arch-versatile/io.h b/include/asm-arm/arch-versatile/io.h new file mode 100644 index 000000000000..dbb7158788fc --- /dev/null +++ b/include/asm-arm/arch-versatile/io.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/io.h | ||
3 | * | ||
4 | * Copyright (C) 2003 ARM Limited | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
21 | #define __ASM_ARM_ARCH_IO_H | ||
22 | |||
23 | #define IO_SPACE_LIMIT 0xffff | ||
24 | |||
25 | #define __io(a) ((void __iomem *)(a)) | ||
26 | #define __mem_pci(a) (a) | ||
27 | #define __mem_isa(a) (a) | ||
28 | |||
29 | #endif | ||
diff --git a/include/asm-arm/arch-versatile/irqs.h b/include/asm-arm/arch-versatile/irqs.h new file mode 100644 index 000000000000..745aa841b31a --- /dev/null +++ b/include/asm-arm/arch-versatile/irqs.h | |||
@@ -0,0 +1,211 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/irqs.h | ||
3 | * | ||
4 | * Copyright (C) 2003 ARM Limited | ||
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | |||
22 | #include <asm/arch/platform.h> | ||
23 | |||
24 | /* | ||
25 | * IRQ interrupts definitions are the same the INT definitions | ||
26 | * held within platform.h | ||
27 | */ | ||
28 | #define IRQ_VIC_START 0 | ||
29 | #define IRQ_WDOGINT (IRQ_VIC_START + INT_WDOGINT) | ||
30 | #define IRQ_SOFTINT (IRQ_VIC_START + INT_SOFTINT) | ||
31 | #define IRQ_COMMRx (IRQ_VIC_START + INT_COMMRx) | ||
32 | #define IRQ_COMMTx (IRQ_VIC_START + INT_COMMTx) | ||
33 | #define IRQ_TIMERINT0_1 (IRQ_VIC_START + INT_TIMERINT0_1) | ||
34 | #define IRQ_TIMERINT2_3 (IRQ_VIC_START + INT_TIMERINT2_3) | ||
35 | #define IRQ_GPIOINT0 (IRQ_VIC_START + INT_GPIOINT0) | ||
36 | #define IRQ_GPIOINT1 (IRQ_VIC_START + INT_GPIOINT1) | ||
37 | #define IRQ_GPIOINT2 (IRQ_VIC_START + INT_GPIOINT2) | ||
38 | #define IRQ_GPIOINT3 (IRQ_VIC_START + INT_GPIOINT3) | ||
39 | #define IRQ_RTCINT (IRQ_VIC_START + INT_RTCINT) | ||
40 | #define IRQ_SSPINT (IRQ_VIC_START + INT_SSPINT) | ||
41 | #define IRQ_UARTINT0 (IRQ_VIC_START + INT_UARTINT0) | ||
42 | #define IRQ_UARTINT1 (IRQ_VIC_START + INT_UARTINT1) | ||
43 | #define IRQ_UARTINT2 (IRQ_VIC_START + INT_UARTINT2) | ||
44 | #define IRQ_SCIINT (IRQ_VIC_START + INT_SCIINT) | ||
45 | #define IRQ_CLCDINT (IRQ_VIC_START + INT_CLCDINT) | ||
46 | #define IRQ_DMAINT (IRQ_VIC_START + INT_DMAINT) | ||
47 | #define IRQ_PWRFAILINT (IRQ_VIC_START + INT_PWRFAILINT) | ||
48 | #define IRQ_MBXINT (IRQ_VIC_START + INT_MBXINT) | ||
49 | #define IRQ_GNDINT (IRQ_VIC_START + INT_GNDINT) | ||
50 | #define IRQ_VICSOURCE21 (IRQ_VIC_START + INT_VICSOURCE21) | ||
51 | #define IRQ_VICSOURCE22 (IRQ_VIC_START + INT_VICSOURCE22) | ||
52 | #define IRQ_VICSOURCE23 (IRQ_VIC_START + INT_VICSOURCE23) | ||
53 | #define IRQ_VICSOURCE24 (IRQ_VIC_START + INT_VICSOURCE24) | ||
54 | #define IRQ_VICSOURCE25 (IRQ_VIC_START + INT_VICSOURCE25) | ||
55 | #define IRQ_VICSOURCE26 (IRQ_VIC_START + INT_VICSOURCE26) | ||
56 | #define IRQ_VICSOURCE27 (IRQ_VIC_START + INT_VICSOURCE27) | ||
57 | #define IRQ_VICSOURCE28 (IRQ_VIC_START + INT_VICSOURCE28) | ||
58 | #define IRQ_VICSOURCE29 (IRQ_VIC_START + INT_VICSOURCE29) | ||
59 | #define IRQ_VICSOURCE30 (IRQ_VIC_START + INT_VICSOURCE30) | ||
60 | #define IRQ_VICSOURCE31 (IRQ_VIC_START + INT_VICSOURCE31) | ||
61 | #define IRQ_VIC_END (IRQ_VIC_START + 31) | ||
62 | |||
63 | #define IRQMASK_WDOGINT INTMASK_WDOGINT | ||
64 | #define IRQMASK_SOFTINT INTMASK_SOFTINT | ||
65 | #define IRQMASK_COMMRx INTMASK_COMMRx | ||
66 | #define IRQMASK_COMMTx INTMASK_COMMTx | ||
67 | #define IRQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 | ||
68 | #define IRQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 | ||
69 | #define IRQMASK_GPIOINT0 INTMASK_GPIOINT0 | ||
70 | #define IRQMASK_GPIOINT1 INTMASK_GPIOINT1 | ||
71 | #define IRQMASK_GPIOINT2 INTMASK_GPIOINT2 | ||
72 | #define IRQMASK_GPIOINT3 INTMASK_GPIOINT3 | ||
73 | #define IRQMASK_RTCINT INTMASK_RTCINT | ||
74 | #define IRQMASK_SSPINT INTMASK_SSPINT | ||
75 | #define IRQMASK_UARTINT0 INTMASK_UARTINT0 | ||
76 | #define IRQMASK_UARTINT1 INTMASK_UARTINT1 | ||
77 | #define IRQMASK_UARTINT2 INTMASK_UARTINT2 | ||
78 | #define IRQMASK_SCIINT INTMASK_SCIINT | ||
79 | #define IRQMASK_CLCDINT INTMASK_CLCDINT | ||
80 | #define IRQMASK_DMAINT INTMASK_DMAINT | ||
81 | #define IRQMASK_PWRFAILINT INTMASK_PWRFAILINT | ||
82 | #define IRQMASK_MBXINT INTMASK_MBXINT | ||
83 | #define IRQMASK_GNDINT INTMASK_GNDINT | ||
84 | #define IRQMASK_VICSOURCE21 INTMASK_VICSOURCE21 | ||
85 | #define IRQMASK_VICSOURCE22 INTMASK_VICSOURCE22 | ||
86 | #define IRQMASK_VICSOURCE23 INTMASK_VICSOURCE23 | ||
87 | #define IRQMASK_VICSOURCE24 INTMASK_VICSOURCE24 | ||
88 | #define IRQMASK_VICSOURCE25 INTMASK_VICSOURCE25 | ||
89 | #define IRQMASK_VICSOURCE26 INTMASK_VICSOURCE26 | ||
90 | #define IRQMASK_VICSOURCE27 INTMASK_VICSOURCE27 | ||
91 | #define IRQMASK_VICSOURCE28 INTMASK_VICSOURCE28 | ||
92 | #define IRQMASK_VICSOURCE29 INTMASK_VICSOURCE29 | ||
93 | #define IRQMASK_VICSOURCE30 INTMASK_VICSOURCE30 | ||
94 | #define IRQMASK_VICSOURCE31 INTMASK_VICSOURCE31 | ||
95 | |||
96 | /* | ||
97 | * FIQ interrupts definitions are the same the INT definitions. | ||
98 | */ | ||
99 | #define FIQ_WDOGINT INT_WDOGINT | ||
100 | #define FIQ_SOFTINT INT_SOFTINT | ||
101 | #define FIQ_COMMRx INT_COMMRx | ||
102 | #define FIQ_COMMTx INT_COMMTx | ||
103 | #define FIQ_TIMERINT0_1 INT_TIMERINT0_1 | ||
104 | #define FIQ_TIMERINT2_3 INT_TIMERINT2_3 | ||
105 | #define FIQ_GPIOINT0 INT_GPIOINT0 | ||
106 | #define FIQ_GPIOINT1 INT_GPIOINT1 | ||
107 | #define FIQ_GPIOINT2 INT_GPIOINT2 | ||
108 | #define FIQ_GPIOINT3 INT_GPIOINT3 | ||
109 | #define FIQ_RTCINT INT_RTCINT | ||
110 | #define FIQ_SSPINT INT_SSPINT | ||
111 | #define FIQ_UARTINT0 INT_UARTINT0 | ||
112 | #define FIQ_UARTINT1 INT_UARTINT1 | ||
113 | #define FIQ_UARTINT2 INT_UARTINT2 | ||
114 | #define FIQ_SCIINT INT_SCIINT | ||
115 | #define FIQ_CLCDINT INT_CLCDINT | ||
116 | #define FIQ_DMAINT INT_DMAINT | ||
117 | #define FIQ_PWRFAILINT INT_PWRFAILINT | ||
118 | #define FIQ_MBXINT INT_MBXINT | ||
119 | #define FIQ_GNDINT INT_GNDINT | ||
120 | #define FIQ_VICSOURCE21 INT_VICSOURCE21 | ||
121 | #define FIQ_VICSOURCE22 INT_VICSOURCE22 | ||
122 | #define FIQ_VICSOURCE23 INT_VICSOURCE23 | ||
123 | #define FIQ_VICSOURCE24 INT_VICSOURCE24 | ||
124 | #define FIQ_VICSOURCE25 INT_VICSOURCE25 | ||
125 | #define FIQ_VICSOURCE26 INT_VICSOURCE26 | ||
126 | #define FIQ_VICSOURCE27 INT_VICSOURCE27 | ||
127 | #define FIQ_VICSOURCE28 INT_VICSOURCE28 | ||
128 | #define FIQ_VICSOURCE29 INT_VICSOURCE29 | ||
129 | #define FIQ_VICSOURCE30 INT_VICSOURCE30 | ||
130 | #define FIQ_VICSOURCE31 INT_VICSOURCE31 | ||
131 | |||
132 | |||
133 | #define FIQMASK_WDOGINT INTMASK_WDOGINT | ||
134 | #define FIQMASK_SOFTINT INTMASK_SOFTINT | ||
135 | #define FIQMASK_COMMRx INTMASK_COMMRx | ||
136 | #define FIQMASK_COMMTx INTMASK_COMMTx | ||
137 | #define FIQMASK_TIMERINT0_1 INTMASK_TIMERINT0_1 | ||
138 | #define FIQMASK_TIMERINT2_3 INTMASK_TIMERINT2_3 | ||
139 | #define FIQMASK_GPIOINT0 INTMASK_GPIOINT0 | ||
140 | #define FIQMASK_GPIOINT1 INTMASK_GPIOINT1 | ||
141 | #define FIQMASK_GPIOINT2 INTMASK_GPIOINT2 | ||
142 | #define FIQMASK_GPIOINT3 INTMASK_GPIOINT3 | ||
143 | #define FIQMASK_RTCINT INTMASK_RTCINT | ||
144 | #define FIQMASK_SSPINT INTMASK_SSPINT | ||
145 | #define FIQMASK_UARTINT0 INTMASK_UARTINT0 | ||
146 | #define FIQMASK_UARTINT1 INTMASK_UARTINT1 | ||
147 | #define FIQMASK_UARTINT2 INTMASK_UARTINT2 | ||
148 | #define FIQMASK_SCIINT INTMASK_SCIINT | ||
149 | #define FIQMASK_CLCDINT INTMASK_CLCDINT | ||
150 | #define FIQMASK_DMAINT INTMASK_DMAINT | ||
151 | #define FIQMASK_PWRFAILINT INTMASK_PWRFAILINT | ||
152 | #define FIQMASK_MBXINT INTMASK_MBXINT | ||
153 | #define FIQMASK_GNDINT INTMASK_GNDINT | ||
154 | #define FIQMASK_VICSOURCE21 INTMASK_VICSOURCE21 | ||
155 | #define FIQMASK_VICSOURCE22 INTMASK_VICSOURCE22 | ||
156 | #define FIQMASK_VICSOURCE23 INTMASK_VICSOURCE23 | ||
157 | #define FIQMASK_VICSOURCE24 INTMASK_VICSOURCE24 | ||
158 | #define FIQMASK_VICSOURCE25 INTMASK_VICSOURCE25 | ||
159 | #define FIQMASK_VICSOURCE26 INTMASK_VICSOURCE26 | ||
160 | #define FIQMASK_VICSOURCE27 INTMASK_VICSOURCE27 | ||
161 | #define FIQMASK_VICSOURCE28 INTMASK_VICSOURCE28 | ||
162 | #define FIQMASK_VICSOURCE29 INTMASK_VICSOURCE29 | ||
163 | #define FIQMASK_VICSOURCE30 INTMASK_VICSOURCE30 | ||
164 | #define FIQMASK_VICSOURCE31 INTMASK_VICSOURCE31 | ||
165 | |||
166 | /* | ||
167 | * Secondary interrupt controller | ||
168 | */ | ||
169 | #define IRQ_SIC_START 32 | ||
170 | #define IRQ_SIC_MMCI0B (IRQ_SIC_START + SIC_INT_MMCI0B) | ||
171 | #define IRQ_SIC_MMCI1B (IRQ_SIC_START + SIC_INT_MMCI1B) | ||
172 | #define IRQ_SIC_KMI0 (IRQ_SIC_START + SIC_INT_KMI0) | ||
173 | #define IRQ_SIC_KMI1 (IRQ_SIC_START + SIC_INT_KMI1) | ||
174 | #define IRQ_SIC_SCI3 (IRQ_SIC_START + SIC_INT_SCI3) | ||
175 | #define IRQ_SIC_UART3 (IRQ_SIC_START + SIC_INT_UART3) | ||
176 | #define IRQ_SIC_CLCD (IRQ_SIC_START + SIC_INT_CLCD) | ||
177 | #define IRQ_SIC_TOUCH (IRQ_SIC_START + SIC_INT_TOUCH) | ||
178 | #define IRQ_SIC_KEYPAD (IRQ_SIC_START + SIC_INT_KEYPAD) | ||
179 | #define IRQ_SIC_DoC (IRQ_SIC_START + SIC_INT_DoC) | ||
180 | #define IRQ_SIC_MMCI0A (IRQ_SIC_START + SIC_INT_MMCI0A) | ||
181 | #define IRQ_SIC_MMCI1A (IRQ_SIC_START + SIC_INT_MMCI1A) | ||
182 | #define IRQ_SIC_AACI (IRQ_SIC_START + SIC_INT_AACI) | ||
183 | #define IRQ_SIC_ETH (IRQ_SIC_START + SIC_INT_ETH) | ||
184 | #define IRQ_SIC_USB (IRQ_SIC_START + SIC_INT_USB) | ||
185 | #define IRQ_SIC_PCI0 (IRQ_SIC_START + SIC_INT_PCI0) | ||
186 | #define IRQ_SIC_PCI1 (IRQ_SIC_START + SIC_INT_PCI1) | ||
187 | #define IRQ_SIC_PCI2 (IRQ_SIC_START + SIC_INT_PCI2) | ||
188 | #define IRQ_SIC_PCI3 (IRQ_SIC_START + SIC_INT_PCI3) | ||
189 | #define IRQ_SIC_END 63 | ||
190 | |||
191 | #define SIC_IRQMASK_MMCI0B SIC_INTMASK_MMCI0B | ||
192 | #define SIC_IRQMASK_MMCI1B SIC_INTMASK_MMCI1B | ||
193 | #define SIC_IRQMASK_KMI0 SIC_INTMASK_KMI0 | ||
194 | #define SIC_IRQMASK_KMI1 SIC_INTMASK_KMI1 | ||
195 | #define SIC_IRQMASK_SCI3 SIC_INTMASK_SCI3 | ||
196 | #define SIC_IRQMASK_UART3 SIC_INTMASK_UART3 | ||
197 | #define SIC_IRQMASK_CLCD SIC_INTMASK_CLCD | ||
198 | #define SIC_IRQMASK_TOUCH SIC_INTMASK_TOUCH | ||
199 | #define SIC_IRQMASK_KEYPAD SIC_INTMASK_KEYPAD | ||
200 | #define SIC_IRQMASK_DoC SIC_INTMASK_DoC | ||
201 | #define SIC_IRQMASK_MMCI0A SIC_INTMASK_MMCI0A | ||
202 | #define SIC_IRQMASK_MMCI1A SIC_INTMASK_MMCI1A | ||
203 | #define SIC_IRQMASK_AACI SIC_INTMASK_AACI | ||
204 | #define SIC_IRQMASK_ETH SIC_INTMASK_ETH | ||
205 | #define SIC_IRQMASK_USB SIC_INTMASK_USB | ||
206 | #define SIC_IRQMASK_PCI0 SIC_INTMASK_PCI0 | ||
207 | #define SIC_IRQMASK_PCI1 SIC_INTMASK_PCI1 | ||
208 | #define SIC_IRQMASK_PCI2 SIC_INTMASK_PCI2 | ||
209 | #define SIC_IRQMASK_PCI3 SIC_INTMASK_PCI3 | ||
210 | |||
211 | #define NR_IRQS 64 | ||
diff --git a/include/asm-arm/arch-versatile/memory.h b/include/asm-arm/arch-versatile/memory.h new file mode 100644 index 000000000000..7b8b7cc422fa --- /dev/null +++ b/include/asm-arm/arch-versatile/memory.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/memory.h | ||
3 | * | ||
4 | * Copyright (C) 2003 ARM Limited | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #ifndef __ASM_ARCH_MEMORY_H | ||
21 | #define __ASM_ARCH_MEMORY_H | ||
22 | |||
23 | /* | ||
24 | * Physical DRAM offset. | ||
25 | */ | ||
26 | #define PHYS_OFFSET (0x00000000UL) | ||
27 | |||
28 | /* | ||
29 | * Virtual view <-> DMA view memory address translations | ||
30 | * virt_to_bus: Used to translate the virtual address to an | ||
31 | * address suitable to be passed to set_dma_addr | ||
32 | * bus_to_virt: Used to convert an address for DMA operations | ||
33 | * to an address that the kernel can use. | ||
34 | */ | ||
35 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET) | ||
36 | #define __bus_to_virt(x) ((x) + PAGE_OFFSET) | ||
37 | |||
38 | #endif | ||
diff --git a/include/asm-arm/arch-versatile/param.h b/include/asm-arm/arch-versatile/param.h new file mode 100644 index 000000000000..34b897335f87 --- /dev/null +++ b/include/asm-arm/arch-versatile/param.h | |||
@@ -0,0 +1,19 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/param.h | ||
3 | * | ||
4 | * Copyright (C) 2002 ARM Limited | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
diff --git a/include/asm-arm/arch-versatile/platform.h b/include/asm-arm/arch-versatile/platform.h new file mode 100644 index 000000000000..2598d1f08548 --- /dev/null +++ b/include/asm-arm/arch-versatile/platform.h | |||
@@ -0,0 +1,510 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/platform.h | ||
3 | * | ||
4 | * Copyright (c) ARM Limited 2003. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | |||
21 | #ifndef __address_h | ||
22 | #define __address_h 1 | ||
23 | |||
24 | /* | ||
25 | * Memory definitions | ||
26 | */ | ||
27 | #define VERSATILE_BOOT_ROM_LO 0x30000000 /* DoC Base (64Mb)...*/ | ||
28 | #define VERSATILE_BOOT_ROM_HI 0x30000000 | ||
29 | #define VERSATILE_BOOT_ROM_BASE VERSATILE_BOOT_ROM_HI /* Normal position */ | ||
30 | #define VERSATILE_BOOT_ROM_SIZE SZ_64M | ||
31 | |||
32 | #define VERSATILE_SSRAM_BASE /* VERSATILE_SSMC_BASE ? */ | ||
33 | #define VERSATILE_SSRAM_SIZE SZ_2M | ||
34 | |||
35 | #define VERSATILE_FLASH_BASE 0x34000000 | ||
36 | #define VERSATILE_FLASH_SIZE SZ_64M | ||
37 | |||
38 | /* | ||
39 | * SDRAM | ||
40 | */ | ||
41 | #define VERSATILE_SDRAM_BASE 0x00000000 | ||
42 | |||
43 | /* | ||
44 | * Logic expansion modules | ||
45 | * | ||
46 | */ | ||
47 | |||
48 | |||
49 | /* ------------------------------------------------------------------------ | ||
50 | * Versatile Registers | ||
51 | * ------------------------------------------------------------------------ | ||
52 | * | ||
53 | */ | ||
54 | #define VERSATILE_SYS_ID_OFFSET 0x00 | ||
55 | #define VERSATILE_SYS_SW_OFFSET 0x04 | ||
56 | #define VERSATILE_SYS_LED_OFFSET 0x08 | ||
57 | #define VERSATILE_SYS_OSC0_OFFSET 0x0C | ||
58 | |||
59 | #if defined(CONFIG_ARCH_VERSATILE_PB) | ||
60 | #define VERSATILE_SYS_OSC1_OFFSET 0x10 | ||
61 | #define VERSATILE_SYS_OSC2_OFFSET 0x14 | ||
62 | #define VERSATILE_SYS_OSC3_OFFSET 0x18 | ||
63 | #define VERSATILE_SYS_OSC4_OFFSET 0x1C | ||
64 | #elif defined(CONFIG_MACH_VERSATILE_AB) | ||
65 | #define VERSATILE_SYS_OSC1_OFFSET 0x1C | ||
66 | #endif | ||
67 | |||
68 | #define VERSATILE_SYS_LOCK_OFFSET 0x20 | ||
69 | #define VERSATILE_SYS_100HZ_OFFSET 0x24 | ||
70 | #define VERSATILE_SYS_CFGDATA1_OFFSET 0x28 | ||
71 | #define VERSATILE_SYS_CFGDATA2_OFFSET 0x2C | ||
72 | #define VERSATILE_SYS_FLAGS_OFFSET 0x30 | ||
73 | #define VERSATILE_SYS_FLAGSSET_OFFSET 0x30 | ||
74 | #define VERSATILE_SYS_FLAGSCLR_OFFSET 0x34 | ||
75 | #define VERSATILE_SYS_NVFLAGS_OFFSET 0x38 | ||
76 | #define VERSATILE_SYS_NVFLAGSSET_OFFSET 0x38 | ||
77 | #define VERSATILE_SYS_NVFLAGSCLR_OFFSET 0x3C | ||
78 | #define VERSATILE_SYS_RESETCTL_OFFSET 0x40 | ||
79 | #define VERSATILE_SYS_PICCTL_OFFSET 0x44 | ||
80 | #define VERSATILE_SYS_MCI_OFFSET 0x48 | ||
81 | #define VERSATILE_SYS_FLASH_OFFSET 0x4C | ||
82 | #define VERSATILE_SYS_CLCD_OFFSET 0x50 | ||
83 | #define VERSATILE_SYS_CLCDSER_OFFSET 0x54 | ||
84 | #define VERSATILE_SYS_BOOTCS_OFFSET 0x58 | ||
85 | #define VERSATILE_SYS_24MHz_OFFSET 0x5C | ||
86 | #define VERSATILE_SYS_MISC_OFFSET 0x60 | ||
87 | #define VERSATILE_SYS_TEST_OSC0_OFFSET 0x80 | ||
88 | #define VERSATILE_SYS_TEST_OSC1_OFFSET 0x84 | ||
89 | #define VERSATILE_SYS_TEST_OSC2_OFFSET 0x88 | ||
90 | #define VERSATILE_SYS_TEST_OSC3_OFFSET 0x8C | ||
91 | #define VERSATILE_SYS_TEST_OSC4_OFFSET 0x90 | ||
92 | |||
93 | #define VERSATILE_SYS_BASE 0x10000000 | ||
94 | #define VERSATILE_SYS_ID (VERSATILE_SYS_BASE + VERSATILE_SYS_ID_OFFSET) | ||
95 | #define VERSATILE_SYS_SW (VERSATILE_SYS_BASE + VERSATILE_SYS_SW_OFFSET) | ||
96 | #define VERSATILE_SYS_LED (VERSATILE_SYS_BASE + VERSATILE_SYS_LED_OFFSET) | ||
97 | #define VERSATILE_SYS_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC0_OFFSET) | ||
98 | #define VERSATILE_SYS_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC1_OFFSET) | ||
99 | |||
100 | #if defined(CONFIG_ARCH_VERSATILE_PB) | ||
101 | #define VERSATILE_SYS_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC2_OFFSET) | ||
102 | #define VERSATILE_SYS_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC3_OFFSET) | ||
103 | #define VERSATILE_SYS_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_OSC4_OFFSET) | ||
104 | #endif | ||
105 | |||
106 | #define VERSATILE_SYS_LOCK (VERSATILE_SYS_BASE + VERSATILE_SYS_LOCK_OFFSET) | ||
107 | #define VERSATILE_SYS_100HZ (VERSATILE_SYS_BASE + VERSATILE_SYS_100HZ_OFFSET) | ||
108 | #define VERSATILE_SYS_CFGDATA1 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA1_OFFSET) | ||
109 | #define VERSATILE_SYS_CFGDATA2 (VERSATILE_SYS_BASE + VERSATILE_SYS_CFGDATA2_OFFSET) | ||
110 | #define VERSATILE_SYS_FLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGS_OFFSET) | ||
111 | #define VERSATILE_SYS_FLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSSET_OFFSET) | ||
112 | #define VERSATILE_SYS_FLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_FLAGSCLR_OFFSET) | ||
113 | #define VERSATILE_SYS_NVFLAGS (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGS_OFFSET) | ||
114 | #define VERSATILE_SYS_NVFLAGSSET (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSSET_OFFSET) | ||
115 | #define VERSATILE_SYS_NVFLAGSCLR (VERSATILE_SYS_BASE + VERSATILE_SYS_NVFLAGSCLR_OFFSET) | ||
116 | #define VERSATILE_SYS_RESETCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_RESETCTL_OFFSET) | ||
117 | #define VERSATILE_SYS_PICCTL (VERSATILE_SYS_BASE + VERSATILE_SYS_PICCTL_OFFSET) | ||
118 | #define VERSATILE_SYS_MCI (VERSATILE_SYS_BASE + VERSATILE_SYS_MCI_OFFSET) | ||
119 | #define VERSATILE_SYS_FLASH (VERSATILE_SYS_BASE + VERSATILE_SYS_FLASH_OFFSET) | ||
120 | #define VERSATILE_SYS_CLCD (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCD_OFFSET) | ||
121 | #define VERSATILE_SYS_CLCDSER (VERSATILE_SYS_BASE + VERSATILE_SYS_CLCDSER_OFFSET) | ||
122 | #define VERSATILE_SYS_BOOTCS (VERSATILE_SYS_BASE + VERSATILE_SYS_BOOTCS_OFFSET) | ||
123 | #define VERSATILE_SYS_24MHz (VERSATILE_SYS_BASE + VERSATILE_SYS_24MHz_OFFSET) | ||
124 | #define VERSATILE_SYS_MISC (VERSATILE_SYS_BASE + VERSATILE_SYS_MISC_OFFSET) | ||
125 | #define VERSATILE_SYS_TEST_OSC0 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC0_OFFSET) | ||
126 | #define VERSATILE_SYS_TEST_OSC1 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC1_OFFSET) | ||
127 | #define VERSATILE_SYS_TEST_OSC2 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC2_OFFSET) | ||
128 | #define VERSATILE_SYS_TEST_OSC3 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC3_OFFSET) | ||
129 | #define VERSATILE_SYS_TEST_OSC4 (VERSATILE_SYS_BASE + VERSATILE_SYS_TEST_OSC4_OFFSET) | ||
130 | |||
131 | /* | ||
132 | * Values for VERSATILE_SYS_RESET_CTRL | ||
133 | */ | ||
134 | #define VERSATILE_SYS_CTRL_RESET_CONFIGCLR 0x01 | ||
135 | #define VERSATILE_SYS_CTRL_RESET_CONFIGINIT 0x02 | ||
136 | #define VERSATILE_SYS_CTRL_RESET_DLLRESET 0x03 | ||
137 | #define VERSATILE_SYS_CTRL_RESET_PLLRESET 0x04 | ||
138 | #define VERSATILE_SYS_CTRL_RESET_POR 0x05 | ||
139 | #define VERSATILE_SYS_CTRL_RESET_DoC 0x06 | ||
140 | |||
141 | #define VERSATILE_SYS_CTRL_LED (1 << 0) | ||
142 | |||
143 | |||
144 | /* ------------------------------------------------------------------------ | ||
145 | * Versatile control registers | ||
146 | * ------------------------------------------------------------------------ | ||
147 | */ | ||
148 | |||
149 | /* | ||
150 | * VERSATILE_IDFIELD | ||
151 | * | ||
152 | * 31:24 = manufacturer (0x41 = ARM) | ||
153 | * 23:16 = architecture (0x08 = AHB system bus, ASB processor bus) | ||
154 | * 15:12 = FPGA (0x3 = XVC600 or XVC600E) | ||
155 | * 11:4 = build value | ||
156 | * 3:0 = revision number (0x1 = rev B (AHB)) | ||
157 | */ | ||
158 | |||
159 | /* | ||
160 | * VERSATILE_SYS_LOCK | ||
161 | * control access to SYS_OSCx, SYS_CFGDATAx, SYS_RESETCTL, | ||
162 | * SYS_CLD, SYS_BOOTCS | ||
163 | */ | ||
164 | #define VERSATILE_SYS_LOCK_LOCKED (1 << 16) | ||
165 | #define VERSATILE_SYS_LOCKVAL_MASK 0xFFFF /* write 0xA05F to enable write access */ | ||
166 | |||
167 | /* | ||
168 | * VERSATILE_SYS_FLASH | ||
169 | */ | ||
170 | #define VERSATILE_FLASHPROG_FLVPPEN (1 << 0) /* Enable writing to flash */ | ||
171 | |||
172 | /* | ||
173 | * VERSATILE_INTREG | ||
174 | * - used to acknowledge and control MMCI and UART interrupts | ||
175 | */ | ||
176 | #define VERSATILE_INTREG_WPROT 0x00 /* MMC protection status (no interrupt generated) */ | ||
177 | #define VERSATILE_INTREG_RI0 0x01 /* Ring indicator UART0 is asserted, */ | ||
178 | #define VERSATILE_INTREG_CARDIN 0x08 /* MMCI card in detect */ | ||
179 | /* write 1 to acknowledge and clear */ | ||
180 | #define VERSATILE_INTREG_RI1 0x02 /* Ring indicator UART1 is asserted, */ | ||
181 | #define VERSATILE_INTREG_CARDINSERT 0x03 /* Signal insertion of MMC card */ | ||
182 | |||
183 | /* | ||
184 | * VERSATILE peripheral addresses | ||
185 | */ | ||
186 | #define VERSATILE_PCI_CORE_BASE 0x10001000 /* PCI core control */ | ||
187 | #define VERSATILE_I2C_BASE 0x10002000 /* I2C control */ | ||
188 | #define VERSATILE_SIC_BASE 0x10003000 /* Secondary interrupt controller */ | ||
189 | #define VERSATILE_AACI_BASE 0x10004000 /* Audio */ | ||
190 | #define VERSATILE_MMCI0_BASE 0x10005000 /* MMC interface */ | ||
191 | #define VERSATILE_KMI0_BASE 0x10006000 /* KMI interface */ | ||
192 | #define VERSATILE_KMI1_BASE 0x10007000 /* KMI 2nd interface */ | ||
193 | #define VERSATILE_CHAR_LCD_BASE 0x10008000 /* Character LCD */ | ||
194 | #define VERSATILE_UART3_BASE 0x10009000 /* UART 3 */ | ||
195 | #define VERSATILE_SCI1_BASE 0x1000A000 | ||
196 | #define VERSATILE_MMCI1_BASE 0x1000B000 /* MMC Interface */ | ||
197 | /* 0x1000C000 - 0x1000CFFF = reserved */ | ||
198 | #define VERSATILE_ETH_BASE 0x10010000 /* Ethernet */ | ||
199 | #define VERSATILE_USB_BASE 0x10020000 /* USB */ | ||
200 | /* 0x10030000 - 0x100FFFFF = reserved */ | ||
201 | #define VERSATILE_SMC_BASE 0x10100000 /* SMC */ | ||
202 | #define VERSATILE_MPMC_BASE 0x10110000 /* MPMC */ | ||
203 | #define VERSATILE_CLCD_BASE 0x10120000 /* CLCD */ | ||
204 | #define VERSATILE_DMAC_BASE 0x10130000 /* DMA controller */ | ||
205 | #define VERSATILE_VIC_BASE 0x10140000 /* Vectored interrupt controller */ | ||
206 | #define VERSATILE_PERIPH_BASE 0x10150000 /* off-chip peripherals alias from */ | ||
207 | /* 0x10000000 - 0x100FFFFF */ | ||
208 | #define VERSATILE_AHBM_BASE 0x101D0000 /* AHB monitor */ | ||
209 | #define VERSATILE_SCTL_BASE 0x101E0000 /* System controller */ | ||
210 | #define VERSATILE_WATCHDOG_BASE 0x101E1000 /* Watchdog */ | ||
211 | #define VERSATILE_TIMER0_1_BASE 0x101E2000 /* Timer 0 and 1 */ | ||
212 | #define VERSATILE_TIMER2_3_BASE 0x101E3000 /* Timer 2 and 3 */ | ||
213 | #define VERSATILE_GPIO0_BASE 0x101E4000 /* GPIO port 0 */ | ||
214 | #define VERSATILE_GPIO1_BASE 0x101E5000 /* GPIO port 1 */ | ||
215 | #define VERSATILE_GPIO2_BASE 0x101E6000 /* GPIO port 2 */ | ||
216 | #define VERSATILE_GPIO3_BASE 0x101E7000 /* GPIO port 3 */ | ||
217 | #define VERSATILE_RTC_BASE 0x101E8000 /* Real Time Clock */ | ||
218 | /* 0x101E9000 - reserved */ | ||
219 | #define VERSATILE_SCI_BASE 0x101F0000 /* Smart card controller */ | ||
220 | #define VERSATILE_UART0_BASE 0x101F1000 /* Uart 0 */ | ||
221 | #define VERSATILE_UART1_BASE 0x101F2000 /* Uart 1 */ | ||
222 | #define VERSATILE_UART2_BASE 0x101F3000 /* Uart 2 */ | ||
223 | #define VERSATILE_SSP_BASE 0x101F4000 /* Synchronous Serial Port */ | ||
224 | |||
225 | #define VERSATILE_SSMC_BASE 0x20000000 /* SSMC */ | ||
226 | #define VERSATILE_IB2_BASE 0x24000000 /* IB2 module */ | ||
227 | #define VERSATILE_MBX_BASE 0x40000000 /* MBX */ | ||
228 | #define VERSATILE_PCI_BASE 0x41000000 /* PCI Interface */ | ||
229 | #define VERSATILE_SDRAM67_BASE 0x70000000 /* SDRAM banks 6 and 7 */ | ||
230 | #define VERSATILE_LT_BASE 0x80000000 /* Logic Tile expansion */ | ||
231 | |||
232 | /* | ||
233 | * Disk on Chip | ||
234 | */ | ||
235 | #define VERSATILE_DOC_BASE 0x2C000000 | ||
236 | #define VERSATILE_DOC_SIZE (16 << 20) | ||
237 | #define VERSATILE_DOC_PAGE_SIZE 512 | ||
238 | #define VERSATILE_DOC_TOTAL_PAGES (DOC_SIZE / PAGE_SIZE) | ||
239 | |||
240 | #define ERASE_UNIT_PAGES 32 | ||
241 | #define START_PAGE 0x80 | ||
242 | |||
243 | /* | ||
244 | * LED settings, bits [7:0] | ||
245 | */ | ||
246 | #define VERSATILE_SYS_LED0 (1 << 0) | ||
247 | #define VERSATILE_SYS_LED1 (1 << 1) | ||
248 | #define VERSATILE_SYS_LED2 (1 << 2) | ||
249 | #define VERSATILE_SYS_LED3 (1 << 3) | ||
250 | #define VERSATILE_SYS_LED4 (1 << 4) | ||
251 | #define VERSATILE_SYS_LED5 (1 << 5) | ||
252 | #define VERSATILE_SYS_LED6 (1 << 6) | ||
253 | #define VERSATILE_SYS_LED7 (1 << 7) | ||
254 | |||
255 | #define ALL_LEDS 0xFF | ||
256 | |||
257 | #define LED_BANK VERSATILE_SYS_LED | ||
258 | |||
259 | /* | ||
260 | * Control registers | ||
261 | */ | ||
262 | #define VERSATILE_IDFIELD_OFFSET 0x0 /* Versatile build information */ | ||
263 | #define VERSATILE_FLASHPROG_OFFSET 0x4 /* Flash devices */ | ||
264 | #define VERSATILE_INTREG_OFFSET 0x8 /* Interrupt control */ | ||
265 | #define VERSATILE_DECODE_OFFSET 0xC /* Fitted logic modules */ | ||
266 | |||
267 | |||
268 | /* ------------------------------------------------------------------------ | ||
269 | * Versatile Interrupt Controller - control registers | ||
270 | * ------------------------------------------------------------------------ | ||
271 | * | ||
272 | * Offsets from interrupt controller base | ||
273 | * | ||
274 | * System Controller interrupt controller base is | ||
275 | * | ||
276 | * VERSATILE_IC_BASE | ||
277 | * | ||
278 | * Core Module interrupt controller base is | ||
279 | * | ||
280 | * VERSATILE_SYS_IC | ||
281 | * | ||
282 | */ | ||
283 | #define VIC_IRQ_STATUS 0 | ||
284 | #define VIC_FIQ_STATUS 0x04 | ||
285 | #define VIC_IRQ_RAW_STATUS 0x08 | ||
286 | #define VIC_INT_SELECT 0x0C /* 1 = FIQ, 0 = IRQ */ | ||
287 | #define VIC_IRQ_ENABLE 0x10 /* 1 = enable, 0 = disable */ | ||
288 | #define VIC_IRQ_ENABLE_CLEAR 0x14 | ||
289 | #define VIC_IRQ_SOFT 0x18 | ||
290 | #define VIC_IRQ_SOFT_CLEAR 0x1C | ||
291 | #define VIC_PROTECT 0x20 | ||
292 | #define VIC_VECT_ADDR 0x30 | ||
293 | #define VIC_DEF_VECT_ADDR 0x34 | ||
294 | #define VIC_VECT_ADDR0 0x100 /* 0 to 15 */ | ||
295 | #define VIC_VECT_CNTL0 0x200 /* 0 to 15 */ | ||
296 | #define VIC_ITCR 0x300 /* VIC test control register */ | ||
297 | |||
298 | #define VIC_FIQ_RAW_STATUS 0x08 | ||
299 | #define VIC_FIQ_ENABLE 0x10 /* 1 = enable, 0 = disable */ | ||
300 | #define VIC_FIQ_ENABLE_CLEAR 0x14 | ||
301 | #define VIC_FIQ_SOFT 0x18 | ||
302 | #define VIC_FIQ_SOFT_CLEAR 0x1C | ||
303 | |||
304 | #define SIC_IRQ_STATUS 0 | ||
305 | #define SIC_IRQ_RAW_STATUS 0x04 | ||
306 | #define SIC_IRQ_ENABLE 0x08 | ||
307 | #define SIC_IRQ_ENABLE_SET 0x08 | ||
308 | #define SIC_IRQ_ENABLE_CLEAR 0x0C | ||
309 | #define SIC_INT_SOFT_SET 0x10 | ||
310 | #define SIC_INT_SOFT_CLEAR 0x14 | ||
311 | #define SIC_INT_PIC_ENABLE 0x20 /* read status of pass through mask */ | ||
312 | #define SIC_INT_PIC_ENABLES 0x20 /* set interrupt pass through bits */ | ||
313 | #define SIC_INT_PIC_ENABLEC 0x24 /* Clear interrupt pass through bits */ | ||
314 | |||
315 | #define VICVectCntl_Enable (1 << 5) | ||
316 | |||
317 | /* ------------------------------------------------------------------------ | ||
318 | * Interrupts - bit assignment (primary) | ||
319 | * ------------------------------------------------------------------------ | ||
320 | */ | ||
321 | |||
322 | #define INT_WDOGINT 0 /* Watchdog timer */ | ||
323 | #define INT_SOFTINT 1 /* Software interrupt */ | ||
324 | #define INT_COMMRx 2 /* Debug Comm Rx interrupt */ | ||
325 | #define INT_COMMTx 3 /* Debug Comm Tx interrupt */ | ||
326 | #define INT_TIMERINT0_1 4 /* Timer 0 and 1 */ | ||
327 | #define INT_TIMERINT2_3 5 /* Timer 2 and 3 */ | ||
328 | #define INT_GPIOINT0 6 /* GPIO 0 */ | ||
329 | #define INT_GPIOINT1 7 /* GPIO 1 */ | ||
330 | #define INT_GPIOINT2 8 /* GPIO 2 */ | ||
331 | #define INT_GPIOINT3 9 /* GPIO 3 */ | ||
332 | #define INT_RTCINT 10 /* Real Time Clock */ | ||
333 | #define INT_SSPINT 11 /* Synchronous Serial Port */ | ||
334 | #define INT_UARTINT0 12 /* UART 0 on development chip */ | ||
335 | #define INT_UARTINT1 13 /* UART 1 on development chip */ | ||
336 | #define INT_UARTINT2 14 /* UART 2 on development chip */ | ||
337 | #define INT_SCIINT 15 /* Smart Card Interface */ | ||
338 | #define INT_CLCDINT 16 /* CLCD controller */ | ||
339 | #define INT_DMAINT 17 /* DMA controller */ | ||
340 | #define INT_PWRFAILINT 18 /* Power failure */ | ||
341 | #define INT_MBXINT 19 /* Graphics processor */ | ||
342 | #define INT_GNDINT 20 /* Reserved */ | ||
343 | /* External interrupt signals from logic tiles or secondary controller */ | ||
344 | #define INT_VICSOURCE21 21 /* Disk on Chip */ | ||
345 | #define INT_VICSOURCE22 22 /* MCI0A */ | ||
346 | #define INT_VICSOURCE23 23 /* MCI1A */ | ||
347 | #define INT_VICSOURCE24 24 /* AACI */ | ||
348 | #define INT_VICSOURCE25 25 /* Ethernet */ | ||
349 | #define INT_VICSOURCE26 26 /* USB */ | ||
350 | #define INT_VICSOURCE27 27 /* PCI 0 */ | ||
351 | #define INT_VICSOURCE28 28 /* PCI 1 */ | ||
352 | #define INT_VICSOURCE29 29 /* PCI 2 */ | ||
353 | #define INT_VICSOURCE30 30 /* PCI 3 */ | ||
354 | #define INT_VICSOURCE31 31 /* SIC source */ | ||
355 | |||
356 | /* | ||
357 | * Interrupt bit positions | ||
358 | * | ||
359 | */ | ||
360 | #define INTMASK_WDOGINT (1 << INT_WDOGINT) | ||
361 | #define INTMASK_SOFTINT (1 << INT_SOFTINT) | ||
362 | #define INTMASK_COMMRx (1 << INT_COMMRx) | ||
363 | #define INTMASK_COMMTx (1 << INT_COMMTx) | ||
364 | #define INTMASK_TIMERINT0_1 (1 << INT_TIMERINT0_1) | ||
365 | #define INTMASK_TIMERINT2_3 (1 << INT_TIMERINT2_3) | ||
366 | #define INTMASK_GPIOINT0 (1 << INT_GPIOINT0) | ||
367 | #define INTMASK_GPIOINT1 (1 << INT_GPIOINT1) | ||
368 | #define INTMASK_GPIOINT2 (1 << INT_GPIOINT2) | ||
369 | #define INTMASK_GPIOINT3 (1 << INT_GPIOINT3) | ||
370 | #define INTMASK_RTCINT (1 << INT_RTCINT) | ||
371 | #define INTMASK_SSPINT (1 << INT_SSPINT) | ||
372 | #define INTMASK_UARTINT0 (1 << INT_UARTINT0) | ||
373 | #define INTMASK_UARTINT1 (1 << INT_UARTINT1) | ||
374 | #define INTMASK_UARTINT2 (1 << INT_UARTINT2) | ||
375 | #define INTMASK_SCIINT (1 << INT_SCIINT) | ||
376 | #define INTMASK_CLCDINT (1 << INT_CLCDINT) | ||
377 | #define INTMASK_DMAINT (1 << INT_DMAINT) | ||
378 | #define INTMASK_PWRFAILINT (1 << INT_PWRFAILINT) | ||
379 | #define INTMASK_MBXINT (1 << INT_MBXINT) | ||
380 | #define INTMASK_GNDINT (1 << INT_GNDINT) | ||
381 | #define INTMASK_VICSOURCE21 (1 << INT_VICSOURCE21) | ||
382 | #define INTMASK_VICSOURCE22 (1 << INT_VICSOURCE22) | ||
383 | #define INTMASK_VICSOURCE23 (1 << INT_VICSOURCE23) | ||
384 | #define INTMASK_VICSOURCE24 (1 << INT_VICSOURCE24) | ||
385 | #define INTMASK_VICSOURCE25 (1 << INT_VICSOURCE25) | ||
386 | #define INTMASK_VICSOURCE26 (1 << INT_VICSOURCE26) | ||
387 | #define INTMASK_VICSOURCE27 (1 << INT_VICSOURCE27) | ||
388 | #define INTMASK_VICSOURCE28 (1 << INT_VICSOURCE28) | ||
389 | #define INTMASK_VICSOURCE29 (1 << INT_VICSOURCE29) | ||
390 | #define INTMASK_VICSOURCE30 (1 << INT_VICSOURCE30) | ||
391 | #define INTMASK_VICSOURCE31 (1 << INT_VICSOURCE31) | ||
392 | |||
393 | |||
394 | #define VERSATILE_SC_VALID_INT 0x003FFFFF | ||
395 | |||
396 | #define MAXIRQNUM 31 | ||
397 | #define MAXFIQNUM 31 | ||
398 | #define MAXSWINUM 31 | ||
399 | |||
400 | /* ------------------------------------------------------------------------ | ||
401 | * Interrupts - bit assignment (secondary) | ||
402 | * ------------------------------------------------------------------------ | ||
403 | */ | ||
404 | #define SIC_INT_MMCI0B 1 /* Multimedia Card 0B */ | ||
405 | #define SIC_INT_MMCI1B 2 /* Multimedia Card 1B */ | ||
406 | #define SIC_INT_KMI0 3 /* Keyboard/Mouse port 0 */ | ||
407 | #define SIC_INT_KMI1 4 /* Keyboard/Mouse port 1 */ | ||
408 | #define SIC_INT_SCI3 5 /* Smart Card interface */ | ||
409 | #define SIC_INT_UART3 6 /* UART 3 empty or data available */ | ||
410 | #define SIC_INT_CLCD 7 /* Character LCD */ | ||
411 | #define SIC_INT_TOUCH 8 /* Touchscreen */ | ||
412 | #define SIC_INT_KEYPAD 9 /* Key pressed on display keypad */ | ||
413 | /* 10:20 - reserved */ | ||
414 | #define SIC_INT_DoC 21 /* Disk on Chip memory controller */ | ||
415 | #define SIC_INT_MMCI0A 22 /* MMC 0A */ | ||
416 | #define SIC_INT_MMCI1A 23 /* MMC 1A */ | ||
417 | #define SIC_INT_AACI 24 /* Audio Codec */ | ||
418 | #define SIC_INT_ETH 25 /* Ethernet controller */ | ||
419 | #define SIC_INT_USB 26 /* USB controller */ | ||
420 | #define SIC_INT_PCI0 27 | ||
421 | #define SIC_INT_PCI1 28 | ||
422 | #define SIC_INT_PCI2 29 | ||
423 | #define SIC_INT_PCI3 30 | ||
424 | |||
425 | |||
426 | #define SIC_INTMASK_MMCI0B (1 << SIC_INT_MMCI0B) | ||
427 | #define SIC_INTMASK_MMCI1B (1 << SIC_INT_MMCI1B) | ||
428 | #define SIC_INTMASK_KMI0 (1 << SIC_INT_KMI0) | ||
429 | #define SIC_INTMASK_KMI1 (1 << SIC_INT_KMI1) | ||
430 | #define SIC_INTMASK_SCI3 (1 << SIC_INT_SCI3) | ||
431 | #define SIC_INTMASK_UART3 (1 << SIC_INT_UART3) | ||
432 | #define SIC_INTMASK_CLCD (1 << SIC_INT_CLCD) | ||
433 | #define SIC_INTMASK_TOUCH (1 << SIC_INT_TOUCH) | ||
434 | #define SIC_INTMASK_KEYPAD (1 << SIC_INT_KEYPAD) | ||
435 | #define SIC_INTMASK_DoC (1 << SIC_INT_DoC) | ||
436 | #define SIC_INTMASK_MMCI0A (1 << SIC_INT_MMCI0A) | ||
437 | #define SIC_INTMASK_MMCI1A (1 << SIC_INT_MMCI1A) | ||
438 | #define SIC_INTMASK_AACI (1 << SIC_INT_AACI) | ||
439 | #define SIC_INTMASK_ETH (1 << SIC_INT_ETH) | ||
440 | #define SIC_INTMASK_USB (1 << SIC_INT_USB) | ||
441 | #define SIC_INTMASK_PCI0 (1 << SIC_INT_PCI0) | ||
442 | #define SIC_INTMASK_PCI1 (1 << SIC_INT_PCI1) | ||
443 | #define SIC_INTMASK_PCI2 (1 << SIC_INT_PCI2) | ||
444 | #define SIC_INTMASK_PCI3 (1 << SIC_INT_PCI3) | ||
445 | /* | ||
446 | * Application Flash | ||
447 | * | ||
448 | */ | ||
449 | #define FLASH_BASE VERSATILE_FLASH_BASE | ||
450 | #define FLASH_SIZE VERSATILE_FLASH_SIZE | ||
451 | #define FLASH_END (FLASH_BASE + FLASH_SIZE - 1) | ||
452 | #define FLASH_BLOCK_SIZE SZ_128K | ||
453 | |||
454 | /* | ||
455 | * Boot Flash | ||
456 | * | ||
457 | */ | ||
458 | #define EPROM_BASE VERSATILE_BOOT_ROM_HI | ||
459 | #define EPROM_SIZE VERSATILE_BOOT_ROM_SIZE | ||
460 | #define EPROM_END (EPROM_BASE + EPROM_SIZE - 1) | ||
461 | |||
462 | /* | ||
463 | * Clean base - dummy | ||
464 | * | ||
465 | */ | ||
466 | #define CLEAN_BASE EPROM_BASE | ||
467 | |||
468 | /* | ||
469 | * System controller bit assignment | ||
470 | */ | ||
471 | #define VERSATILE_REFCLK 0 | ||
472 | #define VERSATILE_TIMCLK 1 | ||
473 | |||
474 | #define VERSATILE_TIMER1_EnSel 15 | ||
475 | #define VERSATILE_TIMER2_EnSel 17 | ||
476 | #define VERSATILE_TIMER3_EnSel 19 | ||
477 | #define VERSATILE_TIMER4_EnSel 21 | ||
478 | |||
479 | |||
480 | #define MAX_TIMER 2 | ||
481 | #define MAX_PERIOD 699050 | ||
482 | #define TICKS_PER_uSEC 1 | ||
483 | |||
484 | /* | ||
485 | * These are useconds NOT ticks. | ||
486 | * | ||
487 | */ | ||
488 | #define mSEC_1 1000 | ||
489 | #define mSEC_5 (mSEC_1 * 5) | ||
490 | #define mSEC_10 (mSEC_1 * 10) | ||
491 | #define mSEC_25 (mSEC_1 * 25) | ||
492 | #define SEC_1 (mSEC_1 * 1000) | ||
493 | |||
494 | #define VERSATILE_CSR_BASE 0x10000000 | ||
495 | #define VERSATILE_CSR_SIZE 0x10000000 | ||
496 | |||
497 | #ifdef CONFIG_MACH_VERSATILE_AB | ||
498 | /* | ||
499 | * IB2 Versatile/AB expansion board definitions | ||
500 | */ | ||
501 | #define VERSATILE_IB2_CAMERA_BANK 0x24000000 | ||
502 | #define VERSATILE_IB2_KBD_DATAREG 0x25000000 | ||
503 | #define VERSATILE_IB2_IER 0x26000000 /* for VICINTSOURCE27 */ | ||
504 | #define VERSATILE_IB2_CTRL 0x27000000 | ||
505 | #define VERSATILE_IB2_STAT 0x27000004 | ||
506 | #endif | ||
507 | |||
508 | #endif | ||
509 | |||
510 | /* END */ | ||
diff --git a/include/asm-arm/arch-versatile/system.h b/include/asm-arm/arch-versatile/system.h new file mode 100644 index 000000000000..8889a189739f --- /dev/null +++ b/include/asm-arm/arch-versatile/system.h | |||
@@ -0,0 +1,51 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/system.h | ||
3 | * | ||
4 | * Copyright (C) 2003 ARM Limited | ||
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | #ifndef __ASM_ARCH_SYSTEM_H | ||
22 | #define __ASM_ARCH_SYSTEM_H | ||
23 | |||
24 | #include <asm/hardware.h> | ||
25 | #include <asm/io.h> | ||
26 | #include <asm/arch/platform.h> | ||
27 | |||
28 | static inline void arch_idle(void) | ||
29 | { | ||
30 | /* | ||
31 | * This should do all the clock switching | ||
32 | * and wait for interrupt tricks | ||
33 | */ | ||
34 | cpu_do_idle(); | ||
35 | } | ||
36 | |||
37 | static inline void arch_reset(char mode) | ||
38 | { | ||
39 | unsigned int hdr_ctrl = (IO_ADDRESS(VERSATILE_SYS_BASE) + VERSATILE_SYS_RESETCTL_OFFSET); | ||
40 | unsigned int val; | ||
41 | |||
42 | /* | ||
43 | * To reset, we hit the on-board reset register | ||
44 | * in the system FPGA | ||
45 | */ | ||
46 | val = __raw_readl(hdr_ctrl); | ||
47 | val |= VERSATILE_SYS_CTRL_RESET_CONFIGCLR; | ||
48 | __raw_writel(val, hdr_ctrl); | ||
49 | } | ||
50 | |||
51 | #endif | ||
diff --git a/include/asm-arm/arch-versatile/timex.h b/include/asm-arm/arch-versatile/timex.h new file mode 100644 index 000000000000..38fd04fc9141 --- /dev/null +++ b/include/asm-arm/arch-versatile/timex.h | |||
@@ -0,0 +1,23 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/timex.h | ||
3 | * | ||
4 | * Versatile architecture timex specifications | ||
5 | * | ||
6 | * Copyright (C) 2003 ARM Limited | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License as published by | ||
10 | * the Free Software Foundation; either version 2 of the License, or | ||
11 | * (at your option) any later version. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | * You should have received a copy of the GNU General Public License | ||
19 | * along with this program; if not, write to the Free Software | ||
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
21 | */ | ||
22 | |||
23 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/include/asm-arm/arch-versatile/uncompress.h b/include/asm-arm/arch-versatile/uncompress.h new file mode 100644 index 000000000000..2f57499c7b92 --- /dev/null +++ b/include/asm-arm/arch-versatile/uncompress.h | |||
@@ -0,0 +1,52 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/uncompress.h | ||
3 | * | ||
4 | * Copyright (C) 2003 ARM Limited | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #define AMBA_UART_DR (*(volatile unsigned char *)0x101F1000) | ||
21 | #define AMBA_UART_LCRH (*(volatile unsigned char *)0x101F102C) | ||
22 | #define AMBA_UART_CR (*(volatile unsigned char *)0x101F1030) | ||
23 | #define AMBA_UART_FR (*(volatile unsigned char *)0x101F1018) | ||
24 | |||
25 | /* | ||
26 | * This does not append a newline | ||
27 | */ | ||
28 | static void putstr(const char *s) | ||
29 | { | ||
30 | while (*s) { | ||
31 | while (AMBA_UART_FR & (1 << 5)) | ||
32 | barrier(); | ||
33 | |||
34 | AMBA_UART_DR = *s; | ||
35 | |||
36 | if (*s == '\n') { | ||
37 | while (AMBA_UART_FR & (1 << 5)) | ||
38 | barrier(); | ||
39 | |||
40 | AMBA_UART_DR = '\r'; | ||
41 | } | ||
42 | s++; | ||
43 | } | ||
44 | while (AMBA_UART_FR & (1 << 3)) | ||
45 | barrier(); | ||
46 | } | ||
47 | |||
48 | /* | ||
49 | * nothing to do | ||
50 | */ | ||
51 | #define arch_decomp_setup() | ||
52 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-versatile/vmalloc.h b/include/asm-arm/arch-versatile/vmalloc.h new file mode 100644 index 000000000000..adfb34829bfc --- /dev/null +++ b/include/asm-arm/arch-versatile/vmalloc.h | |||
@@ -0,0 +1,33 @@ | |||
1 | /* | ||
2 | * linux/include/asm-arm/arch-versatile/vmalloc.h | ||
3 | * | ||
4 | * Copyright (C) 2003 ARM Limited | ||
5 | * Copyright (C) 2000 Russell King. | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License as published by | ||
9 | * the Free Software Foundation; either version 2 of the License, or | ||
10 | * (at your option) any later version. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program; if not, write to the Free Software | ||
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
20 | */ | ||
21 | |||
22 | /* | ||
23 | * Just any arbitrary offset to the start of the vmalloc VM area: the | ||
24 | * current 8MB value just means that there will be a 8MB "hole" after the | ||
25 | * physical memory until the kernel virtual memory starts. That means that | ||
26 | * any out-of-bounds memory accesses will hopefully be caught. | ||
27 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | ||
28 | * area for the same reason. ;) | ||
29 | */ | ||
30 | #define VMALLOC_OFFSET (8*1024*1024) | ||
31 | #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) | ||
32 | #define VMALLOC_VMADDR(x) ((unsigned long)(x)) | ||
33 | #define VMALLOC_END (PAGE_OFFSET + 0x18000000) | ||