diff options
author | Ben Dooks <ben-linux@fluff.org> | 2006-09-15 18:42:24 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-09-25 05:25:15 -0400 |
commit | 505788cccbb96cd496b646594c8a5fcdc26bc2d9 (patch) | |
tree | 9dbf59540c937cada2c5ae81e8459c50842374a3 /include/asm-arm/arch-s3c2410 | |
parent | fd88edd20fb0e8e2729aa8ce565316242189ceea (diff) |
[ARM] 3796/1: S3C24XX: Add per-cpu DMA channel mapper
Allow each CPU type in the S3C24XX range to
select the DMA channel mapping it supports.
We change the DMA registration to use an
virtual channel number that the DMA system
will allocate to a hardware channel at
request time.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410')
-rw-r--r-- | include/asm-arm/arch-s3c2410/dma.h | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/dma.h b/include/asm-arm/arch-s3c2410/dma.h index 3661e465b0a5..166fc89d62d7 100644 --- a/include/asm-arm/arch-s3c2410/dma.h +++ b/include/asm-arm/arch-s3c2410/dma.h | |||
@@ -23,6 +23,36 @@ | |||
23 | #define MAX_DMA_ADDRESS 0x40000000 | 23 | #define MAX_DMA_ADDRESS 0x40000000 |
24 | #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ | 24 | #define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */ |
25 | 25 | ||
26 | /* We use `virtual` dma channels to hide the fact we have only a limited | ||
27 | * number of DMA channels, and not of all of them (dependant on the device) | ||
28 | * can be attached to any DMA source. We therefore let the DMA core handle | ||
29 | * the allocation of hardware channels to clients. | ||
30 | */ | ||
31 | |||
32 | enum dma_ch { | ||
33 | DMACH_XD0, | ||
34 | DMACH_XD1, | ||
35 | DMACH_SDI, | ||
36 | DMACH_SPI0, | ||
37 | DMACH_SPI1, | ||
38 | DMACH_UART0, | ||
39 | DMACH_UART1, | ||
40 | DMACH_UART2, | ||
41 | DMACH_TIMER, | ||
42 | DMACH_I2S_IN, | ||
43 | DMACH_I2S_OUT, | ||
44 | DMACH_PCM_IN, | ||
45 | DMACH_PCM_OUT, | ||
46 | DMACH_MIC_IN, | ||
47 | DMACH_USB_EP1, | ||
48 | DMACH_USB_EP2, | ||
49 | DMACH_USB_EP3, | ||
50 | DMACH_USB_EP4, | ||
51 | DMACH_MAX, /* the end entry */ | ||
52 | }; | ||
53 | |||
54 | #define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */ | ||
55 | |||
26 | /* we have 4 dma channels */ | 56 | /* we have 4 dma channels */ |
27 | #define S3C2410_DMA_CHANNELS (4) | 57 | #define S3C2410_DMA_CHANNELS (4) |
28 | 58 | ||
@@ -149,6 +179,8 @@ struct s3c2410_dma_stats { | |||
149 | unsigned long timeout_failed; | 179 | unsigned long timeout_failed; |
150 | }; | 180 | }; |
151 | 181 | ||
182 | struct s3c2410_dma_map; | ||
183 | |||
152 | /* struct s3c2410_dma_chan | 184 | /* struct s3c2410_dma_chan |
153 | * | 185 | * |
154 | * full state information for each DMA channel | 186 | * full state information for each DMA channel |
@@ -174,6 +206,8 @@ struct s3c2410_dma_chan { | |||
174 | unsigned long load_timeout; | 206 | unsigned long load_timeout; |
175 | unsigned int flags; /* channel flags */ | 207 | unsigned int flags; /* channel flags */ |
176 | 208 | ||
209 | struct s3c24xx_dma_map *map; /* channel hw maps */ | ||
210 | |||
177 | /* channel's hardware position and configuration */ | 211 | /* channel's hardware position and configuration */ |
178 | void __iomem *regs; /* channels registers */ | 212 | void __iomem *regs; /* channels registers */ |
179 | void __iomem *addr_reg; /* data address register */ | 213 | void __iomem *addr_reg; /* data address register */ |