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authorBen Dooks <ben-linux@fluff.org>2007-07-22 11:05:25 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2007-07-22 11:44:24 -0400
commit531b617c71e780b14af5931428e0611f930c2134 (patch)
tree24cc4a76e68b9415d6dad9389d06c308bc4bbdce /include/asm-arm/arch-s3c2410
parent9a79b2274186fade17134929d4f85b70d59a3840 (diff)
[ARM] 4508/1: S3C: Move items to include/asm-arm/plat-s3c
This patch moves items of the s3c24xx support into a new plat-s3c directory for items that use the s3c24xx support but are not directly s3c24xx compatible, such as the s3c2400 and s3c6400. git mv commands: git mv include/asm-arm/arch-s3c2410/iic.h include/asm-arm/plat-s3c/iic.h git mv include/asm-arm/arch-s3c2410/nand.h include/asm-arm/plat-s3c/nand.h git mv include/asm-arm/arch-s3c2410/regs-iic.h include/asm-arm/plat-s3c/regs-iic.h git mv include/asm-arm/arch-s3c2410/regs-nand.h include/asm-arm/plat-s3c/regs-nand.h git mv include/asm-arm/arch-s3c2410/regs-rtc.h include/asm-arm/plat-s3c/regs-rtc.h git mv include/asm-arm/arch-s3c2410/regs-serial.h include/asm-arm/plat-s3c/regs-serial.h git mv include/asm-arm/arch-s3c2410/regs-timer.h include/asm-arm/plat-s3c/regs-timer.h git mv include/asm-arm/arch-s3c2410/regs-watchdog.h include/asm-arm/plat-s3c/regs-watchdog.h Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410')
-rw-r--r--include/asm-arm/arch-s3c2410/debug-macro.S2
-rw-r--r--include/asm-arm/arch-s3c2410/iic.h32
-rw-r--r--include/asm-arm/arch-s3c2410/nand.h45
-rw-r--r--include/asm-arm/arch-s3c2410/regs-iic.h56
-rw-r--r--include/asm-arm/arch-s3c2410/regs-nand.h123
-rw-r--r--include/asm-arm/arch-s3c2410/regs-rtc.h61
-rw-r--r--include/asm-arm/arch-s3c2410/regs-serial.h232
-rw-r--r--include/asm-arm/arch-s3c2410/regs-timer.h106
-rw-r--r--include/asm-arm/arch-s3c2410/regs-watchdog.h41
-rw-r--r--include/asm-arm/arch-s3c2410/system.h2
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h4
11 files changed, 4 insertions, 700 deletions
diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 93064860e0e5..90dfba45a291 100644
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -13,7 +13,7 @@
13*/ 13*/
14 14
15#include <asm/arch/map.h> 15#include <asm/arch/map.h>
16#include <asm/arch/regs-serial.h> 16#include <asm/plat-s3c/regs-serial.h>
17#include <asm/arch/regs-gpio.h> 17#include <asm/arch/regs-gpio.h>
18 18
19#define S3C2410_UART1_OFF (0x4000) 19#define S3C2410_UART1_OFF (0x4000)
diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/arch-s3c2410/iic.h
deleted file mode 100644
index 71211c8b5384..000000000000
--- a/include/asm-arm/arch-s3c2410/iic.h
+++ /dev/null
@@ -1,32 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/iic.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - I2C Controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IIC_H
14#define __ASM_ARCH_IIC_H __FILE__
15
16#define S3C_IICFLG_FILTER (1<<0) /* enable s3c2440 filter */
17
18/* Notes:
19 * 1) All frequencies are expressed in Hz
20 * 2) A value of zero is `do not care`
21*/
22
23struct s3c2410_platform_i2c {
24 unsigned int flags;
25 unsigned int slave_addr; /* slave address for controller */
26 unsigned long bus_freq; /* standard bus frequency */
27 unsigned long max_freq; /* max frequency for the bus */
28 unsigned long min_freq; /* min frequency for the bus */
29 unsigned int sda_delay; /* pclks (s3c2440 only) */
30};
31
32#endif /* __ASM_ARCH_IIC_H */
diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/arch-s3c2410/nand.h
deleted file mode 100644
index 8816f7f9cee1..000000000000
--- a/include/asm-arm/arch-s3c2410/nand.h
+++ /dev/null
@@ -1,45 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/nand.h
2 *
3 * Copyright (c) 2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * S3C2410 - NAND device controller platfrom_device info
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* struct s3c2410_nand_set
14 *
15 * define an set of one or more nand chips registered with an unique mtd
16 *
17 * nr_chips = number of chips in this set
18 * nr_partitions = number of partitions pointed to be partitoons (or zero)
19 * name = name of set (optional)
20 * nr_map = map for low-layer logical to physical chip numbers (option)
21 * partitions = mtd partition list
22*/
23
24struct s3c2410_nand_set {
25 int nr_chips;
26 int nr_partitions;
27 char *name;
28 int *nr_map;
29 struct mtd_partition *partitions;
30};
31
32struct s3c2410_platform_nand {
33 /* timing information for controller, all times in nanoseconds */
34
35 int tacls; /* time for active CLE/ALE to nWE/nOE */
36 int twrph0; /* active time for nWE/nOE */
37 int twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
38
39 int nr_sets;
40 struct s3c2410_nand_set *sets;
41
42 void (*select_chip)(struct s3c2410_nand_set *,
43 int chip);
44};
45
diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/arch-s3c2410/regs-iic.h
deleted file mode 100644
index 2ae29522f253..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-iic.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-iic.h
2 *
3 * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 I2C Controller
11*/
12
13#ifndef __ASM_ARCH_REGS_IIC_H
14#define __ASM_ARCH_REGS_IIC_H __FILE__
15
16/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
17
18#define S3C2410_IICREG(x) (x)
19
20#define S3C2410_IICCON S3C2410_IICREG(0x00)
21#define S3C2410_IICSTAT S3C2410_IICREG(0x04)
22#define S3C2410_IICADD S3C2410_IICREG(0x08)
23#define S3C2410_IICDS S3C2410_IICREG(0x0C)
24#define S3C2440_IICLC S3C2410_IICREG(0x10)
25
26#define S3C2410_IICCON_ACKEN (1<<7)
27#define S3C2410_IICCON_TXDIV_16 (0<<6)
28#define S3C2410_IICCON_TXDIV_512 (1<<6)
29#define S3C2410_IICCON_IRQEN (1<<5)
30#define S3C2410_IICCON_IRQPEND (1<<4)
31#define S3C2410_IICCON_SCALE(x) ((x)&15)
32#define S3C2410_IICCON_SCALEMASK (0xf)
33
34#define S3C2410_IICSTAT_MASTER_RX (2<<6)
35#define S3C2410_IICSTAT_MASTER_TX (3<<6)
36#define S3C2410_IICSTAT_SLAVE_RX (0<<6)
37#define S3C2410_IICSTAT_SLAVE_TX (1<<6)
38#define S3C2410_IICSTAT_MODEMASK (3<<6)
39
40#define S3C2410_IICSTAT_START (1<<5)
41#define S3C2410_IICSTAT_BUSBUSY (1<<5)
42#define S3C2410_IICSTAT_TXRXEN (1<<4)
43#define S3C2410_IICSTAT_ARBITR (1<<3)
44#define S3C2410_IICSTAT_ASSLAVE (1<<2)
45#define S3C2410_IICSTAT_ADDR0 (1<<1)
46#define S3C2410_IICSTAT_LASTBIT (1<<0)
47
48#define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
49#define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
50#define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
51#define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
52#define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
53
54#define S3C2410_IICLC_FILTER_ON (1<<2)
55
56#endif /* __ASM_ARCH_REGS_IIC_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/arch-s3c2410/regs-nand.h
deleted file mode 100644
index b824d371ae0b..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-nand.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
2 *
3 * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 NAND register definitions
11*/
12
13#ifndef __ASM_ARM_REGS_NAND
14#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
15
16
17#define S3C2410_NFREG(x) (x)
18
19#define S3C2410_NFCONF S3C2410_NFREG(0x00)
20#define S3C2410_NFCMD S3C2410_NFREG(0x04)
21#define S3C2410_NFADDR S3C2410_NFREG(0x08)
22#define S3C2410_NFDATA S3C2410_NFREG(0x0C)
23#define S3C2410_NFSTAT S3C2410_NFREG(0x10)
24#define S3C2410_NFECC S3C2410_NFREG(0x14)
25
26#define S3C2440_NFCONT S3C2410_NFREG(0x04)
27#define S3C2440_NFCMD S3C2410_NFREG(0x08)
28#define S3C2440_NFADDR S3C2410_NFREG(0x0C)
29#define S3C2440_NFDATA S3C2410_NFREG(0x10)
30#define S3C2440_NFECCD0 S3C2410_NFREG(0x14)
31#define S3C2440_NFECCD1 S3C2410_NFREG(0x18)
32#define S3C2440_NFECCD S3C2410_NFREG(0x1C)
33#define S3C2440_NFSTAT S3C2410_NFREG(0x20)
34#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
35#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
36#define S3C2440_NFMECC0 S3C2410_NFREG(0x2C)
37#define S3C2440_NFMECC1 S3C2410_NFREG(0x30)
38#define S3C2440_NFSECC S3C24E10_NFREG(0x34)
39#define S3C2440_NFSBLK S3C2410_NFREG(0x38)
40#define S3C2440_NFEBLK S3C2410_NFREG(0x3C)
41
42#define S3C2412_NFSBLK S3C2410_NFREG(0x20)
43#define S3C2412_NFEBLK S3C2410_NFREG(0x24)
44#define S3C2412_NFSTAT S3C2410_NFREG(0x28)
45#define S3C2412_NFMECC_ERR0 S3C2410_NFREG(0x2C)
46#define S3C2412_NFMECC_ERR1 S3C2410_NFREG(0x30)
47#define S3C2412_NFMECC0 S3C2410_NFREG(0x34)
48#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
49#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
50
51#define S3C2410_NFCONF_EN (1<<15)
52#define S3C2410_NFCONF_512BYTE (1<<14)
53#define S3C2410_NFCONF_4STEP (1<<13)
54#define S3C2410_NFCONF_INITECC (1<<12)
55#define S3C2410_NFCONF_nFCE (1<<11)
56#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
57#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
58#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
59
60#define S3C2410_NFSTAT_BUSY (1<<0)
61
62#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
63#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
64#define S3C2440_NFCONF_ADVFLASH (1<<3)
65#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
66#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
67#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
68
69#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
70#define S3C2440_NFCONT_SOFTLOCK (1<<12)
71#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
72#define S3C2440_NFCONT_RNBINT_EN (1<<9)
73#define S3C2440_NFCONT_RN_FALLING (1<<8)
74#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
75#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
76#define S3C2440_NFCONT_INITECC (1<<4)
77#define S3C2440_NFCONT_nFCE (1<<1)
78#define S3C2440_NFCONT_ENABLE (1<<0)
79
80#define S3C2440_NFSTAT_READY (1<<0)
81#define S3C2440_NFSTAT_nCE (1<<1)
82#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
83#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
84
85#define S3C2412_NFCONF_NANDBOOT (1<<31)
86#define S3C2412_NFCONF_ECCCLKCON (1<<30)
87#define S3C2412_NFCONF_ECC_MLC (1<<24)
88#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
89
90#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
91#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
92#define S3C2412_NFCONT_SOFTLOCK (1<<16)
93#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
94#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
95#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
96#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
97#define S3C2412_NFCONT_nFCE1 (1<<2)
98#define S3C2412_NFCONT_nFCE0 (1<<1)
99
100#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
101#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
102#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
103#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
104#define S3C2412_NFSTAT_nFCE1 (1<<3)
105#define S3C2412_NFSTAT_nFCE0 (1<<2)
106#define S3C2412_NFSTAT_Res1 (1<<1)
107#define S3C2412_NFSTAT_READY (1<<0)
108
109#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
110#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
111#define S3C2412_NFECCERR_MERRDATA(x) (((x) >> 7) & 0x3ff)
112#define S3C2412_NFECCERR_MERRBIT(x) (((x) >> 4) & 0x7)
113#define S3C2412_NFECCERR_SPARE_ERR(x) (((x) >> 2) & 0x3)
114#define S3C2412_NFECCERR_MAIN_ERR(x) (((x) >> 2) & 0x3)
115#define S3C2412_NFECCERR_NONE (0)
116#define S3C2412_NFECCERR_1BIT (1)
117#define S3C2412_NFECCERR_MULTIBIT (2)
118#define S3C2412_NFECCERR_ECCAREA (3)
119
120
121
122#endif /* __ASM_ARM_REGS_NAND */
123
diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/arch-s3c2410/regs-rtc.h
deleted file mode 100644
index 93b03c49710a..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-rtc.h
+++ /dev/null
@@ -1,61 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-rtc.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Internal RTC register definition
11*/
12
13#ifndef __ASM_ARCH_REGS_RTC_H
14#define __ASM_ARCH_REGS_RTC_H __FILE__
15
16#define S3C2410_RTCREG(x) (x)
17
18#define S3C2410_RTCCON S3C2410_RTCREG(0x40)
19#define S3C2410_RTCCON_RTCEN (1<<0)
20#define S3C2410_RTCCON_CLKSEL (1<<1)
21#define S3C2410_RTCCON_CNTSEL (1<<2)
22#define S3C2410_RTCCON_CLKRST (1<<3)
23
24#define S3C2410_TICNT S3C2410_RTCREG(0x44)
25#define S3C2410_TICNT_ENABLE (1<<7)
26
27#define S3C2410_RTCALM S3C2410_RTCREG(0x50)
28#define S3C2410_RTCALM_ALMEN (1<<6)
29#define S3C2410_RTCALM_YEAREN (1<<5)
30#define S3C2410_RTCALM_MONEN (1<<4)
31#define S3C2410_RTCALM_DAYEN (1<<3)
32#define S3C2410_RTCALM_HOUREN (1<<2)
33#define S3C2410_RTCALM_MINEN (1<<1)
34#define S3C2410_RTCALM_SECEN (1<<0)
35
36#define S3C2410_RTCALM_ALL \
37 S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
38 S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
39 S3C2410_RTCALM_SECEN
40
41
42#define S3C2410_ALMSEC S3C2410_RTCREG(0x54)
43#define S3C2410_ALMMIN S3C2410_RTCREG(0x58)
44#define S3C2410_ALMHOUR S3C2410_RTCREG(0x5c)
45
46#define S3C2410_ALMDATE S3C2410_RTCREG(0x60)
47#define S3C2410_ALMMON S3C2410_RTCREG(0x64)
48#define S3C2410_ALMYEAR S3C2410_RTCREG(0x68)
49
50#define S3C2410_RTCRST S3C2410_RTCREG(0x6c)
51
52#define S3C2410_RTCSEC S3C2410_RTCREG(0x70)
53#define S3C2410_RTCMIN S3C2410_RTCREG(0x74)
54#define S3C2410_RTCHOUR S3C2410_RTCREG(0x78)
55#define S3C2410_RTCDATE S3C2410_RTCREG(0x7c)
56#define S3C2410_RTCDAY S3C2410_RTCREG(0x80)
57#define S3C2410_RTCMON S3C2410_RTCREG(0x84)
58#define S3C2410_RTCYEAR S3C2410_RTCREG(0x88)
59
60
61#endif /* __ASM_ARCH_REGS_RTC_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
deleted file mode 100644
index 8946702a87f5..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ /dev/null
@@ -1,232 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
2 *
3 * From linux/include/asm-arm/hardware/serial_s3c2410.h
4 *
5 * Internal header file for Samsung S3C2410 serial ports (UART0-2)
6 *
7 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
8 *
9 * Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
10 *
11 * Adapted from:
12 *
13 * Internal header file for MX1ADS serial ports (UART1 & 2)
14 *
15 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
30*/
31
32#ifndef __ASM_ARM_REGS_SERIAL_H
33#define __ASM_ARM_REGS_SERIAL_H
34
35#define S3C24XX_VA_UART0 (S3C24XX_VA_UART)
36#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 )
37#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 )
38#define S3C24XX_VA_UART3 (S3C24XX_VA_UART + 0xC000 )
39
40#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
41#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
42#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
43#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
44
45#define S3C2410_URXH (0x24)
46#define S3C2410_UTXH (0x20)
47#define S3C2410_ULCON (0x00)
48#define S3C2410_UCON (0x04)
49#define S3C2410_UFCON (0x08)
50#define S3C2410_UMCON (0x0C)
51#define S3C2410_UBRDIV (0x28)
52#define S3C2410_UTRSTAT (0x10)
53#define S3C2410_UERSTAT (0x14)
54#define S3C2410_UFSTAT (0x18)
55#define S3C2410_UMSTAT (0x1C)
56
57#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
58
59#define S3C2410_LCON_CS5 (0x0)
60#define S3C2410_LCON_CS6 (0x1)
61#define S3C2410_LCON_CS7 (0x2)
62#define S3C2410_LCON_CS8 (0x3)
63#define S3C2410_LCON_CSMASK (0x3)
64
65#define S3C2410_LCON_PNONE (0x0)
66#define S3C2410_LCON_PEVEN (0x5 << 3)
67#define S3C2410_LCON_PODD (0x4 << 3)
68#define S3C2410_LCON_PMASK (0x7 << 3)
69
70#define S3C2410_LCON_STOPB (1<<2)
71#define S3C2410_LCON_IRM (1<<6)
72
73#define S3C2440_UCON_CLKMASK (3<<10)
74#define S3C2440_UCON_PCLK (0<<10)
75#define S3C2440_UCON_UCLK (1<<10)
76#define S3C2440_UCON_PCLK2 (2<<10)
77#define S3C2440_UCON_FCLK (3<<10)
78#define S3C2443_UCON_EPLL (3<<10)
79
80#define S3C2440_UCON2_FCLK_EN (1<<15)
81#define S3C2440_UCON0_DIVMASK (15 << 12)
82#define S3C2440_UCON1_DIVMASK (15 << 12)
83#define S3C2440_UCON2_DIVMASK (7 << 12)
84#define S3C2440_UCON_DIVSHIFT (12)
85
86#define S3C2412_UCON_CLKMASK (3<<10)
87#define S3C2412_UCON_UCLK (1<<10)
88#define S3C2412_UCON_USYSCLK (3<<10)
89#define S3C2412_UCON_PCLK (0<<10)
90#define S3C2412_UCON_PCLK2 (2<<10)
91
92#define S3C2410_UCON_UCLK (1<<10)
93#define S3C2410_UCON_SBREAK (1<<4)
94
95#define S3C2410_UCON_TXILEVEL (1<<9)
96#define S3C2410_UCON_RXILEVEL (1<<8)
97#define S3C2410_UCON_TXIRQMODE (1<<2)
98#define S3C2410_UCON_RXIRQMODE (1<<0)
99#define S3C2410_UCON_RXFIFO_TOI (1<<7)
100#define S3C2443_UCON_RXERR_IRQEN (1<<6)
101#define S3C2443_UCON_LOOPBACK (1<<5)
102
103#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
104 S3C2410_UCON_RXILEVEL | \
105 S3C2410_UCON_TXIRQMODE | \
106 S3C2410_UCON_RXIRQMODE | \
107 S3C2410_UCON_RXFIFO_TOI)
108
109#define S3C2410_UFCON_FIFOMODE (1<<0)
110#define S3C2410_UFCON_TXTRIG0 (0<<6)
111#define S3C2410_UFCON_RXTRIG8 (1<<4)
112#define S3C2410_UFCON_RXTRIG12 (2<<4)
113
114/* S3C2440 FIFO trigger levels */
115#define S3C2440_UFCON_RXTRIG1 (0<<4)
116#define S3C2440_UFCON_RXTRIG8 (1<<4)
117#define S3C2440_UFCON_RXTRIG16 (2<<4)
118#define S3C2440_UFCON_RXTRIG32 (3<<4)
119
120#define S3C2440_UFCON_TXTRIG0 (0<<6)
121#define S3C2440_UFCON_TXTRIG16 (1<<6)
122#define S3C2440_UFCON_TXTRIG32 (2<<6)
123#define S3C2440_UFCON_TXTRIG48 (3<<6)
124
125#define S3C2410_UFCON_RESETBOTH (3<<1)
126#define S3C2410_UFCON_RESETTX (1<<2)
127#define S3C2410_UFCON_RESETRX (1<<1)
128
129#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
130 S3C2410_UFCON_TXTRIG0 | \
131 S3C2410_UFCON_RXTRIG8 )
132
133#define S3C2410_UMCOM_AFC (1<<4)
134#define S3C2410_UMCOM_RTS_LOW (1<<0)
135
136#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
137#define S3C2412_UMCON_AFC_56 (1<<5)
138#define S3C2412_UMCON_AFC_48 (2<<5)
139#define S3C2412_UMCON_AFC_40 (3<<5)
140#define S3C2412_UMCON_AFC_32 (4<<5)
141#define S3C2412_UMCON_AFC_24 (5<<5)
142#define S3C2412_UMCON_AFC_16 (6<<5)
143#define S3C2412_UMCON_AFC_8 (7<<5)
144
145#define S3C2410_UFSTAT_TXFULL (1<<9)
146#define S3C2410_UFSTAT_RXFULL (1<<8)
147#define S3C2410_UFSTAT_TXMASK (15<<4)
148#define S3C2410_UFSTAT_TXSHIFT (4)
149#define S3C2410_UFSTAT_RXMASK (15<<0)
150#define S3C2410_UFSTAT_RXSHIFT (0)
151
152/* UFSTAT S3C2443 same as S3C2440 */
153#define S3C2440_UFSTAT_TXFULL (1<<14)
154#define S3C2440_UFSTAT_RXFULL (1<<6)
155#define S3C2440_UFSTAT_TXSHIFT (8)
156#define S3C2440_UFSTAT_RXSHIFT (0)
157#define S3C2440_UFSTAT_TXMASK (63<<8)
158#define S3C2440_UFSTAT_RXMASK (63)
159
160#define S3C2410_UTRSTAT_TXE (1<<2)
161#define S3C2410_UTRSTAT_TXFE (1<<1)
162#define S3C2410_UTRSTAT_RXDR (1<<0)
163
164#define S3C2410_UERSTAT_OVERRUN (1<<0)
165#define S3C2410_UERSTAT_FRAME (1<<2)
166#define S3C2410_UERSTAT_BREAK (1<<3)
167#define S3C2443_UERSTAT_PARITY (1<<1)
168
169#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
170 S3C2410_UERSTAT_FRAME | \
171 S3C2410_UERSTAT_BREAK)
172
173#define S3C2410_UMSTAT_CTS (1<<0)
174#define S3C2410_UMSTAT_DeltaCTS (1<<2)
175
176#define S3C2443_DIVSLOT (0x2C)
177
178#ifndef __ASSEMBLY__
179
180/* struct s3c24xx_uart_clksrc
181 *
182 * this structure defines a named clock source that can be used for the
183 * uart, so that the best clock can be selected for the requested baud
184 * rate.
185 *
186 * min_baud and max_baud define the range of baud-rates this clock is
187 * acceptable for, if they are both zero, it is assumed any baud rate that
188 * can be generated from this clock will be used.
189 *
190 * divisor gives the divisor from the clock to the one seen by the uart
191*/
192
193struct s3c24xx_uart_clksrc {
194 const char *name;
195 unsigned int divisor;
196 unsigned int min_baud;
197 unsigned int max_baud;
198};
199
200/* configuration structure for per-machine configurations for the
201 * serial port
202 *
203 * the pointer is setup by the machine specific initialisation from the
204 * arch/arm/mach-s3c2410/ directory.
205*/
206
207struct s3c2410_uartcfg {
208 unsigned char hwport; /* hardware port number */
209 unsigned char unused;
210 unsigned short flags;
211 upf_t uart_flags; /* default uart flags */
212
213 unsigned long ucon; /* value of ucon for port */
214 unsigned long ulcon; /* value of ulcon for port */
215 unsigned long ufcon; /* value of ufcon for port */
216
217 struct s3c24xx_uart_clksrc *clocks;
218 unsigned int clocks_size;
219};
220
221/* s3c24xx_uart_devs
222 *
223 * this is exported from the core as we cannot use driver_register(),
224 * or platform_add_device() before the console_initcall()
225*/
226
227extern struct platform_device *s3c24xx_uart_devs[3];
228
229#endif /* __ASSEMBLY__ */
230
231#endif /* __ASM_ARM_REGS_SERIAL_H */
232
diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/arch-s3c2410/regs-timer.h
deleted file mode 100644
index 6f8fe432fe3a..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-timer.h
+++ /dev/null
@@ -1,106 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-timer.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Timer configuration
11*/
12
13
14#ifndef __ASM_ARCH_REGS_TIMER_H
15#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
16
17#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
18#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
19
20#define S3C2410_TCFG0 S3C2410_TIMERREG(0x00)
21#define S3C2410_TCFG1 S3C2410_TIMERREG(0x04)
22#define S3C2410_TCON S3C2410_TIMERREG(0x08)
23
24#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
25#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
26#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
27#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
28#define S3C2410_TCFG_DEADZONE_SHIFT (16)
29
30#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
31#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
32#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
33#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
34#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
35#define S3C2410_TCFG1_MUX4_MASK (15<<16)
36#define S3C2410_TCFG1_MUX4_SHIFT (16)
37
38#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
39#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
40#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
41#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
42#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
43#define S3C2410_TCFG1_MUX3_MASK (15<<12)
44
45
46#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
47#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
48#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
49#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
50#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
51#define S3C2410_TCFG1_MUX2_MASK (15<<8)
52
53
54#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
55#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
56#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
57#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
58#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
59#define S3C2410_TCFG1_MUX1_MASK (15<<4)
60
61#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
62#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
63#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
64#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
65#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
66#define S3C2410_TCFG1_MUX0_MASK (15<<0)
67
68/* for each timer, we have an count buffer, an compare buffer and
69 * an observation buffer
70*/
71
72/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
73
74#define S3C2410_TCNTB(tmr) S3C2410_TIMERREG2(tmr, 0x00)
75#define S3C2410_TCMPB(tmr) S3C2410_TIMERREG2(tmr, 0x04)
76#define S3C2410_TCNTO(tmr) S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
77
78#define S3C2410_TCON_T4RELOAD (1<<22)
79#define S3C2410_TCON_T4MANUALUPD (1<<21)
80#define S3C2410_TCON_T4START (1<<20)
81
82#define S3C2410_TCON_T3RELOAD (1<<19)
83#define S3C2410_TCON_T3INVERT (1<<18)
84#define S3C2410_TCON_T3MANUALUPD (1<<17)
85#define S3C2410_TCON_T3START (1<<16)
86
87#define S3C2410_TCON_T2RELOAD (1<<15)
88#define S3C2410_TCON_T2INVERT (1<<14)
89#define S3C2410_TCON_T2MANUALUPD (1<<13)
90#define S3C2410_TCON_T2START (1<<12)
91
92#define S3C2410_TCON_T1RELOAD (1<<11)
93#define S3C2410_TCON_T1INVERT (1<<10)
94#define S3C2410_TCON_T1MANUALUPD (1<<9)
95#define S3C2410_TCON_T1START (1<<8)
96
97#define S3C2410_TCON_T0DEADZONE (1<<4)
98#define S3C2410_TCON_T0RELOAD (1<<3)
99#define S3C2410_TCON_T0INVERT (1<<2)
100#define S3C2410_TCON_T0MANUALUPD (1<<1)
101#define S3C2410_TCON_T0START (1<<0)
102
103#endif /* __ASM_ARCH_REGS_TIMER_H */
104
105
106
diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/arch-s3c2410/regs-watchdog.h
deleted file mode 100644
index a9c5d491bdb6..000000000000
--- a/include/asm-arm/arch-s3c2410/regs-watchdog.h
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/include/asm-arm/arch-s3c2410/regs-watchdog.h
2 *
3 * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
4 * http://www.simtec.co.uk/products/SWLINUX/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * S3C2410 Watchdog timer control
11*/
12
13
14#ifndef __ASM_ARCH_REGS_WATCHDOG_H
15#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
16
17#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
18
19#define S3C2410_WTCON S3C2410_WDOGREG(0x00)
20#define S3C2410_WTDAT S3C2410_WDOGREG(0x04)
21#define S3C2410_WTCNT S3C2410_WDOGREG(0x08)
22
23/* the watchdog can either generate a reset pulse, or an
24 * interrupt.
25 */
26
27#define S3C2410_WTCON_RSTEN (0x01)
28#define S3C2410_WTCON_INTEN (1<<2)
29#define S3C2410_WTCON_ENABLE (1<<5)
30
31#define S3C2410_WTCON_DIV16 (0<<3)
32#define S3C2410_WTCON_DIV32 (1<<3)
33#define S3C2410_WTCON_DIV64 (2<<3)
34#define S3C2410_WTCON_DIV128 (3<<3)
35
36#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
37#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
38
39#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
40
41
diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 1c74ef17da33..63891786dfa0 100644
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -17,7 +17,7 @@
17#include <asm/arch/idle.h> 17#include <asm/arch/idle.h>
18#include <asm/arch/reset.h> 18#include <asm/arch/reset.h>
19 19
20#include <asm/arch/regs-watchdog.h> 20#include <asm/plat-s3c/regs-watchdog.h>
21#include <asm/arch/regs-clock.h> 21#include <asm/arch/regs-clock.h>
22 22
23void (*s3c24xx_idle)(void); 23void (*s3c24xx_idle)(void);
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index dcb2cef38f50..295c89c8ff2c 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -16,9 +16,9 @@
16typedef unsigned int upf_t; /* cannot include linux/serial_core.h */ 16typedef unsigned int upf_t; /* cannot include linux/serial_core.h */
17 17
18/* defines for UART registers */ 18/* defines for UART registers */
19#include "asm/arch/regs-serial.h" 19#include "asm/plat-s3c/regs-serial.h"
20#include "asm/arch/regs-gpio.h" 20#include "asm/arch/regs-gpio.h"
21#include "asm/arch/regs-watchdog.h" 21#include "asm/plat-s3c/regs-watchdog.h"
22 22
23#include <asm/arch/map.h> 23#include <asm/arch/map.h>
24 24
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