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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-s3c2410/vr1000-map.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-arm/arch-s3c2410/vr1000-map.h')
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1 files changed, 116 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/vr1000-map.h b/include/asm-arm/arch-s3c2410/vr1000-map.h
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1/* linux/include/asm-arm/arch-s3c2410/vr1000-map.h
2 *
3 * (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Changelog:
13 * 06-Jan-2003 BJD Linux 2.6.0 version, split specifics from arch/map.h
14 * 12-Mar-2004 BJD Fixed header include protection
15 * 19-Mar-2004 BJD Copied to VR1000 machine headers.
16 * 19-Jan-2005 BJD Updated map definitions
17*/
18
19/* needs arch/map.h including with this */
20
21/* ok, we've used up to 0x13000000, now we need to find space for the
22 * peripherals that live in the nGCS[x] areas, which are quite numerous
23 * in their space. We also have the board's CPLD to find register space
24 * for.
25 */
26
27#ifndef __ASM_ARCH_VR1000MAP_H
28#define __ASM_ARCH_VR1000MAP_H
29
30#include <asm/arch/bast-map.h>
31
32#define VR1000_IOADDR(x) BAST_IOADDR(x)
33
34/* we put the CPLD registers next, to get them out of the way */
35
36#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
37#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
38
39#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
40#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
41
42#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
43#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
44
45#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
46#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
47
48/* next, we have the PC104 ISA interrupt registers */
49
50#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
51#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
52
53#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
54#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
55
56#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
57#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
58
59/* 0xE0000000 contains the IO space that is split by speed and
60 * wether the access is for 8 or 16bit IO... this ensures that
61 * the correct access is made
62 *
63 * 0x10000000 of space, partitioned as so:
64 *
65 * 0x00000000 to 0x04000000 8bit, slow
66 * 0x04000000 to 0x08000000 16bit, slow
67 * 0x08000000 to 0x0C000000 16bit, net
68 * 0x0C000000 to 0x10000000 16bit, fast
69 *
70 * each of these spaces has the following in:
71 *
72 * 0x02000000 to 0x02100000 1MB IDE primary channel
73 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
74 * 0x02200000 to 0x02400000 1MB IDE secondary channel
75 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
76 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
77 * 0x02600000 to 0x02700000 1MB
78 *
79 * the phyiscal layout of the zones are:
80 * nGCS2 - 8bit, slow
81 * nGCS3 - 16bit, slow
82 * nGCS4 - 16bit, net
83 * nGCS5 - 16bit, fast
84 */
85
86#define VR1000_VA_MULTISPACE (0xE0000000)
87
88#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
89#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
90#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
91#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
92#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
93#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
94#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
95#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
96#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
97
98/* physical offset addresses for the peripherals */
99
100#define VR1000_PA_IDEPRI (0x02000000)
101#define VR1000_PA_IDEPRIAUX (0x02800000)
102#define VR1000_PA_IDESEC (0x03000000)
103#define VR1000_PA_IDESECAUX (0x03800000)
104#define VR1000_PA_DM9000 (0x05000000)
105
106#define VR1000_PA_SERIAL (0x11800000)
107#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
108
109/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
110#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
111
112/* some configurations for the peripherals */
113
114#define VR1000_DM9000_CS VR1000_VAM_CS4
115
116#endif /* __ASM_ARCH_VR1000MAP_H */