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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2006-06-24 17:21:49 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-06-24 17:21:49 -0400
commite11c910b5bcc1dbc38a5af7a24be2812fc956b27 (patch)
tree38fb4c1b23bf2085cd0b05db9c85e3b91819130f /include/asm-arm/arch-s3c2410/regs-serial.h
parentc1e08adc86f886ba0ad7c8f29c240d6e833e7ec7 (diff)
parentc9b949a734adef5d05cbaa0b0546b924ca517155 (diff)
Merge S3C24xx branch
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-serial.h')
-rw-r--r--include/asm-arm/arch-s3c2410/regs-serial.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
index 83b01254c4ac..93f651ae2967 100644
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ b/include/asm-arm/arch-s3c2410/regs-serial.h
@@ -82,6 +82,12 @@
82#define S3C2440_UCON2_DIVMASK (7 << 12) 82#define S3C2440_UCON2_DIVMASK (7 << 12)
83#define S3C2440_UCON_DIVSHIFT (12) 83#define S3C2440_UCON_DIVSHIFT (12)
84 84
85#define S3C2412_UCON_CLKMASK (3<<10)
86#define S3C2412_UCON_UCLK (1<<10)
87#define S3C2412_UCON_USYSCLK (3<<10)
88#define S3C2412_UCON_PCLK (0<<10)
89#define S3C2412_UCON_PCLK2 (2<<10)
90
85#define S3C2410_UCON_UCLK (1<<10) 91#define S3C2410_UCON_UCLK (1<<10)
86#define S3C2410_UCON_SBREAK (1<<4) 92#define S3C2410_UCON_SBREAK (1<<4)
87 93
@@ -124,6 +130,15 @@
124#define S3C2410_UMCOM_AFC (1<<4) 130#define S3C2410_UMCOM_AFC (1<<4)
125#define S3C2410_UMCOM_RTS_LOW (1<<0) 131#define S3C2410_UMCOM_RTS_LOW (1<<0)
126 132
133#define S3C2412_UMCON_AFC_63 (0<<5)
134#define S3C2412_UMCON_AFC_56 (1<<5)
135#define S3C2412_UMCON_AFC_48 (2<<5)
136#define S3C2412_UMCON_AFC_40 (3<<5)
137#define S3C2412_UMCON_AFC_32 (4<<5)
138#define S3C2412_UMCON_AFC_24 (5<<5)
139#define S3C2412_UMCON_AFC_16 (6<<5)
140#define S3C2412_UMCON_AFC_8 (7<<5)
141
127#define S3C2410_UFSTAT_TXFULL (1<<9) 142#define S3C2410_UFSTAT_TXFULL (1<<9)
128#define S3C2410_UFSTAT_RXFULL (1<<8) 143#define S3C2410_UFSTAT_RXFULL (1<<8)
129#define S3C2410_UFSTAT_TXMASK (15<<4) 144#define S3C2410_UFSTAT_TXMASK (15<<4)