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author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-24 20:48:14 -0400 |
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committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-24 20:48:14 -0400 |
commit | dfd8317d3340f03bc06eba6b58f0ec0861da4a13 (patch) | |
tree | 43bd5c93ad045355687c26beb0983fcf6ca18a6b /include/asm-arm/arch-s3c2410/regs-serial.h | |
parent | 83626b01275d0228516b4d97da008328fc37c934 (diff) | |
parent | c0897856553d45aee1780bed455b7c2e888dd64b (diff) |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (25 commits)
[ARM] 3648/1: Update struct ucontext layout for coprocessor registers
[ARM] Add identifying number for non-rt sigframe
[ARM] Gather common sigframe saving code into setup_sigframe()
[ARM] Gather common sigframe restoration code into restore_sigframe()
[ARM] Re-use sigframe within rt_sigframe
[ARM] Merge sigcontext and sigmask members of sigframe
[ARM] Replace extramask with a full copy of the sigmask
[ARM] Remove rt_sigframe puc and pinfo pointers
[ARM] 3647/1: S3C24XX: add Osiris to the list of simtec pm machines
[ARM] 3645/1: S3C2412: irq support for external interrupts
[ARM] 3643/1: S3C2410: Add new usb clocks
[ARM] 3642/1: S3C24XX: Add machine SMDK2413
[ARM] 3641/1: S3C2412: Fixup gpio register naming
[ARM] 3640/1: S3C2412: Use S3C24XX_DCLKCON instead of S3C2410_DCLKCON
[ARM] 3639/1: S3C2412: serial port support
[ARM] 3638/1: S3C2412: core clocks
[ARM] 3637/1: S3C24XX: Add mpll clock, and set as fclk parent
[ARM] 3636/1: S3C2412: Add selection of CPU_ARM926
[ARM] 3635/1: S3C24XX: Add S3C2412 core cpu support
[ARM] 3633/1: S3C24XX: s3c2410 gpio bugfix - wrong pin nos
...
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-serial.h')
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-serial.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h index 83b01254c4ac..93f651ae2967 100644 --- a/include/asm-arm/arch-s3c2410/regs-serial.h +++ b/include/asm-arm/arch-s3c2410/regs-serial.h | |||
@@ -82,6 +82,12 @@ | |||
82 | #define S3C2440_UCON2_DIVMASK (7 << 12) | 82 | #define S3C2440_UCON2_DIVMASK (7 << 12) |
83 | #define S3C2440_UCON_DIVSHIFT (12) | 83 | #define S3C2440_UCON_DIVSHIFT (12) |
84 | 84 | ||
85 | #define S3C2412_UCON_CLKMASK (3<<10) | ||
86 | #define S3C2412_UCON_UCLK (1<<10) | ||
87 | #define S3C2412_UCON_USYSCLK (3<<10) | ||
88 | #define S3C2412_UCON_PCLK (0<<10) | ||
89 | #define S3C2412_UCON_PCLK2 (2<<10) | ||
90 | |||
85 | #define S3C2410_UCON_UCLK (1<<10) | 91 | #define S3C2410_UCON_UCLK (1<<10) |
86 | #define S3C2410_UCON_SBREAK (1<<4) | 92 | #define S3C2410_UCON_SBREAK (1<<4) |
87 | 93 | ||
@@ -124,6 +130,15 @@ | |||
124 | #define S3C2410_UMCOM_AFC (1<<4) | 130 | #define S3C2410_UMCOM_AFC (1<<4) |
125 | #define S3C2410_UMCOM_RTS_LOW (1<<0) | 131 | #define S3C2410_UMCOM_RTS_LOW (1<<0) |
126 | 132 | ||
133 | #define S3C2412_UMCON_AFC_63 (0<<5) | ||
134 | #define S3C2412_UMCON_AFC_56 (1<<5) | ||
135 | #define S3C2412_UMCON_AFC_48 (2<<5) | ||
136 | #define S3C2412_UMCON_AFC_40 (3<<5) | ||
137 | #define S3C2412_UMCON_AFC_32 (4<<5) | ||
138 | #define S3C2412_UMCON_AFC_24 (5<<5) | ||
139 | #define S3C2412_UMCON_AFC_16 (6<<5) | ||
140 | #define S3C2412_UMCON_AFC_8 (7<<5) | ||
141 | |||
127 | #define S3C2410_UFSTAT_TXFULL (1<<9) | 142 | #define S3C2410_UFSTAT_TXFULL (1<<9) |
128 | #define S3C2410_UFSTAT_RXFULL (1<<8) | 143 | #define S3C2410_UFSTAT_RXFULL (1<<8) |
129 | #define S3C2410_UFSTAT_TXMASK (15<<4) | 144 | #define S3C2410_UFSTAT_TXMASK (15<<4) |