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authorDmitry Torokhov <dtor@insightbb.com>2007-02-10 01:26:32 -0500
committerDmitry Torokhov <dtor@insightbb.com>2007-02-10 01:26:32 -0500
commitb22364c8eec89e6b0c081a237f3b6348df87796f (patch)
tree233a923281fb640106465d076997ff511efb6edf /include/asm-arm/arch-s3c2410/regs-mem.h
parent2c8dc071517ec2843869024dc82be2e246f41064 (diff)
parent66efc5a7e3061c3597ac43a8bb1026488d57e66b (diff)
Merge rsync://rsync.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-mem.h')
-rw-r--r--include/asm-arm/arch-s3c2410/regs-mem.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index 375dca50364e..e4d82341f7ba 100644
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -133,10 +133,10 @@
133#define S3C2410_BANKCON_SDRAM (0x3 << 15) 133#define S3C2410_BANKCON_SDRAM (0x3 << 15)
134 134
135/* next bits only for EDO DRAM in 6,7 */ 135/* next bits only for EDO DRAM in 6,7 */
136#define S3C2400_BANKCON_EDO_Trdc1 (0x00 << 4) 136#define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4)
137#define S3C2400_BANKCON_EDO_Trdc2 (0x01 << 4) 137#define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4)
138#define S3C2400_BANKCON_EDO_Trdc3 (0x02 << 4) 138#define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4)
139#define S3C2400_BANKCON_EDO_Trdc4 (0x03 << 4) 139#define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4)
140 140
141/* CAS pulse width */ 141/* CAS pulse width */
142#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3) 142#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3)
@@ -153,9 +153,9 @@
153#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0) 153#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0)
154 154
155/* next bits only for SDRAM in 6,7 */ 155/* next bits only for SDRAM in 6,7 */
156#define S3C2410_BANKCON_Trdc2 (0x00 << 2) 156#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
157#define S3C2410_BANKCON_Trdc3 (0x01 << 2) 157#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
158#define S3C2410_BANKCON_Trdc4 (0x02 << 2) 158#define S3C2410_BANKCON_Trcd4 (0x02 << 2)
159 159
160/* control column address select */ 160/* control column address select */
161#define S3C2410_BANKCON_SCANb8 (0x00 << 0) 161#define S3C2410_BANKCON_SCANb8 (0x00 << 0)