Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits)
  [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms
  [ARM] 3855/1: Add generic time support
  [ARM] 3873/1: S3C24XX: Add irq_chip names
  [ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips
  [ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23
  [ARM] nommu: confirms the CR_V bit in nommu mode
  [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
  [ARM] 3870/1: AT91: Start removing static memory mappings
  [ARM] 3869/1: AT91: NAND support for DK and KB9202 boards
  [ARM] 3868/1: AT91 hardware header update
  [ARM] 3867/1: AT91 GPIO update
  [ARM] 3866/1: AT91 clock update
  [ARM] 3865/1: AT91RM9200 header updates
  [ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series
  [ARM] kthread: switch arch/arm/kernel/apm.c
  [ARM] Off-by-one in arch/arm/common/icst*
  [ARM] 3864/1: Refactore sharpsl_pm
  [ARM] 3863/1: Add Locomo SPI Device
  [ARM] 3847/2:  Convert LOMOMO to use struct device for GPIOs
  [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h
  ...

1 files changed, 30 insertions, 0 deletions

diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index b306d6e3135d..6d7881c8cfc8 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -63,6 +63,8 @@
 #define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
 #define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >>  0) & 0xFF)
 
+/* LDCCON4 changes for STN mode on the S3C2412 */
+
 #define S3C2410_LCDCON4_MVAL(x)     ((x) << 8)
 #define S3C2410_LCDCON4_HSPW(x)     ((x) << 0)
 #define S3C2410_LCDCON4_WLH(x)      ((x) << 0)
@@ -113,10 +115,38 @@
 #define S3C2410_LCDINT_FRSYNC   (1<<1)
 #define S3C2410_LCDINT_FICNT    (1<<0)
 
+/* s3c2442 extra stn registers */
+
+#define S3C2442_REDLUT          S3C2410_LCDREG(0x20)
+#define S3C2442_GREENLUT        S3C2410_LCDREG(0x24)
+#define S3C2442_BLUELUT         S3C2410_LCDREG(0x28)
+#define S3C2442_DITHMODE        S3C2410_LCDREG(0x20)
+
 #define S3C2410_LPCSEL     S3C2410_LCDREG(0x60)
 
 #define S3C2410_TFTPAL(x)  S3C2410_LCDREG((0x400 + (x)*4))
 
+/* S3C2412 registers */
+
+#define S3C2412_TPAL            S3C2410_LCDREG(0x20)
+
+#define S3C2412_LCDINTPND       S3C2410_LCDREG(0x24)
+#define S3C2412_LCDSRCPND       S3C2410_LCDREG(0x28)
+#define S3C2412_LCDINTMSK       S3C2410_LCDREG(0x2C)
+
+#define S3C2412_TCONSEL         S3C2410_LCDREG(0x30)
+
+#define S3C2412_LCDCON6         S3C2410_LCDREG(0x34)
+#define S3C2412_LCDCON7         S3C2410_LCDREG(0x38)
+#define S3C2412_LCDCON8         S3C2410_LCDREG(0x3C)
+#define S3C2412_LCDCON9         S3C2410_LCDREG(0x40)
+
+#define S3C2412_REDLUT(x)       S3C2410_LCDREG(0x44 + ((x)*4))
+#define S3C2412_GREENLUT(x)     S3C2410_LCDREG(0x60 + ((x)*4))
+#define S3C2412_BLUELUT(x)      S3C2410_LCDREG(0x98 + ((x)*4))
+
+#define S3C2412_FRCPAT(x)       S3C2410_LCDREG(0xB4 + ((x)*4))
+
 #endif /* ___ASM_ARCH_REGS_LCD_H */