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authorBen Dooks <ben-linux@fluff.org>2006-09-15 19:12:53 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2006-09-25 05:25:23 -0400
commit34148c6990d2f0107b53fe4ddf29b1ba30e613d3 (patch)
tree235cdd81392bc8c78bf9bd3de31d287f420ff494 /include/asm-arm/arch-s3c2410/regs-lcd.h
parent3e9fc8e5de0fb00226325cf34eb08411eb72ec6d (diff)
[ARM] 3805/1: S3C2412: LCD register update
Add LCD register definitions for the S3C2412. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-lcd.h')
-rw-r--r--include/asm-arm/arch-s3c2410/regs-lcd.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-lcd.h b/include/asm-arm/arch-s3c2410/regs-lcd.h
index d8f1adfd17f0..6d7881c8cfc8 100644
--- a/include/asm-arm/arch-s3c2410/regs-lcd.h
+++ b/include/asm-arm/arch-s3c2410/regs-lcd.h
@@ -63,6 +63,8 @@
63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F) 63#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF) 64#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
65 65
66/* LDCCON4 changes for STN mode on the S3C2412 */
67
66#define S3C2410_LCDCON4_MVAL(x) ((x) << 8) 68#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
67#define S3C2410_LCDCON4_HSPW(x) ((x) << 0) 69#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
68#define S3C2410_LCDCON4_WLH(x) ((x) << 0) 70#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
@@ -124,6 +126,27 @@
124 126
125#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4)) 127#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
126 128
129/* S3C2412 registers */
130
131#define S3C2412_TPAL S3C2410_LCDREG(0x20)
132
133#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
134#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
135#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
136
137#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
138
139#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
140#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
141#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
142#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
143
144#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
145#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
146#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
147
148#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
149
127#endif /* ___ASM_ARCH_REGS_LCD_H */ 150#endif /* ___ASM_ARCH_REGS_LCD_H */
128 151
129 152