diff options
author | Ben Dooks <ben-linux@fluff.org> | 2006-06-18 18:06:41 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-18 18:06:41 -0400 |
commit | 96ce2385dd2817da549910001a69ac0a2762a1b9 (patch) | |
tree | 18ec36e9e1e8a6b7c19aacb53c256fdb941c4ecd /include/asm-arm/arch-s3c2410/regs-gpio.h | |
parent | 66a9b49a370baac75d90b7da9a2445997a8a9438 (diff) |
[ARM] 3559/1: S3C2442: core and serial port
Patch from Ben Dooks
Core support for the Samsung S3C2442, and the
serial port driver update to allow the serial
port blocks to be used.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-gpio.h')
-rw-r--r-- | include/asm-arm/arch-s3c2410/regs-gpio.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index d2574084697f..5f10334f06bf 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h | |||
@@ -450,12 +450,14 @@ | |||
450 | #define S3C2410_GPD0_OUTP (0x01 << 0) | 450 | #define S3C2410_GPD0_OUTP (0x01 << 0) |
451 | #define S3C2410_GPD0_VD8 (0x02 << 0) | 451 | #define S3C2410_GPD0_VD8 (0x02 << 0) |
452 | #define S3C2400_GPD0_VFRAME (0x02 << 0) | 452 | #define S3C2400_GPD0_VFRAME (0x02 << 0) |
453 | #define S3C2442_GPD0_nSPICS1 (0x03 << 0) | ||
453 | 454 | ||
454 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) | 455 | #define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) |
455 | #define S3C2410_GPD1_INP (0x00 << 2) | 456 | #define S3C2410_GPD1_INP (0x00 << 2) |
456 | #define S3C2410_GPD1_OUTP (0x01 << 2) | 457 | #define S3C2410_GPD1_OUTP (0x01 << 2) |
457 | #define S3C2410_GPD1_VD9 (0x02 << 2) | 458 | #define S3C2410_GPD1_VD9 (0x02 << 2) |
458 | #define S3C2400_GPD1_VM (0x02 << 2) | 459 | #define S3C2400_GPD1_VM (0x02 << 2) |
460 | #define S3C2442_GPD1_SPICLK1 (0x03 << 2) | ||
459 | 461 | ||
460 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) | 462 | #define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) |
461 | #define S3C2410_GPD2_INP (0x00 << 4) | 463 | #define S3C2410_GPD2_INP (0x00 << 4) |
@@ -858,6 +860,7 @@ | |||
858 | #define S3C2410_GPG12_OUTP (0x01 << 24) | 860 | #define S3C2410_GPG12_OUTP (0x01 << 24) |
859 | #define S3C2410_GPG12_EINT20 (0x02 << 24) | 861 | #define S3C2410_GPG12_EINT20 (0x02 << 24) |
860 | #define S3C2410_GPG12_XMON (0x03 << 24) | 862 | #define S3C2410_GPG12_XMON (0x03 << 24) |
863 | #define S3C2442_GPG12_nSPICS0 (0x03 << 24) | ||
861 | 864 | ||
862 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) | 865 | #define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) |
863 | #define S3C2410_GPG13_INP (0x00 << 26) | 866 | #define S3C2410_GPG13_INP (0x00 << 26) |
@@ -943,6 +946,7 @@ | |||
943 | #define S3C2410_GPH9_INP (0x00 << 18) | 946 | #define S3C2410_GPH9_INP (0x00 << 18) |
944 | #define S3C2410_GPH9_OUTP (0x01 << 18) | 947 | #define S3C2410_GPH9_OUTP (0x01 << 18) |
945 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) | 948 | #define S3C2410_GPH9_CLKOUT0 (0x02 << 18) |
949 | #define S3C2442_GPH9_nSPICS0 (0x03 << 18) | ||
946 | 950 | ||
947 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) | 951 | #define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) |
948 | #define S3C2410_GPH10_INP (0x00 << 20) | 952 | #define S3C2410_GPH10_INP (0x00 << 20) |
@@ -1051,6 +1055,7 @@ | |||
1051 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) | 1055 | #define S3C2410_GSTATUS1_IDMASK (0xffff0000) |
1052 | #define S3C2410_GSTATUS1_2410 (0x32410000) | 1056 | #define S3C2410_GSTATUS1_2410 (0x32410000) |
1053 | #define S3C2410_GSTATUS1_2440 (0x32440000) | 1057 | #define S3C2410_GSTATUS1_2440 (0x32440000) |
1058 | #define S3C2410_GSTATUS1_2442 (0x32440aaa) | ||
1054 | 1059 | ||
1055 | #define S3C2410_GSTATUS2_WTRESET (1<<2) | 1060 | #define S3C2410_GSTATUS2_WTRESET (1<<2) |
1056 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) | 1061 | #define S3C2410_GSTATUS2_OFFRESET (1<<1) |