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authorLucas Correia Villa Real <lucasvr@gobolinux.org>2005-11-28 13:08:43 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-11-28 13:08:43 -0500
commit192cdc5809f676841d16d58e1f249176e38d7dda (patch)
tree1a265ef371dbce6556577e6c43b3d50e899fa834 /include/asm-arm/arch-s3c2410/regs-gpio.h
parent79a558ffba25ecefe21a5203077971a08dda598b (diff)
[ARM] 3178/1: S3C2400 - adds GPIO registers definitions to regs-gpio.h
Patch from Lucas Correia Villa Real This patch adds definitions to GPIO registers for the S3C2400 into include/asm-arm/arch-s3c2410/regs-gpio.h. Signed-off-by: Lucas Correia Villa Real <lucasvr@gobolinux.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-s3c2410/regs-gpio.h')
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h239
1 files changed, 227 insertions, 12 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index cb33d57c146c..7f1be48ad67e 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -21,6 +21,7 @@
21 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA 21 * 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
22 * 28-Mar-2005 LCVR Fixed definition of GPB10 22 * 28-Mar-2005 LCVR Fixed definition of GPB10
23 * 26-Oct-2005 BJD Added generic configuration types 23 * 26-Oct-2005 BJD Added generic configuration types
24 * 27-Nov-2005 LCVR Added definitions to S3C2400 registers
24*/ 25*/
25 26
26 27
@@ -54,12 +55,16 @@
54 55
55#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO) 56#define S3C2410_GPIOREG(x) ((x) + S3C24XX_VA_GPIO)
56 57
57/* port A - 22bits, zero in bit X makes pin X output 58/* port A - S3C2410: 22bits, zero in bit X makes pin X output
59 * S3C2400: 18bits, zero in bit X makes pin X output
58 * 1 makes port special function, this is default 60 * 1 makes port special function, this is default
59*/ 61*/
60#define S3C2410_GPACON S3C2410_GPIOREG(0x00) 62#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
61#define S3C2410_GPADAT S3C2410_GPIOREG(0x04) 63#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
62 64
65#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
66#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
67
63#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0) 68#define S3C2410_GPA0 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 0)
64#define S3C2410_GPA0_OUT (0<<0) 69#define S3C2410_GPA0_OUT (0<<0)
65#define S3C2410_GPA0_ADDR0 (1<<0) 70#define S3C2410_GPA0_ADDR0 (1<<0)
@@ -103,34 +108,42 @@
103#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10) 108#define S3C2410_GPA10 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 10)
104#define S3C2410_GPA10_OUT (0<<10) 109#define S3C2410_GPA10_OUT (0<<10)
105#define S3C2410_GPA10_ADDR25 (1<<10) 110#define S3C2410_GPA10_ADDR25 (1<<10)
111#define S3C2400_GPA10_SCKE (1<<10)
106 112
107#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11) 113#define S3C2410_GPA11 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 11)
108#define S3C2410_GPA11_OUT (0<<11) 114#define S3C2410_GPA11_OUT (0<<11)
109#define S3C2410_GPA11_ADDR26 (1<<11) 115#define S3C2410_GPA11_ADDR26 (1<<11)
116#define S3C2400_GPA11_nCAS0 (1<<11)
110 117
111#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12) 118#define S3C2410_GPA12 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 12)
112#define S3C2410_GPA12_OUT (0<<12) 119#define S3C2410_GPA12_OUT (0<<12)
113#define S3C2410_GPA12_nGCS1 (1<<12) 120#define S3C2410_GPA12_nGCS1 (1<<12)
121#define S3C2400_GPA12_nCAS1 (1<<12)
114 122
115#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13) 123#define S3C2410_GPA13 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 13)
116#define S3C2410_GPA13_OUT (0<<13) 124#define S3C2410_GPA13_OUT (0<<13)
117#define S3C2410_GPA13_nGCS2 (1<<13) 125#define S3C2410_GPA13_nGCS2 (1<<13)
126#define S3C2400_GPA13_nGCS1 (1<<13)
118 127
119#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14) 128#define S3C2410_GPA14 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 14)
120#define S3C2410_GPA14_OUT (0<<14) 129#define S3C2410_GPA14_OUT (0<<14)
121#define S3C2410_GPA14_nGCS3 (1<<14) 130#define S3C2410_GPA14_nGCS3 (1<<14)
131#define S3C2400_GPA14_nGCS2 (1<<14)
122 132
123#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15) 133#define S3C2410_GPA15 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 15)
124#define S3C2410_GPA15_OUT (0<<15) 134#define S3C2410_GPA15_OUT (0<<15)
125#define S3C2410_GPA15_nGCS4 (1<<15) 135#define S3C2410_GPA15_nGCS4 (1<<15)
136#define S3C2400_GPA15_nGCS3 (1<<15)
126 137
127#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16) 138#define S3C2410_GPA16 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 16)
128#define S3C2410_GPA16_OUT (0<<16) 139#define S3C2410_GPA16_OUT (0<<16)
129#define S3C2410_GPA16_nGCS5 (1<<16) 140#define S3C2410_GPA16_nGCS5 (1<<16)
141#define S3C2400_GPA16_nGCS4 (1<<16)
130 142
131#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17) 143#define S3C2410_GPA17 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 17)
132#define S3C2410_GPA17_OUT (0<<17) 144#define S3C2410_GPA17_OUT (0<<17)
133#define S3C2410_GPA17_CLE (1<<17) 145#define S3C2410_GPA17_CLE (1<<17)
146#define S3C2400_GPA17_nGCS5 (1<<17)
134 147
135#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18) 148#define S3C2410_GPA18 S3C2410_GPIONO(S3C2410_GPIO_BANKA, 18)
136#define S3C2410_GPA18_OUT (0<<18) 149#define S3C2410_GPA18_OUT (0<<18)
@@ -152,10 +165,16 @@
152#define S3C2410_GPA22_OUT (0<<22) 165#define S3C2410_GPA22_OUT (0<<22)
153#define S3C2410_GPA22_nFCE (1<<22) 166#define S3C2410_GPA22_nFCE (1<<22)
154 167
155/* 0x08 and 0x0c are reserved */ 168/* 0x08 and 0x0c are reserved on S3C2410 */
156 169
157/* GPB is 10 IO pins, each configured by 2 bits each in GPBCON. 170/* S3C2410:
171 * GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
158 * 00 = input, 01 = output, 10=special function, 11=reserved 172 * 00 = input, 01 = output, 10=special function, 11=reserved
173
174 * S3C2400:
175 * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
176 * 00 = input, 01 = output, 10=data, 11=special function
177
159 * bit 0,1 = pin 0, 2,3= pin 1... 178 * bit 0,1 = pin 0, 2,3= pin 1...
160 * 179 *
161 * CPBUP = pull up resistor control, 1=disabled, 0=enabled 180 * CPBUP = pull up resistor control, 1=disabled, 0=enabled
@@ -165,63 +184,113 @@
165#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14) 184#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
166#define S3C2410_GPBUP S3C2410_GPIOREG(0x18) 185#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
167 186
187#define S3C2400_GPBCON S3C2410_GPIOREG(0x08)
188#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
189#define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
190
168/* no i/o pin in port b can have value 3! */ 191/* no i/o pin in port b can have value 3! */
169 192
170#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0) 193#define S3C2410_GPB0 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 0)
171#define S3C2410_GPB0_INP (0x00 << 0) 194#define S3C2410_GPB0_INP (0x00 << 0)
172#define S3C2410_GPB0_OUTP (0x01 << 0) 195#define S3C2410_GPB0_OUTP (0x01 << 0)
173#define S3C2410_GPB0_TOUT0 (0x02 << 0) 196#define S3C2410_GPB0_TOUT0 (0x02 << 0)
197#define S3C2400_GPB0_DATA16 (0x02 << 0)
174 198
175#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1) 199#define S3C2410_GPB1 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 1)
176#define S3C2410_GPB1_INP (0x00 << 2) 200#define S3C2410_GPB1_INP (0x00 << 2)
177#define S3C2410_GPB1_OUTP (0x01 << 2) 201#define S3C2410_GPB1_OUTP (0x01 << 2)
178#define S3C2410_GPB1_TOUT1 (0x02 << 2) 202#define S3C2410_GPB1_TOUT1 (0x02 << 2)
203#define S3C2400_GPB1_DATA17 (0x02 << 2)
179 204
180#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2) 205#define S3C2410_GPB2 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 2)
181#define S3C2410_GPB2_INP (0x00 << 4) 206#define S3C2410_GPB2_INP (0x00 << 4)
182#define S3C2410_GPB2_OUTP (0x01 << 4) 207#define S3C2410_GPB2_OUTP (0x01 << 4)
183#define S3C2410_GPB2_TOUT2 (0x02 << 4) 208#define S3C2410_GPB2_TOUT2 (0x02 << 4)
209#define S3C2400_GPB2_DATA18 (0x02 << 4)
210#define S3C2400_GPB2_TCLK1 (0x03 << 4)
184 211
185#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3) 212#define S3C2410_GPB3 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 3)
186#define S3C2410_GPB3_INP (0x00 << 6) 213#define S3C2410_GPB3_INP (0x00 << 6)
187#define S3C2410_GPB3_OUTP (0x01 << 6) 214#define S3C2410_GPB3_OUTP (0x01 << 6)
188#define S3C2410_GPB3_TOUT3 (0x02 << 6) 215#define S3C2410_GPB3_TOUT3 (0x02 << 6)
216#define S3C2400_GPB3_DATA19 (0x02 << 6)
217#define S3C2400_GPB3_TXD1 (0x03 << 6)
189 218
190#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4) 219#define S3C2410_GPB4 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 4)
191#define S3C2410_GPB4_INP (0x00 << 8) 220#define S3C2410_GPB4_INP (0x00 << 8)
192#define S3C2410_GPB4_OUTP (0x01 << 8) 221#define S3C2410_GPB4_OUTP (0x01 << 8)
193#define S3C2410_GPB4_TCLK0 (0x02 << 8) 222#define S3C2410_GPB4_TCLK0 (0x02 << 8)
223#define S3C2400_GPB4_DATA20 (0x02 << 8)
194#define S3C2410_GPB4_MASK (0x03 << 8) 224#define S3C2410_GPB4_MASK (0x03 << 8)
225#define S3C2400_GPB4_RXD1 (0x03 << 8)
226#define S3C2400_GPB4_MASK (0x03 << 8)
195 227
196#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5) 228#define S3C2410_GPB5 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 5)
197#define S3C2410_GPB5_INP (0x00 << 10) 229#define S3C2410_GPB5_INP (0x00 << 10)
198#define S3C2410_GPB5_OUTP (0x01 << 10) 230#define S3C2410_GPB5_OUTP (0x01 << 10)
199#define S3C2410_GPB5_nXBACK (0x02 << 10) 231#define S3C2410_GPB5_nXBACK (0x02 << 10)
232#define S3C2400_GPB5_DATA21 (0x02 << 10)
233#define S3C2400_GPB5_nCTS1 (0x03 << 10)
200 234
201#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6) 235#define S3C2410_GPB6 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 6)
202#define S3C2410_GPB6_INP (0x00 << 12) 236#define S3C2410_GPB6_INP (0x00 << 12)
203#define S3C2410_GPB6_OUTP (0x01 << 12) 237#define S3C2410_GPB6_OUTP (0x01 << 12)
204#define S3C2410_GPB6_nXBREQ (0x02 << 12) 238#define S3C2410_GPB6_nXBREQ (0x02 << 12)
239#define S3C2400_GPB6_DATA22 (0x02 << 12)
240#define S3C2400_GPB6_nRTS1 (0x03 << 12)
205 241
206#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7) 242#define S3C2410_GPB7 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 7)
207#define S3C2410_GPB7_INP (0x00 << 14) 243#define S3C2410_GPB7_INP (0x00 << 14)
208#define S3C2410_GPB7_OUTP (0x01 << 14) 244#define S3C2410_GPB7_OUTP (0x01 << 14)
209#define S3C2410_GPB7_nXDACK1 (0x02 << 14) 245#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
246#define S3C2400_GPB7_DATA23 (0x02 << 14)
210 247
211#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8) 248#define S3C2410_GPB8 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 8)
212#define S3C2410_GPB8_INP (0x00 << 16) 249#define S3C2410_GPB8_INP (0x00 << 16)
213#define S3C2410_GPB8_OUTP (0x01 << 16) 250#define S3C2410_GPB8_OUTP (0x01 << 16)
214#define S3C2410_GPB8_nXDREQ1 (0x02 << 16) 251#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
252#define S3C2400_GPB8_DATA24 (0x02 << 16)
215 253
216#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9) 254#define S3C2410_GPB9 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 9)
217#define S3C2410_GPB9_INP (0x00 << 18) 255#define S3C2410_GPB9_INP (0x00 << 18)
218#define S3C2410_GPB9_OUTP (0x01 << 18) 256#define S3C2410_GPB9_OUTP (0x01 << 18)
219#define S3C2410_GPB9_nXDACK0 (0x02 << 18) 257#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
258#define S3C2400_GPB9_DATA25 (0x02 << 18)
259#define S3C2400_GPB9_I2SSDI (0x03 << 18)
220 260
221#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10) 261#define S3C2410_GPB10 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 10)
222#define S3C2410_GPB10_INP (0x00 << 20) 262#define S3C2410_GPB10_INP (0x00 << 20)
223#define S3C2410_GPB10_OUTP (0x01 << 20) 263#define S3C2410_GPB10_OUTP (0x01 << 20)
224#define S3C2410_GPB10_nXDRE0 (0x02 << 20) 264#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
265#define S3C2400_GPB10_DATA26 (0x02 << 20)
266#define S3C2400_GPB10_nSS (0x03 << 20)
267
268#define S3C2400_GPB11 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 11)
269#define S3C2400_GPB11_INP (0x00 << 22)
270#define S3C2400_GPB11_OUTP (0x01 << 22)
271#define S3C2400_GPB11_DATA27 (0x02 << 22)
272
273#define S3C2400_GPB12 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 12)
274#define S3C2400_GPB12_INP (0x00 << 24)
275#define S3C2400_GPB12_OUTP (0x01 << 24)
276#define S3C2400_GPB12_DATA28 (0x02 << 24)
277
278#define S3C2400_GPB13 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 13)
279#define S3C2400_GPB13_INP (0x00 << 26)
280#define S3C2400_GPB13_OUTP (0x01 << 26)
281#define S3C2400_GPB13_DATA29 (0x02 << 26)
282
283#define S3C2400_GPB14 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 14)
284#define S3C2400_GPB14_INP (0x00 << 28)
285#define S3C2400_GPB14_OUTP (0x01 << 28)
286#define S3C2400_GPB14_DATA30 (0x02 << 28)
287
288#define S3C2400_GPB15 S3C2410_GPIONO(S3C2410_GPIO_BANKB, 15)
289#define S3C2400_GPB15_INP (0x00 << 30)
290#define S3C2400_GPB15_OUTP (0x01 << 30)
291#define S3C2400_GPB15_DATA31 (0x02 << 30)
292
293#define S3C2410_GPB_PUPDIS(x) (1<<(x))
225 294
226/* Port C consits of 16 GPIO/Special function 295/* Port C consits of 16 GPIO/Special function
227 * 296 *
@@ -233,150 +302,193 @@
233#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24) 302#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
234#define S3C2410_GPCUP S3C2410_GPIOREG(0x28) 303#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
235 304
305#define S3C2400_GPCCON S3C2410_GPIOREG(0x14)
306#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
307#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
308
236#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0) 309#define S3C2410_GPC0 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 0)
237#define S3C2410_GPC0_INP (0x00 << 0) 310#define S3C2410_GPC0_INP (0x00 << 0)
238#define S3C2410_GPC0_OUTP (0x01 << 0) 311#define S3C2410_GPC0_OUTP (0x01 << 0)
239#define S3C2410_GPC0_LEND (0x02 << 0) 312#define S3C2410_GPC0_LEND (0x02 << 0)
313#define S3C2400_GPC0_VD0 (0x02 << 0)
240 314
241#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1) 315#define S3C2410_GPC1 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 1)
242#define S3C2410_GPC1_INP (0x00 << 2) 316#define S3C2410_GPC1_INP (0x00 << 2)
243#define S3C2410_GPC1_OUTP (0x01 << 2) 317#define S3C2410_GPC1_OUTP (0x01 << 2)
244#define S3C2410_GPC1_VCLK (0x02 << 2) 318#define S3C2410_GPC1_VCLK (0x02 << 2)
319#define S3C2400_GPC1_VD1 (0x02 << 2)
245 320
246#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2) 321#define S3C2410_GPC2 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 2)
247#define S3C2410_GPC2_INP (0x00 << 4) 322#define S3C2410_GPC2_INP (0x00 << 4)
248#define S3C2410_GPC2_OUTP (0x01 << 4) 323#define S3C2410_GPC2_OUTP (0x01 << 4)
249#define S3C2410_GPC2_VLINE (0x02 << 4) 324#define S3C2410_GPC2_VLINE (0x02 << 4)
325#define S3C2400_GPC2_VD2 (0x02 << 4)
250 326
251#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3) 327#define S3C2410_GPC3 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 3)
252#define S3C2410_GPC3_INP (0x00 << 6) 328#define S3C2410_GPC3_INP (0x00 << 6)
253#define S3C2410_GPC3_OUTP (0x01 << 6) 329#define S3C2410_GPC3_OUTP (0x01 << 6)
254#define S3C2410_GPC3_VFRAME (0x02 << 6) 330#define S3C2410_GPC3_VFRAME (0x02 << 6)
331#define S3C2400_GPC3_VD3 (0x02 << 6)
255 332
256#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4) 333#define S3C2410_GPC4 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 4)
257#define S3C2410_GPC4_INP (0x00 << 8) 334#define S3C2410_GPC4_INP (0x00 << 8)
258#define S3C2410_GPC4_OUTP (0x01 << 8) 335#define S3C2410_GPC4_OUTP (0x01 << 8)
259#define S3C2410_GPC4_VM (0x02 << 8) 336#define S3C2410_GPC4_VM (0x02 << 8)
337#define S3C2400_GPC4_VD4 (0x02 << 8)
260 338
261#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5) 339#define S3C2410_GPC5 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 5)
262#define S3C2410_GPC5_INP (0x00 << 10) 340#define S3C2410_GPC5_INP (0x00 << 10)
263#define S3C2410_GPC5_OUTP (0x01 << 10) 341#define S3C2410_GPC5_OUTP (0x01 << 10)
264#define S3C2410_GPC5_LCDVF0 (0x02 << 10) 342#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
343#define S3C2400_GPC5_VD5 (0x02 << 10)
265 344
266#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6) 345#define S3C2410_GPC6 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 6)
267#define S3C2410_GPC6_INP (0x00 << 12) 346#define S3C2410_GPC6_INP (0x00 << 12)
268#define S3C2410_GPC6_OUTP (0x01 << 12) 347#define S3C2410_GPC6_OUTP (0x01 << 12)
269#define S3C2410_GPC6_LCDVF1 (0x02 << 12) 348#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
349#define S3C2400_GPC6_VD6 (0x02 << 12)
270 350
271#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7) 351#define S3C2410_GPC7 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 7)
272#define S3C2410_GPC7_INP (0x00 << 14) 352#define S3C2410_GPC7_INP (0x00 << 14)
273#define S3C2410_GPC7_OUTP (0x01 << 14) 353#define S3C2410_GPC7_OUTP (0x01 << 14)
274#define S3C2410_GPC7_LCDVF2 (0x02 << 14) 354#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
355#define S3C2400_GPC7_VD7 (0x02 << 14)
275 356
276#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8) 357#define S3C2410_GPC8 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 8)
277#define S3C2410_GPC8_INP (0x00 << 16) 358#define S3C2410_GPC8_INP (0x00 << 16)
278#define S3C2410_GPC8_OUTP (0x01 << 16) 359#define S3C2410_GPC8_OUTP (0x01 << 16)
279#define S3C2410_GPC8_VD0 (0x02 << 16) 360#define S3C2410_GPC8_VD0 (0x02 << 16)
361#define S3C2400_GPC8_VD8 (0x02 << 16)
280 362
281#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9) 363#define S3C2410_GPC9 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 9)
282#define S3C2410_GPC9_INP (0x00 << 18) 364#define S3C2410_GPC9_INP (0x00 << 18)
283#define S3C2410_GPC9_OUTP (0x01 << 18) 365#define S3C2410_GPC9_OUTP (0x01 << 18)
284#define S3C2410_GPC9_VD1 (0x02 << 18) 366#define S3C2410_GPC9_VD1 (0x02 << 18)
367#define S3C2400_GPC9_VD9 (0x02 << 18)
285 368
286#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10) 369#define S3C2410_GPC10 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 10)
287#define S3C2410_GPC10_INP (0x00 << 20) 370#define S3C2410_GPC10_INP (0x00 << 20)
288#define S3C2410_GPC10_OUTP (0x01 << 20) 371#define S3C2410_GPC10_OUTP (0x01 << 20)
289#define S3C2410_GPC10_VD2 (0x02 << 20) 372#define S3C2410_GPC10_VD2 (0x02 << 20)
373#define S3C2400_GPC10_VD10 (0x02 << 20)
290 374
291#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11) 375#define S3C2410_GPC11 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 11)
292#define S3C2410_GPC11_INP (0x00 << 22) 376#define S3C2410_GPC11_INP (0x00 << 22)
293#define S3C2410_GPC11_OUTP (0x01 << 22) 377#define S3C2410_GPC11_OUTP (0x01 << 22)
294#define S3C2410_GPC11_VD3 (0x02 << 22) 378#define S3C2410_GPC11_VD3 (0x02 << 22)
379#define S3C2400_GPC11_VD11 (0x02 << 22)
295 380
296#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12) 381#define S3C2410_GPC12 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 12)
297#define S3C2410_GPC12_INP (0x00 << 24) 382#define S3C2410_GPC12_INP (0x00 << 24)
298#define S3C2410_GPC12_OUTP (0x01 << 24) 383#define S3C2410_GPC12_OUTP (0x01 << 24)
299#define S3C2410_GPC12_VD4 (0x02 << 24) 384#define S3C2410_GPC12_VD4 (0x02 << 24)
385#define S3C2400_GPC12_VD12 (0x02 << 24)
300 386
301#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13) 387#define S3C2410_GPC13 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 13)
302#define S3C2410_GPC13_INP (0x00 << 26) 388#define S3C2410_GPC13_INP (0x00 << 26)
303#define S3C2410_GPC13_OUTP (0x01 << 26) 389#define S3C2410_GPC13_OUTP (0x01 << 26)
304#define S3C2410_GPC13_VD5 (0x02 << 26) 390#define S3C2410_GPC13_VD5 (0x02 << 26)
391#define S3C2400_GPC13_VD13 (0x02 << 26)
305 392
306#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14) 393#define S3C2410_GPC14 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 14)
307#define S3C2410_GPC14_INP (0x00 << 28) 394#define S3C2410_GPC14_INP (0x00 << 28)
308#define S3C2410_GPC14_OUTP (0x01 << 28) 395#define S3C2410_GPC14_OUTP (0x01 << 28)
309#define S3C2410_GPC14_VD6 (0x02 << 28) 396#define S3C2410_GPC14_VD6 (0x02 << 28)
397#define S3C2400_GPC14_VD14 (0x02 << 28)
310 398
311#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15) 399#define S3C2410_GPC15 S3C2410_GPIONO(S3C2410_GPIO_BANKC, 15)
312#define S3C2410_GPC15_INP (0x00 << 30) 400#define S3C2410_GPC15_INP (0x00 << 30)
313#define S3C2410_GPC15_OUTP (0x01 << 30) 401#define S3C2410_GPC15_OUTP (0x01 << 30)
314#define S3C2410_GPC15_VD7 (0x02 << 30) 402#define S3C2410_GPC15_VD7 (0x02 << 30)
403#define S3C2400_GPC15_VD15 (0x02 << 30)
404
405#define S3C2410_GPC_PUPDIS(x) (1<<(x))
315 406
316/* Port D consists of 16 GPIO/Special function 407/*
408 * S3C2410: Port D consists of 16 GPIO/Special function
317 * 409 *
318 * almost identical setup to port b, but the special functions are mostly 410 * almost identical setup to port b, but the special functions are mostly
319 * to do with the video system's data. 411 * to do with the video system's data.
412 *
413 * S3C2400: Port D consists of 11 GPIO/Special function
414 *
415 * almost identical setup to port c
320*/ 416*/
321 417
322#define S3C2410_GPDCON S3C2410_GPIOREG(0x30) 418#define S3C2410_GPDCON S3C2410_GPIOREG(0x30)
323#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34) 419#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
324#define S3C2410_GPDUP S3C2410_GPIOREG(0x38) 420#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
325 421
422#define S3C2400_GPDCON S3C2410_GPIOREG(0x20)
423#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
424#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
425
326#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0) 426#define S3C2410_GPD0 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 0)
327#define S3C2410_GPD0_INP (0x00 << 0) 427#define S3C2410_GPD0_INP (0x00 << 0)
328#define S3C2410_GPD0_OUTP (0x01 << 0) 428#define S3C2410_GPD0_OUTP (0x01 << 0)
329#define S3C2410_GPD0_VD8 (0x02 << 0) 429#define S3C2410_GPD0_VD8 (0x02 << 0)
430#define S3C2400_GPD0_VFRAME (0x02 << 0)
330 431
331#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) 432#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
332#define S3C2410_GPD1_INP (0x00 << 2) 433#define S3C2410_GPD1_INP (0x00 << 2)
333#define S3C2410_GPD1_OUTP (0x01 << 2) 434#define S3C2410_GPD1_OUTP (0x01 << 2)
334#define S3C2410_GPD1_VD9 (0x02 << 2) 435#define S3C2410_GPD1_VD9 (0x02 << 2)
436#define S3C2400_GPD1_VM (0x02 << 2)
335 437
336#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) 438#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
337#define S3C2410_GPD2_INP (0x00 << 4) 439#define S3C2410_GPD2_INP (0x00 << 4)
338#define S3C2410_GPD2_OUTP (0x01 << 4) 440#define S3C2410_GPD2_OUTP (0x01 << 4)
339#define S3C2410_GPD2_VD10 (0x02 << 4) 441#define S3C2410_GPD2_VD10 (0x02 << 4)
442#define S3C2400_GPD2_VLINE (0x02 << 4)
340 443
341#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3) 444#define S3C2410_GPD3 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 3)
342#define S3C2410_GPD3_INP (0x00 << 6) 445#define S3C2410_GPD3_INP (0x00 << 6)
343#define S3C2410_GPD3_OUTP (0x01 << 6) 446#define S3C2410_GPD3_OUTP (0x01 << 6)
344#define S3C2410_GPD3_VD11 (0x02 << 6) 447#define S3C2410_GPD3_VD11 (0x02 << 6)
448#define S3C2400_GPD3_VCLK (0x02 << 6)
345 449
346#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4) 450#define S3C2410_GPD4 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 4)
347#define S3C2410_GPD4_INP (0x00 << 8) 451#define S3C2410_GPD4_INP (0x00 << 8)
348#define S3C2410_GPD4_OUTP (0x01 << 8) 452#define S3C2410_GPD4_OUTP (0x01 << 8)
349#define S3C2410_GPD4_VD12 (0x02 << 8) 453#define S3C2410_GPD4_VD12 (0x02 << 8)
454#define S3C2400_GPD4_LEND (0x02 << 8)
350 455
351#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5) 456#define S3C2410_GPD5 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 5)
352#define S3C2410_GPD5_INP (0x00 << 10) 457#define S3C2410_GPD5_INP (0x00 << 10)
353#define S3C2410_GPD5_OUTP (0x01 << 10) 458#define S3C2410_GPD5_OUTP (0x01 << 10)
354#define S3C2410_GPD5_VD13 (0x02 << 10) 459#define S3C2410_GPD5_VD13 (0x02 << 10)
460#define S3C2400_GPD5_TOUT0 (0x02 << 10)
355 461
356#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6) 462#define S3C2410_GPD6 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 6)
357#define S3C2410_GPD6_INP (0x00 << 12) 463#define S3C2410_GPD6_INP (0x00 << 12)
358#define S3C2410_GPD6_OUTP (0x01 << 12) 464#define S3C2410_GPD6_OUTP (0x01 << 12)
359#define S3C2410_GPD6_VD14 (0x02 << 12) 465#define S3C2410_GPD6_VD14 (0x02 << 12)
466#define S3C2400_GPD6_TOUT1 (0x02 << 12)
360 467
361#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7) 468#define S3C2410_GPD7 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 7)
362#define S3C2410_GPD7_INP (0x00 << 14) 469#define S3C2410_GPD7_INP (0x00 << 14)
363#define S3C2410_GPD7_OUTP (0x01 << 14) 470#define S3C2410_GPD7_OUTP (0x01 << 14)
364#define S3C2410_GPD7_VD15 (0x02 << 14) 471#define S3C2410_GPD7_VD15 (0x02 << 14)
472#define S3C2400_GPD7_TOUT2 (0x02 << 14)
365 473
366#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8) 474#define S3C2410_GPD8 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 8)
367#define S3C2410_GPD8_INP (0x00 << 16) 475#define S3C2410_GPD8_INP (0x00 << 16)
368#define S3C2410_GPD8_OUTP (0x01 << 16) 476#define S3C2410_GPD8_OUTP (0x01 << 16)
369#define S3C2410_GPD8_VD16 (0x02 << 16) 477#define S3C2410_GPD8_VD16 (0x02 << 16)
478#define S3C2400_GPD8_TOUT3 (0x02 << 16)
370 479
371#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9) 480#define S3C2410_GPD9 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 9)
372#define S3C2410_GPD9_INP (0x00 << 18) 481#define S3C2410_GPD9_INP (0x00 << 18)
373#define S3C2410_GPD9_OUTP (0x01 << 18) 482#define S3C2410_GPD9_OUTP (0x01 << 18)
374#define S3C2410_GPD9_VD17 (0x02 << 18) 483#define S3C2410_GPD9_VD17 (0x02 << 18)
484#define S3C2400_GPD9_TCLK0 (0x02 << 18)
485#define S3C2410_GPD9_MASK (0x03 << 18)
375 486
376#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10) 487#define S3C2410_GPD10 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 10)
377#define S3C2410_GPD10_INP (0x00 << 20) 488#define S3C2410_GPD10_INP (0x00 << 20)
378#define S3C2410_GPD10_OUTP (0x01 << 20) 489#define S3C2410_GPD10_OUTP (0x01 << 20)
379#define S3C2410_GPD10_VD18 (0x02 << 20) 490#define S3C2410_GPD10_VD18 (0x02 << 20)
491#define S3C2400_GPD10_nWAIT (0x02 << 20)
380 492
381#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11) 493#define S3C2410_GPD11 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 11)
382#define S3C2410_GPD11_INP (0x00 << 22) 494#define S3C2410_GPD11_INP (0x00 << 22)
@@ -403,37 +515,56 @@
403#define S3C2410_GPD15_OUTP (0x01 << 30) 515#define S3C2410_GPD15_OUTP (0x01 << 30)
404#define S3C2410_GPD15_VD23 (0x02 << 30) 516#define S3C2410_GPD15_VD23 (0x02 << 30)
405 517
406/* Port E consists of 16 GPIO/Special function 518#define S3C2410_GPD_PUPDIS(x) (1<<(x))
519
520/* S3C2410:
521 * Port E consists of 16 GPIO/Special function
407 * 522 *
408 * again, the same as port B, but dealing with I2S, SDI, and 523 * again, the same as port B, but dealing with I2S, SDI, and
409 * more miscellaneous functions 524 * more miscellaneous functions
525 *
526 * S3C2400:
527 * Port E consists of 12 GPIO/Special function
528 *
529 * GPIO / interrupt inputs
410*/ 530*/
411 531
412#define S3C2410_GPECON S3C2410_GPIOREG(0x40) 532#define S3C2410_GPECON S3C2410_GPIOREG(0x40)
413#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44) 533#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
414#define S3C2410_GPEUP S3C2410_GPIOREG(0x48) 534#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
415 535
536#define S3C2400_GPECON S3C2410_GPIOREG(0x2C)
537#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
538#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
539
416#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0) 540#define S3C2410_GPE0 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 0)
417#define S3C2410_GPE0_INP (0x00 << 0) 541#define S3C2410_GPE0_INP (0x00 << 0)
418#define S3C2410_GPE0_OUTP (0x01 << 0) 542#define S3C2410_GPE0_OUTP (0x01 << 0)
419#define S3C2410_GPE0_I2SLRCK (0x02 << 0) 543#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
544#define S3C2400_GPE0_EINT0 (0x02 << 0)
420#define S3C2410_GPE0_MASK (0x03 << 0) 545#define S3C2410_GPE0_MASK (0x03 << 0)
421 546
422#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1) 547#define S3C2410_GPE1 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 1)
423#define S3C2410_GPE1_INP (0x00 << 2) 548#define S3C2410_GPE1_INP (0x00 << 2)
424#define S3C2410_GPE1_OUTP (0x01 << 2) 549#define S3C2410_GPE1_OUTP (0x01 << 2)
425#define S3C2410_GPE1_I2SSCLK (0x02 << 2) 550#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
551#define S3C2400_GPE1_EINT1 (0x02 << 2)
552#define S3C2400_GPE1_nSS (0x03 << 2)
426#define S3C2410_GPE1_MASK (0x03 << 2) 553#define S3C2410_GPE1_MASK (0x03 << 2)
427 554
428#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2) 555#define S3C2410_GPE2 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 2)
429#define S3C2410_GPE2_INP (0x00 << 4) 556#define S3C2410_GPE2_INP (0x00 << 4)
430#define S3C2410_GPE2_OUTP (0x01 << 4) 557#define S3C2410_GPE2_OUTP (0x01 << 4)
431#define S3C2410_GPE2_CDCLK (0x02 << 4) 558#define S3C2410_GPE2_CDCLK (0x02 << 4)
559#define S3C2400_GPE2_EINT2 (0x02 << 4)
560#define S3C2400_GPE2_I2SSDI (0x03 << 4)
432 561
433#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3) 562#define S3C2410_GPE3 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 3)
434#define S3C2410_GPE3_INP (0x00 << 6) 563#define S3C2410_GPE3_INP (0x00 << 6)
435#define S3C2410_GPE3_OUTP (0x01 << 6) 564#define S3C2410_GPE3_OUTP (0x01 << 6)
436#define S3C2410_GPE3_I2SSDI (0x02 << 6) 565#define S3C2410_GPE3_I2SSDI (0x02 << 6)
566#define S3C2400_GPE3_EINT3 (0x02 << 6)
567#define S3C2400_GPE3_nCTS1 (0x03 << 6)
437#define S3C2410_GPE3_nSS0 (0x03 << 6) 568#define S3C2410_GPE3_nSS0 (0x03 << 6)
438#define S3C2410_GPE3_MASK (0x03 << 6) 569#define S3C2410_GPE3_MASK (0x03 << 6)
439 570
@@ -441,6 +572,8 @@
441#define S3C2410_GPE4_INP (0x00 << 8) 572#define S3C2410_GPE4_INP (0x00 << 8)
442#define S3C2410_GPE4_OUTP (0x01 << 8) 573#define S3C2410_GPE4_OUTP (0x01 << 8)
443#define S3C2410_GPE4_I2SSDO (0x02 << 8) 574#define S3C2410_GPE4_I2SSDO (0x02 << 8)
575#define S3C2400_GPE4_EINT4 (0x02 << 8)
576#define S3C2400_GPE4_nRTS1 (0x03 << 8)
444#define S3C2410_GPE4_I2SSDI (0x03 << 8) 577#define S3C2410_GPE4_I2SSDI (0x03 << 8)
445#define S3C2410_GPE4_MASK (0x03 << 8) 578#define S3C2410_GPE4_MASK (0x03 << 8)
446 579
@@ -448,36 +581,46 @@
448#define S3C2410_GPE5_INP (0x00 << 10) 581#define S3C2410_GPE5_INP (0x00 << 10)
449#define S3C2410_GPE5_OUTP (0x01 << 10) 582#define S3C2410_GPE5_OUTP (0x01 << 10)
450#define S3C2410_GPE5_SDCLK (0x02 << 10) 583#define S3C2410_GPE5_SDCLK (0x02 << 10)
584#define S3C2400_GPE5_EINT5 (0x02 << 10)
585#define S3C2400_GPE5_TCLK1 (0x03 << 10)
451 586
452#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6) 587#define S3C2410_GPE6 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 6)
453#define S3C2410_GPE6_INP (0x00 << 12) 588#define S3C2410_GPE6_INP (0x00 << 12)
454#define S3C2410_GPE6_OUTP (0x01 << 12) 589#define S3C2410_GPE6_OUTP (0x01 << 12)
455#define S3C2410_GPE6_SDCMD (0x02 << 12) 590#define S3C2410_GPE6_SDCMD (0x02 << 12)
591#define S3C2400_GPE6_EINT6 (0x02 << 12)
456 592
457#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7) 593#define S3C2410_GPE7 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 7)
458#define S3C2410_GPE7_INP (0x00 << 14) 594#define S3C2410_GPE7_INP (0x00 << 14)
459#define S3C2410_GPE7_OUTP (0x01 << 14) 595#define S3C2410_GPE7_OUTP (0x01 << 14)
460#define S3C2410_GPE7_SDDAT0 (0x02 << 14) 596#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
597#define S3C2400_GPE7_EINT7 (0x02 << 14)
461 598
462#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8) 599#define S3C2410_GPE8 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 8)
463#define S3C2410_GPE8_INP (0x00 << 16) 600#define S3C2410_GPE8_INP (0x00 << 16)
464#define S3C2410_GPE8_OUTP (0x01 << 16) 601#define S3C2410_GPE8_OUTP (0x01 << 16)
465#define S3C2410_GPE8_SDDAT1 (0x02 << 16) 602#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
603#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
466 604
467#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9) 605#define S3C2410_GPE9 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 9)
468#define S3C2410_GPE9_INP (0x00 << 18) 606#define S3C2410_GPE9_INP (0x00 << 18)
469#define S3C2410_GPE9_OUTP (0x01 << 18) 607#define S3C2410_GPE9_OUTP (0x01 << 18)
470#define S3C2410_GPE9_SDDAT2 (0x02 << 18) 608#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
609#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
610#define S3C2400_GPE9_nXBACK (0x03 << 18)
471 611
472#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10) 612#define S3C2410_GPE10 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 10)
473#define S3C2410_GPE10_INP (0x00 << 20) 613#define S3C2410_GPE10_INP (0x00 << 20)
474#define S3C2410_GPE10_OUTP (0x01 << 20) 614#define S3C2410_GPE10_OUTP (0x01 << 20)
475#define S3C2410_GPE10_SDDAT3 (0x02 << 20) 615#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
616#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
476 617
477#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11) 618#define S3C2410_GPE11 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 11)
478#define S3C2410_GPE11_INP (0x00 << 22) 619#define S3C2410_GPE11_INP (0x00 << 22)
479#define S3C2410_GPE11_OUTP (0x01 << 22) 620#define S3C2410_GPE11_OUTP (0x01 << 22)
480#define S3C2410_GPE11_SPIMISO0 (0x02 << 22) 621#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
622#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
623#define S3C2400_GPE11_nXBREQ (0x03 << 22)
481 624
482#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12) 625#define S3C2410_GPE12 S3C2410_GPIONO(S3C2410_GPIO_BANKE, 12)
483#define S3C2410_GPE12_INP (0x00 << 24) 626#define S3C2410_GPE12_INP (0x00 << 24)
@@ -509,7 +652,8 @@
509 652
510#define S3C2410_GPE_PUPDIS(x) (1<<(x)) 653#define S3C2410_GPE_PUPDIS(x) (1<<(x))
511 654
512/* Port F consists of 8 GPIO/Special function 655/* S3C2410:
656 * Port F consists of 8 GPIO/Special function
513 * 657 *
514 * GPIO / interrupt inputs 658 * GPIO / interrupt inputs
515 * 659 *
@@ -517,100 +661,141 @@
517 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined 661 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 undefined
518 * 662 *
519 * pull up works like all other ports. 663 * pull up works like all other ports.
664 *
665 * S3C2400:
666 * Port F consists of 7 GPIO/Special function
667 *
668 * GPIO/serial/misc pins
520*/ 669*/
521 670
522#define S3C2410_GPFCON S3C2410_GPIOREG(0x50) 671#define S3C2410_GPFCON S3C2410_GPIOREG(0x50)
523#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54) 672#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
524#define S3C2410_GPFUP S3C2410_GPIOREG(0x58) 673#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
525 674
675#define S3C2400_GPFCON S3C2410_GPIOREG(0x38)
676#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
677#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
678
526#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0) 679#define S3C2410_GPF0 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 0)
527#define S3C2410_GPF0_INP (0x00 << 0) 680#define S3C2410_GPF0_INP (0x00 << 0)
528#define S3C2410_GPF0_OUTP (0x01 << 0) 681#define S3C2410_GPF0_OUTP (0x01 << 0)
529#define S3C2410_GPF0_EINT0 (0x02 << 0) 682#define S3C2410_GPF0_EINT0 (0x02 << 0)
683#define S3C2400_GPF0_RXD0 (0x02 << 0)
530 684
531#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1) 685#define S3C2410_GPF1 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 1)
532#define S3C2410_GPF1_INP (0x00 << 2) 686#define S3C2410_GPF1_INP (0x00 << 2)
533#define S3C2410_GPF1_OUTP (0x01 << 2) 687#define S3C2410_GPF1_OUTP (0x01 << 2)
534#define S3C2410_GPF1_EINT1 (0x02 << 2) 688#define S3C2410_GPF1_EINT1 (0x02 << 2)
689#define S3C2400_GPF1_RXD1 (0x02 << 2)
690#define S3C2400_GPF1_IICSDA (0x03 << 2)
535 691
536#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2) 692#define S3C2410_GPF2 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 2)
537#define S3C2410_GPF2_INP (0x00 << 4) 693#define S3C2410_GPF2_INP (0x00 << 4)
538#define S3C2410_GPF2_OUTP (0x01 << 4) 694#define S3C2410_GPF2_OUTP (0x01 << 4)
539#define S3C2410_GPF2_EINT2 (0x02 << 4) 695#define S3C2410_GPF2_EINT2 (0x02 << 4)
696#define S3C2400_GPF2_TXD0 (0x02 << 4)
540 697
541#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3) 698#define S3C2410_GPF3 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 3)
542#define S3C2410_GPF3_INP (0x00 << 6) 699#define S3C2410_GPF3_INP (0x00 << 6)
543#define S3C2410_GPF3_OUTP (0x01 << 6) 700#define S3C2410_GPF3_OUTP (0x01 << 6)
544#define S3C2410_GPF3_EINT3 (0x02 << 6) 701#define S3C2410_GPF3_EINT3 (0x02 << 6)
702#define S3C2400_GPF3_TXD1 (0x02 << 6)
703#define S3C2400_GPF3_IICSCL (0x03 << 6)
545 704
546#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4) 705#define S3C2410_GPF4 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 4)
547#define S3C2410_GPF4_INP (0x00 << 8) 706#define S3C2410_GPF4_INP (0x00 << 8)
548#define S3C2410_GPF4_OUTP (0x01 << 8) 707#define S3C2410_GPF4_OUTP (0x01 << 8)
549#define S3C2410_GPF4_EINT4 (0x02 << 8) 708#define S3C2410_GPF4_EINT4 (0x02 << 8)
709#define S3C2400_GPF4_nRTS0 (0x02 << 8)
710#define S3C2400_GPF4_nXBACK (0x03 << 8)
550 711
551#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5) 712#define S3C2410_GPF5 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 5)
552#define S3C2410_GPF5_INP (0x00 << 10) 713#define S3C2410_GPF5_INP (0x00 << 10)
553#define S3C2410_GPF5_OUTP (0x01 << 10) 714#define S3C2410_GPF5_OUTP (0x01 << 10)
554#define S3C2410_GPF5_EINT5 (0x02 << 10) 715#define S3C2410_GPF5_EINT5 (0x02 << 10)
716#define S3C2400_GPF5_nCTS0 (0x02 << 10)
717#define S3C2400_GPF5_nXBREQ (0x03 << 10)
555 718
556#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6) 719#define S3C2410_GPF6 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 6)
557#define S3C2410_GPF6_INP (0x00 << 12) 720#define S3C2410_GPF6_INP (0x00 << 12)
558#define S3C2410_GPF6_OUTP (0x01 << 12) 721#define S3C2410_GPF6_OUTP (0x01 << 12)
559#define S3C2410_GPF6_EINT6 (0x02 << 12) 722#define S3C2410_GPF6_EINT6 (0x02 << 12)
723#define S3C2400_GPF6_CLKOUT (0x02 << 12)
560 724
561#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7) 725#define S3C2410_GPF7 S3C2410_GPIONO(S3C2410_GPIO_BANKF, 7)
562#define S3C2410_GPF7_INP (0x00 << 14) 726#define S3C2410_GPF7_INP (0x00 << 14)
563#define S3C2410_GPF7_OUTP (0x01 << 14) 727#define S3C2410_GPF7_OUTP (0x01 << 14)
564#define S3C2410_GPF7_EINT7 (0x02 << 14) 728#define S3C2410_GPF7_EINT7 (0x02 << 14)
565 729
566/* Port G consists of 8 GPIO/IRQ/Special function 730#define S3C2410_GPF_PUPDIS(x) (1<<(x))
731
732/* S3C2410:
733 * Port G consists of 8 GPIO/IRQ/Special function
567 * 734 *
568 * GPGCON has 2 bits for each of the input pins on port F 735 * GPGCON has 2 bits for each of the input pins on port F
569 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func 736 * 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
570 * 737 *
571 * pull up works like all other ports. 738 * pull up works like all other ports.
739 *
740 * S3C2400:
741 * Port G consists of 10 GPIO/Special function
572*/ 742*/
573 743
574#define S3C2410_GPGCON S3C2410_GPIOREG(0x60) 744#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
575#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64) 745#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
576#define S3C2410_GPGUP S3C2410_GPIOREG(0x68) 746#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
577 747
748#define S3C2400_GPGCON S3C2410_GPIOREG(0x44)
749#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
750#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
751
578#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0) 752#define S3C2410_GPG0 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 0)
579#define S3C2410_GPG0_INP (0x00 << 0) 753#define S3C2410_GPG0_INP (0x00 << 0)
580#define S3C2410_GPG0_OUTP (0x01 << 0) 754#define S3C2410_GPG0_OUTP (0x01 << 0)
581#define S3C2410_GPG0_EINT8 (0x02 << 0) 755#define S3C2410_GPG0_EINT8 (0x02 << 0)
756#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
582 757
583#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1) 758#define S3C2410_GPG1 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 1)
584#define S3C2410_GPG1_INP (0x00 << 2) 759#define S3C2410_GPG1_INP (0x00 << 2)
585#define S3C2410_GPG1_OUTP (0x01 << 2) 760#define S3C2410_GPG1_OUTP (0x01 << 2)
586#define S3C2410_GPG1_EINT9 (0x02 << 2) 761#define S3C2410_GPG1_EINT9 (0x02 << 2)
762#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
587 763
588#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2) 764#define S3C2410_GPG2 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 2)
589#define S3C2410_GPG2_INP (0x00 << 4) 765#define S3C2410_GPG2_INP (0x00 << 4)
590#define S3C2410_GPG2_OUTP (0x01 << 4) 766#define S3C2410_GPG2_OUTP (0x01 << 4)
591#define S3C2410_GPG2_EINT10 (0x02 << 4) 767#define S3C2410_GPG2_EINT10 (0x02 << 4)
768#define S3C2400_GPG2_CDCLK (0x02 << 4)
592 769
593#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3) 770#define S3C2410_GPG3 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 3)
594#define S3C2410_GPG3_INP (0x00 << 6) 771#define S3C2410_GPG3_INP (0x00 << 6)
595#define S3C2410_GPG3_OUTP (0x01 << 6) 772#define S3C2410_GPG3_OUTP (0x01 << 6)
596#define S3C2410_GPG3_EINT11 (0x02 << 6) 773#define S3C2410_GPG3_EINT11 (0x02 << 6)
774#define S3C2400_GPG3_I2SSDO (0x02 << 6)
775#define S3C2400_GPG3_I2SSDI (0x03 << 6)
597 776
598#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4) 777#define S3C2410_GPG4 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 4)
599#define S3C2410_GPG4_INP (0x00 << 8) 778#define S3C2410_GPG4_INP (0x00 << 8)
600#define S3C2410_GPG4_OUTP (0x01 << 8) 779#define S3C2410_GPG4_OUTP (0x01 << 8)
601#define S3C2410_GPG4_EINT12 (0x02 << 8) 780#define S3C2410_GPG4_EINT12 (0x02 << 8)
781#define S3C2400_GPG4_MMCCLK (0x02 << 8)
782#define S3C2400_GPG4_I2SSDI (0x03 << 8)
602#define S3C2410_GPG4_LCDPWREN (0x03 << 8) 783#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
603 784
604#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5) 785#define S3C2410_GPG5 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 5)
605#define S3C2410_GPG5_INP (0x00 << 10) 786#define S3C2410_GPG5_INP (0x00 << 10)
606#define S3C2410_GPG5_OUTP (0x01 << 10) 787#define S3C2410_GPG5_OUTP (0x01 << 10)
607#define S3C2410_GPG5_EINT13 (0x02 << 10) 788#define S3C2410_GPG5_EINT13 (0x02 << 10)
789#define S3C2400_GPG5_MMCCMD (0x02 << 10)
790#define S3C2400_GPG5_IICSDA (0x03 << 10)
608#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) 791#define S3C2410_GPG5_SPIMISO1 (0x03 << 10)
609 792
610#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6) 793#define S3C2410_GPG6 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 6)
611#define S3C2410_GPG6_INP (0x00 << 12) 794#define S3C2410_GPG6_INP (0x00 << 12)
612#define S3C2410_GPG6_OUTP (0x01 << 12) 795#define S3C2410_GPG6_OUTP (0x01 << 12)
613#define S3C2410_GPG6_EINT14 (0x02 << 12) 796#define S3C2410_GPG6_EINT14 (0x02 << 12)
797#define S3C2400_GPG6_MMCDAT (0x02 << 12)
798#define S3C2400_GPG6_IICSCL (0x03 << 12)
614#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12) 799#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
615 800
616#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7) 801#define S3C2410_GPG7 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 7)
@@ -618,16 +803,22 @@
618#define S3C2410_GPG7_OUTP (0x01 << 14) 803#define S3C2410_GPG7_OUTP (0x01 << 14)
619#define S3C2410_GPG7_EINT15 (0x02 << 14) 804#define S3C2410_GPG7_EINT15 (0x02 << 14)
620#define S3C2410_GPG7_SPICLK1 (0x03 << 14) 805#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
806#define S3C2400_GPG7_SPIMISO (0x02 << 14)
807#define S3C2400_GPG7_IICSDA (0x03 << 14)
621 808
622#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8) 809#define S3C2410_GPG8 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 8)
623#define S3C2410_GPG8_INP (0x00 << 16) 810#define S3C2410_GPG8_INP (0x00 << 16)
624#define S3C2410_GPG8_OUTP (0x01 << 16) 811#define S3C2410_GPG8_OUTP (0x01 << 16)
625#define S3C2410_GPG8_EINT16 (0x02 << 16) 812#define S3C2410_GPG8_EINT16 (0x02 << 16)
813#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
814#define S3C2400_GPG8_IICSCL (0x03 << 16)
626 815
627#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9) 816#define S3C2410_GPG9 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 9)
628#define S3C2410_GPG9_INP (0x00 << 18) 817#define S3C2410_GPG9_INP (0x00 << 18)
629#define S3C2410_GPG9_OUTP (0x01 << 18) 818#define S3C2410_GPG9_OUTP (0x01 << 18)
630#define S3C2410_GPG9_EINT17 (0x02 << 18) 819#define S3C2410_GPG9_EINT17 (0x02 << 18)
820#define S3C2400_GPG9_SPICLK (0x02 << 18)
821#define S3C2400_GPG9_MMCCLK (0x03 << 18)
631 822
632#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10) 823#define S3C2410_GPG10 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 10)
633#define S3C2410_GPG10_INP (0x00 << 20) 824#define S3C2410_GPG10_INP (0x00 << 20)
@@ -737,19 +928,27 @@
737#define S3C2410_GPH10_CLKOUT1 (0x02 << 20) 928#define S3C2410_GPH10_CLKOUT1 (0x02 << 20)
738 929
739/* miscellaneous control */ 930/* miscellaneous control */
740 931#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
741#define S3C2410_MISCCR S3C2410_GPIOREG(0x80) 932#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
742#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84) 933#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
743 934
744/* see clock.h for dclk definitions */ 935/* see clock.h for dclk definitions */
745 936
746/* pullup control on databus */ 937/* pullup control on databus */
747#define S3C2410_MISCCR_SPUCR_HEN (0) 938#define S3C2410_MISCCR_SPUCR_HEN (0<<0)
748#define S3C2410_MISCCR_SPUCR_HDIS (1<<0) 939#define S3C2410_MISCCR_SPUCR_HDIS (1<<0)
749#define S3C2410_MISCCR_SPUCR_LEN (0) 940#define S3C2410_MISCCR_SPUCR_LEN (0<<1)
750#define S3C2410_MISCCR_SPUCR_LDIS (1<<1) 941#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
751 942
752#define S3C2410_MISCCR_USBDEV (0) 943#define S3C2400_MISCCR_SPUCR_LEN (0<<0)
944#define S3C2400_MISCCR_SPUCR_LDIS (1<<0)
945#define S3C2400_MISCCR_SPUCR_HEN (0<<1)
946#define S3C2400_MISCCR_SPUCR_HDIS (1<<1)
947
948#define S3C2400_MISCCR_HZ_STOPEN (0<<2)
949#define S3C2400_MISCCR_HZ_STOPPREV (1<<2)
950
951#define S3C2410_MISCCR_USBDEV (0<<3)
753#define S3C2410_MISCCR_USBHOST (1<<3) 952#define S3C2410_MISCCR_USBHOST (1<<3)
754 953
755#define S3C2410_MISCCR_CLK0_MPLL (0<<4) 954#define S3C2410_MISCCR_CLK0_MPLL (0<<4)
@@ -785,7 +984,7 @@
785 * 984 *
786 * Samsung datasheet p9-25 985 * Samsung datasheet p9-25
787*/ 986*/
788 987#define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58)
789#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88) 988#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
790#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C) 989#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
791#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90) 990#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
@@ -833,5 +1032,21 @@
833#define S3C2410_GSTATUS2_OFFRESET (1<<1) 1032#define S3C2410_GSTATUS2_OFFRESET (1<<1)
834#define S3C2410_GSTATUS2_PONRESET (1<<0) 1033#define S3C2410_GSTATUS2_PONRESET (1<<0)
835 1034
1035/* open drain control register */
1036#define S3C2400_OPENCR S3C2410_GPIOREG(0x50)
1037
1038#define S3C2400_OPENCR_OPC_RXD1DIS (0<<0)
1039#define S3C2400_OPENCR_OPC_RXD1EN (1<<0)
1040#define S3C2400_OPENCR_OPC_TXD1DIS (0<<1)
1041#define S3C2400_OPENCR_OPC_TXD1EN (1<<1)
1042#define S3C2400_OPENCR_OPC_CMDDIS (0<<2)
1043#define S3C2400_OPENCR_OPC_CMDEN (1<<2)
1044#define S3C2400_OPENCR_OPC_DATDIS (0<<3)
1045#define S3C2400_OPENCR_OPC_DATEN (1<<3)
1046#define S3C2400_OPENCR_OPC_MISODIS (0<<4)
1047#define S3C2400_OPENCR_OPC_MISOEN (1<<4)
1048#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
1049#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
1050
836#endif /* __ASM_ARCH_REGS_GPIO_H */ 1051#endif /* __ASM_ARCH_REGS_GPIO_H */
837 1052