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authorLinus Torvalds <torvalds@g5.osdl.org>2006-09-28 17:40:39 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-09-28 17:40:39 -0400
commitebdea46fecae40c4d7effcd33f40918a37a1df4b (patch)
treee4312bf7f1f3d184738963a0ec300aa9fdfd55c1 /include/asm-arm/arch-s3c2410/osiris-map.h
parentfecf3404f4aba6d0edeba31eeb018cbb6326dff2 (diff)
parent250d375d1da45a5e08ab8baf5eaa7eb258afd82b (diff)
Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits) [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms [ARM] 3855/1: Add generic time support [ARM] 3873/1: S3C24XX: Add irq_chip names [ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips [ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23 [ARM] nommu: confirms the CR_V bit in nommu mode [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores. [ARM] 3870/1: AT91: Start removing static memory mappings [ARM] 3869/1: AT91: NAND support for DK and KB9202 boards [ARM] 3868/1: AT91 hardware header update [ARM] 3867/1: AT91 GPIO update [ARM] 3866/1: AT91 clock update [ARM] 3865/1: AT91RM9200 header updates [ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series [ARM] kthread: switch arch/arm/kernel/apm.c [ARM] Off-by-one in arch/arm/common/icst* [ARM] 3864/1: Refactore sharpsl_pm [ARM] 3863/1: Add Locomo SPI Device [ARM] 3847/2: Convert LOMOMO to use struct device for GPIOs [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h ...
Diffstat (limited to 'include/asm-arm/arch-s3c2410/osiris-map.h')
-rw-r--r--include/asm-arm/arch-s3c2410/osiris-map.h18
1 files changed, 9 insertions, 9 deletions
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h
index e2d406218ae5..a14164dfa525 100644
--- a/include/asm-arm/arch-s3c2410/osiris-map.h
+++ b/include/asm-arm/arch-s3c2410/osiris-map.h
@@ -18,22 +18,22 @@
18 18
19/* start peripherals off after the S3C2410 */ 19/* start peripherals off after the S3C2410 */
20 20
21#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x05000000)) 21#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000))
22 22
23#define OSIRIS_PA_CPLD (S3C2410_CS1 | (3<<25)) 23#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26))
24 24
25/* we put the CPLD registers next, to get them out of the way */ 25/* we put the CPLD registers next, to get them out of the way */
26 26
27#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) /* 0x01300000 */ 27#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000)
28#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD) 28#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD)
29 29
30#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) /* 0x01400000 */ 30#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000)
31#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<24)) 31#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<23))
32 32
33#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) /* 0x01500000 */ 33#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000)
34#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<24)) 34#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23))
35 35
36#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) /* 0x01600000 */ 36#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000)
37#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<24)) 37#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<23))
38 38
39#endif /* __ASM_ARCH_OSIRISMAP_H */ 39#endif /* __ASM_ARCH_OSIRISMAP_H */