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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /include/asm-arm/arch-s3c2410/irqs.h
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'include/asm-arm/arch-s3c2410/irqs.h')
-rw-r--r--include/asm-arm/arch-s3c2410/irqs.h126
1 files changed, 126 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h
new file mode 100644
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+++ b/include/asm-arm/arch-s3c2410/irqs.h
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1/* linux/include/asm-arm/arch-s3c2410/irqs.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Changelog:
11 * 12-May-2003 BJD Created file
12 * 08-Jan-2003 BJD Linux 2.6.0 version, moved BAST bits out
13 * 12-Mar-2004 BJD Fixed bug in header protection
14 * 10-Feb-2005 BJD Added camera IRQ from guillaume.gourat@nexvision.tv
15 * 28-Feb-2005 BJD Updated s3c2440 IRQs
16 */
17
18
19#ifndef __ASM_ARCH_IRQS_H
20#define __ASM_ARCH_IRQS_H __FILE__
21
22
23/* we keep the first set of CPU IRQs out of the range of
24 * the ISA space, so that the PC104 has them to itself
25 * and we don't end up having to do horrible things to the
26 * standard ISA drivers....
27 */
28
29#define S3C2410_CPUIRQ_OFFSET (16)
30
31#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
32
33/* main cpu interrupts */
34#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
35#define IRQ_EINT1 S3C2410_IRQ(1)
36#define IRQ_EINT2 S3C2410_IRQ(2)
37#define IRQ_EINT3 S3C2410_IRQ(3)
38#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
39#define IRQ_EINT8t23 S3C2410_IRQ(5)
40#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
41#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440 */
42#define IRQ_BATT_FLT S3C2410_IRQ(7)
43#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
44#define IRQ_WDT S3C2410_IRQ(9)
45#define IRQ_TIMER0 S3C2410_IRQ(10)
46#define IRQ_TIMER1 S3C2410_IRQ(11)
47#define IRQ_TIMER2 S3C2410_IRQ(12)
48#define IRQ_TIMER3 S3C2410_IRQ(13)
49#define IRQ_TIMER4 S3C2410_IRQ(14)
50#define IRQ_UART2 S3C2410_IRQ(15)
51#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
52#define IRQ_DMA0 S3C2410_IRQ(17)
53#define IRQ_DMA1 S3C2410_IRQ(18)
54#define IRQ_DMA2 S3C2410_IRQ(19)
55#define IRQ_DMA3 S3C2410_IRQ(20)
56#define IRQ_SDI S3C2410_IRQ(21)
57#define IRQ_SPI0 S3C2410_IRQ(22)
58#define IRQ_UART1 S3C2410_IRQ(23)
59#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
60#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
61#define IRQ_USBD S3C2410_IRQ(25)
62#define IRQ_USBH S3C2410_IRQ(26)
63#define IRQ_IIC S3C2410_IRQ(27)
64#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
65#define IRQ_SPI1 S3C2410_IRQ(29)
66#define IRQ_RTC S3C2410_IRQ(30)
67#define IRQ_ADCPARENT S3C2410_IRQ(31)
68
69/* interrupts generated from the external interrupts sources */
70#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
71#define IRQ_EINT5 S3C2410_IRQ(33)
72#define IRQ_EINT6 S3C2410_IRQ(34)
73#define IRQ_EINT7 S3C2410_IRQ(35)
74#define IRQ_EINT8 S3C2410_IRQ(36)
75#define IRQ_EINT9 S3C2410_IRQ(37)
76#define IRQ_EINT10 S3C2410_IRQ(38)
77#define IRQ_EINT11 S3C2410_IRQ(39)
78#define IRQ_EINT12 S3C2410_IRQ(40)
79#define IRQ_EINT13 S3C2410_IRQ(41)
80#define IRQ_EINT14 S3C2410_IRQ(42)
81#define IRQ_EINT15 S3C2410_IRQ(43)
82#define IRQ_EINT16 S3C2410_IRQ(44)
83#define IRQ_EINT17 S3C2410_IRQ(45)
84#define IRQ_EINT18 S3C2410_IRQ(46)
85#define IRQ_EINT19 S3C2410_IRQ(47)
86#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */
87#define IRQ_EINT21 S3C2410_IRQ(49)
88#define IRQ_EINT22 S3C2410_IRQ(50)
89#define IRQ_EINT23 S3C2410_IRQ(51)
90
91
92#define IRQ_EINT(x) S3C2410_IRQ((x >= 4) ? (IRQ_EINT4 + (x) - 4) : (S3C2410_IRQ(0) + (x)))
93
94#define IRQ_LCD_FIFO S3C2410_IRQ(52)
95#define IRQ_LCD_FRAME S3C2410_IRQ(53)
96
97/* IRQs for the interal UARTs, and ADC
98 * these need to be ordered in number of appearance in the
99 * SUBSRC mask register
100*/
101#define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */
102#define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */
103#define IRQ_S3CUART_ERR0 S3C2410_IRQ(56)
104
105#define IRQ_S3CUART_RX1 S3C2410_IRQ(57)
106#define IRQ_S3CUART_TX1 S3C2410_IRQ(58)
107#define IRQ_S3CUART_ERR1 S3C2410_IRQ(59)
108
109#define IRQ_S3CUART_RX2 S3C2410_IRQ(60)
110#define IRQ_S3CUART_TX2 S3C2410_IRQ(61)
111#define IRQ_S3CUART_ERR2 S3C2410_IRQ(62)
112
113#define IRQ_TC S3C2410_IRQ(63)
114#define IRQ_ADC S3C2410_IRQ(64)
115
116/* extra irqs for s3c2440 */
117
118#define IRQ_S3C2440_CAM_C S3C2410_IRQ(65)
119#define IRQ_S3C2440_CAM_P S3C2410_IRQ(66)
120#define IRQ_S3C2440_WDT S3C2410_IRQ(67)
121#define IRQ_S3C2440_AC97 S3C2410_IRQ(68)
122
123#define NR_IRQS (IRQ_S3C2440_AC97+1)
124
125
126#endif /* __ASM_ARCH_IRQ_H */