diff options
author | Jeff Garzik <jgarzik@pobox.com> | 2005-10-03 19:48:49 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@pobox.com> | 2005-10-03 19:48:49 -0400 |
commit | 0fbbbf2bde4da5cb01a949c3d7b21c0627f520a8 (patch) | |
tree | f081ef10f3067b28a1ee316a8e7292eeda143419 /include/asm-arm/arch-s3c2410/anubis-map.h | |
parent | 54f00389563c80fa1de250a21256313ba01ca07d (diff) | |
parent | 2b235826098bb653982894dfc3f70fd029f6c2e4 (diff) |
Merge libata upstream (which includes C/H/S support) include irq-pio branch.
Merge branch 'upstream'
Diffstat (limited to 'include/asm-arm/arch-s3c2410/anubis-map.h')
-rw-r--r-- | include/asm-arm/arch-s3c2410/anubis-map.h | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/include/asm-arm/arch-s3c2410/anubis-map.h b/include/asm-arm/arch-s3c2410/anubis-map.h index 97741d6e506a..d529ffda8599 100644 --- a/include/asm-arm/arch-s3c2410/anubis-map.h +++ b/include/asm-arm/arch-s3c2410/anubis-map.h | |||
@@ -20,22 +20,22 @@ | |||
20 | 20 | ||
21 | /* start peripherals off after the S3C2410 */ | 21 | /* start peripherals off after the S3C2410 */ |
22 | 22 | ||
23 | #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x02000000)) | 23 | #define ANUBIS_IOADDR(x) (S3C2410_ADDR((x) + 0x01800000)) |
24 | 24 | ||
25 | #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) | 25 | #define ANUBIS_PA_CPLD (S3C2410_CS1 | (1<<26)) |
26 | 26 | ||
27 | /* we put the CPLD registers next, to get them out of the way */ | 27 | /* we put the CPLD registers next, to get them out of the way */ |
28 | 28 | ||
29 | #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01300000 */ | 29 | #define ANUBIS_VA_CTRL1 ANUBIS_IOADDR(0x00000000) /* 0x01800000 */ |
30 | #define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) | 30 | #define ANUBIS_PA_CTRL1 (ANUBIS_PA_CPLD) |
31 | 31 | ||
32 | #define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01400000 */ | 32 | #define ANUBIS_VA_CTRL2 ANUBIS_IOADDR(0x00100000) /* 0x01900000 */ |
33 | #define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD) | 33 | #define ANUBIS_PA_CTRL2 (ANUBIS_PA_CPLD) |
34 | 34 | ||
35 | #define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01500000 */ | 35 | #define ANUBIS_VA_CTRL3 ANUBIS_IOADDR(0x00200000) /* 0x01A00000 */ |
36 | #define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD) | 36 | #define ANUBIS_PA_CTRL3 (ANUBIS_PA_CPLD) |
37 | 37 | ||
38 | #define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01600000 */ | 38 | #define ANUBIS_VA_CTRL4 ANUBIS_IOADDR(0x00300000) /* 0x01B00000 */ |
39 | #define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD) | 39 | #define ANUBIS_PA_CTRL4 (ANUBIS_PA_CPLD) |
40 | 40 | ||
41 | #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) | 41 | #define ANUBIS_IDEPRI ANUBIS_IOADDR(0x01000000) |