[ARM] 4109/2: Add support for the RealView/EB MPCore revC platform

The kernel originally supported revB only. This patch enables revC by
default and adds a config option for building the kernel for the revB
platform. Since the SCU base address was hard-coded in the proc-v6.S
file (and only valid for RealView/EB revB), this patch also adds a
more generic support for defining the SCU information.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

1 files changed, 10 insertions, 0 deletions

diff --git a/include/asm-arm/arch-realview/platform.h b/include/asm-arm/arch-realview/platform.h
index bf52ca752a75..87acd9c191e6 100644
--- a/include/asm-arm/arch-realview/platform.h
+++ b/include/asm-arm/arch-realview/platform.h
@@ -207,11 +207,21 @@
 #define REALVIEW_GIC_CPU_BASE         0x10040000        /* Generic interrupt controller CPU interface */
 #define REALVIEW_GIC_DIST_BASE        0x10041000        /* Generic interrupt controller distributor */
 #else
+#ifdef CONFIG_REALVIEW_MPCORE_REVB
 #define REALVIEW_MPCORE_SCU_BASE        0x10100000      /*  SCU registers */
 #define REALVIEW_GIC_CPU_BASE           0x10100100      /* Generic interrupt controller CPU interface */
 #define REALVIEW_TWD_BASE               0x10100700
 #define REALVIEW_TWD_SIZE               0x00000100
 #define REALVIEW_GIC_DIST_BASE          0x10101000      /* Generic interrupt controller distributor */
+#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0xD8              /*  Register offset for MPCore sysctl */
+#else
+#define REALVIEW_MPCORE_SCU_BASE      0x1F000000        /*  SCU registers */
+#define REALVIEW_GIC_CPU_BASE         0x1F000100        /* Generic interrupt controller CPU interface */
+#define REALVIEW_TWD_BASE             0x1F000700
+#define REALVIEW_TWD_SIZE             0x00000100
+#define REALVIEW_GIC_DIST_BASE        0x1F001000        /* Generic interrupt controller distributor */
+#define REALVIEW_MPCORE_SYS_PLD_CTRL1 0x74              /*  Register offset for MPCore sysctl */
+#endif
 #define REALVIEW_GIC1_CPU_BASE        0x10040000        /* Generic interrupt controller CPU interface */
 #define REALVIEW_GIC1_DIST_BASE       0x10041000        /* Generic interrupt controller distributor */
 #endif