diff options
author | Catalin Marinas <catalin.marinas@arm.com> | 2007-02-14 13:18:09 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-02-15 09:51:21 -0500 |
commit | 3edf22ab34e1fdffc8c0c7c7b7da4d0aebdba118 (patch) | |
tree | ded29b4b8f5d624fcc226ef2b8b009838126fe91 /include/asm-arm/arch-realview/irqs.h | |
parent | b3a1bde4db9889feb116330bff21214811c940e4 (diff) |
[ARM] 4190/2: Add the secondary GIC support for the RealView/EB
MPCore platform
This patch adds the registration of the secondary GIC on the
baseboard, together with the IRQ chaining setup.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-realview/irqs.h')
-rw-r--r-- | include/asm-arm/arch-realview/irqs.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/asm-arm/arch-realview/irqs.h b/include/asm-arm/arch-realview/irqs.h index 76b498eb20a6..5a5db56f86b8 100644 --- a/include/asm-arm/arch-realview/irqs.h +++ b/include/asm-arm/arch-realview/irqs.h | |||
@@ -78,6 +78,9 @@ | |||
78 | #define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6) | 78 | #define IRQ_PMU_SCU6 (IRQ_GIC_START + INT_PMU_SCU6) |
79 | #define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7) | 79 | #define IRQ_PMU_SCU7 (IRQ_GIC_START + INT_PMU_SCU7) |
80 | 80 | ||
81 | #define IRQ_EB_IRQ1 (IRQ_GIC_START + INT_EB_IRQ1) | ||
82 | #define IRQ_EB_IRQ2 (IRQ_GIC_START + INT_EB_IRQ2) | ||
83 | |||
81 | #define IRQMASK_WDOGINT INTMASK_WDOGINT | 84 | #define IRQMASK_WDOGINT INTMASK_WDOGINT |
82 | #define IRQMASK_SOFTINT INTMASK_SOFTINT | 85 | #define IRQMASK_SOFTINT INTMASK_SOFTINT |
83 | #define IRQMASK_COMMRx INTMASK_COMMRx | 86 | #define IRQMASK_COMMRx INTMASK_COMMRx |
@@ -115,4 +118,4 @@ | |||
115 | #define IRQMASK_ETH INTMASK_ETH | 118 | #define IRQMASK_ETH INTMASK_ETH |
116 | #define IRQMASK_USB INTMASK_USB | 119 | #define IRQMASK_USB INTMASK_USB |
117 | 120 | ||
118 | #define NR_IRQS (IRQ_GIC_START + 64) | 121 | #define NR_IRQS (IRQ_GIC_START + 96) |