Merge ../linus

Conflicts:

	drivers/cpufreq/cpufreq.c

5 files changed, 17 insertions, 65 deletions

diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h
index f3bc70eee35b..67ed43674c63 100644
--- a/include/asm-arm/arch-pxa/irqs.h
+++ b/include/asm-arm/arch-pxa/irqs.h
@@ -73,7 +73,7 @@
 #define IRQ_TO_GPIO(i)  (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i))
 
 #if defined(CONFIG_PXA25x)
-#define PXA_LAST_GPIO   80
+#define PXA_LAST_GPIO   84
 #elif defined(CONFIG_PXA27x)
 #define PXA_LAST_GPIO   127
 #endif
diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h
index eaf6d43939e9..e17f9881faf0 100644
--- a/include/asm-arm/arch-pxa/memory.h
+++ b/include/asm-arm/arch-pxa/memory.h
@@ -27,7 +27,6 @@
 #define __virt_to_bus(x)         __virt_to_phys(x)
 #define __bus_to_virt(x)         __phys_to_virt(x)
 
-#ifdef CONFIG_DISCONTIGMEM
 /*
  * The nodes are matched with the physical SDRAM banks as follows:
  *
@@ -35,38 +34,9 @@
  *      node 1:  0xa4000000-0xa7ffffff  -->  0xc4000000-0xc7ffffff
  *      node 2:  0xa8000000-0xabffffff  -->  0xc8000000-0xcbffffff
  *      node 3:  0xac000000-0xafffffff  -->  0xcc000000-0xcfffffff
+ *
+ * This needs a node mem size of 26 bits.
  */
-
-/*
- * Given a kernel address, find the home node of the underlying memory.
- */
-#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
-
-/*
- * Given a page frame number, convert it to a node id.
- */
-#define PFN_TO_NID(pfn)         (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
-
-/*
- * Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define ADDR_TO_MAPBASE(kaddr)  NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
-
-/*
- * Given a page frame number, find the owning node of the memory
- * and returns the mem_map of that node.
- */
-#define PFN_TO_MAPBASE(pfn)     NODE_MEM_MAP(PFN_TO_NID(pfn))
-
-/*
- * Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
- * and returns the index corresponding to the appropriate page in the
- * node's mem_map.
- */
-#define LOCAL_MAP_NR(addr) \
-        (((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
-
-#endif
+#define NODE_MEM_SIZE_BITS      26
 
 #endif
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index f5cc65dd7d0d..083e03c5639f 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -99,7 +99,7 @@
 #define DCSR_SETCMPST   (1 << 25)       /* Set Descriptor Compare Status */
 #define DCSR_CLRCMPST   (1 << 24)       /* Clear Descriptor Compare Status */
 #define DCSR_CMPST      (1 << 10)       /* The Descriptor Compare Status */
-#define DCSR_ENRINTR    (1 << 9)        /* The end of Receive */
+#define DCSR_EORINTR    (1 << 9)        /* The end of Receive */
 #endif
 #define DCSR_REQPEND    (1 << 8)        /* Request Pending (read-only) */
 #define DCSR_STOPSTATE  (1 << 3)        /* Stop State (read-only) */
@@ -803,12 +803,11 @@
 #define UDCISR0         __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
 #define UDCISR1         __REG(0x40600010) /* UDC Interrupt Status Register 1 */
 #define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
-#define UDCISR1_IECC    (1 << 31)       /* IntEn - Configuration Change */
-#define UDCISR1_IESOF   (1 << 30)       /* IntEn - Start of Frame */
-#define UDCISR1_IERU    (1 << 29)       /* IntEn - Resume */
-#define UDCISR1_IESU    (1 << 28)       /* IntEn - Suspend */
-#define UDCISR1_IERS    (1 << 27)       /* IntEn - Reset */
-
+#define UDCISR1_IRCC    (1 << 31)       /* IntReq - Configuration Change */
+#define UDCISR1_IRSOF   (1 << 30)       /* IntReq - Start of Frame */
+#define UDCISR1_IRRU    (1 << 29)       /* IntReq - Resume */
+#define UDCISR1_IRSU    (1 << 28)       /* IntReq - Suspend */
+#define UDCISR1_IRRS    (1 << 27)       /* IntReq - Reset */
 
 #define UDCFNR          __REG(0x40600014) /* UDC Frame Number Register */
 #define UDCOTGICR       __REG(0x40600018) /* UDC On-The-Go interrupt control */
@@ -1681,6 +1680,7 @@
 #define SSSR_TINT               (1 << 19)       /* Receiver Time-out Interrupt */
 #define SSSR_PINT               (1 << 18)       /* Peripheral Trailing Byte Interrupt */
 
+#define SSPSP_FSRT              (1 << 25)       /* Frame Sync Relative Timing */
 #define SSPSP_DMYSTOP(x)        (x << 23)       /* Dummy Stop */
 #define SSPSP_SFRMWDTH(x)       (x << 16)       /* Serial Frame Width */
 #define SSPSP_SFRMDLY(x)        (x << 9)        /* Serial Frame Delay */
@@ -2241,7 +2241,7 @@
 
 #define CICR1_TBIT      (1 << 31)       /* Transparency bit */
 #define CICR1_RGBT_CONV (0x3 << 30)     /* RGBT conversion mask */
-#define CICR1_PPL       (0x3f << 15)    /* Pixels per line mask */
+#define CICR1_PPL       (0x7ff << 15)   /* Pixels per line mask */
 #define CICR1_RGB_CONV  (0x7 << 12)     /* RGB conversion mask */
 #define CICR1_RGB_F     (1 << 11)       /* RGB format */
 #define CICR1_YCBCR_F   (1 << 10)       /* YCbCr format */
@@ -2267,7 +2267,7 @@
 #define CICR3_VSW       (0x3f << 10)    /* Vertical sync pulse width mask */
 #define CICR3_BFPW      (0x3f << 3)     /* Beginning-of-frame pixel clock
                                            wait count mask */
-#define CICR3_LPF       (0x3ff << 0)    /* Lines per frame mask */
+#define CICR3_LPF       (0x7ff << 0)    /* Lines per frame mask */
 
 #define CICR4_MCLK_DLY  (0x3 << 24)     /* MCLK Data Capture Delay mask */
 #define CICR4_PCLK_EN   (1 << 23)       /* Pixel clock enable */
@@ -2288,8 +2288,8 @@
 #define CISR_EOL        (1 << 8)        /* End of line */
 #define CISR_PAR_ERR    (1 << 7)        /* Parity error */
 #define CISR_CQD        (1 << 6)        /* Camera interface quick disable */
-#define CISR_SOF        (1 << 5)        /* Start of frame */
-#define CISR_CDD        (1 << 4)        /* Camera interface disable done */
+#define CISR_CDD        (1 << 5)        /* Camera interface disable done */
+#define CISR_SOF        (1 << 4)        /* Start of frame */
 #define CISR_EOF        (1 << 3)        /* End of frame */
 #define CISR_IFO_2      (1 << 2)        /* FIFO overrun for Channel 2 */
 #define CISR_IFO_1      (1 << 1)        /* FIFO overrun for Channel 1 */
diff --git a/include/asm-arm/arch-pxa/pxa2xx_spi.h b/include/asm-arm/arch-pxa/pxa2xx_spi.h
index 915590c391c8..acc7ec7a84a1 100644
--- a/include/asm-arm/arch-pxa/pxa2xx_spi.h
+++ b/include/asm-arm/arch-pxa/pxa2xx_spi.h
@@ -27,16 +27,13 @@
 #define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
 #define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
 #define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP_TIMEOUT_SCALE (2712)
 #elif defined(CONFIG_PXA27x)
 #define CLOCK_SPEED_HZ 13000000
 #define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
 #define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
 #define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
-#define SSP_TIMEOUT_SCALE (769)
 #endif
 
-#define SSP_TIMEOUT(x) ((x*10000)/SSP_TIMEOUT_SCALE)
 #define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
 #define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
 #define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
@@ -63,7 +60,7 @@ struct pxa2xx_spi_chip {
         u8 tx_threshold;
         u8 rx_threshold;
         u8 dma_burst_size;
-        u32 timeout_microsecs;
+        u32 timeout;
         u8 enable_loopback;
         void (*cs_control)(u32 command);
 };
diff --git a/include/asm-arm/arch-pxa/udc.h b/include/asm-arm/arch-pxa/udc.h
index 121cd241115d..646480d37256 100644
--- a/include/asm-arm/arch-pxa/udc.h
+++ b/include/asm-arm/arch-pxa/udc.h
@@ -4,23 +4,8 @@
  * This supports machine-specific differences in how the PXA2xx
  * USB Device Controller (UDC) is wired.
  *
- * It is set in linux/arch/arm/mach-pxa/<machine>.c and used in
- * the probe routine of linux/drivers/usb/gadget/pxa2xx_udc.c
  */
-struct pxa2xx_udc_mach_info {
-        int  (*udc_is_connected)(void);         /* do we see host? */
-        void (*udc_command)(int cmd);
-#define PXA2XX_UDC_CMD_CONNECT          0       /* let host see us */
-#define PXA2XX_UDC_CMD_DISCONNECT       1       /* so host won't see us */
-
-        /* Boards following the design guidelines in the developer's manual,
-         * with on-chip GPIOs not Lubbock's wierd hardware, can have a sane
-         * VBUS IRQ and omit the methods above.  Store the GPIO number
-         * here; for GPIO 0, also mask in one of the pxa_gpio_mode() bits.
-         */
-        u16     gpio_vbus;                      /* high == vbus present */
-        u16     gpio_pullup;                    /* high == pullup activated */
-};
+#include <asm/mach/udc_pxa2xx.h>
 
 extern void pxa_set_udc_info(struct pxa2xx_udc_mach_info *info);