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authoreric miao <eric.miao@marvell.com>2008-04-30 03:52:21 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2008-04-30 11:29:31 -0400
commitce4fb7b892a6d6c6a0f87366b26fd834d2923dd7 (patch)
tree1b30869071a065f24ab0976b23c9c47998022b24 /include/asm-arm/arch-pxa
parent92ac73c1e4b4e039162f5d3980c2da8192b28060 (diff)
pxafb: convert fb driver to use ioremap() and __raw_{readl, writel}
This is part of the effort moving peripheral registers outside of pxa-regs.h, and using ioremap() make it possible the same IP can be re-used on different processors with different registers space As a result, the fixed mapping in pxa_map_io() is removed. The regs-lcd.h can actually moved to where closer to pxafb.c but some of its bit definitions are directly used by various platform code, though this is not a good style. Signed-off-by: eric miao <eric.miao@marvell.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'include/asm-arm/arch-pxa')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h196
-rw-r--r--include/asm-arm/arch-pxa/pxafb.h1
-rw-r--r--include/asm-arm/arch-pxa/regs-lcd.h139
3 files changed, 140 insertions, 196 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index a322012f16ac..4b2ea1e95c57 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1406,202 +1406,6 @@
1406#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */ 1406#define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
1407#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */ 1407#define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
1408 1408
1409
1410/*
1411 * LCD
1412 */
1413
1414#define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
1415#define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
1416#define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
1417#define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
1418#define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 3 */
1419#define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
1420#define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
1421#define LCSR __REG(0x44000038) /* LCD Controller Status Register */
1422#define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
1423#define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
1424#define TMEDCR __REG(0x44000044) /* TMED Control Register */
1425
1426#define LCCR3_1BPP (0 << 24)
1427#define LCCR3_2BPP (1 << 24)
1428#define LCCR3_4BPP (2 << 24)
1429#define LCCR3_8BPP (3 << 24)
1430#define LCCR3_16BPP (4 << 24)
1431
1432#define LCCR3_PDFOR_0 (0 << 30)
1433#define LCCR3_PDFOR_1 (1 << 30)
1434#define LCCR3_PDFOR_2 (2 << 30)
1435#define LCCR3_PDFOR_3 (3 << 30)
1436
1437#define LCCR4_PAL_FOR_0 (0 << 15)
1438#define LCCR4_PAL_FOR_1 (1 << 15)
1439#define LCCR4_PAL_FOR_2 (2 << 15)
1440#define LCCR4_PAL_FOR_MASK (3 << 15)
1441
1442#define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
1443#define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
1444#define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
1445#define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
1446#define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
1447#define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
1448#define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
1449#define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
1450
1451#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
1452#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
1453#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
1454#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
1455#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display */
1456 /* Select */
1457#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
1458#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
1459
1460#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
1461#define LCCR0_SFM (1 << 4) /* Start of frame mask */
1462#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
1463#define LCCR0_EFM (1 << 6) /* End of Frame mask */
1464#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
1465#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
1466#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
1467#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome */
1468 /* display mode) */
1469#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
1470 /* display */
1471#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
1472 /* display */
1473#define LCCR0_DIS (1 << 10) /* LCD Disable */
1474#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
1475#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
1476#define LCCR0_PDD_S 12
1477#define LCCR0_BM (1 << 20) /* Branch mask */
1478#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
1479#define LCCR0_LCDT (1 << 22) /* LCD panel type */
1480#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
1481#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
1482#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
1483#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
1484
1485#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
1486#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
1487 (((Pixel) - 1) << FShft (LCCR1_PPL))
1488
1489#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
1490#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
1491 /* pulse Width [1..64 Tpix] */ \
1492 (((Tpix) - 1) << FShft (LCCR1_HSW))
1493
1494#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1495 /* count - 1 [Tpix] */
1496#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
1497 /* [1..256 Tpix] */ \
1498 (((Tpix) - 1) << FShft (LCCR1_ELW))
1499
1500#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1501 /* Wait count - 1 [Tpix] */
1502#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
1503 /* [1..256 Tpix] */ \
1504 (((Tpix) - 1) << FShft (LCCR1_BLW))
1505
1506
1507#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1508#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
1509 (((Line) - 1) << FShft (LCCR2_LPP))
1510
1511#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
1512 /* Width - 1 [Tln] (L_FCLK) */
1513#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
1514 /* Width [1..64 Tln] */ \
1515 (((Tln) - 1) << FShft (LCCR2_VSW))
1516
1517#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1518 /* count [Tln] */
1519#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
1520 /* [0..255 Tln] */ \
1521 ((Tln) << FShft (LCCR2_EFW))
1522
1523#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1524 /* Wait count [Tln] */
1525#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
1526 /* [0..255 Tln] */ \
1527 ((Tln) << FShft (LCCR2_BFW))
1528
1529#if 0
1530#define LCCR3_PCD (0xff) /* Pixel clock divisor */
1531#define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
1532#define LCCR3_ACB_S 8
1533#endif
1534
1535#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
1536#define LCCR3_API_S 16
1537#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
1538#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
1539#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
1540#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
1541#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
1542
1543#define LCCR3_OEP (1 << 23) /* Output Enable Polarity (L_BIAS, */
1544 /* active display mode) */
1545#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
1546#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
1547
1548#if 0
1549#define LCCR3_BPP (7 << 24) /* bits per pixel */
1550#define LCCR3_BPP_S 24
1551#endif
1552#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
1553
1554
1555#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
1556#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
1557 (((Div) << FShft (LCCR3_PCD)))
1558
1559
1560#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
1561#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
1562 (((Bpp) << FShft (LCCR3_BPP)))
1563
1564#define LCCR3_ACB Fld (8, 8) /* AC Bias */
1565#define LCCR3_Acb(Acb) /* BAC Bias */ \
1566 (((Acb) << FShft (LCCR3_ACB)))
1567
1568#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
1569 /* pulse active High */
1570#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
1571
1572#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
1573 /* active High */
1574#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
1575 /* active Low */
1576
1577#define LCSR_LDD (1 << 0) /* LCD Disable Done */
1578#define LCSR_SOF (1 << 1) /* Start of frame */
1579#define LCSR_BER (1 << 2) /* Bus error */
1580#define LCSR_ABC (1 << 3) /* AC Bias count */
1581#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1582#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1583#define LCSR_OU (1 << 6) /* output FIFO underrun */
1584#define LCSR_QD (1 << 7) /* quick disable */
1585#define LCSR_EOF (1 << 8) /* end of frame */
1586#define LCSR_BS (1 << 9) /* branch status */
1587#define LCSR_SINT (1 << 10) /* subsequent interrupt */
1588
1589#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1590
1591#define LCSR_LDD (1 << 0) /* LCD Disable Done */
1592#define LCSR_SOF (1 << 1) /* Start of frame */
1593#define LCSR_BER (1 << 2) /* Bus error */
1594#define LCSR_ABC (1 << 3) /* AC Bias count */
1595#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
1596#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
1597#define LCSR_OU (1 << 6) /* output FIFO underrun */
1598#define LCSR_QD (1 << 7) /* quick disable */
1599#define LCSR_EOF (1 << 8) /* end of frame */
1600#define LCSR_BS (1 << 9) /* branch status */
1601#define LCSR_SINT (1 << 10) /* subsequent interrupt */
1602
1603#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
1604
1605#ifdef CONFIG_PXA27x 1409#ifdef CONFIG_PXA27x
1606 1410
1607/* Camera Interface */ 1411/* Camera Interface */
diff --git a/include/asm-arm/arch-pxa/pxafb.h b/include/asm-arm/arch-pxa/pxafb.h
index ea2336aa70e4..5cf51a5137b7 100644
--- a/include/asm-arm/arch-pxa/pxafb.h
+++ b/include/asm-arm/arch-pxa/pxafb.h
@@ -13,6 +13,7 @@
13 */ 13 */
14 14
15#include <linux/fb.h> 15#include <linux/fb.h>
16#include <asm/arch/regs-lcd.h>
16 17
17/* 18/*
18 * This structure describes the machine which we are running on. 19 * This structure describes the machine which we are running on.
diff --git a/include/asm-arm/arch-pxa/regs-lcd.h b/include/asm-arm/arch-pxa/regs-lcd.h
new file mode 100644
index 000000000000..f84dd47be28a
--- /dev/null
+++ b/include/asm-arm/arch-pxa/regs-lcd.h
@@ -0,0 +1,139 @@
1#ifndef __ASM_ARCH_REGS_LCD_H
2#define __ASM_ARCH_REGS_LCD_H
3/*
4 * LCD Controller Registers and Bits Definitions
5 */
6#define LCCR0 (0x000) /* LCD Controller Control Register 0 */
7#define LCCR1 (0x004) /* LCD Controller Control Register 1 */
8#define LCCR2 (0x008) /* LCD Controller Control Register 2 */
9#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
10#define LCCR4 (0x010) /* LCD Controller Control Register 3 */
11#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
12#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
13#define LCSR (0x038) /* LCD Controller Status Register */
14#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */
15#define TMEDRGBR (0x040) /* TMED RGB Seed Register */
16#define TMEDCR (0x044) /* TMED Control Register */
17
18#define LCCR3_1BPP (0 << 24)
19#define LCCR3_2BPP (1 << 24)
20#define LCCR3_4BPP (2 << 24)
21#define LCCR3_8BPP (3 << 24)
22#define LCCR3_16BPP (4 << 24)
23
24#define LCCR3_PDFOR_0 (0 << 30)
25#define LCCR3_PDFOR_1 (1 << 30)
26#define LCCR3_PDFOR_2 (2 << 30)
27#define LCCR3_PDFOR_3 (3 << 30)
28
29#define LCCR4_PAL_FOR_0 (0 << 15)
30#define LCCR4_PAL_FOR_1 (1 << 15)
31#define LCCR4_PAL_FOR_2 (2 << 15)
32#define LCCR4_PAL_FOR_MASK (3 << 15)
33
34#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
35#define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */
36#define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */
37#define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */
38#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
39#define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */
40#define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */
41#define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */
42
43#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
44#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
45#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
46#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
47#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */
48#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
49#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
50
51#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
52#define LCCR0_SFM (1 << 4) /* Start of frame mask */
53#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
54#define LCCR0_EFM (1 << 6) /* End of Frame mask */
55#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
56#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
57#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
58#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */
59#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
60#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
61#define LCCR0_DIS (1 << 10) /* LCD Disable */
62#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
63#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
64#define LCCR0_PDD_S 12
65#define LCCR0_BM (1 << 20) /* Branch mask */
66#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
67#define LCCR0_LCDT (1 << 22) /* LCD panel type */
68#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
69#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
70#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
71#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
72
73#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
74#define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
75
76#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
77#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
78
79#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
80#define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
81
82#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
83#define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
84
85#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
86#define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP))
87
88#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */
89#define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
90
91#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
92#define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW))
93
94#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
95#define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW))
96
97#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
98#define LCCR3_API_S 16
99#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
100#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
101#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
102#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
103#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
104
105#define LCCR3_OEP (1 << 23) /* Output Enable Polarity */
106#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
107#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
108
109#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
110#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
111#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD)))
112
113#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
114#define LCCR3_Bpp(Bpp) (((Bpp) << FShft (LCCR3_BPP)))
115
116#define LCCR3_ACB Fld (8, 8) /* AC Bias */
117#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB)))
118
119#define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */
120#define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */
121
122#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */
123#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */
124
125#define LCSR_LDD (1 << 0) /* LCD Disable Done */
126#define LCSR_SOF (1 << 1) /* Start of frame */
127#define LCSR_BER (1 << 2) /* Bus error */
128#define LCSR_ABC (1 << 3) /* AC Bias count */
129#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
130#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
131#define LCSR_OU (1 << 6) /* output FIFO underrun */
132#define LCSR_QD (1 << 7) /* quick disable */
133#define LCSR_EOF (1 << 8) /* end of frame */
134#define LCSR_BS (1 << 9) /* branch status */
135#define LCSR_SINT (1 << 10) /* subsequent interrupt */
136
137#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
138
139#endif /* __ASM_ARCH_REGS_LCD_H */
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