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authorDavid S. Miller <davem@davemloft.net>2008-02-23 23:38:20 -0500
committerDavid S. Miller <davem@davemloft.net>2008-02-23 23:38:20 -0500
commit8d3c202be23c5a915f7053ebd4e96f44700c6a62 (patch)
treee0f017aff86d3ad0b858fe85f44e11096087ed00 /include/asm-arm/arch-pxa/regs-ssp.h
parent1b04ab4597725f75f94942da9aa40daa7b9a4bd9 (diff)
parent038eb0ea04b245351be34b0ae76b55eee4603989 (diff)
Merge branch 'master' of ../linux-2.6/
Diffstat (limited to 'include/asm-arm/arch-pxa/regs-ssp.h')
-rw-r--r--include/asm-arm/arch-pxa/regs-ssp.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/regs-ssp.h b/include/asm-arm/arch-pxa/regs-ssp.h
index 991cb688db75..0255328c3c18 100644
--- a/include/asm-arm/arch-pxa/regs-ssp.h
+++ b/include/asm-arm/arch-pxa/regs-ssp.h
@@ -85,6 +85,7 @@
85#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */ 85#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
86#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */ 86#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
87#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */ 87#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
88#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
88#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */ 89#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
89#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */ 90#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
90 91