diff options
| author | eric miao <eric.miao@marvell.com> | 2008-03-02 20:44:25 -0500 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-04-19 06:29:04 -0400 |
| commit | a683b14df8f4320d0ef6cac93a6d9806173bf339 (patch) | |
| tree | d398ad79e265d7664a36f053ba7b5cc9595b8d26 /include/asm-arm/arch-pxa/pxa2xx-gpio.h | |
| parent | 4be35e236c4a0e346442d98de3e470cf87c4e947 (diff) | |
[ARM] pxa: separate GPIOs and their mode definitions to pxa2xx-gpio.h
two reasons:
1. GPIO namings and their mode definitions are conceptually not part
of the PXA register definitions
2. this is actually a temporary move in the transition of PXA2xx to
use MFP-alike APIs (as what PXA3xx is now doing), so that legacy
code will still work and new code can be added in step by step
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-pxa/pxa2xx-gpio.h')
| -rw-r--r-- | include/asm-arm/arch-pxa/pxa2xx-gpio.h | 304 |
1 files changed, 304 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/pxa2xx-gpio.h b/include/asm-arm/arch-pxa/pxa2xx-gpio.h new file mode 100644 index 000000000000..fb4189447538 --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa2xx-gpio.h | |||
| @@ -0,0 +1,304 @@ | |||
| 1 | #ifndef __ASM_ARCH_PXA2XX_GPIO_H | ||
| 2 | #define __ASM_ARCH_PXA2XX_GPIO_H | ||
| 3 | |||
| 4 | /* GPIO alternate function assignments */ | ||
| 5 | |||
| 6 | #define GPIO1_RST 1 /* reset */ | ||
| 7 | #define GPIO6_MMCCLK 6 /* MMC Clock */ | ||
| 8 | #define GPIO7_48MHz 7 /* 48 MHz clock output */ | ||
| 9 | #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */ | ||
| 10 | #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */ | ||
| 11 | #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */ | ||
| 12 | #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */ | ||
| 13 | #define GPIO12_32KHz 12 /* 32 kHz out */ | ||
| 14 | #define GPIO12_CIF_DD_7 12 /* Camera data pin 7 */ | ||
| 15 | #define GPIO13_MBGNT 13 /* memory controller grant */ | ||
| 16 | #define GPIO14_MBREQ 14 /* alternate bus master request */ | ||
| 17 | #define GPIO15_nCS_1 15 /* chip select 1 */ | ||
| 18 | #define GPIO16_PWM0 16 /* PWM0 output */ | ||
| 19 | #define GPIO17_PWM1 17 /* PWM1 output */ | ||
| 20 | #define GPIO17_CIF_DD_6 17 /* Camera data pin 6 */ | ||
| 21 | #define GPIO18_RDY 18 /* Ext. Bus Ready */ | ||
| 22 | #define GPIO19_DREQ1 19 /* External DMA Request */ | ||
| 23 | #define GPIO20_DREQ0 20 /* External DMA Request */ | ||
| 24 | #define GPIO23_SCLK 23 /* SSP clock */ | ||
| 25 | #define GPIO24_SFRM 24 /* SSP Frame */ | ||
| 26 | #define GPIO25_STXD 25 /* SSP transmit */ | ||
| 27 | #define GPIO26_SRXD 26 /* SSP receive */ | ||
| 28 | #define GPIO27_SEXTCLK 27 /* SSP ext_clk */ | ||
| 29 | #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */ | ||
| 30 | #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */ | ||
| 31 | #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */ | ||
| 32 | #define GPIO31_SYNC 31 /* AC97/I2S sync */ | ||
| 33 | #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */ | ||
| 34 | #define GPIO32_SYSCLK 32 /* I2S System Clock */ | ||
| 35 | #define GPIO32_MMCCLK 32 /* MMC Clock (PXA270) */ | ||
| 36 | #define GPIO33_nCS_5 33 /* chip select 5 */ | ||
| 37 | #define GPIO34_FFRXD 34 /* FFUART receive */ | ||
| 38 | #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */ | ||
| 39 | #define GPIO35_FFCTS 35 /* FFUART Clear to send */ | ||
| 40 | #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */ | ||
| 41 | #define GPIO37_FFDSR 37 /* FFUART data set ready */ | ||
| 42 | #define GPIO38_FFRI 38 /* FFUART Ring Indicator */ | ||
| 43 | #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */ | ||
| 44 | #define GPIO39_FFTXD 39 /* FFUART transmit data */ | ||
| 45 | #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */ | ||
| 46 | #define GPIO41_FFRTS 41 /* FFUART request to send */ | ||
| 47 | #define GPIO42_BTRXD 42 /* BTUART receive data */ | ||
| 48 | #define GPIO42_HWRXD 42 /* HWUART receive data */ | ||
| 49 | #define GPIO43_BTTXD 43 /* BTUART transmit data */ | ||
| 50 | #define GPIO43_HWTXD 43 /* HWUART transmit data */ | ||
| 51 | #define GPIO44_BTCTS 44 /* BTUART clear to send */ | ||
| 52 | #define GPIO44_HWCTS 44 /* HWUART clear to send */ | ||
| 53 | #define GPIO45_BTRTS 45 /* BTUART request to send */ | ||
| 54 | #define GPIO45_HWRTS 45 /* HWUART request to send */ | ||
| 55 | #define GPIO45_AC97_SYSCLK 45 /* AC97 System Clock */ | ||
| 56 | #define GPIO46_ICPRXD 46 /* ICP receive data */ | ||
| 57 | #define GPIO46_STRXD 46 /* STD_UART receive data */ | ||
| 58 | #define GPIO47_ICPTXD 47 /* ICP transmit data */ | ||
| 59 | #define GPIO47_STTXD 47 /* STD_UART transmit data */ | ||
| 60 | #define GPIO48_nPOE 48 /* Output Enable for Card Space */ | ||
| 61 | #define GPIO49_nPWE 49 /* Write Enable for Card Space */ | ||
| 62 | #define GPIO50_nPIOR 50 /* I/O Read for Card Space */ | ||
| 63 | #define GPIO50_CIF_DD_3 50 /* Camera data pin 3 */ | ||
| 64 | #define GPIO51_nPIOW 51 /* I/O Write for Card Space */ | ||
| 65 | #define GPIO51_CIF_DD_2 51 /* Camera data pin 2 */ | ||
| 66 | #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */ | ||
| 67 | #define GPIO52_CIF_DD_4 52 /* Camera data pin 4 */ | ||
| 68 | #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */ | ||
| 69 | #define GPIO53_MMCCLK 53 /* MMC Clock */ | ||
| 70 | #define GPIO53_CIF_MCLK 53 /* Camera Master Clock */ | ||
| 71 | #define GPIO54_MMCCLK 54 /* MMC Clock */ | ||
| 72 | #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */ | ||
| 73 | #define GPIO54_nPCE_2 54 /* Card Enable for Card Space (PXA27x) */ | ||
| 74 | #define GPIO54_CIF_PCLK 54 /* Camera Pixel Clock */ | ||
| 75 | #define GPIO55_nPREG 55 /* Card Address bit 26 */ | ||
| 76 | #define GPIO55_CIF_DD_1 55 /* Camera data pin 1 */ | ||
| 77 | #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */ | ||
| 78 | #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */ | ||
| 79 | #define GPIO58_LDD_0 58 /* LCD data pin 0 */ | ||
| 80 | #define GPIO59_LDD_1 59 /* LCD data pin 1 */ | ||
| 81 | #define GPIO60_LDD_2 60 /* LCD data pin 2 */ | ||
| 82 | #define GPIO61_LDD_3 61 /* LCD data pin 3 */ | ||
| 83 | #define GPIO62_LDD_4 62 /* LCD data pin 4 */ | ||
| 84 | #define GPIO63_LDD_5 63 /* LCD data pin 5 */ | ||
| 85 | #define GPIO64_LDD_6 64 /* LCD data pin 6 */ | ||
| 86 | #define GPIO65_LDD_7 65 /* LCD data pin 7 */ | ||
| 87 | #define GPIO66_LDD_8 66 /* LCD data pin 8 */ | ||
| 88 | #define GPIO66_MBREQ 66 /* alternate bus master req */ | ||
| 89 | #define GPIO67_LDD_9 67 /* LCD data pin 9 */ | ||
| 90 | #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */ | ||
| 91 | #define GPIO68_LDD_10 68 /* LCD data pin 10 */ | ||
| 92 | #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */ | ||
| 93 | #define GPIO69_LDD_11 69 /* LCD data pin 11 */ | ||
| 94 | #define GPIO69_MMCCLK 69 /* MMC_CLK */ | ||
| 95 | #define GPIO70_LDD_12 70 /* LCD data pin 12 */ | ||
| 96 | #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */ | ||
| 97 | #define GPIO71_LDD_13 71 /* LCD data pin 13 */ | ||
| 98 | #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */ | ||
| 99 | #define GPIO72_LDD_14 72 /* LCD data pin 14 */ | ||
| 100 | #define GPIO72_32kHz 72 /* 32 kHz clock */ | ||
| 101 | #define GPIO73_LDD_15 73 /* LCD data pin 15 */ | ||
| 102 | #define GPIO73_MBGNT 73 /* Memory controller grant */ | ||
| 103 | #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */ | ||
| 104 | #define GPIO75_LCD_LCLK 75 /* LCD line clock */ | ||
| 105 | #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */ | ||
| 106 | #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */ | ||
| 107 | #define GPIO78_nCS_2 78 /* chip select 2 */ | ||
| 108 | #define GPIO79_nCS_3 79 /* chip select 3 */ | ||
| 109 | #define GPIO80_nCS_4 80 /* chip select 4 */ | ||
| 110 | #define GPIO81_NSCLK 81 /* NSSP clock */ | ||
| 111 | #define GPIO81_CIF_DD_0 81 /* Camera data pin 0 */ | ||
| 112 | #define GPIO82_NSFRM 82 /* NSSP Frame */ | ||
| 113 | #define GPIO82_CIF_DD_5 82 /* Camera data pin 5 */ | ||
| 114 | #define GPIO83_NSTXD 83 /* NSSP transmit */ | ||
| 115 | #define GPIO84_NSRXD 84 /* NSSP receive */ | ||
| 116 | #define GPIO84_CIF_FV 84 /* Camera frame start signal */ | ||
| 117 | #define GPIO85_nPCE_1 85 /* Card Enable for Card Space (PXA27x) */ | ||
| 118 | #define GPIO85_CIF_LV 85 /* Camera line start signal */ | ||
| 119 | #define GPIO92_MMCDAT0 92 /* MMC DAT0 (PXA27x) */ | ||
| 120 | #define GPIO102_nPCE_1 102 /* PCMCIA (PXA27x) */ | ||
| 121 | #define GPIO109_MMCDAT1 109 /* MMC DAT1 (PXA27x) */ | ||
| 122 | #define GPIO110_MMCDAT2 110 /* MMC DAT2 (PXA27x) */ | ||
| 123 | #define GPIO110_MMCCS0 110 /* MMC Chip Select 0 (PXA27x) */ | ||
| 124 | #define GPIO111_MMCDAT3 111 /* MMC DAT3 (PXA27x) */ | ||
| 125 | #define GPIO111_MMCCS1 111 /* MMC Chip Select 1 (PXA27x) */ | ||
| 126 | #define GPIO112_MMCCMD 112 /* MMC CMD (PXA27x) */ | ||
| 127 | #define GPIO113_I2S_SYSCLK 113 /* I2S System Clock (PXA27x) */ | ||
| 128 | #define GPIO113_AC97_RESET_N 113 /* AC97 NRESET on (PXA27x) */ | ||
| 129 | |||
| 130 | /* GPIO alternate function mode & direction */ | ||
| 131 | |||
| 132 | #define GPIO_IN 0x000 | ||
| 133 | #define GPIO_OUT 0x080 | ||
| 134 | #define GPIO_ALT_FN_1_IN 0x100 | ||
| 135 | #define GPIO_ALT_FN_1_OUT 0x180 | ||
| 136 | #define GPIO_ALT_FN_2_IN 0x200 | ||
| 137 | #define GPIO_ALT_FN_2_OUT 0x280 | ||
| 138 | #define GPIO_ALT_FN_3_IN 0x300 | ||
| 139 | #define GPIO_ALT_FN_3_OUT 0x380 | ||
| 140 | #define GPIO_MD_MASK_NR 0x07f | ||
| 141 | #define GPIO_MD_MASK_DIR 0x080 | ||
| 142 | #define GPIO_MD_MASK_FN 0x300 | ||
| 143 | #define GPIO_DFLT_LOW 0x400 | ||
| 144 | #define GPIO_DFLT_HIGH 0x800 | ||
| 145 | |||
| 146 | #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN) | ||
| 147 | #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT) | ||
| 148 | #define GPIO7_48MHz_MD ( 7 | GPIO_ALT_FN_1_OUT) | ||
| 149 | #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT) | ||
| 150 | #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT) | ||
| 151 | #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT) | ||
| 152 | #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT) | ||
| 153 | #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT) | ||
| 154 | #define GPIO12_CIF_DD_7_MD (12 | GPIO_ALT_FN_2_IN) | ||
| 155 | #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT) | ||
| 156 | #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN) | ||
| 157 | #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT) | ||
| 158 | #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT) | ||
| 159 | #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT) | ||
| 160 | #define GPIO17_CIF_DD_6_MD (17 | GPIO_ALT_FN_2_IN) | ||
| 161 | #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN) | ||
| 162 | #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN) | ||
| 163 | #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN) | ||
| 164 | #define GPIO23_SCLK_MD (23 | GPIO_ALT_FN_2_OUT) | ||
| 165 | #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT) | ||
| 166 | #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT) | ||
| 167 | #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN) | ||
| 168 | #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN) | ||
| 169 | #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN) | ||
| 170 | #define GPIO28_BITCLK_IN_I2S_MD (28 | GPIO_ALT_FN_2_IN) | ||
| 171 | #define GPIO28_BITCLK_OUT_I2S_MD (28 | GPIO_ALT_FN_1_OUT) | ||
| 172 | #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN) | ||
| 173 | #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN) | ||
| 174 | #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT) | ||
| 175 | #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT) | ||
| 176 | #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT) | ||
| 177 | #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT) | ||
| 178 | #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN) | ||
| 179 | #define GPIO32_SYSCLK_I2S_MD (32 | GPIO_ALT_FN_1_OUT) | ||
| 180 | #define GPIO32_MMCCLK_MD (32 | GPIO_ALT_FN_2_OUT) | ||
| 181 | #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT) | ||
| 182 | #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN) | ||
| 183 | #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT) | ||
| 184 | #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN) | ||
| 185 | #define GPIO35_KP_MKOUT6_MD (35 | GPIO_ALT_FN_2_OUT) | ||
| 186 | #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN) | ||
| 187 | #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN) | ||
| 188 | #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN) | ||
| 189 | #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT) | ||
| 190 | #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT) | ||
| 191 | #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT) | ||
| 192 | #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT) | ||
| 193 | #define GPIO41_KP_MKOUT7_MD (41 | GPIO_ALT_FN_1_OUT) | ||
| 194 | #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN) | ||
| 195 | #define GPIO42_HWRXD_MD (42 | GPIO_ALT_FN_3_IN) | ||
| 196 | #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT) | ||
| 197 | #define GPIO43_HWTXD_MD (43 | GPIO_ALT_FN_3_OUT) | ||
| 198 | #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN) | ||
| 199 | #define GPIO44_HWCTS_MD (44 | GPIO_ALT_FN_3_IN) | ||
| 200 | #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT) | ||
| 201 | #define GPIO45_HWRTS_MD (45 | GPIO_ALT_FN_3_OUT) | ||
| 202 | #define GPIO45_SYSCLK_AC97_MD (45 | GPIO_ALT_FN_1_OUT) | ||
| 203 | #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN) | ||
| 204 | #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN) | ||
| 205 | #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT) | ||
| 206 | #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT) | ||
| 207 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 208 | #define GPIO48_HWTXD_MD (48 | GPIO_ALT_FN_1_OUT) | ||
| 209 | #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT) | ||
| 210 | #define GPIO49_HWRXD_MD (49 | GPIO_ALT_FN_1_IN) | ||
| 211 | #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT) | ||
| 212 | #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT) | ||
| 213 | #define GPIO50_HWCTS_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 214 | #define GPIO50_CIF_DD_3_MD (50 | GPIO_ALT_FN_1_IN) | ||
| 215 | #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT) | ||
| 216 | #define GPIO51_HWRTS_MD (51 | GPIO_ALT_FN_1_OUT) | ||
| 217 | #define GPIO51_CIF_DD_2_MD (51 | GPIO_ALT_FN_1_IN) | ||
| 218 | #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT) | ||
| 219 | #define GPIO52_CIF_DD_4_MD (52 | GPIO_ALT_FN_1_IN) | ||
| 220 | #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT) | ||
| 221 | #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT) | ||
| 222 | #define GPIO53_CIF_MCLK_MD (53 | GPIO_ALT_FN_2_OUT) | ||
| 223 | #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT) | ||
| 224 | #define GPIO54_nPCE_2_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 225 | #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT) | ||
| 226 | #define GPIO54_CIF_PCLK_MD (54 | GPIO_ALT_FN_3_IN) | ||
| 227 | #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT) | ||
| 228 | #define GPIO55_CIF_DD_1_MD (55 | GPIO_ALT_FN_1_IN) | ||
| 229 | #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN) | ||
| 230 | #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN) | ||
| 231 | #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT) | ||
| 232 | #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT) | ||
| 233 | #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT) | ||
| 234 | #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT) | ||
| 235 | #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT) | ||
| 236 | #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT) | ||
| 237 | #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT) | ||
| 238 | #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT) | ||
| 239 | #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT) | ||
| 240 | #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN) | ||
| 241 | #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT) | ||
| 242 | #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT) | ||
| 243 | #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT) | ||
| 244 | #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT) | ||
| 245 | #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT) | ||
| 246 | #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT) | ||
| 247 | #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT) | ||
| 248 | #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT) | ||
| 249 | #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT) | ||
| 250 | #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT) | ||
| 251 | #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT) | ||
| 252 | #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT) | ||
| 253 | #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT) | ||
| 254 | #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT) | ||
| 255 | #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT) | ||
| 256 | #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT) | ||
| 257 | #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT) | ||
| 258 | #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT) | ||
| 259 | #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT) | ||
| 260 | #define GPIO78_nPCE_2_MD (78 | GPIO_ALT_FN_1_OUT) | ||
| 261 | #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT) | ||
| 262 | #define GPIO79_pSKTSEL_MD (79 | GPIO_ALT_FN_1_OUT) | ||
| 263 | #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT) | ||
| 264 | #define GPIO81_NSSP_CLK_OUT (81 | GPIO_ALT_FN_1_OUT) | ||
| 265 | #define GPIO81_NSSP_CLK_IN (81 | GPIO_ALT_FN_1_IN) | ||
| 266 | #define GPIO81_CIF_DD_0_MD (81 | GPIO_ALT_FN_2_IN) | ||
| 267 | #define GPIO82_NSSP_FRM_OUT (82 | GPIO_ALT_FN_1_OUT) | ||
| 268 | #define GPIO82_NSSP_FRM_IN (82 | GPIO_ALT_FN_1_IN) | ||
| 269 | #define GPIO82_CIF_DD_5_MD (82 | GPIO_ALT_FN_3_IN) | ||
| 270 | #define GPIO83_NSSP_TX (83 | GPIO_ALT_FN_1_OUT) | ||
| 271 | #define GPIO83_NSSP_RX (83 | GPIO_ALT_FN_2_IN) | ||
| 272 | #define GPIO84_NSSP_TX (84 | GPIO_ALT_FN_1_OUT) | ||
| 273 | #define GPIO84_NSSP_RX (84 | GPIO_ALT_FN_2_IN) | ||
| 274 | #define GPIO84_CIF_FV_MD (84 | GPIO_ALT_FN_3_IN) | ||
| 275 | #define GPIO85_nPCE_1_MD (85 | GPIO_ALT_FN_1_OUT) | ||
| 276 | #define GPIO85_CIF_LV_MD (85 | GPIO_ALT_FN_3_IN) | ||
| 277 | #define GPIO86_nPCE_1_MD (86 | GPIO_ALT_FN_1_OUT) | ||
| 278 | #define GPIO92_MMCDAT0_MD (92 | GPIO_ALT_FN_1_OUT) | ||
| 279 | #define GPIO95_KP_MKIN6_MD (95 | GPIO_ALT_FN_3_IN) | ||
| 280 | #define GPIO96_KP_DKIN3_MD (96 | GPIO_ALT_FN_1_IN) | ||
| 281 | #define GPIO97_KP_MKIN3_MD (97 | GPIO_ALT_FN_3_IN) | ||
| 282 | #define GPIO100_KP_MKIN0_MD (100 | GPIO_ALT_FN_1_IN) | ||
| 283 | #define GPIO101_KP_MKIN1_MD (101 | GPIO_ALT_FN_1_IN) | ||
| 284 | #define GPIO102_nPCE_1_MD (102 | GPIO_ALT_FN_1_OUT) | ||
| 285 | #define GPIO102_KP_MKIN2_MD (102 | GPIO_ALT_FN_1_IN) | ||
| 286 | #define GPIO103_KP_MKOUT0_MD (103 | GPIO_ALT_FN_2_OUT) | ||
| 287 | #define GPIO104_pSKTSEL_MD (104 | GPIO_ALT_FN_1_OUT) | ||
| 288 | #define GPIO104_KP_MKOUT1_MD (104 | GPIO_ALT_FN_2_OUT) | ||
| 289 | #define GPIO105_KP_MKOUT2_MD (105 | GPIO_ALT_FN_2_OUT) | ||
| 290 | #define GPIO106_KP_MKOUT3_MD (106 | GPIO_ALT_FN_2_OUT) | ||
| 291 | #define GPIO107_KP_MKOUT4_MD (107 | GPIO_ALT_FN_2_OUT) | ||
| 292 | #define GPIO108_KP_MKOUT5_MD (108 | GPIO_ALT_FN_2_OUT) | ||
| 293 | #define GPIO109_MMCDAT1_MD (109 | GPIO_ALT_FN_1_OUT) | ||
| 294 | #define GPIO110_MMCDAT2_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 295 | #define GPIO110_MMCCS0_MD (110 | GPIO_ALT_FN_1_OUT) | ||
| 296 | #define GPIO111_MMCDAT3_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 297 | #define GPIO110_MMCCS1_MD (111 | GPIO_ALT_FN_1_OUT) | ||
| 298 | #define GPIO112_MMCCMD_MD (112 | GPIO_ALT_FN_1_OUT) | ||
| 299 | #define GPIO113_I2S_SYSCLK_MD (113 | GPIO_ALT_FN_1_OUT) | ||
| 300 | #define GPIO113_AC97_RESET_N_MD (113 | GPIO_ALT_FN_2_OUT) | ||
| 301 | #define GPIO117_I2CSCL_MD (117 | GPIO_ALT_FN_1_IN) | ||
| 302 | #define GPIO118_I2CSDA_MD (118 | GPIO_ALT_FN_1_IN) | ||
| 303 | |||
| 304 | #endif /* __ASM_ARCH_PXA2XX_GPIO_H */ | ||