Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm

* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (42 commits)
  [ARM] Fix tosa build error
  [ARM] 3610/1: Make reboot work on Versatile
  [ARM] 3609/1: S3C24XX: defconfig update for s3c2410_defconfig
  [ARM] 3591/1: Anubis: IDE device definitions
  [ARM] Include asm/hardware.h not asm/arch/hardware.h
  [ARM] 3594/1: Poodle: Add touchscreen support + other updates
  [ARM] 3564/1: sharpsl_pm: Abstract some machine specific parameters
  [ARM] 3561/1: Poodle: Correct the MMC/SD power control
  [ARM] 3593/1: Add reboot and shutdown handlers for Zaurus handhelds
  [ARM] 3599/1: AT91RM9200 remove global variables
  [ARM] 3607/1: AT91RM9200 misc fixes
  [ARM] 3605/1: AT91RM9200 Power Management
  [ARM] 3604/1: AT91RM9200 New boards
  [ARM] 3603/1: AT91RM9200 remove old files
  [ARM] 3592/1: AT91RM9200 Serial driver update
  [ARM] 3590/1: AT91RM9200 Platform devices support
  [ARM] 3589/1: AT91RM9200 DK/EK board update
  [ARM] 3588/1: AT91RM9200 CSB337/637 board update
  [ARM] 3587/1: AT91RM9200 hardware headers
  [ARM] 3586/1: AT91RM9200 header update
  ...

1 files changed, 17 insertions, 1 deletions

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 6650d4decaeb..9f83f4adfbf3 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1625,7 +1625,7 @@
 #define SSCR0_RIM       (1 << 22)       /* Receive FIFO overrrun interrupt mask */
 #define SSCR0_TUM       (1 << 23)       /* Transmit FIFO underrun interrupt mask */
 #define SSCR0_FRDC      (0x07000000)    /* Frame rate divider control (mask) */
-#define SSCR0_SlotsPerFrm(c) ((x) - 1)  /* Time slots per frame [1..8] */
+#define SSCR0_SlotsPerFrm(x) ((x) - 1)  /* Time slots per frame [1..8] */
 #define SSCR0_ADC       (1 << 30)       /* Audio clock select */
 #define SSCR0_MOD       (1 << 31)       /* Mode (normal or network) */
 #endif
@@ -1706,6 +1706,10 @@
 #if defined (CONFIG_PXA27x)
 #define SSTO_P1         __REG(0x41000028)  /* SSP Port 1 Time Out Register */
 #define SSPSP_P1        __REG(0x4100002C)  /* SSP Port 1 Programmable Serial Protocol */
+#define SSTSA_P1        __REG(0x41000030)  /* SSP Port 1 Tx Timeslot Active */
+#define SSRSA_P1        __REG(0x41000034)  /* SSP Port 1 Rx Timeslot Active */
+#define SSTSS_P1        __REG(0x41000038)  /* SSP Port 1 Timeslot Status */
+#define SSACD_P1        __REG(0x4100003C)  /* SSP Port 1 Audio Clock Divider */
 #define SSCR0_P2        __REG(0x41700000)  /* SSP Port 2 Control Register 0 */
 #define SSCR1_P2        __REG(0x41700004)  /* SSP Port 2 Control Register 1 */
 #define SSSR_P2         __REG(0x41700008)  /* SSP Port 2 Status Register */
@@ -1713,6 +1717,10 @@
 #define SSDR_P2         __REG(0x41700010)  /* (Write / Read) SSP Port 2 Data Write Register/SSP Data Read Register */
 #define SSTO_P2         __REG(0x41700028)  /* SSP Port 2 Time Out Register */
 #define SSPSP_P2        __REG(0x4170002C)  /* SSP Port 2 Programmable Serial Protocol */
+#define SSTSA_P2        __REG(0x41700030)  /* SSP Port 2 Tx Timeslot Active */
+#define SSRSA_P2        __REG(0x41700034)  /* SSP Port 2 Rx Timeslot Active */
+#define SSTSS_P2        __REG(0x41700038)  /* SSP Port 2 Timeslot Status */
+#define SSACD_P2        __REG(0x4170003C)  /* SSP Port 2 Audio Clock Divider */
 #define SSCR0_P3        __REG(0x41900000)  /* SSP Port 3 Control Register 0 */
 #define SSCR1_P3        __REG(0x41900004)  /* SSP Port 3 Control Register 1 */
 #define SSSR_P3         __REG(0x41900008)  /* SSP Port 3 Status Register */
@@ -1720,6 +1728,10 @@
 #define SSDR_P3         __REG(0x41900010)  /* (Write / Read) SSP Port 3 Data Write Register/SSP Data Read Register */
 #define SSTO_P3         __REG(0x41900028)  /* SSP Port 3 Time Out Register */
 #define SSPSP_P3        __REG(0x4190002C)  /* SSP Port 3 Programmable Serial Protocol */
+#define SSTSA_P3        __REG(0x41900030)  /* SSP Port 3 Tx Timeslot Active */
+#define SSRSA_P3        __REG(0x41900034)  /* SSP Port 3 Rx Timeslot Active */
+#define SSTSS_P3        __REG(0x41900038)  /* SSP Port 3 Timeslot Status */
+#define SSACD_P3        __REG(0x4190003C)  /* SSP Port 3 Audio Clock Divider */
 #else /* PXA255 (only port 2) and PXA26x ports*/
 #define SSTO_P1         __REG(0x41000028)  /* SSP Port 1 Time Out Register */
 #define SSPSP_P1        __REG(0x4100002C)  /* SSP Port 1 Programmable Serial Protocol */
@@ -1746,6 +1758,10 @@
 #define SSDR_P(x) (*(((x) == 1) ? &SSDR_P1 : ((x) == 2) ? &SSDR_P2 : ((x) == 3) ? &SSDR_P3 : NULL))
 #define SSTO_P(x) (*(((x) == 1) ? &SSTO_P1 : ((x) == 2) ? &SSTO_P2 : ((x) == 3) ? &SSTO_P3 : NULL))
 #define SSPSP_P(x) (*(((x) == 1) ? &SSPSP_P1 : ((x) == 2) ? &SSPSP_P2 : ((x) == 3) ? &SSPSP_P3 : NULL))
+#define SSTSA_P(x) (*(((x) == 1) ? &SSTSA_P1 : ((x) == 2) ? &SSTSA_P2 : ((x) == 3) ? &SSTSA_P3 : NULL))
+#define SSRSA_P(x) (*(((x) == 1) ? &SSRSA_P1 : ((x) == 2) ? &SSRSA_P2 : ((x) == 3) ? &SSRSA_P3 : NULL))
+#define SSTSS_P(x) (*(((x) == 1) ? &SSTSS_P1 : ((x) == 2) ? &SSTSS_P2 : ((x) == 3) ? &SSTSS_P3 : NULL))
+#define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL))
 
 /*
  * MultiMediaCard (MMC) controller