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authorNicolas Pitre <nico@cam.org>2005-10-28 11:39:33 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2005-10-28 11:39:33 -0400
commit6f475c0133eb91c7df3b056843dc33d2824368a2 (patch)
tree051e35468fb1965c72e6fa5b679fac48975508b8 /include/asm-arm/arch-pxa/pxa-regs.h
parenta999cb04b4bfb4a2243383f00d5714b8d7163035 (diff)
[ARM] 2897/2: PXA2xx IRDA support
Patch from Nicolas Pitre This is the PXA2xx common IRDA driver, plus platform support for Lubbock and Mainstone. Signed-off-by: Nicolas Pitre <nico@cam.org> Acked-by: Jean Tourrilhes <jt@hpl.hp.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-pxa/pxa-regs.h')
-rw-r--r--include/asm-arm/arch-pxa/pxa-regs.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 75f085dc9894..a75a2470f4f5 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1032,14 +1032,12 @@
1032#define ICCR0_LBM (1 << 1) /* Loopback mode */ 1032#define ICCR0_LBM (1 << 1) /* Loopback mode */
1033#define ICCR0_ITR (1 << 0) /* IrDA transmission */ 1033#define ICCR0_ITR (1 << 0) /* IrDA transmission */
1034 1034
1035#ifdef CONFIG_PXA27x
1036#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */ 1035#define ICCR2_RXP (1 << 3) /* Receive Pin Polarity select */
1037#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */ 1036#define ICCR2_TXP (1 << 2) /* Transmit Pin Polarity select */
1038#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */ 1037#define ICCR2_TRIG (3 << 0) /* Receive FIFO Trigger threshold */
1039#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */ 1038#define ICCR2_TRIG_8 (0 << 0) /* >= 8 bytes */
1040#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */ 1039#define ICCR2_TRIG_16 (1 << 0) /* >= 16 bytes */
1041#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */ 1040#define ICCR2_TRIG_32 (2 << 0) /* >= 32 bytes */
1042#endif
1043 1041
1044#ifdef CONFIG_PXA27x 1042#ifdef CONFIG_PXA27x
1045#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */ 1043#define ICSR0_EOC (1 << 6) /* DMA End of Descriptor Chain */