diff options
author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2007-05-16 10:44:37 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2007-07-12 09:27:56 -0400 |
commit | 7a2b94bc39915041304578188441f0f21aa5532a (patch) | |
tree | 50937d7cb453dab5c1b0de6e96031f219fc8c1cc /include/asm-arm/arch-pxa/pxa-regs.h | |
parent | f4b6a0a401f2cec5e6199e805ed42f30d8c04e94 (diff) |
[ARM] pxa: remove MMC register defines from pxa-regs.h
pxamci.h redefines the MMC registers differently so they can be used
with ioremap. Remove the incompatible definitions from pxa-regs.h.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-pxa/pxa-regs.h')
-rw-r--r-- | include/asm-arm/arch-pxa/pxa-regs.h | 22 |
1 files changed, 1 insertions, 21 deletions
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index dbcc9298b0c8..e68b593d69da 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h | |||
@@ -1765,29 +1765,9 @@ | |||
1765 | #define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) | 1765 | #define SSACD_P(x) (*(((x) == 1) ? &SSACD_P1 : ((x) == 2) ? &SSACD_P2 : ((x) == 3) ? &SSACD_P3 : NULL)) |
1766 | 1766 | ||
1767 | /* | 1767 | /* |
1768 | * MultiMediaCard (MMC) controller | 1768 | * MultiMediaCard (MMC) controller - see drivers/mmc/host/pxamci.h |
1769 | */ | 1769 | */ |
1770 | 1770 | ||
1771 | #define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */ | ||
1772 | #define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */ | ||
1773 | #define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */ | ||
1774 | #define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */ | ||
1775 | #define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */ | ||
1776 | #define MMC_RESTO __REG(0x41100014) /* Expected response time out */ | ||
1777 | #define MMC_RDTO __REG(0x41100018) /* Expected data read time out */ | ||
1778 | #define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */ | ||
1779 | #define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */ | ||
1780 | #define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */ | ||
1781 | #define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */ | ||
1782 | #define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */ | ||
1783 | #define MMC_CMD __REG(0x41100030) /* Index of current command */ | ||
1784 | #define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */ | ||
1785 | #define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */ | ||
1786 | #define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */ | ||
1787 | #define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */ | ||
1788 | #define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */ | ||
1789 | |||
1790 | |||
1791 | /* | 1771 | /* |
1792 | * Core Clock | 1772 | * Core Clock |
1793 | */ | 1773 | */ |