diff options
author | eric miao <eric.miao@marvell.com> | 2008-01-02 22:25:56 -0500 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2008-01-26 10:07:56 -0500 |
commit | 7f7c8a619253c83cf3b1071df3b001811d0c1a6c (patch) | |
tree | b4a80e57ef93e3d669e1cadb561ba975e2ce2228 /include/asm-arm/arch-pxa/mfp-pxa3xx.h | |
parent | 0ad1fbc86045c2a27ff082c02344131be072699f (diff) |
[ARM] pxa: make MFP configuration processor independent
There are two reasons for making the MFP configuration to be processor
independent, i.e. removing the relationship of configuration bits with
actual MFPR register settings:
1. power management sometimes requires the MFP to be configured
differently when in run mode or in low power mode
2. for future integration of pxa{25x,27x} GPIO configurations
The modifications include:
1. introducing of processor independent MFP configuration bits, as
defined in [include/asm-arm/arch-pxa/mfp.h]:
bit 0.. 9 - MFP Pin Number (1024 Pins Maximum)
bit 10..12 - Alternate Function Selection
bit 13..15 - Drive Strength
bit 16..18 - Low Power Mode State
bit 19..20 - Low Power Mode Edge Detection
bit 21..22 - Run Mode Pull State
and so on,
2. moving the processor dependent code from mfp.h into mfp-pxa3xx.h
3. cleaning up of the MFPR bit definitions
4. mapping of processor independent MFP configuration into processor
specific MFPR register settings is now totally encapsulated within
pxa3xx_mfp_config()
5. using of "unsigned long" instead of invented type of "mfp_cfg_t"
according to Documentation/CodingStyle Chapter 5, usage of this
in platform code will be slowly removed in later patches
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-pxa/mfp-pxa3xx.h')
-rw-r--r-- | include/asm-arm/arch-pxa/mfp-pxa3xx.h | 115 |
1 files changed, 115 insertions, 0 deletions
diff --git a/include/asm-arm/arch-pxa/mfp-pxa3xx.h b/include/asm-arm/arch-pxa/mfp-pxa3xx.h index 5da1857d5476..1f6b35c015d0 100644 --- a/include/asm-arm/arch-pxa/mfp-pxa3xx.h +++ b/include/asm-arm/arch-pxa/mfp-pxa3xx.h | |||
@@ -1,6 +1,69 @@ | |||
1 | #ifndef __ASM_ARCH_MFP_PXA3XX_H | 1 | #ifndef __ASM_ARCH_MFP_PXA3XX_H |
2 | #define __ASM_ARCH_MFP_PXA3XX_H | 2 | #define __ASM_ARCH_MFP_PXA3XX_H |
3 | 3 | ||
4 | #define MFPR_BASE (0x40e10000) | ||
5 | #define MFPR_SIZE (PAGE_SIZE) | ||
6 | |||
7 | /* MFPR register bit definitions */ | ||
8 | #define MFPR_PULL_SEL (0x1 << 15) | ||
9 | #define MFPR_PULLUP_EN (0x1 << 14) | ||
10 | #define MFPR_PULLDOWN_EN (0x1 << 13) | ||
11 | #define MFPR_SLEEP_SEL (0x1 << 9) | ||
12 | #define MFPR_SLEEP_OE_N (0x1 << 7) | ||
13 | #define MFPR_EDGE_CLEAR (0x1 << 6) | ||
14 | #define MFPR_EDGE_FALL_EN (0x1 << 5) | ||
15 | #define MFPR_EDGE_RISE_EN (0x1 << 4) | ||
16 | |||
17 | #define MFPR_SLEEP_DATA(x) ((x) << 8) | ||
18 | #define MFPR_DRIVE(x) (((x) & 0x7) << 10) | ||
19 | #define MFPR_AF_SEL(x) (((x) & 0x7) << 0) | ||
20 | |||
21 | #define MFPR_EDGE_NONE (0) | ||
22 | #define MFPR_EDGE_RISE (MFPR_EDGE_RISE_EN) | ||
23 | #define MFPR_EDGE_FALL (MFPR_EDGE_FALL_EN) | ||
24 | #define MFPR_EDGE_BOTH (MFPR_EDGE_RISE | MFPR_EDGE_FALL) | ||
25 | |||
26 | /* | ||
27 | * Table that determines the low power modes outputs, with actual settings | ||
28 | * used in parentheses for don't-care values. Except for the float output, | ||
29 | * the configured driven and pulled levels match, so if there is a need for | ||
30 | * non-LPM pulled output, the same configuration could probably be used. | ||
31 | * | ||
32 | * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel | ||
33 | * (bit 7) (bit 8) (bit 14) (bit 13) (bit 15) | ||
34 | * | ||
35 | * Input 0 X(0) X(0) X(0) 0 | ||
36 | * Drive 0 0 0 0 X(1) 0 | ||
37 | * Drive 1 0 1 X(1) 0 0 | ||
38 | * Pull hi (1) 1 X(1) 1 0 0 | ||
39 | * Pull lo (0) 1 X(0) 0 1 0 | ||
40 | * Z (float) 1 X(0) 0 0 0 | ||
41 | */ | ||
42 | #define MFPR_LPM_INPUT (0) | ||
43 | #define MFPR_LPM_DRIVE_LOW (MFPR_SLEEP_DATA(0) | MFPR_PULLDOWN_EN) | ||
44 | #define MFPR_LPM_DRIVE_HIGH (MFPR_SLEEP_DATA(1) | MFPR_PULLUP_EN) | ||
45 | #define MFPR_LPM_PULL_LOW (MFPR_LPM_DRIVE_LOW | MFPR_SLEEP_OE_N) | ||
46 | #define MFPR_LPM_PULL_HIGH (MFPR_LPM_DRIVE_HIGH | MFPR_SLEEP_OE_N) | ||
47 | #define MFPR_LPM_FLOAT (MFPR_SLEEP_OE_N) | ||
48 | #define MFPR_LPM_MASK (0xe080) | ||
49 | |||
50 | /* | ||
51 | * The pullup and pulldown state of the MFP pin at run mode is by default | ||
52 | * determined by the selected alternate function. In case that some buggy | ||
53 | * devices need to override this default behavior, the definitions below | ||
54 | * indicates the setting of corresponding MFPR bits | ||
55 | * | ||
56 | * Definition pull_sel pullup_en pulldown_en | ||
57 | * MFPR_PULL_NONE 0 0 0 | ||
58 | * MFPR_PULL_LOW 1 0 1 | ||
59 | * MFPR_PULL_HIGH 1 1 0 | ||
60 | * MFPR_PULL_BOTH 1 1 1 | ||
61 | */ | ||
62 | #define MFPR_PULL_NONE (0) | ||
63 | #define MFPR_PULL_LOW (MFPR_PULL_SEL | MFPR_PULLDOWN_EN) | ||
64 | #define MFPR_PULL_BOTH (MFPR_PULL_LOW | MFPR_PULLUP_EN) | ||
65 | #define MFPR_PULL_HIGH (MFPR_PULL_SEL | MFPR_PULLUP_EN) | ||
66 | |||
4 | /* PXA3xx common MFP configurations - processor specific ones defined | 67 | /* PXA3xx common MFP configurations - processor specific ones defined |
5 | * in mfp-pxa300.h and mfp-pxa320.h | 68 | * in mfp-pxa300.h and mfp-pxa320.h |
6 | */ | 69 | */ |
@@ -134,4 +197,56 @@ | |||
134 | #define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) | 197 | #define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) |
135 | #define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) | 198 | #define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) |
136 | 199 | ||
200 | /* | ||
201 | * each MFP pin will have a MFPR register, since the offset of the | ||
202 | * register varies between processors, the processor specific code | ||
203 | * should initialize the pin offsets by pxa3xx_mfp_init_addr() | ||
204 | * | ||
205 | * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" | ||
206 | * structure, which represents a range of MFP pins from "start" to | ||
207 | * "end", with the offset begining at "offset", to define a single | ||
208 | * pin, let "end" = -1 | ||
209 | * | ||
210 | * use | ||
211 | * | ||
212 | * MFP_ADDR_X() to define a range of pins | ||
213 | * MFP_ADDR() to define a single pin | ||
214 | * MFP_ADDR_END to signal the end of pin offset definitions | ||
215 | */ | ||
216 | struct pxa3xx_mfp_addr_map { | ||
217 | unsigned int start; | ||
218 | unsigned int end; | ||
219 | unsigned long offset; | ||
220 | }; | ||
221 | |||
222 | #define MFP_ADDR_X(start, end, offset) \ | ||
223 | { MFP_PIN_##start, MFP_PIN_##end, offset } | ||
224 | |||
225 | #define MFP_ADDR(pin, offset) \ | ||
226 | { MFP_PIN_##pin, -1, offset } | ||
227 | |||
228 | #define MFP_ADDR_END { MFP_PIN_INVALID, 0 } | ||
229 | |||
230 | /* | ||
231 | * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access | ||
232 | * to the MFPR register | ||
233 | */ | ||
234 | unsigned long pxa3xx_mfp_read(int mfp); | ||
235 | void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); | ||
236 | |||
237 | /* | ||
238 | * pxa3xx_mfp_config - configure the MFPR registers | ||
239 | * | ||
240 | * used by board specific initialization code | ||
241 | */ | ||
242 | void pxa3xx_mfp_config(unsigned long *mfp_cfgs, int num); | ||
243 | |||
244 | /* | ||
245 | * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin | ||
246 | * index and MFPR register offset | ||
247 | * | ||
248 | * used by processor specific code | ||
249 | */ | ||
250 | void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); | ||
251 | void __init pxa3xx_init_mfp(void); | ||
137 | #endif /* __ASM_ARCH_MFP_PXA3XX_H */ | 252 | #endif /* __ASM_ARCH_MFP_PXA3XX_H */ |