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authorRussell King <rmk@dyn-67.arm.linux.org.uk>2008-08-05 11:14:15 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-08-07 04:55:48 -0400
commita09e64fbc0094e3073dbb09c3b4bfe4ab669244b (patch)
tree69689f467179891b498bd7423fcf61925173db31 /include/asm-arm/arch-pnx4008/irq.h
parenta1b81a84fff05dbfef45b7012c26e1fee9973e5d (diff)
[ARM] Move include/asm-arm/arch-* to arch/arm/*/include/mach
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'include/asm-arm/arch-pnx4008/irq.h')
-rw-r--r--include/asm-arm/arch-pnx4008/irq.h42
1 files changed, 0 insertions, 42 deletions
diff --git a/include/asm-arm/arch-pnx4008/irq.h b/include/asm-arm/arch-pnx4008/irq.h
deleted file mode 100644
index fabff5dc337f..000000000000
--- a/include/asm-arm/arch-pnx4008/irq.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * include/asm-arm/arch-pnx4008/irq.h
3 *
4 * PNX4008 IRQ controller driver - header file
5 * this one is used in entry-arnv.S as well so it cannot contain C code
6 *
7 * Copyright (c) 2005 Philips Semiconductors
8 * Copyright (c) 2005 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __PNX4008_IRQ_H__
16#define __PNX4008_IRQ_H__
17
18#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
19#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
20#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
21
22/* Manual: Chapter 20, page 195 */
23
24#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
25
26#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
27#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
28#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
29#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
30#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
31#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
32
33#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
34
35#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
36#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
37#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
38#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
39
40extern void __init pnx4008_init_irq(void);
41
42#endif /* __PNX4008_IRQ_H__ */