Orion: orion -> orion5x rename

Do a global s/orion/orion5x/ of the Orion 5x-specific bits (i.e.
not the plat-orion bits.)

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>
Acked-by: Saeed Bishara <saeed@marvell.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Nicolas Pitre <nico@marvell.com>

13 files changed, 492 insertions, 0 deletions

diff --git a/include/asm-arm/arch-orion5x/debug-macro.S b/include/asm-arm/arch-orion5x/debug-macro.S
new file mode 100644
index 000000000000..4f98f3ba2929
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/debug-macro.S
@@ -0,0 +1,22 @@
+/*
+ * include/asm-arm/arch-orion5x/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <asm/arch/orion5x.h>
+
+        .macro  addruart,rx
+        mrc     p15, 0, \rx, c1, c0
+        tst     \rx, #1                                 @ MMU enabled?
+        ldreq   \rx, =ORION5X_REGS_PHYS_BASE
+        ldrne   \rx, =ORION5X_REGS_VIRT_BASE
+        orr     \rx, \rx, #0x00012000
+        .endm
+
+#define UART_SHIFT      2
+#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-orion5x/dma.h b/include/asm-arm/arch-orion5x/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/dma.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/include/asm-arm/arch-orion5x/entry-macro.S b/include/asm-arm/arch-orion5x/entry-macro.S
new file mode 100644
index 000000000000..d8ef54c0ee9a
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/entry-macro.S
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-orion5x/entry-macro.S
+ *
+ * Low-level IRQ helper macros for Orion platforms
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/orion5x.h>
+
+        .macro  disable_fiq
+        .endm
+
+        .macro  arch_ret_to_user, tmp1, tmp2
+        .endm
+
+        .macro  get_irqnr_preamble, base, tmp
+        ldr     \base, =MAIN_IRQ_CAUSE
+        .endm
+
+        .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
+        ldr     \irqstat, [\base, #0]           @ main cause
+        ldr     \tmp, [\base, #(MAIN_IRQ_MASK - MAIN_IRQ_CAUSE)] @ main mask
+        mov     \irqnr, #0                      @ default irqnr
+        @ find cause bits that are unmasked
+        ands    \irqstat, \irqstat, \tmp        @ clear Z flag if any
+        clzne   \irqnr, \irqstat                @ calc irqnr
+        rsbne   \irqnr, \irqnr, #31
+        .endm
diff --git a/include/asm-arm/arch-orion5x/gpio.h b/include/asm-arm/arch-orion5x/gpio.h
new file mode 100644
index 000000000000..c85e498388b6
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * include/asm-arm/arch-orion5x/gpio.h
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+extern int gpio_request(unsigned pin, const char *label);
+extern void gpio_free(unsigned pin);
+extern int gpio_direction_input(unsigned pin);
+extern int gpio_direction_output(unsigned pin, int value);
+extern int gpio_get_value(unsigned pin);
+extern void gpio_set_value(unsigned pin, int value);
+extern void orion5x_gpio_set_blink(unsigned pin, int blink);
+extern void gpio_display(void);         /* debug */
+
+static inline int gpio_to_irq(int pin)
+{
+        return pin + IRQ_ORION5X_GPIO_START;
+}
+
+static inline int irq_to_gpio(int irq)
+{
+        return irq - IRQ_ORION5X_GPIO_START;
+}
+
+#include <asm-generic/gpio.h>           /* cansleep wrappers */
diff --git a/include/asm-arm/arch-orion5x/hardware.h b/include/asm-arm/arch-orion5x/hardware.h
new file mode 100644
index 000000000000..5d2d8e0b5630
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/hardware.h
@@ -0,0 +1,21 @@
+/*
+ * include/asm-arm/arch-orion5x/hardware.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include "orion5x.h"
+
+#define pcibios_assign_all_busses()     1
+
+#define PCIBIOS_MIN_IO          0x00001000
+#define PCIBIOS_MIN_MEM         0x01000000
+#define PCIMEM_BASE             ORION5X_PCIE_MEM_PHYS_BASE
+
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/io.h b/include/asm-arm/arch-orion5x/io.h
new file mode 100644
index 000000000000..5148ab7ad1f8
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/io.h
@@ -0,0 +1,68 @@
+/*
+ * include/asm-arm/arch-orion5x/io.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IO_H
+#define __ASM_ARCH_IO_H
+
+#include "orion5x.h"
+
+#define IO_SPACE_LIMIT          0xffffffff
+#define IO_SPACE_REMAP          ORION5X_PCI_SYS_IO_BASE
+
+static inline void __iomem *
+__arch_ioremap(unsigned long paddr, size_t size, unsigned int mtype)
+{
+        void __iomem *retval;
+
+        if (mtype == MT_DEVICE && size && paddr >= ORION5X_REGS_PHYS_BASE &&
+            paddr + size <= ORION5X_REGS_PHYS_BASE + ORION5X_REGS_SIZE) {
+                retval = (void __iomem *)ORION5X_REGS_VIRT_BASE +
+                                (paddr - ORION5X_REGS_PHYS_BASE);
+        } else {
+                retval = __arm_ioremap(paddr, size, mtype);
+        }
+
+        return retval;
+}
+
+static inline void
+__arch_iounmap(void __iomem *addr)
+{
+        if (addr < (void __iomem *)ORION5X_REGS_VIRT_BASE ||
+            addr >= (void __iomem *)(ORION5X_REGS_VIRT_BASE + ORION5X_REGS_SIZE))
+                __iounmap(addr);
+}
+
+static inline void __iomem *__io(unsigned long addr)
+{
+        return (void __iomem *)addr;
+}
+
+#define __arch_ioremap(p, s, m) __arch_ioremap(p, s, m)
+#define __arch_iounmap(a)       __arch_iounmap(a)
+#define __io(a)                 __io(a)
+#define __mem_pci(a)            (a)
+
+
+/*****************************************************************************
+ * Helpers to access Orion registers
+ ****************************************************************************/
+#define orion5x_read(r)         __raw_readl(r)
+#define orion5x_write(r, val)   __raw_writel(val, r)
+
+/*
+ * These are not preempt-safe.  Locks, if needed, must be taken
+ * care of by the caller.
+ */
+#define orion5x_setbits(r, mask)        orion5x_write((r), orion5x_read(r) | (mask))
+#define orion5x_clrbits(r, mask)        orion5x_write((r), orion5x_read(r) & ~(mask))
+
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/irqs.h b/include/asm-arm/arch-orion5x/irqs.h
new file mode 100644
index 000000000000..abdd61a4833a
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/irqs.h
@@ -0,0 +1,62 @@
+/*
+ * include/asm-arm/arch-orion5x/irqs.h
+ *
+ * IRQ definitions for Orion SoC
+ *
+ *  Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ *  This file is licensed under the terms of the GNU General Public
+ *  License version 2. This program is licensed "as is" without any
+ *  warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#include "orion5x.h"    /* need GPIO_MAX */
+
+/*
+ * Orion Main Interrupt Controller
+ */
+#define IRQ_ORION5X_BRIDGE              0
+#define IRQ_ORION5X_DOORBELL_H2C        1
+#define IRQ_ORION5X_DOORBELL_C2H        2
+#define IRQ_ORION5X_UART0               3
+#define IRQ_ORION5X_UART1               4
+#define IRQ_ORION5X_I2C                 5
+#define IRQ_ORION5X_GPIO_0_7            6
+#define IRQ_ORION5X_GPIO_8_15           7
+#define IRQ_ORION5X_GPIO_16_23          8
+#define IRQ_ORION5X_GPIO_24_31          9
+#define IRQ_ORION5X_PCIE0_ERR           10
+#define IRQ_ORION5X_PCIE0_INT           11
+#define IRQ_ORION5X_USB1_CTRL           12
+#define IRQ_ORION5X_DEV_BUS_ERR         14
+#define IRQ_ORION5X_PCI_ERR             15
+#define IRQ_ORION5X_USB_BR_ERR          16
+#define IRQ_ORION5X_USB0_CTRL           17
+#define IRQ_ORION5X_ETH_RX              18
+#define IRQ_ORION5X_ETH_TX              19
+#define IRQ_ORION5X_ETH_MISC            20
+#define IRQ_ORION5X_ETH_SUM             21
+#define IRQ_ORION5X_ETH_ERR             22
+#define IRQ_ORION5X_IDMA_ERR            23
+#define IRQ_ORION5X_IDMA_0              24
+#define IRQ_ORION5X_IDMA_1              25
+#define IRQ_ORION5X_IDMA_2              26
+#define IRQ_ORION5X_IDMA_3              27
+#define IRQ_ORION5X_CESA                28
+#define IRQ_ORION5X_SATA                29
+#define IRQ_ORION5X_XOR0                30
+#define IRQ_ORION5X_XOR1                31
+
+/*
+ * Orion General Purpose Pins
+ */
+#define IRQ_ORION5X_GPIO_START  32
+#define NR_GPIO_IRQS            GPIO_MAX
+
+#define NR_IRQS                 (IRQ_ORION5X_GPIO_START + NR_GPIO_IRQS)
+
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/memory.h b/include/asm-arm/arch-orion5x/memory.h
new file mode 100644
index 000000000000..80053a7afc7a
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/memory.h
@@ -0,0 +1,16 @@
+/*
+ * include/asm-arm/arch-orion5x/memory.h
+ *
+ * Marvell Orion memory definitions
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PHYS_OFFSET     UL(0x00000000)
+
+#define __virt_to_bus(x)        __virt_to_phys(x)
+#define __bus_to_virt(x)        __phys_to_virt(x)
+
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/orion5x.h b/include/asm-arm/arch-orion5x/orion5x.h
new file mode 100644
index 000000000000..206ddd71e193
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/orion5x.h
@@ -0,0 +1,159 @@
+/*
+ * include/asm-arm/arch-orion5x/orion5x.h
+ *
+ * Generic definitions of Orion SoC flavors:
+ *  Orion-1, Orion-NAS, Orion-VoIP, and Orion-2.
+ *
+ * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_ORION5X_H
+#define __ASM_ARCH_ORION5X_H
+
+/*****************************************************************************
+ * Orion Address Maps
+ *
+ * phys
+ * e0000000     PCIe MEM space
+ * e8000000     PCI MEM space
+ * f0000000     PCIe WA space (Orion-1/Orion-NAS only)
+ * f1000000     on-chip peripheral registers
+ * f2000000     PCIe I/O space
+ * f2100000     PCI I/O space
+ * f4000000     device bus mappings (boot)
+ * fa000000     device bus mappings (cs0)
+ * fa800000     device bus mappings (cs2)
+ * fc000000     device bus mappings (cs0/cs1)
+ *
+ * virt         phys            size
+ * fdd00000     f1000000        1M      on-chip peripheral registers
+ * fde00000     f2000000        1M      PCIe I/O space
+ * fdf00000     f2100000        1M      PCI I/O space
+ * fe000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
+ ****************************************************************************/
+#define ORION5X_REGS_PHYS_BASE          0xf1000000
+#define ORION5X_REGS_VIRT_BASE          0xfdd00000
+#define ORION5X_REGS_SIZE               SZ_1M
+
+#define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
+#define ORION5X_PCIE_IO_VIRT_BASE       0xfde00000
+#define ORION5X_PCIE_IO_BUS_BASE        0x00000000
+#define ORION5X_PCIE_IO_SIZE            SZ_1M
+
+#define ORION5X_PCI_IO_PHYS_BASE        0xf2100000
+#define ORION5X_PCI_IO_VIRT_BASE        0xfdf00000
+#define ORION5X_PCI_IO_BUS_BASE         0x00100000
+#define ORION5X_PCI_IO_SIZE             SZ_1M
+
+/* Relevant only for Orion-1/Orion-NAS */
+#define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
+#define ORION5X_PCIE_WA_VIRT_BASE       0xfe000000
+#define ORION5X_PCIE_WA_SIZE            SZ_16M
+
+#define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
+#define ORION5X_PCIE_MEM_SIZE           SZ_128M
+
+#define ORION5X_PCI_MEM_PHYS_BASE       0xe8000000
+#define ORION5X_PCI_MEM_SIZE            SZ_128M
+
+/*******************************************************************************
+ * Supported Devices & Revisions
+ ******************************************************************************/
+/* Orion-1 (88F5181) */
+#define MV88F5181_DEV_ID        0x5181
+#define MV88F5181_REV_B1        3
+/* Orion-NAS (88F5182) */
+#define MV88F5182_DEV_ID        0x5182
+#define MV88F5182_REV_A2        2
+/* Orion-2 (88F5281) */
+#define MV88F5281_DEV_ID        0x5281
+#define MV88F5281_REV_D1        5
+#define MV88F5281_REV_D2        6
+
+/*******************************************************************************
+ * Orion Registers Map
+ ******************************************************************************/
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
+#define ORION5X_DDR_REG(x)              (ORION5X_DDR_VIRT_BASE | (x))
+
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
+#define ORION5X_BRIDGE_REG(x)           (ORION5X_BRIDGE_VIRT_BASE | (x))
+#define  TIMER_VIRT_BASE                (ORION5X_BRIDGE_VIRT_BASE | 0x300)
+
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_REG(x)              (ORION5X_PCI_VIRT_BASE | (x))
+
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_REG(x)             (ORION5X_PCIE_VIRT_BASE | (x))
+
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_REG(x)             (ORION5X_USB0_VIRT_BASE | (x))
+
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_REG(x)              (ORION5X_ETH_VIRT_BASE | (x))
+
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_REG(x)             (ORION5X_SATA_VIRT_BASE | (x))
+
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_REG(x)             (ORION5X_USB1_VIRT_BASE | (x))
+
+/*******************************************************************************
+ * Device Bus Registers
+ ******************************************************************************/
+#define MPP_0_7_CTRL            ORION5X_DEV_BUS_REG(0x000)
+#define MPP_8_15_CTRL           ORION5X_DEV_BUS_REG(0x004)
+#define MPP_16_19_CTRL          ORION5X_DEV_BUS_REG(0x050)
+#define MPP_DEV_CTRL            ORION5X_DEV_BUS_REG(0x008)
+#define MPP_RESET_SAMPLE        ORION5X_DEV_BUS_REG(0x010)
+#define GPIO_OUT                ORION5X_DEV_BUS_REG(0x100)
+#define GPIO_IO_CONF            ORION5X_DEV_BUS_REG(0x104)
+#define GPIO_BLINK_EN           ORION5X_DEV_BUS_REG(0x108)
+#define GPIO_IN_POL             ORION5X_DEV_BUS_REG(0x10c)
+#define GPIO_DATA_IN            ORION5X_DEV_BUS_REG(0x110)
+#define GPIO_EDGE_CAUSE         ORION5X_DEV_BUS_REG(0x114)
+#define GPIO_EDGE_MASK          ORION5X_DEV_BUS_REG(0x118)
+#define GPIO_LEVEL_MASK         ORION5X_DEV_BUS_REG(0x11c)
+#define DEV_BANK_0_PARAM        ORION5X_DEV_BUS_REG(0x45c)
+#define DEV_BANK_1_PARAM        ORION5X_DEV_BUS_REG(0x460)
+#define DEV_BANK_2_PARAM        ORION5X_DEV_BUS_REG(0x464)
+#define DEV_BANK_BOOT_PARAM     ORION5X_DEV_BUS_REG(0x46c)
+#define DEV_BUS_CTRL            ORION5X_DEV_BUS_REG(0x4c0)
+#define DEV_BUS_INT_CAUSE       ORION5X_DEV_BUS_REG(0x4d0)
+#define DEV_BUS_INT_MASK        ORION5X_DEV_BUS_REG(0x4d4)
+#define GPIO_MAX                32
+
+/***************************************************************************
+ * Orion CPU Bridge Registers
+ **************************************************************************/
+#define CPU_CONF                ORION5X_BRIDGE_REG(0x100)
+#define CPU_CTRL                ORION5X_BRIDGE_REG(0x104)
+#define CPU_RESET_MASK          ORION5X_BRIDGE_REG(0x108)
+#define CPU_SOFT_RESET          ORION5X_BRIDGE_REG(0x10c)
+#define POWER_MNG_CTRL_REG      ORION5X_BRIDGE_REG(0x11C)
+#define BRIDGE_CAUSE            ORION5X_BRIDGE_REG(0x110)
+#define BRIDGE_MASK             ORION5X_BRIDGE_REG(0x114)
+#define  BRIDGE_INT_TIMER0      0x0002
+#define  BRIDGE_INT_TIMER1      0x0004
+#define MAIN_IRQ_CAUSE          ORION5X_BRIDGE_REG(0x200)
+#define MAIN_IRQ_MASK           ORION5X_BRIDGE_REG(0x204)
+
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/system.h b/include/asm-arm/arch-orion5x/system.h
new file mode 100644
index 000000000000..3f1d1e2d38f8
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/system.h
@@ -0,0 +1,32 @@
+/*
+ * include/asm-arm/arch-orion5x/system.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+#include <asm/arch/hardware.h>
+#include <asm/arch/orion5x.h>
+
+static inline void arch_idle(void)
+{
+        cpu_do_idle();
+}
+
+static inline void arch_reset(char mode)
+{
+        /*
+         * Enable and issue soft reset
+         */
+        orion5x_setbits(CPU_RESET_MASK, (1 << 2));
+        orion5x_setbits(CPU_SOFT_RESET, 1);
+}
+
+
+#endif
diff --git a/include/asm-arm/arch-orion5x/timex.h b/include/asm-arm/arch-orion5x/timex.h
new file mode 100644
index 000000000000..31c568e28cc3
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/timex.h
@@ -0,0 +1,13 @@
+/*
+ * include/asm-arm/arch-orion5x/timex.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#define CLOCK_TICK_RATE         (100 * HZ)
+
+#define ORION5X_TCLK            166666667
diff --git a/include/asm-arm/arch-orion5x/uncompress.h b/include/asm-arm/arch-orion5x/uncompress.h
new file mode 100644
index 000000000000..5c13d4fafb4e
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/uncompress.h
@@ -0,0 +1,34 @@
+/*
+ * include/asm-arm/arch-orion5x/uncompress.h
+ *
+ * Tzachi Perelstein <tzachi@marvell.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <asm/arch/orion5x.h>
+
+#define MV_UART_THR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x0))
+#define MV_UART_LSR     ((volatile unsigned char *)(UART0_PHYS_BASE + 0x14))
+
+#define LSR_THRE        0x20
+
+static void putc(const char c)
+{
+        int j = 0x1000;
+        while (--j && !(*MV_UART_LSR & LSR_THRE))
+                barrier();
+        *MV_UART_THR = c;
+}
+
+static void flush(void)
+{
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-orion5x/vmalloc.h b/include/asm-arm/arch-orion5x/vmalloc.h
new file mode 100644
index 000000000000..2b3061e90dc1
--- /dev/null
+++ b/include/asm-arm/arch-orion5x/vmalloc.h
@@ -0,0 +1,5 @@
+/*
+ * include/asm-arm/arch-orion5x/vmalloc.h
+ */
+
+#define VMALLOC_END       0xfd800000